JP4737211B2 - Level shift circuit and solid-state imaging device using the same - Google Patents

Description

  The present invention relates to a level shift circuit and a solid-state imaging device using the level shift circuit, and particularly operates by being connected between a power supply and a ground (hereinafter referred to as GND), and shifts a power supply voltage or a GND level to a predetermined level therebetween. The present invention relates to a level shift circuit and a solid-state imaging device using the level shift circuit as a clock pulse driver.

As solid-state image sensors, XY address type image sensors represented by MOS type image sensors and charge transfer type image sensors represented by CCD (Charge Coupled Device) type image sensors are known. Among these solid-state imaging devices, for example, a CMOS type imaging device (see, for example, Patent Document 1) is shown as an example of a conventional example in FIG.

  In FIG. 14, a unit pixel 101 includes a photodiode 111, a readout transistor 112, an amplification transistor 113, a reset transistor 114, and an XY address transistor 115, and is two-dimensionally arranged in a matrix to form an imaging region. Here, for simplification of the drawing, only the unit pixel in the m-th row and the n-th column is shown.

  In the unit pixel 101, the source of the amplification transistor 113 is directly connected to the vertical signal line 121, and the amplification transistor 113 has a four-transistor structure that also functions as a selection transistor. The gate of the reset transistor 114 is connected to the horizontal reset line 122. The drain of the reset transistor 114 is connected to the vertical reset line 123. The gate of the XY address transistor 115 is connected to the vertical read line 124 and the drain thereof is connected to the horizontal read line 125.

Outside the imaging region, a vertical scanning circuit 102, a vertical scanning pulse driver 103, a horizontal selection transistor 104, a horizontal scanning circuit 105, and a voltage source 106 are arranged. From the vertical scanning circuit 102, vertical readout scanning pulses φV ^R _m (φV ^R ₁ , φV ^R ₂ ,..., ΦV ^R _m ,..., ΦV ^R _M ) and vertical reset scanning pulses φV ^S _m (φV ^S ₁ , φV ^{S). _{2, ..., φV S m,}} ..., φV S M) are sequentially outputted. The vertical readout scanning pulse φV ^R _m is applied to the vertical readout line 123 of the corresponding row, and the vertical reset scanning pulse φV ^S _m is applied to the vertical reset line 123 of the corresponding row via the vertical scanning pulse driver 103. Is done.

From the horizontal scanning circuit 105, horizontal readout scanning pulses φH ^R _n (φH ^R ₁ , φH ^R ₂ ,..., ΦH ^R _n ,..., ΦH ^R _N ), horizontal selection scanning pulses φH _n (φH ₁ , φH ₂ ,. _{, φH n, ..., φH n} ) and horizontal reset scanning pulse _{^{φH S n (φH S 1,}} φH S 2, ..., φH S n, ..., φH S n) are sequentially output. Then, the horizontal readout scanning pulse φH ^R _n is applied to the horizontal reset line 122 of the corresponding column, and the horizontal reset scanning pulse φH ^S _n is applied to the horizontal readout line 125 of the corresponding column. Further, the horizontal selection scanning pulse φH _n is applied to the gate of the horizontal selection transistor 104 in the corresponding column.

In the above configuration, in the unit pixel 101, the potential of the FD (floating diffusion), which is a connection portion between the drain of the readout transistor 112 and the gate of the amplification transistor 113, is set near the power supply voltage VDD and the GND level by the reset operation by the reset transistor 114. As a result, the amplification transistor 113 whose source is directly connected to the vertical signal line 121 has selectivity (function of the selection transistor).

Here, when the potential of the FD is set to the GND level when the amplification transistor 113 is not operated, the charge of the FD (here, electrons) flows back to the photodiode 111 through the read transistor 112. Therefore, it is necessary to set the bias potential for resetting the FD (the potential of the vertical reset line 123) to a potential slightly higher than the GND level, for example, about 0.5V to 0.8V.

  From this point of view, the vertical scanning pulse driver 103 for shifting the GND level to about 0.5 V to 0.8 V and applying the level to the vertical reset line 123 between the vertical reset line 123 and the vertical scanning circuit 102 is provided. Is provided. As the vertical scanning pulse driver 103, a CMOS inverter configuration used in a general CMOS logic circuit as shown in FIG. 15 is used. The power supply side circuit end is connected to the power supply line 107 of the power supply voltage VDD, and the GND side circuit end is connected to the output line 108 of the voltage source 106.

  FIG. 16 shows a specific circuit configuration of the voltage source 106. As can be seen from the figure, the voltage source 106 has a voltage regulator configuration comprising an operational amplifier 131, a voltage control MOS transistor 132, and a resistor 133 for flowing an idling current. In the voltage source 106 having such a configuration, since there is a feedback circuit by the operational amplifier 131, the convergence when the voltage is swung is poor, the vibration 133 is easy to vibrate, or the resistor 133 through which an idling current is passed in order to respond at high speed is small. Therefore, power may be consumed wastefully.

JP-A-9-92815

  As described above, in a conventional solid-state imaging device, for example, a CMOS-type imaging device, vertical scanning, which is a level shift circuit, is used to generate a pulse that requires a voltage other than the power supply voltage VDD and the GND level among scanning pulses. Since the configuration using the voltage source 106 having a high current supply capability in addition to the pulse driver 103 is adopted, the circuit scale as the voltage source 106 increases, or the power consumption increases by the amount consumed by the voltage source 106. There was a problem to do.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a level shift circuit capable of performing a desired level shift operation without using a voltage regulator having a high current supply capability and a clock pulse. The object is to provide a solid-state imaging device used as a driver.

The level shift circuit according to the present invention is connected to a first power supply line that supplies one of a ground voltage or a power supply voltage, and has a drain and a gate connected in common to a driver circuit that drives the output line based on an input pulse, At least one MOS transistor connected in series between the second power supply line that supplies the other of the ground voltage or the power supply voltage and the driver circuit, and an intermediate node that is a connection point between the driver circuit and the MOS transistor And a current source for supplying a bias current to the MOS transistor so that its operating point does not enter the subthreshold region, the transistor in the driver circuit to which the MOS transistor is connected, At least one MOS transistor has a substrate potential of the first Is fixed by the potential of the power supply line, said current source, a gate and a drain connected to said first power source line, a source adopts a configuration consisting of the MOS transistors connected to the intermediate node.

  In the solid-state imaging device according to the present invention, the level shift circuit having the above configuration is used as a clock pulse driver, for example, a reset driver for driving a reset line wired in a row unit in an imaging region in which unit pixels are two-dimensionally arranged in a matrix. The composition which was there is taken.

  In the level shift circuit and the solid-state imaging device configured as described above, when a drain voltage exceeding the threshold voltage is applied to a diode-connected MOS transistor, a drain current proportional to the square of the drain voltage is applied to the MOS transistor. Flowing. As a result, the potential at the GND circuit end or the power supply circuit end of the driver circuit is stabilized near the threshold voltage of the MOS transistor. As a result, when one MOS transistor is connected, the low level (hereinafter referred to as “L” level) side from the driver circuit is higher than the GND level by the threshold voltage of the MOS transistor, or high level (hereinafter referred to as “L” level). , “H” level) is output that is lower than the power supply level by the threshold voltage of the MOS transistor.

In addition, the current source connected to the connection point between the driver circuit and the MOS transistor supplies the bias current to the MOS transistor so that the operating point does not enter the sub-threshold region. Since the point is a linear region outside the subthreshold region, the source-drain resistance of the MOS transistor does not increase.

  According to the present invention, at least one MOS transistor having a diode-connected configuration is connected in series with a GND or a power supply to a driver circuit that drives its output line based on an input pulse. Since a desired level shift operation can be realized with a very simple circuit configuration without using a voltage regulator having a large capacity, it is possible to contribute to low power consumption and to suppress an increase in circuit scale.

In addition, since the operating point of the MOS transistor is a linear region outside the subthreshold region and the resistance between the source and drain of the MOS transistor does not increase, even if a large capacitance is added to the load of the driver circuit, When the output changes from the “H” level to the “L” level, the GND side voltage of the driver circuit is not greatly shaken, so that the voltage can be kept stable.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram showing a solid-state image sensor, for example, a CMOS image sensor according to an embodiment of the present invention.

  In FIG. 1, a CMOS image sensor 10 according to this embodiment includes unit pixels 11 that are two-dimensionally arranged in a matrix to form an imaging region, a vertical scanning circuit 12 that is provided outside the imaging region, and a vertical scanning pulse driver. 13, a horizontal selection transistor 14 and a horizontal scanning circuit 15.

  The unit pixel 11 has a four-transistor configuration including a photodiode 21, a readout transistor 22, an amplification transistor 23, a reset transistor 24, and an XY address transistor 25. As each of the pixel transistors 22 to 25, for example, N-ch. MOS transistors are used. Here, for simplification of the drawing, only the unit pixel in the m-th row and the n-th column is shown.

  In the unit pixel 11, the readout transistor 22 has a source connected to the cathode of the photodiode 11 and a drain connected to the gate of the amplification transistor 23. A connection portion between the drain of the read transistor 22 and the gate of the amplification transistor 23 is an FD (Floating Diffusion Amplifier). The amplification transistor 23 has a drain connected to the power supply VDD and a source connected to the vertical signal line 26.

The reset transistor 24 has a drain connected to the vertical reset line 27, a source connected to a connection portion (FD) between the drain of the read transistor 22 and the gate of the amplification transistor 23, and a gate connected to the horizontal reset line 28. The XY address transistor 25 has a gate connected to the vertical read line 29, a drain connected to the horizontal read line 30, and a source connected to the gate of the read transistor 25.

Outside the imaging area, the vertical scanning circuit 12 outputs a vertical readout scanning pulse φV ^R _m (φV ^R ₁ , φV ^R ₂ ,..., ΦV ^R _m ,..., ΦV ^R _M ) and a vertical reset scanning pulse φV ^S _m (φV _{^{S 1, φV S 2, ...}} , φV S m, ..., φV S M) are sequentially outputted. The vertical readout scanning pulse φV ^R _m is applied to the vertical readout line 29 of the corresponding row, and the vertical reset scanning pulse φV ^S _m is applied to the vertical reset line 27 of the corresponding row via the vertical scanning pulse driver 13. Is done.

The vertical scanning pulse driver 13 has a power supply side circuit end connected to the power supply line 31 of the power supply voltage VDD and a GND side circuit end connected to the GND line 32, respectively, and is based on a vertical reset scanning pulse φV ^S _m given from the vertical scanning circuit 12. Then, the vertical reset line 27 is driven. The vertical scanning pulse driver 13 shifts the GND level of the GND line 32 to about 0.5 V to 0.8 V and applies it to the vertical reset line 27 when the vertical reset scanning pulse φV ^S _m is at “L” level. . Details of a specific circuit configuration and the like of the vertical scanning pulse driver 13 will be described later.

From the horizontal scanning circuit 15, horizontal readout scanning pulses φH ^R _n (φH ^R ₁ , φH ^R ₂ ,..., ΦH ^R _n ,..., ΦH ^R _N ), horizontal selection scanning pulses φH _n (φH ₁ , φH ₂ ,. _{, φH n, ..., φH n} ) and horizontal reset scanning pulse _{^{φH S n (φH S 1,}} φH S 2, ..., φH S n, ..., φH S n) are sequentially output. Then, the horizontal read scanning pulse FaiHR n the horizontal reset line 30 of the corresponding column, the horizontal reset scanning pulse .phi.H ^S _n is applied to the corresponding row of horizontal readout line 28.

Further, the horizontal selection scanning pulse φH _n is applied to the gate of the horizontal selection transistor 14 in the corresponding column. The horizontal selection transistor 14 is connected between one end of the vertical signal line 26 and the horizontal signal line 31 for each column.

  Next, the operation of the CMOS image sensor 10 having the above-described configuration will be described using the timing chart of FIG.

When the m-th row is selected by the vertical scanning circuit 12, the vertical readout scanning pulse φV ^R _m-1 and the vertical reset scanning pulse φV ^S _m-1 fall, and instead the vertical readout scanning pulse φV ^R _m and the vertical reset scanning The pulse φV ^S _m rises. At this time, the vertical readout scanning pulses φV ^R _m−1 and φV ^R _m change (swing) between the GND level and the power supply level (VDD), but the vertical reset scanning pulses φV ^S _m−1 and φV ^S _m are It varies between the intermediate level (about 0.5V to 0.8V) and the power supply level.

When the mth row is selected, the horizontal scanning circuit 15 starts horizontal scanning. Accordingly, scanning is sequentially performed from the first pixel (first column) in the m-th row, and when the n-th column is selected, the horizontal selection scanning pulse φH _n and the horizontal readout scanning pulse φH are included in the one-pixel period. ^R _n and horizontal reset scanning pulse φH ^S _n are generated with the phase relationship shown in FIG. That is, the horizontal selection scanning pulse φH _n maintains the power supply level during one pixel period, the horizontal reset scanning pulse φH ^S _n is generated at the beginning of one pixel period, and the horizontal readout scanning pulse φH ^R _n is generated at the middle of one pixel period. To do.

In this manner, when the m-th row is selected by the vertical scanning circuit 12 and the n-th column is selected by the horizontal scanning circuit 15, the horizontal reset scanning pulse φH ^S _n is generated at the beginning of the one pixel period. reset transistor 24 becomes conductive in response to the horizontal reset scanning pulse .phi.H ^S _n. As a result, the FD corresponding to the connection between the drain of the readout transistor 22 and the gate of the amplification transistor 23 in the unit pixel 11 is reset to the level of the vertical reset scanning pulse φV ^S _m , that is, the power supply level. When the FD reset is completed, a pixel reset level signal is output immediately after that.

In the middle of one pixel period, the horizontal readout scanning pulse φH ^R _n is generated, and therefore the horizontal readout scanning pulse φH ^R _n is read out through the XY address transistor 25 which is turned on by the vertical readout scanning pulse φV ^R _m . Given to the gate. As a result, the read transistor 22 becomes conductive, and the signal charge is read from the photodiode 21 to the FD. As a result, the potential of the FD changes from the reset level according to the amount of signal charges. The potential of the FD is amplified by the amplification transistor 23 and output to the vertical signal line 26 as a signal current.

  Next, a specific circuit example of the vertical scanning pulse driver 13 which is a level shift circuit according to the present invention will be described.

  FIG. 3 is a circuit diagram showing a first embodiment of the vertical scanning pulse driver 13. The vertical scanning pulse driver 13 according to the first embodiment is, for example, P-ch. MOS transistor 31 and N-ch. A general CMOS inverter circuit 33 comprising a MOS transistor 32 and having a power supply side circuit end connected to the power supply VDD, and an N-ch. Circuit connected between the GND side circuit end of the CMOS inverter circuit 33 and GND. The MOS transistor 34 is included.

In the vertical scanning pulse driver 13 configured as described above, the common gate connection point G of the CMOS inverter circuit 33 is a circuit input terminal to which the vertical reset scanning pulse φV ^S _m is input, and the vertical common line D has a vertical reset line 27. Will be connected. N-ch. The MOS transistor 34 has a diode connection configuration in which a gate and a drain are connected in common. P-ch. The back gate of the MOS transistor 31 is connected to the power supply VDD, N-ch. The back gates of the MOS transistors 32 and 34 are respectively connected to GND.

Here, the circuit operation of the vertical scanning pulse driver 13 will be described. N-ch. If a drain voltage V _D exceeding the threshold voltage V _T is applied to the MOS transistor 34, a drain current I _D proportional to the square of the drain voltage V _D flows through the transistor 34. That is, assuming that the channel length of the MOS transistor 34 is L, the channel width is W, the gate oxide film thickness is t _ox , the dielectric constant is ε _ox , the relative dielectric constant is ε _o , and the electron mobility is μ, the drain current I _D is represented by the following equation.

I _D = _{[μ · ε ox · ε o ·} W / t ox · L ] - ^{_{[(V D -V T) 2/}} 2 ]

Thus, N-ch. When the drain voltage V _D exceeds the threshold voltage V _T in the MOS transistor 34, a drain current I _D proportional to the square of the drain voltage V _D flows. Therefore, the potential at the GND side circuit end of the CMOS inverter circuit 33 is N-ch. It tends to stabilize near the threshold voltage V _T of the MOS transistor 34. As a result, the CMOS inverter circuit 33 sets the “L” level to N-ch. A scan pulse having a value close to the threshold voltage V _T of the MOS transistor 34 and having the “H” level as the power supply voltage VDD is output.

  As described above, for example, a CMOS inverter circuit 33 having the vertical scanning pulse driver 13 in FIG. 1 as its basic circuit, N and the gate and drain are commonly connected between the GND side circuit end and GND. -Ch. With the circuit configuration in which the MOS transistor 34 is connected, the “L” level can be reduced to N-ch. A scan pulse having a value close to the threshold voltage VT of the MOS transistor 34 can be generated. Incidentally, the threshold voltage VT of the MOS transistor is about 0.6V to 0.7V.

  In the first embodiment described above, N-ch. Is connected between the GND side circuit end of the CMOS inverter circuit 33 and GND. Although the circuit configuration is such that the MOS transistor 34 is connected, as shown in FIG. 5 (A), the P-channel circuit is connected between the GND side circuit end of the CMOS inverter circuit 33 and the GND. A circuit configuration in which the MOS transistor 35 is connected is also possible.

  In the case of the vertical scanning pulse driver 13A shown in FIG. The MOS transistor 35 has a circuit configuration in which the source of the MOS transistor 35 is connected to the GND side circuit end of the CMOS inverter circuit 33, the gate and drain are commonly connected to GND, and the back gate is connected to the power supply VDD.

In the case of this circuit example, since the polarity of the MOS transistor is different from that in the circuit example of FIG. 3, the same operation as in the case of the circuit example is performed. As a result, the “L” level is set to P -Ch. A scan pulse having a value close to the threshold voltage V _T of the MOS transistor 35 and having the “H” level as the power supply voltage VDD can be generated.

  As a modification of the vertical scanning pulse driver 13A, as shown in FIG. It is also possible to adopt a circuit configuration in which the N-well corresponding to the back gate of the MOS transistor 35 is connected to its own source instead of the power supply VDD. In the case of this vertical scanning pulse driver 13B, the basic operation is exactly the same as in the case of the circuit examples of FIGS. 3 and 5A.

  However, in the case of the vertical scanning pulse driver 13B, P-ch. Due to the back gate effect of the MOS transistor 35, the threshold voltage of the MOS transistor 35 becomes lower than in the case of the circuit example of FIG. As a result, the “L” level of the scanning pulse output from the vertical scanning pulse driver 13B is lower than the “L” level of the scanning pulse output from the vertical scanning pulse driver 13A. Therefore, this is an effective circuit example when it is desired to set the “L” level of the scan pulse low.

  In the above embodiment, N-ch. Is used as the four pixel transistors 22 to 25 constituting the unit pixel 11. Although the case where the present invention is applied to the CMOS image sensor 10 using MOS transistors has been described as an example, P-ch. The present invention can be similarly applied to a CMOS image sensor using a MOS transistor.

  In this case, the “H” level of the scan pulse is symmetrical to the circuit configuration shown in FIGS. 3 and 5A and 5B when the “L” level of the scan pulse is set to a voltage slightly higher than the GND level. The circuit configuration is such that the level is set slightly lower than the power supply voltage VDD. Specifically, as shown in FIGS. 6A to 6C, N-ch. Or P-ch. The MOS transistor is connected between the power supply VDD and the power supply side circuit end of the CMOS inverter circuit 33.

  6A and 6B show N-ch. FIG. 6C shows a circuit example when the MOS transistor 36 of FIG. The circuit examples when the MOS transistors 37 are connected are shown.

  N-ch. In the case of the vertical scanning pulse drivers 13C (A) and 13D (B) to which the MOS transistors 36 are connected, the gate and drain are commonly connected to the power supply VDD, and the source is connected to the power supply side circuit end of the CMOS inverter circuit 33. . In this case, N-ch. Depending on whether the P-well corresponding to the back gate of the MOS transistor 36 is connected to its own source (A) or connected to GND (B), the threshold voltage can be finely controlled.

  On the other hand, P-ch. In the case of the vertical scanning pulse driver 13E (C) for connecting the MOS transistor 37, the source is connected to the power supply VDD, and the gate and the drain are commonly connected to the power supply side circuit end of the CMOS inverter circuit 33. .

  Of the first embodiment described above and its modifications, the scanning pulse “L” level is slightly higher than the GND level, that is, in the case of the circuit examples of FIGS. 3 and 5A and 5B. The input / output waveforms are shown in FIG. In the case of the circuit examples of FIGS. 6A to 6C, the “H” level of the output pulse has a waveform lower than the power supply voltage VDD by a value closer to the threshold voltage VT of the MOS transistor.

In the case of the circuit examples of FIGS. 3 and 5A and 5B, the output pulse maintains the same phase relationship as that of a normal inverter with respect to the input pulse, and the “L” level is higher than the GND level. It is possible to generate a target scan pulse that increases by a value close to the threshold voltage V _T of the MOS transistor connected between the GND side circuit end of the inverter circuit 33 and GND.

  Here, as apparent from the waveform diagram of FIG. 7, the output pulse falls a little late when the output waveform falls and approaches the “L” level. This is because the operating point of the MOS transistor connected between the end and GND enters the subthreshold region, and the resistance between the source and drain of the MOS transistor becomes extremely high.

  FIG. 8 is a circuit diagram showing a second embodiment of the vertical scanning pulse driver. The vertical scanning pulse driver 13 'according to the second embodiment is, for example, P-ch. MOS transistor 41 and N-ch. A general CMOS inverter circuit 43 comprising a MOS transistor 42 and having a power supply side circuit end connected to the power supply VDD, and an N-ch. Circuit connected between the GND side circuit end of the CMOS inverter circuit 43 and GND. MOS transistor 44, CMOS inverter circuit 43 and N-ch. N-ch. Connected between the connection point of the MOS transistor 44 and the power supply VDD. The MOS transistor 45 is included.

  In the vertical scanning pulse driver 13 'configured as described above, N-ch. MOS transistor 45 operates as a current source, and N-ch. A bias current is supplied to the MOS transistor 44 such that the operating point of the MOS transistor 44 enters the sub-threshold region and the source-drain resistance does not increase. As a result, N-ch. Since the operating point of the MOS transistor 44 is a linear region outside the sub-threshold region, the N-ch. The resistance between the source and drain of the MOS transistor 44 does not increase.

  As a result, even if a large capacitance is added to the load of the CMOS inverter circuit 43, N− is low in resistance between the source and drain when the output of the CMOS inverter circuit 43 changes from “H” level to “L” level. ch. The GND voltage of the CMOS inverter circuit 43 is not greatly shaken by the MOS transistor 44, and is thus kept stable.

  The input / output waveforms of the vertical scanning pulse driver 13 'are shown in FIG. While maintaining the same phase relationship between the input pulse and the output pulse as that of a normal inverter, the “L” level is higher than the GND level, and the N-ch. It is possible to generate a target scan pulse that increases by a value close to the threshold voltage VT of the MOS transistor 44.

  Moreover, N-ch. By the action of the MOS transistor 45, N-ch. The operating point of the MOS transistor 44 becomes a linear region outside the sub-threshold region, and N-ch. Since the resistance between the source and drain of the MOS transistor 44 does not increase, the delay of the pulse response can be greatly improved, as is apparent from the comparison of the waveform diagrams of FIGS. As a result, it is possible to realize the rising and falling speed equivalent to that of a driver having only a normal inverter.

  The vertical scanning pulse driver 13 'according to the second embodiment described above has a circuit configuration corresponding to the circuit example of FIG. 3 in the first embodiment, but based on the same operating principle as described above, FIG. Of course, a circuit configuration corresponding to each of the circuit examples (A) and (B) may be employed.

In this embodiment, a single N-ch. Is connected between the GND side circuit end of the CMOS inverter circuit 43 and the GND. The MOS transistor 44 is connected, but, as shown in FIG. The vertical scanning pulse driver 13′A may be configured to be connected to the MOS transistors 44 ₁ , 44 ₂ or more.

  FIG. 11 is a circuit diagram showing another modification of the vertical scanning pulse driver according to the second embodiment. A vertical scanning pulse driver 13'B according to another modified example includes P-ch. A circuit configuration when applied to a CMOS type image pickup device using a MOS transistor is adopted. In the vertical scanning pulse driver 13'A, the "L" level of the output pulse (scanning pulse) is set to the GND level, and the "H" level side is set to a voltage slightly lower than the power supply voltage VDD.

  Specifically, with respect to the CMOS inverter circuit 43, P-ch., Whose gate and drain are commonly connected between the power supply side circuit end and the power supply VDD. The MOS transistor 46 is connected to the CMOS inverter circuit 43 and the P-ch. Between the connection point of the MOS transistor 46 and GND, P-ch. The circuit configuration is such that the MOS transistor 47 is connected.

  In the vertical scanning pulse driver 13'B configured as described above, P-ch. MOS transistor 47 operates as a current source, and P-ch. A bias current is supplied to the MOS transistor 46 so that the operating point of the MOS transistor 46 does not enter the subthreshold region and the source-drain resistance does not increase. As a result, the response delay of the output pulse can be greatly improved, and the rise and fall speeds equivalent to those of a driver having only an ordinary inverter can be realized.

  The vertical scanning pulse driver 13'B according to the present modification has a circuit configuration corresponding to the circuit example of FIG. 6C in the first embodiment. Of course, a circuit configuration corresponding to each circuit example of 6 (A) and (B) can be adopted.

  In the first and second embodiments described above and the modifications thereof, in the CMOS image sensor 10 having the configuration shown in FIG. 1, the entire circuit of the vertical scanning pulse driver 13 is arranged for each vertical reset line 27 wired in units of rows. Although arranged, it is not necessarily limited to this configuration.

As an example, when taken as an example of the circuit configuration of FIG. 8 as a vertical scanning pulse driver 13, as shown in FIG. 12, the vertical reset line _{27 1, 27 2, ......,} CMOS inverter circuits each 27 _M 43 ₁ , 43 ₂ ,..., 43 _M are arranged, while N-ch., Whose gate and drain are connected in common between each GND side circuit end of the CMOS inverter circuit and GND. MOS transistor 44 is connected, and CMOS inverter circuits 43 ₁ , 43 ₂ ,..., 43 _M and N-ch. N-ch. Operating as a current source between the connection point of the MOS transistor 44 and the power supply VDD. The MOS transistor 45 is connected.

  That is, in particular, in an XY address type image pickup device represented by a CMOS type image pickup device, scanning pulses are sequentially output, so that only one or two of the M drivers are applied. Only one or two of the M drivers operate simultaneously. Therefore, N-ch. MOS transistor 44 and N-ch. The number or size of the MOS transistors 45 corresponding to the MOS transistors 45 may be arranged.

According to the arrangement, M-number of CMOS inverter circuits 43 _1, 43 _2, ..., with respect to 43 _M, N-ch. Since only one MOS transistor 44 and 45 is required to be connected, the circuit configuration can be greatly simplified, and the increase in circuit scale can be suppressed.

In this example, N-ch. Although only one MOS transistor 44 and 45 is connected, M CMOS inverter circuits 43 ₁ , 43 ₂ ,..., 43 _M are divided into a plurality of blocks, and N-ch. It is also possible to connect MOS transistors 44 and 45.

  Further, the case where the circuit configuration of FIG. 8 is taken as an example of the vertical scanning pulse driver 13 has been described. However, the circuit configuration of FIG. Needless to say, the present invention can be similarly applied to the vertical scanning pulse drivers having the circuit configurations shown in FIGS. 6 (A) to 6 (C).

  Up to this point, in the level shift circuit according to the present invention, in the CMOS type image sensor, the scanning pulse in which the “H” level is the power supply voltage VDD and the “L” level side is slightly higher than the GND level, or “L” Although the case where the level is the GND level and the vertical scanning pulse driver 13 for generating the scanning pulse in which the “H” level side is slightly lower than the power supply voltage VDD has been described as an example, the present invention is limited to this application example. is not.

  That is, the present invention can be applied to all clock pulse drivers that generate an output pulse that takes a predetermined level between the power supply voltage VDD and the GND level based on a binary input pulse.

For example, in the examples so far, only one MOS transistor having a diode connection configuration responsible for level shift is connected, and the threshold voltage of the MOS transistor is higher than the GND level by the threshold voltage V _{T of the} MOS transistor or higher than the power supply voltage VDD. Although a pulse having a level lower by V _T is generated, by connecting a plurality of MOS transistors responsible for level shifting in series, a level shift that is an integral multiple of the threshold voltage V _T of the MOS transistor, or power supply voltage VDD and GND levels It is also possible to set an intermediate level of approximately ½ between the two.

  Further, not only the level shift of only one of the “L” level side / “H” level side but also the level shift of both the “L” level side / “H” level side can be performed simultaneously. This is shown in FIG. 13 as a third embodiment.

  As is clear from FIG. MOS transistor 51 and N-ch. With respect to a general CMOS inverter circuit 53 comprising a MOS transistor 52, a P-ch. The MOS transistor 54 is connected to an N-ch. The MOS transistors 55 are connected to each other.

  Accordingly, it is possible to generate a pulse whose “H” level side is lower than the power supply voltage VDD by the threshold voltage of the MOS transistor 54 and whose “L” level side is higher than the GND level by the threshold voltage of the MOS transistor 55. Also in this case, by applying the technique described in FIGS. 8 and 11, that is, the technique for supplying the bias current from the current source to the MOS transistors 54 and 55, the speed of the transient response of the output pulse can be increased. it can.

It is a schematic block diagram which shows the CMOS type image pick-up element which concerns on one Embodiment of this invention. 6 is a timing chart for explaining the operation of the CMOS image sensor according to the embodiment. 1 is a circuit diagram illustrating a level shift circuit according to a first embodiment. FIG. It is explanatory drawing of the current source in the level shift circuit which concerns on 1st Example. It is a circuit diagram which shows the level shift circuit which concerns on the modification of 1st Example. FIG. 10 is a circuit diagram showing a level shift circuit according to still another modification of the first embodiment. It is an input / output waveform diagram of the level shift circuit according to the first embodiment. It is a circuit diagram which shows the level shift circuit which concerns on 2nd Example. It is an input / output waveform diagram of the level shift circuit according to the second embodiment. It is a circuit diagram which shows the level shift circuit which concerns on the modification of 2nd Example. It is a circuit diagram which shows the level shift circuit which concerns on the other modification of 2nd Example. It is a circuit diagram which shows an example of a structure in the case of using the level shift circuit which concerns on 2nd Example. It is a circuit diagram which shows the level shift circuit which concerns on 3rd Example. It is a schematic block diagram which shows the CMOS type image pick-up element to which the prior art was applied. It is a circuit diagram of the driver of a CMOS inverter structure. It is a circuit diagram which shows the circuit structure of a voltage source (voltage regulator).

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... CMOS type image pick-up element, 11 ... Unit pixel, 12 ... Vertical scanning circuit, 13, 13A-13E, 13 ', 13' ... Vertical scanning pulse driver, 14 ... Horizontal selection transistor, 15 ... Horizontal scanning circuit, 21 ... Photo Diode, 22 ... Read transistor, 23 ... Amplification transistor, 24 ... Reset transistor, 25 ... XY address transistor, 33, 43, 53 ... CMOS inverter circuit

Claims (6)

A driver circuit connected to a first power supply line for supplying one of a ground voltage or a power supply voltage and driving the output line based on an input pulse;
At least one MOS transistor having a drain and a gate connected in common and connected in series between a second power supply line supplying the other of the ground voltage or the power supply voltage and the driver circuit ;
A current source connected to an intermediate node that is a connection point between the driver circuit and the MOS transistor, and supplying a bias current to the MOS transistor so that the operating point does not enter a sub-threshold region ;
The transistor in the driver circuit to which the MOS transistor is connected and the at least one MOS transistor have their substrate potential fixed at the potential of the second power supply line,
The current source is a level shift circuit comprising a MOS transistor in which a gate and a drain are connected to the first power supply line and a source is connected to the intermediate node . The driver circuit comprises a CMOS inverter circuit
Level shift circuit 請 Motomeko 1 wherein. An imaging region in which unit pixels are arranged in a matrix; and
A driver circuit that is provided in units of rows in the imaging region, is connected to a first power supply line that supplies one of a ground voltage or a power supply voltage, and drives unit pixels in the imaging region in units of rows based on an input pulse;
At least one MOS transistor having a drain and a gate connected in common and connected in series between a second power supply line supplying the other of the ground voltage or the power supply voltage and the driver circuit ;
A current source connected to an intermediate node that is a connection point between the driver circuit and the MOS transistor, and supplying a bias current to the MOS transistor so that the operating point does not enter a sub-threshold region ;
The transistor in the driver circuit to which the MOS transistor is connected and the at least one MOS transistor have their substrate potential fixed at the potential of the second power supply line,
The current source is a solid-state imaging device comprising a MOS transistor in which a gate and a drain are connected to the first power supply line and a source is connected to the intermediate node . A plurality of the at least one MOS transistor and the current source connected to the intermediate node that is a connection point of the at least one MOS transistor and the driver circuit are provided for each row unit of the imaging region. Commonly connected to the driver circuit
The solid-state imaging device according to claim 3 . The output line of the driver circuit is a vertical reset line for resetting unit pixels arranged two-dimensionally in a matrix in units of rows,
The input pulse is a vertical reset scanning pulse that is sequentially output from a vertical scanning circuit that selects the unit pixel in units of rows.
The solid-state image sensor according to claim 3 or 4 . The driver circuit is composed of a CMOS inverter circuit.
The solid-state imaging device according to claim 5.

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