JP4008434B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device, and more particularly to a MOS image sensor in which a photodiode and a MOS transistor are provided for each pixel.

Solid-state imaging devices are widely used in various fields as basic elements for performing image input processing. Currently, solid-state imaging devices that are generally used are roughly classified into CCD image sensors and MOS image sensors. The principle of the MOS image sensor is to provide a photodiode functioning as a light receiving element for each pixel and amplify the output of the photodiode with a MOS transistor. In particular, a CMOS image sensor using a CMOS circuit is Therefore, it is considered promising as a small solid-state imaging device driven with low power consumption. For example, Patent Documents 1 and 2 below disclose operating circuits for MOS image sensors.
Japanese Patent Laid-Open No. 10-322140 JP 2001-268443 A

  In a solid-state imaging device using a photodiode, one end of the photodiode is a fixed end fixed at a constant potential, and the other end is a variation end where potential variation occurs, and the amount of accumulated charge at the variation end is changed as a potential variation at regular intervals. By reading with the MOS transistor, the amount of light received by the photodiode is extracted as an electric signal. Therefore, the dynamic range of the amount of received light that can be detected by each photodiode is limited within the allowable range of potential fluctuation at the fluctuation end. For this reason, when intense light exceeding the dynamic range is irradiated, the output signal is saturated and the correct amount of received light cannot be detected. This phenomenon is called “white jump”.

  In order to prevent such “overexposure” phenomenon, it is necessary to devise a technique for expanding the dynamic range of the received light amount that can be detected. However, the conventional device requires a special circuit configuration or requires a large memory outside, so that the entire apparatus becomes complicated and the cost increases.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a solid-state imaging device that can widen the dynamic range of the amount of received light that can be detected with the simplest possible configuration.

(1) According to a first aspect of the present invention, in a solid-state imaging device configured by arranging a large number of pixels having a function of outputting an electrical signal corresponding to the amount of received light,
Individual pixels,
A photodiode whose one end is fixed at a constant potential and whose other end functions as a variation point P that generates a potential variation according to the amount of received light;
A resetting MOS transistor for resetting the variation point P to a predetermined potential;
A read MOS transistor for reading the potential of the fluctuation point P to the outside;
Further comprising
A reset means for periodically resetting each pixel at a predetermined period T so that the variation point P becomes a predetermined initial potential higher than a constant potential by giving a signal to the reset MOS transistor ;
By applying a signal to the readout MOS transistor, the potential at the variation point P immediately before the periodic reset by the resetting means is read from each pixel, and the difference between the read potential and the initial potential is an electric quantity indicating the amount of light received for the pixel. A potential reading means for outputting as a signal;
Provided,
The potential reading means has a function of reading the potential at the variation point P at the intermediate point of the predetermined period T as an intermediate potential,
Reset means, when the intermediate potential is lower than a predetermined reference potential, as the potential variation point P becomes the reference potential, we have rows intermediate reset at an intermediate point, when the intermediate potential is higher than the reference potential, A function of performing an intermediate reset at an intermediate time is provided so that the potential of the fluctuation point P becomes an intermediate potential .

(2) According to a second aspect of the present invention, in the solid-state imaging device according to the first aspect described above,
The potential reading means reads the potential at the fluctuation point P at the time of periodic reset by the resetting means, and uses this as the initial potential value.

(3) According to a third aspect of the present invention, in the solid-state imaging device according to the first or second aspect described above,
The reset means performs feedback control based on the read value by the potential read means, so that the change point P is reset to the initial potential, the reference potential, or the intermediate potential.

(4) According to a fourth aspect of the present invention, in the solid-state imaging device according to the third aspect described above,
When the reset means has an intermediate potential less than the reference potential, the reset means performs feedback control so that the difference between the read value by the potential read means and the reference value set corresponding to the reference potential is zero. When the reset is performed and the intermediate potential is equal to or higher than the reference potential, the intermediate reset is performed by performing feedback control so that the difference between the read value immediately before the intermediate reset by the potential reading means and the read value at the intermediate reset is zero. Is to do.

(5) According to a fifth aspect of the present invention, in the solid-state imaging device according to the first to fourth aspects described above,
A plurality of intermediate time points are determined within a predetermined period T, and different reference potentials are set for each intermediate time point so that lower reference potentials are set for subsequent intermediate time points.

(6) According to a sixth aspect of the present invention, in a solid-state imaging device configured by arranging a large number of pixels having a function of outputting an electrical signal according to the amount of received light.
Individual pixels,
A photodiode whose one end is fixed at a constant potential and whose other end functions as a variation point P that generates a potential variation according to the amount of received light;
A detection MOS transistor having one end connected to the fluctuation point P and the other end serving as a detection point Q;
A resetting MOS transistor for resetting the variation point P to a predetermined potential;
A reading MOS transistor for reading out the potential of the detection point Q to the outside;
Further comprising
By controlling the gate voltage of the detection MOS transistor, for each pixel, the detection MOS transistor is periodically temporarily turned on at a predetermined cycle T, and the negative charge accumulated at the variation point P is transferred to the detection point Q. Charge transfer means for performing periodic transfer processing, and
Reset means for performing a primary reset on each pixel by giving a signal to the reset MOS transistor so that the detection point Q becomes a predetermined initial potential higher than a constant potential at an intermediate time point of the predetermined period T;
By applying a signal to the reading MOS transistor, the potential at the detection point Q at the time when the periodic transfer processing by the charge transfer means is performed is read from each pixel, and the difference between the read potential and the initial potential is related to the pixel. A potential reading means for outputting an electric signal indicating the amount of received light;
Provided,
The charge transfer means has a function of performing an intermediate transfer process for transferring negative charges accumulated at the fluctuation point P to the detection point Q immediately after the primary reset,
The potential reading means has a function of reading the potential at the detection point Q at the time when the intermediate transfer process is performed as an intermediate potential,
Reset means, when the intermediate potential is lower than a predetermined reference potential, as the potential of the detecting point Q becomes a reference potential, have rows of secondary reset immediately after the intermediate transfer process, the intermediate potential is a reference potential or In some cases, a secondary reset function is provided immediately after the intermediate transfer process so that the potential at the detection point Q becomes an intermediate potential .

(7) According to a seventh aspect of the present invention, in the solid-state imaging device according to the sixth aspect described above,
The potential reading means reads the potential at the detection point Q at the time of the primary reset by the reset means and uses this as the initial potential value.

(8) An eighth aspect of the present invention is the solid-state imaging device according to the sixth or seventh aspect described above,
The reset means performs feedback control based on the read value by the potential read means, thereby resetting the detection point Q to the initial potential, the reference potential, or the intermediate potential.

(9) According to a ninth aspect of the present invention, in the solid-state imaging device according to the eighth aspect described above,
When the reset means has an intermediate potential less than the reference potential, the reset means performs feedback control so that the difference between the read value by the potential read means and the reference value set corresponding to the reference potential is zero. When the secondary reset is performed and the intermediate potential is equal to or higher than the reference potential, feedback control is performed so that the difference between the read value immediately before the secondary reset by the potential reading means and the read value at the secondary reset becomes zero. Is used to perform secondary reset.

(10) A tenth aspect of the present invention is the solid-state imaging device according to the sixth to ninth aspects described above,
A plurality of intermediate time points are determined within a predetermined period T, and different reference potentials are set for each intermediate time point so that lower reference potentials are set in subsequent intermediate time points, and the primary reset is performed only at the first intermediate time point. In the second and subsequent intermediate points, secondary reset is performed as necessary based on the read result of the intermediate potential.

(11) An eleventh aspect of the present invention is the solid-state imaging device according to the first to tenth aspects described above,
The potential reading means includes a first MOS transistor and a second MOS transistor connected in series to each other, and a current source for causing a current to flow through a current path formed by the pair of MOS transistors, The change point P or the detection point Q is connected to the gate of the first MOS transistor, and the selection signal for selecting the read operation for the pixel is applied to the gate of the second MOS transistor so that the reading is performed. .

  With the solid-state imaging device according to the present invention, the dynamic range of the amount of received light that can be detected can be expanded with a simple configuration.

  Hereinafter, the present invention will be described based on the illustrated embodiments.

<<< §1. Conventional general 3-transistor type solid-state imaging device >>
First, for convenience of explanation, a circuit for one pixel used in a conventional general MOS image sensor and its operation will be described based on the circuit diagram of FIG. The illustrated circuit is an example of a so-called “3-transistor type” solid-state imaging device in which a circuit for one pixel is configured by three MOS transistors.

  As shown in the figure, this circuit includes a photodiode PD and three N-type MOS transistors. The ▽ mark in the figure indicates the ground potential, and the opposite end of the photodiode PD is grounded. On the other hand, the forward end of the photodiode PD is connected to one end of the MOS transistor T1 through the point P. The other end of the MOS transistor T1 is connected to the power supply line VDD, and the gate is connected to the reset signal line RST. A capacitive element C1 indicated by a broken line in the figure indicates a parasitic capacitance of the photodiode PD. One end of the photodiode PD is fixed at a constant potential (in this example, the ground potential), but the other end causes a potential fluctuation according to the amount of charge stored in the capacitive element C1. Here, the illustrated point P is referred to as a “variable point P”. As will be described later, the potential at the variation point P varies according to the amount of light received by the photodiode PD.

  Now, when a reset signal is given from the reset signal line RST to the gate of the MOS transistor T1, and the transistor is temporarily turned on, the potential of the variation point P becomes a value almost close to the power supply voltage VDD. This is a state in which this pixel is initialized. Here, the potential at the variation point P in this state is referred to as an initial potential V0. If the threshold voltage of the MOS transistor T1 is Vth, the initial potential V0 = VDD−Vth. Here, since the initial potential V0 is higher than the ground potential, a reverse bias is applied to the photodiode PD, and charges corresponding to the potential of the variation point P are accumulated in the capacitive element C1.

  Thus, when the reset for initialization is completed, the MOS transistor T1 is turned off, and the process of detecting the amount of received light starts. That is, when the transistor T1 is turned off, discharging of the charge accumulated in the photodiode PD (capacitance element C1) starts. At this time, the amount of charge to be discharged depends on the amount of light applied to the photodiode PD. That is, the greater the amount of light received by the photodiode PD, the greater the amount of charge that is discharged, and the accumulated charge decreases. When the accumulated charge in the photodiode PD decreases, the potential at the fluctuation point P also decreases. Eventually, the amount of light received by the photodiode PD can be recognized by measuring how much the potential at the variation point P has decreased from the initial potential V0 when a certain time has elapsed after the reset for initialization described above.

  The MOS transistors T2 and T3 are components that function as potential reading means for reading the potential at the variation point P. As shown in the figure, the transistors T2 and T3 are connected in series with each other, and a current path from the power supply line VDD to the signal output line OUT is formed by the series path including the pair of transistors. In order to read the potential at the variation point P to the outside by this potential reading means, a selection signal for selecting a reading operation for the pixel may be given to the selection signal line SEL. This selection signal is given to the gate of the transistor T2, and this transistor T2 is turned on. On the other hand, the potential of the variation point P is applied to the gate of the transistor T3. Therefore, as shown in the figure, if the current source J is connected to the signal output line OUT, an amount of current corresponding to the potential at the variation point P flows through the signal output line OUT. Specifically, if the amount of light received by the photodiode PD is small, the potential at the variation point P becomes high, and the amount of current flowing through the signal output line OUT increases, but if the amount of light received by the photodiode PD is large, the variation point P , And the amount of current flowing through the signal output line OUT decreases.

  FIG. 2 is a timing chart showing the received light amount detection operation by the circuit shown in FIG. The upper chart shows the potential at the fluctuation point P, the middle chart shows the voltage of the reset signal line RST, and the lower chart shows the voltage of the selection signal line SEL. As shown in the figure, a reset pulse is applied to the reset signal line RST every predetermined period T, and the MOS transistor T1 is turned on only for a period corresponding to the width of this pulse. As a result, the changing point P is reset so as to become the initial voltage V0 every period T. Here, the timing at which this reset pulse is given is called t1. As shown in FIG. 2, a period from one timing t1 to the next timing t1 corresponds to a predetermined period T.

  In the case of a general moving image capturing solid-state imaging device, the period T is set to 1/30 seconds (about 33 msec). On the other hand, since the width of the reset pulse (middle stage in FIG. 2) given at timing t1 and the selection pulse given at timing t0 & t1 (lower stage in FIG. 2) is on the order of μsec, on the real time axis, the period T Compared to the pulse, the pulse has a very short width. However, on the timing chart shown in the figure, for convenience of explanation, these pulses are shown on a scale that ignores the original pulse width on the real time axis.

  As described above, when the reset is performed at the timing t1, the potential at the variation point P rises to the initial potential V0, but thereafter, the potential at the variation point P gradually decreases due to the discharge of the accumulated charge. The upper graph G1 in FIG. 2 is a graph showing such a potential drop. As described above, the level of this potential drop changes according to the amount of light received by the photodiode PD. When weak light is irradiated, the slope of the graph G1 becomes gentle, but strong light is irradiated. If so, the slope of the graph G1 is steep. Eventually, when the period T elapses, a reset pulse is again applied at the timing t1, and the potential at the variation point P rises to the initial potential V0.

  Therefore, the potential at the variation point P is read at the timing t0 immediately before the reset. In the illustrated example, the potential at the variation point P has dropped from the initial potential V0 to V1 within the period T, and the potential at the variation point P read at timing t0 becomes V1. Here, the potential difference ΔV = V0−V1 is a detection value indicating the amount of light received during the period T. As shown in the lower part of FIG. 2, a selection pulse is given on the selection signal line SEL at timing t0. This selection pulse causes the MOS transistor T2 to be turned on, and the variation point P immediately before the resetting. This is because information indicating the potential (electric signal corresponding to the potential at the fluctuation point P) is read onto the signal output line OUT. As described above, “reading the potential at the fluctuation point P” means that an electric signal corresponding to the potential at the fluctuation point P is obtained on the signal output line OUT. In practice, a voltage value related to the potential of the variation point P is output to the outside.

  Incidentally, the width of the selection pulse on the selection signal line SEL reaches two timings t0 and t1, as shown in the lower part of FIG. 2. This is because the potential V1 immediately before the reset is read at the timing t0, and the timing is changed. This is because the reset potential V0 is read at t1. If the potential is read at both timings, a detection value ΔV indicating the amount of received light can be obtained from the difference V0−V1 between the two potentials. Actually, the reading of the potential at the variation point P is performed at a predetermined time point within the range of the pulse width indicated as the timing t0 or the pulse width indicated as the timing t1, but here, for convenience of illustration, The following description will be given on the assumption that the potential is read out at the rising edge of the pulse.

  As described above, the circuit shown in FIG. 1 is a circuit related to one pixel, and an actual solid-state imaging device is configured by arranging a large number of such circuits for one pixel so as to form a matrix vertically and horizontally. The Here, the reset signal line RST and the selection signal line SEL function as a common signal line for a large number of pixels arranged adjacent to each other in the row direction (left-right direction in the drawing), and the timing chart of FIG. The operations indicated by are simultaneously executed. On the other hand, the signal output line OUT functions as a common signal line for a large number of pixels arranged adjacent to each other in the column direction (vertical direction in the figure), and the pixels for one column share the same signal output line OUT. Become. However, since each row is driven such that the phase of the period T shown in FIG. 2 is slightly shifted, the output of the pixels in the first row and the second row are placed on the same signal output line OUT. The detection value relating to the pixels in each row is obtained as a time-series signal, such as the output of the pixels in this row, the output of the pixels in the third row, and so on.

  Next, the reason why the “overexposure” phenomenon occurs in the solid-state imaging device including the pixels having the configuration shown in FIG. 1 will be described with reference to the timing chart of FIG. The timing chart of FIG. 3 shows the potential fluctuation at the fluctuation point P in the period T and the states of the reset signal line RST and the selection signal line SEL, as in the timing chart of FIG. However, a total of six graphs G1 to G6 are shown in the upper graph. These graphs show the results when the photodiodes PD are irradiated with light having six different intensities. That is, the graph G1 shows the potential fluctuation at the fluctuation point P when the weakest light is irradiated, and the graph G6 shows the potential fluctuation at the fluctuation point P when the strongest light is irradiated. As described above, the intensity of light applied to the photodiode PD affects the slope of the graph. When weak light is applied, a gentle slope graph G1 is obtained. When irradiated, a steep slope graph G6 is obtained.

  Focusing on the potential of the variation point P read at timing t0 in each of these six cases, as shown in the figure, the potentials V1, V2, and V3 are read for the graphs G1, G2, and G3, respectively. (Points V1, V2, and V3 indicated by black circles indicate points on the graph having the potentials V1, V2, and V3, respectively, and the same applies to the graphs G4, G5, and G6. ) Is read out. That is, this solid-state imaging device can detect the correct amount of received light up to about the light of the graph G3, but beyond that, the detected value becomes saturated at the maximum intensity, and the correct amount of received light is detected. Can not do. In other words, the upper limit of the dynamic range of the solid-state imaging device is up to the light of the graph G3.

  Various methods are known as methods for expanding the dynamic range of a solid-state imaging device, but each requires a special circuit configuration or requires a large external memory, which complicates the entire device. There is a problem that the cost becomes high. The aim of the present invention is to widen the dynamic range of the amount of received light that can be detected with the simplest possible structure.

<<< §2. Three-transistor solid-state imaging device according to the present invention >>
Subsequently, an embodiment in which the present invention is applied to the above-described three-transistor solid-state imaging device will be described. FIG. 4 is a circuit diagram showing a circuit for one pixel of the three-transistor solid-state imaging device according to the present invention. The basic configuration of the circuit shown in FIG. 4 is substantially the same as the basic configuration of the circuit shown in FIG. The difference between the two is that in the case of the circuit shown in FIG. 1, the power supply line VDD is connected to both the MOS transistors T1 and T3, whereas in the case of the circuit shown in FIG. 4, the power supply line VDD is only the MOS transistor T3. And a separate reset voltage setting line L1 is connected to the MOS transistor T1. The power supply line VDD is a signal line that always supplies a constant voltage, whereas the reset voltage setting line L1 has a function of supplying an arbitrary voltage set by a control circuit (not shown).

  Thus, by providing the reset voltage setting line L1 separately, not only the changing point P is reset to the initial voltage V0, but also a reset to an arbitrary voltage is possible. The feature of the present invention is that an intermediate reset is performed as necessary at an intermediate time point of the period T by using such a function of the reset voltage setting line L1. Hereinafter, the principle of the present invention will be described with reference to the timing charts of FIGS. Similar to the timing chart shown in FIG. 2 or FIG. 3, these timing charts show the potential fluctuation at the fluctuation point P in the period T and the states of the reset signal line RST and the selection signal line SEL.

  First, the timing chart of FIG. 5 will be described. The upper graph G1 shows the potential fluctuation at the changing point P when the photodiode PD is irradiated with relatively weak light, and is the same as the upper graph G1 in FIG. Similar to the conventional apparatus, the potential of the fluctuation point P is gradually lowered from V0 to V1 after a reset pulse (timing t1) is given on the reset signal line RST at a predetermined period T. In addition, a selection pulse (timing t0 & t1) is applied to the selection signal line SEL at a predetermined cycle T, and the difference between the potential V1 read at timing t0 and the potential V0 read at timing t1 The point of detecting the amount of received light is the same as in the conventional apparatus.

  However, in this embodiment, the potential at the fluctuation point P is read even at an intermediate point in the period T. Specifically, as shown in the lower chart of FIG. 5, after the reset at the timing t1, the selection pulse (timing t2 & t3) is also generated on the selection signal line SEL even at the intermediate point where the intermediate time M1 (M1 <T) has elapsed. ) And the process of reading the potential of the variation point P at this intermediate time point is performed. In the illustrated example, at the timing t2, the potential V1m corresponding to the point V1m on the graph G1 is read. Here, the potential of the variation point P read out at the intermediate time point is referred to as “intermediate potential”. In the example of FIG. 5, the potential V1m is read as an intermediate potential.

  If only the intermediate potential is read, the selection pulse on the selection signal line SEL is sufficient only at the timing t2. However, as shown in FIG. Yes. As will be described later, this is in consideration of convenience when an intermediate reset is performed at timing t3.

  As described above, the reason why the intermediate potential V1m is read at the intermediate time point is to determine whether the intermediate potential V1m is larger or smaller than the predetermined reference potential Vx. The reference potential Vx is a potential set in advance as a predetermined value lower than the initial potential V0. In the example shown in the figure, Vx = 1/2 · V0 is set, and the point Vx indicated by a cross is a point on the graph having the reference potential Vx at the timing t2. In the case of the graph G1 shown in FIG. 5, the intermediate potential V1m is larger than the reference potential Vx. On the other hand, in the case of the graph G2 shown in FIG. 6, the intermediate potential V2m is equal to the reference potential Vx. In the case of the graph G3 shown in FIG. 7 or the graph G4 shown in FIG. Is smaller than the reference potential Vx.

  In the embodiment shown here, when the intermediate potential is read at the intermediate time point and the read intermediate potential is equal to or higher than the reference potential Vx, nothing is done at this intermediate time point, and the conventional method described in §1 is performed. The amount of received light is detected by the same method as in the example. For example, in the case of the graph G1 shown in FIG. 5, since the intermediate potential V1m is larger than the reference potential Vx, nothing is performed at the intermediate time point, and the process of reading the potential at the variation point P again at the timing t0 when the period T ends is performed. . As described in section 1 above, the difference between the potential V1 read at timing t0 and the initial potential V0 read at reset timing t1 is detected as the amount of light received in the period T. It is. The same applies to the graph G2 shown in FIG. That is, since the intermediate potential V2m is equal to the reference potential Vx, nothing is performed at the intermediate time point, and the potential V2 read at the timing t0 when the period T ends and the initial potential V0 read at the reset timing t1. Is detected as the amount of received light in the period T.

  The processing unique to the present invention is performed when the intermediate potential read at the intermediate time point is less than the reference potential Vx. In this case, an intermediate reset is performed at timing t3, which is an intermediate time point. This intermediate reset is similar to a normal reset performed in the period T (herein referred to as a periodic reset), a reset pulse is given to the reset signal line RST, the MOS transistor T1 is temporarily turned on, and the variation point The process for forcibly raising the potential of P is characterized in that the potential at the fluctuation point P is not raised to the initial potential V0 but to the reference potential Vx.

  The processing operation of the intermediate reset can be easily understood by looking at a specific example shown on the timing chart. For example, in the case of the graph G3 shown in FIG. 7, since the intermediate potential V3m read at the timing t2 is less than the reference potential Vx, the intermediate reset is performed at the timing t3. Three reset pulses are shown on the reset signal line RST in the middle of FIG. 7, but the reset pulse located at the timing t1 is a pulse for performing a periodic reset as in the prior art. The reset pulse located at t3 is a pulse for performing an intermediate reset.

  As a result of such an intermediate reset, the potential at the fluctuation point P gradually decreases until the timing t1 to t2, but increases to the reference potential Vx at the timing t3. However, after this intermediate reset is performed, the potential at the changing point P continues to decrease again. Eventually, the graph G3 has a saw-tooth shape that rises to the reference potential Vx at the time of the intermediate reset (timing t3), although it tends to decrease overall over the period T. Thus, finally, at the timing t0 when the period T ends, the potential V3 is read as the potential of the variation point P. The point of detecting the difference between the read potential V3 and the initial potential V0 read at the reset timing t1 as the amount of received light in the period T is the same as the conventional detection operation.

  Next, let's look at the example of FIG. In the case of the graph G4 shown in FIG. 8, the intermediate potential V4m (minimum potential) read at the timing t2 is less than the reference potential Vx, so the intermediate reset is performed at the timing t3. Also in this case, of the three reset pulses shown on the reset signal line RST in the middle of FIG. 8, the reset pulse located at the timing t1 is a pulse for performing a periodic reset as in the past, and the timing t3 The reset pulse located at is a pulse for performing an intermediate reset.

  As a result of such an intermediate reset, the potential at the fluctuation point P that has reached the lowest potential at the timing t2 rises to the reference potential Vx at the timing t3. Eventually, at the timing t0 when the period T ends, the potential V4 is read as the potential of the changing point P. The point that the difference between the read potential V4 and the initial potential V0 read at the reset timing t1 is detected as the amount of received light in the period T is the same as the conventional detection operation.

  FIG. 9 is a timing chart showing a difference in detection operation according to the present invention when light of each intensity corresponding to a plurality of graphs G1 to G6 is irradiated. Graph G1 shows the detection operation when the weakest light is irradiated, and graph G6 shows the detection operation when the strongest light is irradiated. Here, in the case of the graphs G1 and G2 in which the intermediate potential read at the timing t2 is equal to or higher than the reference potential Vx, no special processing is performed at the intermediate time point, and therefore, exactly the same as the graphs G1 and G2 shown in FIG. Will be followed. That is, at the timing t0, the potentials V1 and V2 are read out, and the difference from the initial potential V0 is output as a detection value indicating the amount of received light.

  On the other hand, in the graphs G3 to G6 in which the intermediate potential read at the timing t2 is less than the reference potential Vx, the intermediate reset is performed at the timing t3. In the example shown in FIG. 9, the potentials of the graphs G3, G4, G5, and G6 all rise to the reference potential Vx ′ at the timing t3, and then gradually fall again. Since the slope when falling from the reference potential Vx ′ is the same as the slope when falling from the initial potential V0, different potentials V3 to V6 are read for each of the graphs G3 to G6 at timing t0. . The difference between the read potentials V3 to V6 and the initial potential V0 is output as a detection value indicating the amount of received light.

  As a result, in the case of the conventional solid-state imaging device whose detection operation is shown by the timing chart of FIG. In the case of the solid-state imaging device of the present invention whose detection operation is shown by the timing chart of FIG. 9, the irradiation light intensity is relatively strong. Also for G3 to G6, the potential finally read out is different from the potentials V3, V4, V5, and V6, respectively. As in the past, a wide range of “whiteout” phenomenon is avoided.

  This is because the dynamic range related to the portion having a relatively high light intensity is expanded by the present invention. In the case of the example shown in FIG. 9, when light weaker than the light intensity corresponding to the graph G2 is irradiated, the potential of the variation point P read at the timing t0 is in the range of V0 to V2, and corresponds to the graph G2. When light stronger than the light intensity is irradiated, the potential of the fluctuation point P read out at the timing t0 is in the range of V2 to V6. Therefore, the relationship between the actual amount of received light and the detection voltage is not necessarily a linear function, but is at least a monotonically increasing function.

  FIG. 10 is a graph showing how the dynamic range is expanded according to the present invention. In this graph, the horizontal axis indicates the intensity of light applied to the photodiode PD, and the vertical axis indicates the signal level of the detection value indicating the amount of received light (the potential read at timing t0 and the timing read at timing t1). Difference from the initial potential V0). Conventionally, as shown by the dashed line graph, the dynamic range is set in the range of light intensity 0 to I2, and when the light intensity exceeds I2, the signal level reaches the maximum value Lmax and becomes saturated. , I2 or higher light intensity cannot be detected correctly.

  On the other hand, in the present invention, as shown by the solid line graph, for the light in the intensity range of 0 to I1, the range of the signal level 0 to Lx is associated with the range of the intensity I1 to I3. For the light within the range, the signal levels Lx to Lmax are associated with each other, and the dynamic range extends to the range of light intensity 0 to I3. Of course, the detection accuracy in the range of the light intensities I1 to I3 is slightly lower than the detection accuracy in the range of the light intensities 0 to I1, but the dynamic range limited to the light intensity I2 is It is a great merit to spread to the light intensity I3.

  The extent to which the dynamic range is expanded depends on the setting of the intermediate time point and the setting of the reference potential. Specifically, the reference potential Vx is set to be higher as the intermediate point is closer to the end point of the cycle T (in the timing chart of FIG. 9, the closer the intermediate time M1 is to the cycle T). The more you increase the dynamic range. In other words, the intermediate time M1 is a parameter that affects the slope between the light intensities I1 to I3 of the graph shown by the solid line in FIG. 10, and the reference potential Vx is the position of the light intensity I1 in the graph. It becomes a parameter that influences. Therefore, in practice, the intermediate time M1 and the reference potential Vx may be appropriately set in consideration of how a solid-state imaging device with an expanded dynamic range is necessary.

  Strictly speaking, the potential Vx and the potential Vx ′ shown in FIG. 9 do not completely match. According to the basic principle of the present invention, since both the point Vx and the point Vx ′ need to be points on the graph G2, strictly speaking, Vx ′ <Vx. However, as already described, the width of the reset pulse on the reset signal line RST and the selection pulse on the selection signal line SEL is on the order of μsec, whereas the period T is on the order of several tens of msec. The orders are more than 4 digits different. Therefore, even if handling with Vx ′ = Vx is performed, no problem occurs substantially. Therefore, here, the potential Vx ′ and the potential Vx are treated as the same reference potential.

  The circuit shown in FIG. 4 has a configuration suitable for performing the detection operation shown in FIG. First, a reset pulse is given to the reset signal line RST shown in FIG. 4 at the timing shown in the middle stage of FIG. 9, and the MOS transistor T1 is temporarily turned on. At this time, although there is no difference in the reset pulse itself, different types of reset processing are performed for the periodic reset performed at timing t1 and the intermediate reset performed at timing t3. That is, in the periodic reset at the timing t1, the process of setting the fluctuation point P to the initial potential V0 is performed, whereas in the intermediate reset at the timing t3, the process of setting the fluctuation point P to the reference potential Vx is performed.

  In the circuit shown in FIG. 4, the reset voltage setting line L1 is provided so that the reset can be performed with an arbitrary voltage. That is, when the periodic reset is performed at the timing t1, the reset voltage setting line L1 may be set to the same power supply voltage as that of the power supply line VDD. Then, the circuit of FIG. 4 becomes equivalent to the conventional circuit shown in FIG. 1, and when the MOS transistor T1 is turned on, the variation point P is reset to be the initial potential V0 close to the power supply voltage VDD (transistor If the threshold voltage of T1 is Vth, the initial potential V0 = VDD−Vth). On the other hand, when an intermediate reset is performed at timing t3, the reset voltage setting line L1 is a predetermined voltage slightly higher than the reference voltage Vx (a voltage higher by Vth than the reference voltage Vx if the threshold voltage of the transistor T1 is Vth). Just keep it. Then, when the MOS transistor T1 is turned on, the changing point P is reset to become the reference voltage Vx.

  The reset voltage setting line L1 is prepared as a common signal line for a plurality of pixels arranged in the same column (a plurality of pixels adjacently arranged in the vertical direction in the figure), whereas the reset signal line RST is Since a plurality of pixels arranged in the same row (a plurality of pixels arranged adjacent in the horizontal direction in the figure) are prepared as a common signal line, the timing of the reset pulse applied to the reset signal line RST and the reset voltage setting By matching the timing of supplying a desired voltage to the line L1, it is possible to reset a specific pixel among a large number of pixels arranged in a two-dimensional matrix with a specific voltage.

  In the embodiment described here, an intermediate reset is not always performed. As described above, when the intermediate potential read at the intermediate time point (timing t2) is equal to or higher than the reference potential Vx (for example, in the case of FIGS. 5 and 6), the intermediate reset is not performed. The intermediate reset is performed when the read intermediate potential is less than the reference potential Vx (for example, in the case of FIGS. 7 and 8). Therefore, actually, it is necessary to perform a process of comparing the intermediate potential read at timing t2 with the reference potential Vx and then determining whether or not to perform the intermediate reset.

  As described above, if the reset is performed while the reset voltage setting line L1 is set to a predetermined voltage, the changing point P can be set to a desired potential. However, in practice, in order to accurately set the variation point P to a desired potential, it is preferable to perform a reset process with feedback control based on the potential read value at the variation point P. This feedback control will be described in detail in Section 5 with an example.

  On the selection signal line SEL shown in the lower part of the timing charts of FIGS. 5 to 9, selection pulses are given at respective timings t0, t1, t2 and t3. Here, the selection pulse given at the timing t0 is for reading out the potentials V1 to V6 of the fluctuation point P immediately before the periodic reset, and the selection pulse given at the timing t1 is the fluctuation point at the time of the periodic reset. This is for reading the initial potential V0 of P. The selection pulse given at timing t2 is for reading the intermediate potential at the fluctuation point P at the intermediate time point. On the other hand, the selection pulse given at timing t3 is for reading the potential at the variation point P at the time of the intermediate reset. The potential at the fluctuation point P at the time of the intermediate reset at the timing t3 is unnecessary information in the essential operation of the present invention, but the selection pulse at the timing t3 is used for performing the feedback control described above. .

<<< §3. Four-transistor type solid-state imaging device according to the present invention >>
Subsequently, an embodiment in which the present invention is applied to a so-called “4-transistor type” solid-state imaging device in which a circuit for one pixel is constituted by four MOS transistors will be described.

  FIG. 11 is a circuit diagram showing a circuit for one pixel of a conventional general four-transistor solid-state imaging device. As shown in the figure, this circuit includes a photodiode PD and four N-type MOS transistors T10, T20, T30, and T40. A power supply voltage is supplied to the transistors T10 and T30 from the power supply line VDD. Here, the transistor T10 is a transistor having a function substantially equivalent to that of the transistor T1 shown in FIG. 1, and performs a reset process based on a reset pulse supplied from the reset signal line RST. The transistors T20 and T30 have the same functions as those of the transistors T2 and T3 shown in FIG. It performs the function of reading on the output line OUT. A current source J is connected to the signal output line OUT, and the principle of reading out the potential is exactly the same as that of the three-transistor type circuit of FIG.

  The feature of the four-transistor type circuit shown in FIG. 11 is that a fourth MOS transistor T40 is connected in series to the photodiode PD. One end of the MOS transistor T40 is connected to the fluctuation point P that is the forward end of the photodiode PD, and the other end is connected to one end of the transistor T10. Here, the point Q connecting the transistor T10 and the transistor T40 is generally called a floating diffusion terminal, and the amount of light received by the pixel is detected by reading the potential of the floating diffusion terminal. Here, for convenience, this point Q will be referred to as a detection point Q. A capacitive element C10 indicated by a broken line in the figure is a parasitic capacitance of the detection point Q (floating diffusion terminal).

  Another difference between the 4-transistor type circuit and the 3-transistor type circuit is that a transfer signal line TNS for supplying a transfer pulse to the gate of the transistor T40 is provided. The transfer signal line TNS functions as a common signal line for a large number of pixels arranged adjacent to each other in the row direction (the left-right direction in the figure), and the pixels for one row share the same transfer signal line TNS. . When a transfer pulse from the transfer signal line TNS is applied to the gate of the transistor T40, the transistor T40 is temporarily turned on, and the negative charge accumulated at the fluctuation point P is transferred to the detection point Q. Become.

  When the transfer pulse is not supplied on the transfer signal line TNS, the transistor T40 is turned off. In this state, when the photodiode PD is irradiated with light, negative charges are accumulated at the fluctuation point P. The amount of negative charge that is accumulated depends on the amount of light received by the photodiode PD. If the amount of received light is large, the amount of negative charge that is accumulated also increases. In this way, the transfer pulse on the transfer signal line TNS fulfills the function of performing a transfer process for transferring the negative charge accumulated at the fluctuation point P to the detection point Q.

  However, in order to transfer the negative charge accumulated at the variation point P to the detection point Q, the potential at the detection point Q needs to be higher than the potential at the variation point P. For this purpose, reset processing by the transistor T10 is performed. That is, if a reset pulse is supplied onto the reset signal line RST to turn on the transistor T10 temporarily, the potential at the detection point Q becomes the initial potential V0 close to the power supply voltage VDD (the threshold value of the transistor T10). If the voltage is Vth, the initial potential V0 = VDD−Vth). In this state, if a transfer pulse is supplied onto the transfer signal line TNS, the negative charge accumulated at the fluctuation point P is transferred to the detection point Q, and the potential at the detection point Q drops rapidly from the initial potential V0. . The amount of this voltage drop depends on the amount of negative charge accumulated at the fluctuation point P. Therefore, if the potential at the detection point Q after the voltage drop is read out to the signal output line OUT, it is read out. The potential indicates the amount of light received by the photodiode PD.

  FIG. 12 is a timing chart showing an operation of detecting the amount of received light by the circuit shown in FIG. Here, the upper chart shows the potential of the detection point Q, and the lower charts show the voltage of the reset signal line RST, the voltage of the transfer signal line TNS, and the voltage of the selection signal line SEL, respectively. As shown in the figure, a reset pulse is given to the reset signal line RST every predetermined period T, and the MOS transistor T10 is turned on only for a period corresponding to the width of this pulse. As a result, the detection point Q is reset to the initial potential V0 every period T. Here, the timing at which this reset pulse is given is called t1. As shown in FIG. 12, the period from one timing t1 to the next timing t1 is a predetermined period T.

  As already described, while the period T is on the order of several tens of msec, the width of the reset pulse on the reset signal line RST, the transfer pulse on the transfer signal line TNS, and the selection pulse on the selection signal line SEL is μsec. However, on the timing chart shown in the figure, for convenience of explanation, these pulses are shown on a scale ignoring the original pulse width on the real time axis.

  First, when reset processing is performed by applying a reset pulse at timing t1, the potential at the detection point Q rises to the initial potential V0. Therefore, transfer processing is performed by applying a transfer pulse at timing t2 immediately after that, and the negative charge accumulated at the fluctuation point P is transferred to the detection point Q. Then, a voltage drop corresponding to the amount of transferred negative charge occurs at the detection point Q. In the upper chart of FIG. 12, the potential at the detection point Q drops to V1 at timing t2. This potential difference ΔV (ΔV = V0−V1) corresponds to the amount of negative charge accumulated at the fluctuation point P and is a value indicating the amount of received light in the period T.

  Here, paying attention to the state of the fluctuation point P, the accumulated charge becomes zero at the timing t2 when the charge transfer to the detection point Q is performed. Over time, negative charge is gradually accumulated. On the other hand, the potential of the detection point Q is maintained at the potential V1 at the time of transfer at the timing t2 until the reset timing t1 for the next transfer. During the period T, negative charge is steadily accumulated at the variation point P.

  Further, a selection pulse is given on the selection signal line SEL at timings t1 and t2. The selection pulse given at timing t1 is for reading the initial potential V0 of the detection point Q at the time of reset, and the selection pulse given at timing t2 immediately after that reads the potential V1 of the detection point Q at the time of transfer. Is for. When both potentials V0 and V1 are read, the amount of received light within the period T can be detected by obtaining the difference ΔV between the two potentials. When the light irradiated to the photodiode PD is relatively weak, the amount of received light is small, so the potential difference ΔV is small. However, when the light being irradiated is relatively strong, the amount of received light is large and the potential difference ΔV is also small. growing.

  Note that the circuit shown in FIG. 11 is a circuit relating to one pixel, and an actual solid-state imaging device is configured by arranging a large number of such circuits for one pixel so as to form a matrix vertically and horizontally. Here, the reset signal line RST, the selection signal line SEL, and the transfer signal line TNS function as a common signal line for a large number of pixels arranged adjacent to each other in the row direction (left-right direction in the drawing). The operations shown in the timing chart of FIG. 12 are executed simultaneously. On the other hand, the signal output line OUT functions as a common signal line for a large number of pixels arranged adjacent to each other in the column direction (vertical direction in the figure), and the pixels for one column share the same signal output line OUT. Become. However, since each row is driven so that the phase of the period T shown in FIG. 12 is slightly shifted, the output of the pixel in the first row, the second row on the same signal output line OUT. The detection value for the pixels in each row is obtained as a time-series signal, such as the output of the pixels in this row, the output of the pixels in the third row, and so on.

  Next, the reason why the “overexposure” phenomenon occurs in the solid-state imaging device including the pixels having the configuration shown in FIG. 11 will be described with reference to the timing chart of FIG. Similar to the timing chart of FIG. 12, the timing chart of FIG. 13 shows the potential fluctuation of the detection point Q in the period T and the states of the reset signal line RST, the transfer signal line TNS, and the selection signal line SEL. However, the graph shown in the upper part of FIG. 13 shows a state in which the potential at the detection point Q drops to the lowest level Vmin when the transfer process is performed at the timing t2. As described above, the detection point Q is generally called a floating diffusion terminal, and its potential can only drop to the minimum level Vmin determined based on the characteristics of the photodiode PD and the MOS transistor T40. In other words, there is an upper limit value ΔVmax in the potential difference with respect to the initial potential V0.

  This is because, when the photodiode PD is irradiated with a certain intensity of light, if the potential at the detection point Q during the transfer at the timing t2 has already reached the minimum level Vmin, stronger light is applied to the photodiode PD. This means that the potential at the detection point Q during the transfer at the timing t2 does not fall below the minimum level Vmin even if the irradiation is performed, and the “overexposure” phenomenon occurs with respect to the light having the intensity.

  Therefore, in the present invention, the circuit shown in FIG. 14 is used instead of the circuit shown in FIG. The basic configuration of the circuit shown in FIG. 14 is substantially the same as the basic configuration of the circuit shown in FIG. The difference between the two is that in the case of the circuit shown in FIG. 11, the power supply line VDD is connected to both the MOS transistors T10 and T30, whereas in the case of the circuit shown in FIG. 14, the power supply line VDD is only the MOS transistor T30. And a separate reset voltage setting line L10 is connected to the MOS transistor T10. The power supply line VDD is a signal line that always supplies a constant voltage, whereas the reset voltage setting line L10 has a function of supplying an arbitrary voltage set by a control circuit (not shown).

  Thus, by providing the reset voltage setting line L10 separately, not only resetting the detection point Q to the initial potential V0 but also resetting to an arbitrary potential becomes possible. A feature of the present invention resides in that, by using such a function of the reset voltage setting line L10, reset is performed twice as necessary within the period T. Hereinafter, this principle will be described with reference to the timing charts of FIGS. These timing charts show the potential fluctuation at the detection point Q in the period T and the states of the reset signal line RST, the transfer signal line TNS, and the selection signal line SEL, as in the timing chart shown in FIG. is there.

  First, look at the timing chart of FIG. As shown in the figure, a transfer pulse is applied to the transfer signal line TNS at timing t1, and a selection pulse is also applied to the selection signal line SEL at timing t1. That is, a transfer pulse and a selection pulse are given every predetermined period T, and after the negative charge is transferred from the fluctuation point P to the detection point Q, the potential at the detection point Q is read out. . Thus, the difference between the potential read at every cycle T (the potential read at timing t1) and the initial potential V0 becomes a value indicating the amount of received light in the cycle T.

  On the other hand, the reset timing is different from that of the conventional circuit, and as shown in the figure, a reset pulse is applied to the reset signal line RST at the timing t2 when the intermediate time M1 has elapsed from the timing t1. In the example shown in FIG. 15, the reset within the period T is only once at the timing t2, but in the example shown in FIG. 16 described later, the reset is performed twice at the timing t2 and the timing t4. Done. Therefore, for the sake of convenience, the reset performed at timing t2 is referred to as a primary reset, and the reset performed at timing t4 is referred to as a secondary reset.

  This reset process is not the only process performed at the intermediate point. A transfer pulse is applied to the transfer signal line TNS at the intermediate timing t3. Here, for the sake of convenience, the transfer process using the transfer pulse given at the timing t1 is called a periodic transfer process, and the transfer process using the transfer pulse given at the timing t3 is called an intermediate transfer process. Of course, the intermediate transfer process is also a periodic process performed every period T. On the selection signal line SEL, a selection pulse having a width of timings t2, t3, and t4 at the intermediate time point is given, and the potential of the detection point Q at each timing is read out.

  In the example shown in FIG. 15, the potential at the detection point Q rises to the initial potential V0 due to the primary reset at the timing t2. Subsequently, by the intermediate transfer process at the timing t3, the charges accumulated at the fluctuation point P (negative charges accumulated during the timings t1 to t3) are transferred to the detection point Q. As a result, the transferred charge amount The potential at the detection point Q drops by an amount corresponding to. In the illustrated example, a potential drop occurs from the initial potential V0 to the potential V1m. Here, the potential V1m read at the timing t3 is referred to as an “intermediate potential”. After that, by the periodic transfer process at the timing t1, the charge accumulated at the fluctuation point P (the negative charge accumulated between the timings t3 and t1) is again transferred to the detection point Q, and as a result, transferred. The potential at the detection point Q further drops by an amount corresponding to the amount of charge. In the illustrated example, a potential drop occurs from the intermediate potential V1m to the potential V1. The potential V1 read at the timing t1 becomes a value indicating the amount of received light in the period T (the amount of received light is obtained by V0−V1).

  Thus, the intermediate potential V1m is read at the intermediate time point in order to determine whether the intermediate potential V1m is larger or smaller than the predetermined reference potential Vx. The reference potential Vx is a potential set in advance as a predetermined value lower than the initial potential V0, as in the embodiment described in §2. In the example shown in FIG. 15, Vx = ½ · V0 is set, and the level indicated by the alternate long and short dash line in the upper graph corresponds to the reference potential Vx. In this example, the intermediate potential V1m is larger than the reference potential Vx.

  In the embodiment shown here, when the intermediate potential is read at the intermediate time point (timing t3) and the read intermediate potential is equal to or higher than the reference potential Vx, nothing is done at this intermediate time point, and the period T The difference between the potential V1 read at the timing t1 when the process ends and the initial potential V0 is detected as the amount of received light in the period T. On the other hand, when the intermediate potential read at the intermediate time point is lower than the reference potential Vx, the secondary reset process at the timing t4 is added. Hereinafter, the processing in this case will be described with reference to the timing chart of FIG.

  Also in the example shown in FIG. 16, first, the potential at the detection point Q rises to the initial potential V0 by the primary reset at the timing t2. Subsequently, by the intermediate transfer process at the timing t3, the charge accumulated at the variation point P is transferred to the detection point Q, and the potential of the detection point Q drops from the initial potential V0 to the intermediate potential V4m. Since the intermediate potential V4m is lower than the reference potential Vx, a secondary reset is performed at timing t4.

  Similar to the primary reset performed at timing t2, the secondary reset performed at timing t4 gives a reset pulse to the reset signal line RST, temporarily turns on the MOS transistor T1, and forcibly sets the potential at the variation point P. However, the process is characterized in that the potential at the fluctuation point P is not raised to the initial potential V0 but is raised to the reference potential Vx. For example, in the example shown in FIG. 16, the potential at the detection point Q rises to the initial potential V0 by the primary reset at the timing t2, but the potential at the detection point Q reaches the intermediate potential V4m by the intermediate transfer process at the subsequent timing t3. Descend. Then, the secondary reset at the timing t4 raises the potential at the detection point Q to the reference potential Vx. Finally, the potential at the detection point Q drops to the potential V4 by the periodic transfer process at the timing t1 when the cycle T ends. The potential V4 read at the timing t1 becomes a value indicating the amount of received light in the period T (the amount of received light is obtained by V0-V4).

  By executing such a secondary reset, an effect of putting clogs on the potential of the detection point Q at the timing t3 is obtained. That is, by the secondary reset, the potential increases from the intermediate potential V4m to the reference potential Vx, and the potential is raised by the difference voltage (Vx−V4m) between the two. As a result, the potential at the detection point Q can be prevented from reaching the minimum level Vmin. For example, in the example shown in FIG. 16, if the secondary reset is not performed, the potential at the detection point Q immediately before the periodic transfer process at timing t1 is V4m. The potential at the detection point Q reaches the minimum level Vmin, and a so-called “overexposed” phenomenon occurs. By performing the secondary reset, it becomes possible to suppress such a “whiteout” phenomenon.

  Eventually, also in the embodiment described here, the dynamic range relating to the portion having a relatively high light intensity is expanded, and the effect shown by the solid line graph in FIG. 10 is obtained. At this time, as in the embodiment described in §2, the setting of the intermediate time point and the setting of the reference potential are parameters for determining the expansion of the dynamic range.

  The circuit shown in FIG. 14 has a configuration suitable for performing the detection operation shown in FIG. First, a reset pulse is given to the reset signal line RST shown in FIG. 14 at the timing shown in the RST column of FIG. 16, and the MOS transistor T10 is temporarily turned on. At this time, although there is no difference in the reset pulse itself, as described above, different types of reset processing are performed for the primary reset performed at the timing t2 and the secondary reset performed at the timing t4. That is, in the primary reset of the timing t2, the process of setting the detection point Q to the initial potential V0 is performed, whereas in the secondary reset of the timing t4, the process of setting the detection point Q to the reference potential Vx is performed.

  In the circuit shown in FIG. 14, the reset voltage setting line L10 is provided so that the reset can be performed with an arbitrary voltage. That is, when performing the primary reset at the timing t2, the reset voltage setting line L10 may be set to the same power supply voltage as the power supply line VDD. Then, the circuit of FIG. 14 becomes equivalent to the conventional circuit shown in FIG. 11, and when the MOS transistor T10 is turned on, the detection point Q is reset to the initial potential V0 close to the power supply voltage VDD (transistor If the threshold voltage of T10 is Vth, the initial potential V0 = VDD−Vth). On the other hand, when performing the secondary reset at timing t4, the reset voltage setting line L10 is a predetermined voltage slightly higher than the reference voltage Vx (a voltage higher than the reference voltage Vx by Vth if the threshold voltage of the transistor T10 is Vth). ). Then, when the MOS transistor T10 is turned on, the detection point Q is reset to the reference voltage Vx.

  The reset voltage setting line L10 is prepared as a common signal line for a plurality of pixels (a plurality of pixels adjacently arranged in the vertical direction in the figure) arranged in the same column, whereas the reset signal line RST is Since a plurality of pixels arranged in the same row (a plurality of pixels arranged adjacent in the horizontal direction in the figure) are prepared as a common signal line, the timing of the reset pulse applied to the reset signal line RST and the reset voltage setting By matching the timing for supplying a desired voltage to the line L10, it is possible to reset a specific pixel of a large number of pixels arranged in a two-dimensional matrix with a specific voltage.

  In the embodiment described here, the primary reset is always performed at the timing t2, but the secondary reset is not necessarily performed. As described above, when the intermediate potential read at the intermediate time point (timing t3) is equal to or higher than the reference potential Vx (for example, in the case of FIG. 15), the secondary reset is not performed. The secondary reset is performed when the read intermediate potential is less than the reference potential Vx (for example, in the case of FIG. 16). Therefore, actually, it is necessary to perform a process of comparing the intermediate potential read at timing t3 with the reference potential Vx and then determining whether or not to perform secondary reset.

  As described above, if reset is performed with the reset voltage setting line L10 set to a predetermined voltage, the detection point Q can be set to a desired potential. However, in practice, in order to accurately set the detection point Q to a desired potential, it is preferable to perform a reset process with feedback control based on the potential read value of the detection point Q. This feedback control will be described in detail in Section 6 with an example.

  On the selection signal line SEL shown in the timing charts of FIGS. 15 and 16, a selection pulse having a period width of timings t2, t3, and t4 is given in addition to the selection pulse given at timing t1. Here, the former selection pulse is for reading the potential of the detection point Q (V1 in the example of FIG. 15, V4 in the example of FIG. 16) during the periodic transfer process. On the other hand, the latter selection pulse is for performing each processing at the intermediate time point. Specifically, the portion at timing t2 is for reading the potential V0 at the detection point Q at the time of primary reset, and the portion at timing t3 is the potential at the detection point Q at the time of intermediate transfer processing (example in FIG. 15). Is for reading V1m and V4m) in the example of FIG. The portion at timing t4 is for reading the potential at the detection point Q at the time of secondary reset (Vx in the example of FIG. 16). The potential at the detection point Q at the time of the secondary reset at the timing t4 is unnecessary information for the essential operation of the present invention, but is used for performing the feedback control described above.

<<< §4. Modified example to unify reset operation >>>
So far, in §2, a three-transistor type basic embodiment has been described, and in §3, a four-transistor type basic embodiment has been described. Here, a modified example in which the mode of the reset operation in these basic embodiments is changed will be described.

  First, a modification of the three-transistor type embodiment described in §2 will be described. As described above, the basic feature of this three-transistor type is that an intermediate reset is not performed when the intermediate potential of the fluctuation point P read at the intermediate time is equal to or higher than the reference potential Vx (for example, 5 and 6), when the potential is lower than the reference potential Vx, an intermediate reset is performed (for example, FIGS. 7 and 8).

  Here, whether the intermediate potential is larger or smaller than the reference potential Vx is a matter determined depending on the intensity of the light irradiated to the pixel at that time, and therefore naturally differs for each pixel. It is a matter that is different in time. Therefore, whether or not to perform an intermediate reset is a matter to be determined independently for each individual pixel, and even for the same pixel, a matter to be determined independently for each period T. It is. As a result, among the many pixels constituting the solid-state imaging device, pixels that perform intermediate reset and pixels that do not perform are mixed, and pixels that should be given reset pulses and those that should not be given at the middle time are mixed. Will do. For example, in the timing charts of FIGS. 5 and 6, there is no reset pulse at timing t3, but in the timing charts of FIGS. 7 and 8, there is a reset pulse at timing t3.

  Of course, it is technically possible to control whether or not to apply a reset pulse at timing t3 for each individual pixel based on the result of comparing the value of the intermediate potential read at timing t2 with the reference potential Vx. It is possible enough. However, in practice, when such a control is implemented using, for example, a transistor, it becomes necessary to add a transistor for controlling the reset pulse for intermediate reset. The modification described here relates to a device for realizing the present invention with a practically simple circuit configuration by omitting the control of whether or not to provide a reset pulse for intermediate reset.

  The inventor focuses on the idea that even if it is not necessary to perform an intermediate reset in principle, the intermediate reset is performed for convenience. By doing so, since the intermediate reset is always performed for all the pixels in all the cycles T, it is not necessary to perform the control for each pixel for each pixel as to whether or not to perform the intermediate reset. Specifically, in the modification described here, for example, a reset pulse for intermediate reset at timing t3 is also added to the reset signal RST shown in FIGS. 5 and 6, and eventually, FIG. 7 and FIG. This is the same as the reset signal RST shown in FIG. In this way, if the same reset signal RST is always supplied to all the pixels, the reset operation can be unified and the circuit configuration for supplying the reset pulse can be simplified.

  However, correct detection based on the principle described in §2 should be performed for pixels that do not need to be subjected to intermediate reset unless the state equivalent to that when intermediate reset is not performed is maintained. Can't do it. For example, in the example shown in FIG. 5, since the intermediate potential V1m is equal to or higher than the reference potential Vx, it is not necessary to perform an intermediate reset. Therefore, when the intermediate potential V1m is equal to or higher than the reference potential Vx, instead of performing an intermediate reset such that the potential at the changing point P becomes the reference potential Vx, an intermediate at which the potential at the changing point P becomes the intermediate potential V1m. Do a reset.

  For example, in the example shown in FIG. 5, an intermediate reset is performed at the timing t3. At this time, the reset is performed such that the potential at the variation point P becomes the intermediate potential V1m read at the immediately preceding timing t2. It is. Specifically, when a reset pulse is applied to the gate of the MOS transistor T1 in FIG. 4 at timing t3, the voltage of the reset voltage setting line L1 is slightly higher than the intermediate potential V1m (the threshold voltage of the transistor T1 is set to Vth). In this case, the voltage V1m + Vth may be maintained. Eventually, the intermediate reset in this case means a refresh operation in which the intermediate potential V1m of the fluctuation point P read immediately before is written as a new potential of the fluctuation point P as it is. Therefore, the potential fluctuation at the fluctuation point P is not different from that shown in the timing chart in the upper part of FIG. 5, and the potential V1 read at the timing t0 is not changed.

  After all, the main point of this modification is that an intermediate reset at timing t3 is performed for all pixels at all periods T, but when the intermediate potential read at timing t2 is less than the reference potential Vx. The reset is performed so that the potential at the variation point P becomes the reference potential Vx, and when the potential is equal to or higher than the reference potential Vx, the reset is performed so that the potential at the variation point P becomes the intermediate potential read at the timing t2. It will be.

  The above-described modification that unifies the reset operation can also be applied to the four-transistor type embodiment described in §3. As described above, the basic feature of the four-transistor type is that the secondary reset is not performed when the intermediate potential of the detection point Q read at the intermediate time is equal to or higher than the reference potential Vx (for example, 15), when the potential is less than the reference potential Vx, secondary reset is performed (for example, FIG. 16). Therefore, among a large number of pixels constituting the solid-state imaging device, pixels that perform the secondary reset and pixels that do not perform the mixing are mixed.

  Therefore, in the case of the four-transistor type, even if it is not necessary to perform the secondary reset in principle, the secondary reset may be performed for convenience. As a result, both the primary reset and the secondary reset are executed for all the pixels at the intermediate point of all the periods T, and the circuit configuration for supplying the reset pulse can be simplified.

  However, in this case as well, for pixels that do not need to be reset in principle, as described in §3 unless the same state as when the secondary reset is not maintained is maintained. Correct detection based on the principle cannot be performed. Therefore, when the intermediate potential is equal to or higher than the reference potential Vx, instead of performing a secondary reset such that the potential at the detection point Q becomes the reference potential Vx, a secondary where the potential at the detection point Q becomes the intermediate potential. Do a reset.

  For example, in the example shown in FIG. 15, after the primary reset at the timing t2, the secondary reset is performed at the timing t4. At this time, the potential at the detection point Q is the intermediate read out at the immediately preceding timing t3. The reset is performed so that the potential becomes V1m. Specifically, when a reset pulse is applied to the gate of the MOS transistor T10 in FIG. 14 at timing t4, the voltage of the reset voltage setting line L10 is slightly higher than the intermediate potential V1m (the threshold voltage of the transistor T10 is set to Vth). In this case, the voltage V1m + Vth may be maintained. Eventually, the secondary reset in this case means a refresh operation in which the intermediate potential V1m of the detection point Q read immediately before is written as a new potential of the detection point Q as it is. Therefore, the potential fluctuation at the detection point Q is not different from that shown in the upper timing chart of FIG. 15, and the potential V1 read at the timing t1 is not changed.

  After all, the main point of this modification is that secondary reset at timing t4 is performed for all pixels at all periods T, but the intermediate potential read at timing t3 is less than the reference potential Vx. Performs reset so that the potential at the detection point Q becomes the reference potential Vx, and when the potential is equal to or higher than the reference potential Vx, performs reset so that the potential at the detection point Q becomes the intermediate potential read at timing t3. It turns out that.

<<< §5. Control system suitable for 3-transistor type circuit >>>
So far, the configuration of the solid-state imaging device according to the present invention has been described by showing the circuit for one pixel. Here, a specific embodiment including a control system circuit for controlling the circuit for one pixel will be described.

  FIG. 17 is a circuit diagram showing an embodiment in which a control system circuit is added to the three-transistor type circuit shown in FIG. The circuit for one pixel shown in the upper half of FIG. 17 is exactly the same as the circuit shown in FIG. 4, and the circuit shown in the lower half is a pixel for one column (a plurality of pixels arranged in the vertical direction in the figure). Is a control circuit used in common. The differential amplifier A1 is a control element that performs control output so that the difference between two analog input signals is zero, and a voltage applied to an input terminal marked with a “−” mark is marked with a “+” mark. If the voltage is higher than the voltage applied to the input terminal, the output voltage is controlled to decrease, and conversely, the voltage applied to the input terminal marked with the “−” mark is “+”. If the voltage is smaller than the voltage applied to the input terminal marked with “”, control is performed in the direction of increasing the output voltage. However, if necessary, the polarity switching signal SW can be used to switch the polarity of “+/−” of both input terminals to invert the polarity with respect to the illustrated state. That is, in the state shown in the figure, the upper part is “−” and the lower part is “+”. However, when inverted, the upper part is “+” and the lower part is “−”.

  T5, T6, and T7 indicated by rectangular blocks are transistors capable of ON / OFF control. In both cases, the left and right connections are in a conductive state in the ON state, and in the OFF state, the left and right connections are in an insulated state. C2 is a capacitive element for temporarily storing the voltage read on the signal output line OUT, and B1 temporarily stores the comparison result between the voltage read on the signal output line OUT and the reference voltage Vref. This is a 1-bit memory for storing data. Of course, the 1-bit memory B1 can be configured by using one bit of a memory having a function of storing a large number of bits.

  The control circuit shown here is a control circuit suitable for the case where the modification example (unification of reset operation) described in §4 is applied to the three-transistor type embodiment described in §2. In this modification, it is necessary to control the voltage of the reset voltage setting line L1 by dividing it into the following three cases.

  First, the first case is a case of periodic reset at the timing t1 of the reset signal RST shown in FIG. In this case, it is necessary to set the voltage of the reset voltage setting line L1 to “a predetermined voltage necessary for resetting the variation point P to the initial potential V0”. The second case is a case where an intermediate reset is performed at the timing t3 of the reset signal RST shown in FIG. 7, and the intermediate potential read at the timing t2 immediately before that is less than the reference potential Vx. In this case, it is necessary to set the voltage of the reset voltage setting line L1 to “a predetermined voltage necessary for resetting the variation point P to the reference potential Vx”. The third case is a case where an intermediate reset is performed at the timing t3 of the reset signal RST shown in FIG. 7, and the intermediate potential read at the timing t2 immediately before is the reference potential Vx or more (in principle) In the case where there is no need to perform an intermediate reset). In this case, it is necessary to set the voltage of the reset voltage setting line L1 to “a predetermined voltage necessary for resetting the fluctuation point P to the intermediate potential read at the timing t2 immediately before it”.

  If the control circuit shown in the lower half of FIG. 17 is used, voltage control in the above three cases can be accurately performed. This is because the control circuit has a function of performing feedback control based on the potential read value obtained on the signal output line OUT. That is, in the first case, resetting is performed so that the variation point P becomes the initial potential V0, in the second case, resetting is performed so that the variation point P becomes the reference potential Vx, and in the third case, It is necessary to perform reset so that the fluctuation point P becomes the intermediate potential read immediately before. In any case, the potential at the fluctuation point P is set during the reset period (during the period corresponding to the width of the reset pulse). Reading on the signal output line OUT and sequentially monitoring it, and controlling the voltage of the reset voltage setting line L1 so that the read value becomes a predetermined target value, the potential at the variation point P becomes a desired value. Such an accurate reset operation becomes possible.

  First, in the first case where resetting to the initial potential V0 is necessary, the transistors T5 and T7 are turned on, the transistor T6 is turned off, and the voltage corresponding to the initial potential V0 (the fluctuation point P is the initial value) is set as the reference voltage Vref. When the potential is V0, a voltage output on the signal output line OUT is input. As this reference voltage Vref, an analog output such as a DA converter may be used. For example, if an 8-bit DA converter is used, an arbitrary analog voltage in 256 stages can be generated as the reference voltage Vref according to a digital value of 0 to 255.

  As also shown in the timing chart of FIG. 7, at timing t1, since the selection pulse is given together with the reset pulse, the potential at the variation point P is sequentially read out to the signal output line OUT. Therefore, the differential amplifier A1 can fulfill the function of controlling the voltage of the reset voltage setting line L1 so that the voltage value read on the signal output line OUT is equal to the reference voltage Vref. Thus, in the first case, a reset operation is performed such that the fluctuation point P becomes the initial potential V0.

  Subsequently, in the second case or the third case, which case is executed depends on the magnitude of the intermediate potential read at the timing t2 in the timing chart of FIG. is there. This control circuit has a function of recording the determination result of the magnitude of the intermediate potential in the 1-bit memory B1. The intermediate potential magnitude determination process and the writing process to the 1-bit memory B1 are actually performed in the first half period of the timing t2.

  That is, in the first half period of the timing t2, the transistor T5 is turned on, the transistors T6 and T7 are turned off, and the reference voltage Vref is a voltage corresponding to the reference potential Vx (when the variation point P is the reference potential Vx, The voltage output on the output line OUT is input. In such a state, the differential amplifier A1 outputs a low potential when the voltage of the signal output line OUT is higher than the reference voltage Vref (when the potential of the fluctuation point P is equal to or higher than the reference potential Vx), and the signal When the voltage of the output line OUT is lower than the reference voltage Vref (when the potential at the fluctuation point P is less than the reference potential Vx), a high potential is output. In accordance with the two output potentials, a bit indicating a determination result of “more than Vx” or “less than Vx” is written in the 1-bit memory B1.

  Subsequently, in the latter half of the timing t2, the transistor T6 is turned on and the transistors T5 and T7 are turned off. Since the transistor T5 is in the OFF state, the reference voltage Vref has no meaning in this case (it may be set at an arbitrary voltage). At this time, the polarity switching signal SW is supplied to invert ± of the input terminal of the differential amplifier A1 so that the upper input terminal in the drawing becomes “+” and the lower input terminal becomes “−”. Then, the differential amplifier A1 performs a control function such that the voltage at the upper end of the capacitive element C2 connected to the lower input terminal becomes equal to the voltage of the signal output line OUT connected to the upper input terminal. Therefore, the capacitor C2 is in a state where charges corresponding to the voltage of the signal output line OUT at that time are accumulated. After this processing is completed, the inversion state of the input terminal of the differential amplifier A1 is canceled.

  In short, this process is a process for recording the voltage of the signal output line OUT at the timing t2 by using the capacitive element C2, and temporarily stores the potential read value at the variation point P at the timing t2. It is nothing but the saving process for saving. Such a storage process is necessary only when an intermediate reset corresponding to the above-described third case (reset so that the fluctuation point P becomes the intermediate potential read immediately before) is performed at the subsequent timing t3. When the intermediate reset corresponding to the above-mentioned second case (reset so that the fluctuation point P becomes the reference potential Vx) is performed at the timing t3, it is unnecessary. Therefore, whether or not to perform the storage process may be switched in the second half period of the timing t2 according to the determination result of the 1-bit memory B1 written in the first half period of the timing t2. That is, when a determination result “less than Vx” is written in the 1-bit memory B1, an intermediate reset corresponding to the second case is performed. When the determination result “Vx or higher” is written in the bit memory B1, an intermediate reset corresponding to the third case is performed, and therefore the above-described storage process may be executed. However, even when an intermediate reset corresponding to the second case is performed, no particular problem occurs even if the above-described storage process is executed.

  When the above-described processing at the timing t2 is completed, an intermediate reset at the timing t3 is subsequently executed. At this time, the contents of the 1-bit memory B1 are checked, and a determination result “less than Vx” is written. If it is, an intermediate reset corresponding to the second case is performed, and if a determination result of “Vx or higher” is written, an intermediate reset corresponding to the third case is performed.

  First, in the second case where the reset to the reference potential Vx is necessary, the transistors T5 and T7 are turned on, the transistor T6 is turned off, and a voltage corresponding to the reference potential Vx (the fluctuation point P is the reference voltage Vref) is set as the reference voltage Vref. (The voltage output on the signal output line OUT when the potential is Vx). As also shown in the timing chart of FIG. 7, at timing t3, since the selection pulse is given together with the reset pulse, the potential at the variation point P is sequentially read out to the signal output line OUT. Therefore, the differential amplifier A1 can fulfill the function of controlling the voltage of the reset voltage setting line L1 so that the voltage value read on the signal output line OUT is equal to the reference voltage Vref. Thus, in the second case, a reset operation is performed such that the variation point P becomes the reference potential Vx.

  On the other hand, in the third case where the reset to the intermediate potential read immediately before is necessary, the transistor T7 is turned on and the transistors T5 and T6 are turned off. Since the transistor T5 is in the OFF state, the reference voltage Vref has no meaning in this case (it may be set at an arbitrary voltage). As also shown in the timing chart of FIG. 7, at timing t3, since the selection pulse is given together with the reset pulse, the potential at the variation point P is sequentially read out to the signal output line OUT. Therefore, the differential amplifier A1 has a reset voltage so that the voltage value read on the signal output line OUT is equal to the voltage at the upper end of the capacitive element C2 (that is, the voltage stored by the storage process). The function of controlling the voltage of the setting line L1 can be fulfilled. Thus, in the third case, a reset operation (refresh operation) is performed such that the voltage at the variation point P maintains the previous state.

  As described above, the control circuit shown in FIG. 17 has a function of performing control so that the voltage of the reset voltage setting line L1 becomes an appropriate value according to three cases. Furthermore, the function of outputting the detection result of the amount of received light to the outside via the output terminal E1 can be achieved. Here, the operation for outputting the detection result to the outside using this control circuit will be described in two types of output forms. In any output form, the detection result is output based on the voltage value of the signal output line OUT at the timing t0 (immediately before the periodic reset) shown in FIG.

  In the first output form, the detected value of the amount of received light is output as an analog voltage to the output terminal E1. In this case, at the timing t0, the transistor T6 is turned on and the transistors T5 and T7 are turned off. Since the transistor T5 is in the OFF state, the reference voltage Vref has no meaning in this case (it may be set at an arbitrary voltage). At this time, the polarity switching signal SW is supplied to invert ± of the input terminal of the differential amplifier A1 so that the upper input terminal in the drawing becomes “+” and the lower input terminal becomes “−”. Then, the differential amplifier A1 performs a control function such that the voltage of the output terminal E1 connected to the lower input terminal becomes equal to the voltage of the signal output line OUT connected to the upper input terminal. The voltage value of the signal output line OUT at that time is output as it is to the output terminal E1. After this output processing is completed, the inversion state of the input terminal of the differential amplifier A1 is canceled.

  The second output form is a form in which the detected value of the received light amount is output as a PWM (Pulse Width Modulation) signal to the output terminal E1. In this case, at the timing t0, the transistor T5 is turned on and the transistors T6 and T7 are turned off. As the reference voltage Vref, a voltage value that monotonously increases or monotonously decreases with time is given. As described above, when the reference voltage Vref is generated using a DA converter, the digital value is changed to 0 to 255 or 255 to 0 using a clock and a counter, and is stepped in 256 steps. A reference voltage Vref that changes the voltage may be given.

  The differential amplifier A1 determines the magnitude relationship between the reference voltage Vref and the voltage of the signal output line OUT, and outputs a signal indicating which is larger (actually, it can be handled as a binary signal). It fulfills the function of outputting to the terminal E1. Since the reference voltage Vref changes with time, the magnitude relationship between the reference voltage Vref and the voltage of the signal output line OUT is reversed at a predetermined time. This reverse phenomenon can be recognized by the fluctuation of the signal value output to the output terminal E1, and the detected value of the received light amount can be taken out as the time width until the reverse phenomenon occurs.

  The operation of the control circuit shown in the lower half of FIG. 17 has been described above. In order to drive the solid-state imaging device according to the present invention, in addition to this control circuit, a reset pulse is generated and a reset signal line is generated. Means for supplying to RST, means for generating a selection pulse and supplying to selection signal line SEL, reading the contents of 1-bit memory B1, ON / OFF control of transistors T5, T6, T7, setting of reference voltage Vref, differential A means for switching the polarity of the amplifier A1 is required. However, each of these means can be realized by a conventional general solid-state imaging device driving processor or the like and is obvious to those skilled in the art, and thus detailed description thereof is omitted here.

<<< §6. Control system suitable for 4-transistor type circuit >>>
Next, a control system suitable for a 4-transistor type circuit will be described. FIG. 18 is a circuit diagram showing an embodiment in which a control system circuit is added to the 4-transistor type circuit shown in FIG. The circuit for one pixel shown in the upper half of FIG. 18 is exactly the same as the circuit shown in FIG. The control circuit shown in the lower half of FIG. 18 is the same as the control circuit shown in the lower half of FIG. That is, the differential amplifier A10, the capacitive element C20, the 1-bit memory B10, and the transistors T50, T60, and T70 shown in FIG. 18 are respectively the differential amplifier A1, the capacitive element C2, the 1-bit memory B1, and the transistor T5 shown in FIG. It is a component equivalent to T6 and T7, and its basic function is also completely equivalent. However, the operation timing of the 3-transistor type circuit and the 4-transistor type circuit are slightly different. The operation of the control circuit shown in FIG. 18 will be briefly described below.

  The control circuit shown here is a control circuit suitable for the case where the modification example (unification of reset operation) described in §4 is applied to the four-transistor type embodiment described in §3. In this modification, it is necessary to control the voltage of the reset voltage setting line L10 by dividing it into the following three cases.

  First, the first case is a case of primary reset at timing t2 of the reset signal RST shown in FIG. In this case, it is necessary to set the voltage of the reset voltage setting line L10 to “a predetermined voltage necessary for resetting the detection point Q to the initial potential V0”. The second case is a case where a secondary reset is performed at the timing t4 of the reset signal RST shown in FIG. 16, and the intermediate potential read at the immediately preceding timing t3 is less than the reference potential Vx. In this case, it is necessary to set the voltage of the reset voltage setting line L10 to “a predetermined voltage necessary for resetting the detection point Q to the reference potential Vx”. Then, the third case is a case where a secondary reset is performed at timing t4 of the reset signal RST shown in FIG. In the case where there is no need to perform a secondary reset). In this case, it is necessary to set the voltage of the reset voltage setting line L10 to “a predetermined voltage necessary for resetting the detection point Q to the intermediate potential read at the immediately preceding timing t3”.

  If the control circuit shown in the lower half of FIG. 18 is used, voltage control in the above three cases can be accurately performed. This is because the control circuit has a function of performing feedback control based on the potential read value obtained on the signal output line OUT. That is, in the first case, reset is performed so that the detection point Q becomes the initial potential V0, in the second case, reset is performed so that the detection point Q becomes the reference potential Vx, and in the third case, It is necessary to perform reset so that the detection point Q becomes the intermediate potential read immediately before, but in any case, the potential of the detection point Q is set during the reset period (during the period corresponding to the width of the reset pulse). Reading on the signal output line OUT and sequentially monitoring it, and controlling the voltage of the reset voltage setting line L10 so that the read value becomes a predetermined target value, the potential at the detection point Q becomes a desired value. Such an accurate reset operation becomes possible.

  First, in the first case where resetting to the initial potential V0 is necessary, the transistors T50 and T70 are turned on, the transistor T60 is turned off, and the voltage corresponding to the initial potential V0 (the detection point Q is initially set) is set as the reference voltage Vref. When the potential is V0, a voltage output on the signal output line OUT is input. Also in this case, an analog output such as a DA converter may be used as the reference voltage Vref.

  As also shown in the timing chart of FIG. 16, since the selection pulse is given together with the reset pulse at the timing t2, the potential at the detection point Q is sequentially read out to the signal output line OUT. Therefore, the differential amplifier A1 can fulfill the function of controlling the voltage of the reset voltage setting line L10 so that the voltage value read on the signal output line OUT is equal to the reference voltage Vref. Thus, in the first case, a reset operation is performed so that the detection point Q becomes the initial potential V0.

  Subsequently, in the second case or the third case, which case is executed depends on the magnitude of the intermediate potential read at the timing t3 in the timing chart of FIG. is there. This control circuit has a function of recording the determination result of the magnitude of the intermediate potential in the 1-bit memory B10. The intermediate potential magnitude determination process and the writing process to the 1-bit memory B10 are actually performed in the first half period of the timing t3.

  That is, in the first half of the timing t3, the transistor T50 is turned on, the transistors T60 and T70 are turned off, and the reference voltage Vref is a voltage corresponding to the reference potential Vx (when the detection point Q is the reference potential Vx, The voltage output on the output line OUT is input. In such a state, when the voltage of the signal output line OUT is higher than the reference voltage Vref (when the potential of the detection point Q is equal to or higher than the reference potential Vx), the differential amplifier A10 outputs a low potential, and the signal When the voltage of the output line OUT is lower than the reference voltage Vref (when the potential at the detection point Q is less than the reference potential Vx), a high potential is output. In accordance with the two output potentials, a bit indicating a determination result of “more than Vx” or “less than Vx” is written in the 1-bit memory B10.

  Subsequently, in the latter half of the timing t3, the transistor T60 is turned on and the transistors T50 and T70 are turned off. Since the transistor T50 is in the OFF state, the reference voltage Vref has no meaning in this case (it may be set at an arbitrary voltage). At this time, the polarity switching signal SW is supplied to invert ± of the input terminal of the differential amplifier A10 so that the upper input terminal in the drawing becomes “+” and the lower input terminal becomes “−”. Then, the differential amplifier A10 performs a control function such that the voltage at the upper end of the capacitive element C20 connected to the lower input terminal becomes equal to the voltage of the signal output line OUT connected to the upper input terminal. Therefore, the capacitor C20 is in a state where electric charges corresponding to the voltage of the signal output line OUT at that time are accumulated. After this process is completed, the inversion state of the input terminal of the differential amplifier A10 is released.

  In short, this process is a process for recording the voltage of the signal output line OUT at the timing t3 by using the capacitive element C20, and the potential read value at the detection point Q at the timing t3 is temporarily stored. It is nothing but the saving process for saving. Such storage processing is necessary only when a secondary reset corresponding to the above-described third case (reset so that the detection point Q becomes the intermediate potential read immediately before) is performed at the subsequent timing t4. Yes, this is unnecessary when performing a secondary reset corresponding to the above-described second case (reset so that the detection point Q becomes the reference potential Vx) at the timing t4. Therefore, whether or not to perform the storage process may be switched in the second half period of timing t3 according to the determination result of the 1-bit memory B10 written in the first half period of timing t3. That is, when the determination result “less than Vx” is written in the 1-bit memory B10, the secondary reset corresponding to the second case is performed. If the determination result “Vx or higher” is written in the 1-bit memory B10, a secondary reset corresponding to the third case is performed, and therefore the above-described storage process may be executed. . However, even when the secondary reset corresponding to the second case is performed, there is no particular problem even if the storage process is executed.

  Now, when the above-described processing at the timing t3 is completed, the secondary reset is subsequently executed at the timing t4. At this time, the contents of the 1-bit memory B10 are checked, and a determination result “less than Vx” is written. If it is, a secondary reset corresponding to the second case is performed, and if a determination result of “Vx or higher” is written, a secondary reset corresponding to the third case is performed. Is called.

  First, in the second case where the reset to the reference potential Vx is necessary, the transistors T50 and T70 are turned on, the transistor T60 is turned off, and a voltage corresponding to the reference potential Vx (the detection point Q is the reference voltage) is set as the reference voltage Vref. (The voltage output on the signal output line OUT when the potential is Vx). As shown in the timing chart of FIG. 16, at timing t4, the selection pulse is given together with the reset pulse, so that the potential at the detection point Q is sequentially read out to the signal output line OUT. Therefore, the differential amplifier A10 can fulfill the function of controlling the voltage of the reset voltage setting line L10 so that the voltage value read on the signal output line OUT is equal to the reference voltage Vref. Thus, in the second case, a reset operation is performed so that the detection point Q becomes the reference potential Vx.

  On the other hand, in the third case where the reset to the intermediate potential read immediately before is necessary, the transistor T70 is turned on and the transistors T50 and T60 are turned off. Since the transistor T50 is in the OFF state, the reference voltage Vref has no meaning in this case (it may be set at an arbitrary voltage). As shown in the timing chart of FIG. 16, at timing t4, the selection pulse is given together with the reset pulse, so that the potential at the detection point Q is sequentially read out to the signal output line OUT. Therefore, the differential amplifier A10 has a reset voltage so that the voltage value read on the signal output line OUT is equal to the voltage at the upper end of the capacitive element C20 (that is, the voltage stored by the storage process). The function of controlling the voltage of the setting line L10 can be fulfilled. Thus, in the third case, a reset operation (refresh operation) is performed such that the voltage at the detection point Q maintains the previous state.

  As described above, the control circuit shown in FIG. 18 has a function of performing control so that the voltage of the reset voltage setting line L10 has an appropriate value according to three cases. Furthermore, the function of outputting the detection result of the amount of received light to the outside via the output terminal E10 can also be achieved. Here, the operation for outputting the detection result to the outside using this control circuit will be described in two types of output forms. In any output form, the detection result is output based on the voltage value of the signal output line OUT at the timing t1 (during periodic transfer processing) shown in FIG.

  In the first output form, the detected value of the received light amount is output as an analog voltage to the output terminal E10. In this case, at timing t1, the transistor T60 is turned on, and the transistors T50 and T70 are turned off. Since the transistor T50 is in the OFF state, the reference voltage Vref has no meaning in this case (it may be set at an arbitrary voltage). At this time, the polarity switching signal SW is supplied to invert ± of the input terminal of the differential amplifier A10 so that the upper input terminal in the drawing becomes “+” and the lower input terminal becomes “−”. Then, the differential amplifier A10 performs a control function such that the voltage of the output terminal E10 connected to the lower input terminal becomes equal to the voltage of the signal output line OUT connected to the upper input terminal. The voltage value of the signal output line OUT at that time is output as it is to the output terminal E10. After this output processing is completed, the inversion state of the input terminal of the differential amplifier A10 is released.

  The second output form is a form in which the detected value of the received light amount is output as a PWM (Pulse Width Modulation) signal to the output terminal E10. In this case, at timing t1, the transistor T50 is turned on, and the transistors T60 and T70 are turned off. As the reference voltage Vref, a voltage value that monotonously increases or monotonously decreases with time is given. As described above, when the reference voltage Vref is generated using a DA converter, the digital value is changed to 0 to 255 or 255 to 0 using a clock and a counter, and is stepped in 256 steps. A reference voltage Vref that changes the voltage may be given.

  The differential amplifier A10 determines the magnitude relationship between the reference voltage Vref and the voltage of the signal output line OUT, and outputs a signal indicating which is larger (actually, it can be handled as a binary signal). It fulfills the function of outputting to the terminal E10. Since the reference voltage Vref changes with time, the magnitude relationship between the reference voltage Vref and the voltage of the signal output line OUT is reversed at a predetermined time. This reverse phenomenon can be recognized by the fluctuation of the signal value output to the output terminal E10, and the detected value of the received light amount can be taken out as the time width until the reverse phenomenon occurs.

  The operation of the control circuit shown in the lower half of FIG. 18 has been described above. In order to drive the solid-state imaging device according to the present invention, in addition to this control circuit, a reset pulse is generated to generate a reset signal line. Means for supplying to RST; means for generating a selection pulse and supplying it to the selection signal line SEL; means for generating a transfer pulse and supplying it to the transfer signal line TNS; reading out the contents of the 1-bit memory B10; transistors T50, T60, T70 ON / OFF control, setting of the reference voltage Vref, means for switching the polarity of the differential amplifier A10, and the like are required. However, each of these means can also be realized by a conventional general solid-state imaging device driving processor and the like and is obvious to those skilled in the art, and thus detailed description thereof is omitted here.

<<< §7. Other modifications of the present invention >>>
Finally, some further modifications of the solid-state imaging device according to the present invention will be described.

(1) Modified example of setting a plurality of intermediate time points In the embodiments described above or the modified examples thereof, one intermediate time point is set within a predetermined period T and a predetermined process is executed. It is also possible to set two or more intermediate time points within the predetermined period T.

  For example, in the timing chart of FIG. 9, an intermediate time point (timing t2 and t3) is set at a position after an intermediate time M1 from the beginning of a predetermined period T, and intermediate potential reading and intermediate reset processing based on the result are performed. Is going. Here, the second intermediate time point is set at the position (M1 <M2 <T) of the intermediate time M2 at which more time has passed than the intermediate time M1, and the intermediate potential is read out even at the second intermediate time point. If the intermediate reset process based on the result is performed, the dynamic range can be further expanded. However, the reference potential used at the second intermediate time must be set lower than the reference potential used at the first intermediate time.

  FIG. 19 is a timing chart showing the state of potential fluctuation at the fluctuation point P when two intermediate time points are set within the predetermined period T. In this example, the first intermediate time point is set at a position where the intermediate time M1 has elapsed from the beginning of the predetermined period T, and the second intermediate time point is set at a position where the intermediate time M2 has elapsed from the beginning of the predetermined period T Has been. Further, the reference potential Vy at the second intermediate time point is set lower than the reference potential Vx at the first intermediate time point.

  The processing performed at each intermediate point is exactly the same as the embodiment described so far. For example, at the first intermediate time point, the potential at the fluctuation point P at that time point is read as the first intermediate potential, and when this is less than the first reference potential Vx, the potential at the fluctuation point P is An intermediate reset is performed so that the reference potential Vx is 1. Further, at the second intermediate time point, the potential at the fluctuation point P at that time point is read as the second intermediate potential, and when this is less than the second reference potential Vy, the potential at the fluctuation point P is An intermediate reset is performed so that the reference potential Vy is 2.

  FIG. 20 is a graph showing how the dynamic range is further expanded by setting two intermediate points in this way. The horizontal axis of this graph indicates the intensity of light irradiated to the photodiode PD, and the vertical axis indicates the signal level of the detection value indicating the amount of received light. The one-dot chain line graph is a conventional example, the two-dot chain line graph is an example of the present invention in which one intermediate time point is set, and the solid line graph is an example of the present invention in which two intermediate time points are set. In either case, the obtained signal level remains within the range of 0 to Lmax. However, in the example of the present invention in which two intermediate points are set, light within the range of 0 to I3 can be detected correctly. It can be seen that the dynamic range is further expanded.

  That is, in the solid line graph, a range of signal levels 0 to Lx is associated with light in the range of intensity 0 to I1, and a range of signal levels Lx to Ly is associated with light in the range of intensity I1 to I2. Are associated with a range of signal levels Ly to Lmax, and the dynamic range extends to a range of light intensities 0 to I3. The range shown on the right side of the timing chart of FIG. 19 shows the correspondence with these light intensity ranges.

  Of course, the number of intermediate points set within the predetermined period T is not limited to two, and three or more intermediate points can be set. Theoretically, any number of intermediate time points can be set as long as the lower reference potential is set for the subsequent intermediate time points.

  Further, the modification in which a plurality of intermediate points are set is applicable not only to the above-described three-transistor type embodiment but also to the four-transistor type embodiment. For example, in the timing chart of FIG. 16, an intermediate time point (timing t2 to t4) is set at a position where the intermediate time M1 has elapsed from the beginning of the predetermined period T, and primary reset, intermediate transfer processing, and secondary reset are performed. Here, the second intermediate time point is set at the position (M1 <M2 <T) of the intermediate time M2 at which more time has passed than the intermediate time M1, and the same processing is performed also at the second intermediate time point. By doing so, the dynamic range can be further expanded. In this case as well, the reference potential used at the second intermediate time must be set lower than the reference potential used at the first intermediate time. Further, the primary reset is performed only at the first intermediate point, and only the intermediate transfer process and the secondary reset are performed at the second intermediate point.

  Of course, it is possible to set three or more intermediate time points. In short, when applied to a four-transistor type, a plurality of intermediate time points are determined within a predetermined period T, and different reference potentials are set for each intermediate time point so that a lower reference potential is set for subsequent intermediate time points. It is only necessary to set and perform the primary reset only at the first intermediate time point, and at the second and subsequent intermediate time points, the secondary reset may be performed as necessary based on the read result of the intermediate potential.

(2) Modified example omitting potential reading at reset In the timing charts shown so far, when a reset pulse is supplied on the reset signal line RST, the selection pulse is always supplied on the selection signal line SEL. ing. This means that when resetting the fluctuation point P and the detection point Q, the potentials at these points can always be read and monitored on the signal output line OUT. Such a monitor is indispensable for performing the feedback control described in §5 and §6. However, when feedback control is not performed, it is not always necessary to read and monitor the potential at the variation point P or the detection point Q during the reset operation.

  For example, in the timing chart shown in FIG. 9, the selection pulse on the selection signal line SEL is supplied at the minimum at timing t2 (when reading the intermediate potential) and timing t0 (when reading the final potential at the end of the period T). All you need is enough. In the timing chart shown in FIG. 16, the selection pulse on the selection signal line SEL is supplied at the minimum at timing t3 (when reading the intermediate potential) and timing t1 (when reading the final potential at the end of the period T). All you need is enough.

  In practice, however, the characteristics of the MOS transistors T1 and T10 used for the reset operation often vary from lot to lot. Therefore, during the reset operation, the potential at the variation point P or the detection point Q is read and monitored. It is preferable to perform the feedback control described in §5 and §6. If feedback control is performed, it is possible to perform accurate control that absorbs variation in characteristics of each transistor constituting a circuit for each lot. Further, since the initial potential V0 is a reference potential for obtaining a detection value of the amount of received light, it is actually read out by performing readout at the reset operation regardless of whether or not feedback control is performed. The initial potential V0 is preferably used as a reference potential for obtaining a detection value of the amount of received light.

(3) Modification of Reset Pulse Waveform In the timing charts shown so far, the reset pulses are all drawn as rectangular pulses, but practically, like the reset pulse RST1 or RST2 shown in FIG. Although the rising edge is steep, it is preferable to use a pulse having a waveform in which the falling edge is gentle. This is because if the pulse having such a waveform is used for resetting, an effect of suppressing the influence of thermal noise can be obtained.

It is a circuit diagram which shows the circuit for one pixel of the conventional common 3 transistor type solid-state imaging device. 3 is a timing chart showing an operation of detecting the amount of received light by the circuit shown in FIG. 2 is a timing chart for explaining the reason why the “overexposure” phenomenon occurs in a solid-state imaging device including pixels having the configuration illustrated in FIG. 1. It is a circuit diagram which shows the circuit for one pixel of the 3 transistor type solid-state imaging device concerning this invention. 5 is a first timing chart showing an operation of detecting the amount of received light by the circuit according to the present invention shown in FIG. FIG. 5 is a second timing chart showing an operation of detecting the amount of received light by the circuit according to the present invention shown in FIG. 4. FIG. 5 is a third timing chart showing an operation of detecting the amount of received light by the circuit according to the present invention shown in FIG. FIG. 5 is a fourth timing chart showing an operation of detecting the amount of received light by the circuit according to the present invention shown in FIG. 5 is a timing chart showing that the dynamic range is widened by the operation of detecting the amount of received light by the circuit according to the present invention shown in FIG. It is a graph which shows a mode that a dynamic range spreads by this invention. It is a circuit diagram which shows the circuit for one pixel of the conventional general 4 transistor type solid-state imaging device. 12 is a timing chart showing an operation of detecting the amount of received light by the circuit shown in FIG. 12 is a timing chart for explaining the reason why a “whiteout” phenomenon occurs in a solid-state imaging device including pixels having the configuration shown in FIG. 11. It is a circuit diagram which shows the circuit for one pixel of the 4 transistor type solid-state imaging device concerning this invention. FIG. 15 is a first timing chart showing an operation of detecting the amount of received light by the circuit according to the present invention shown in FIG. 14. FIG. 15 is a second timing chart showing an operation of detecting the amount of received light by the circuit according to the present invention shown in FIG. 14. FIG. 5 is a circuit diagram showing an embodiment in which a control system circuit is added to the three-transistor type circuit shown in FIG. 4. FIG. 15 is a circuit diagram showing an embodiment in which a control system circuit is added to the 4-transistor type circuit shown in FIG. 14. 5 is a timing chart showing the state of potential fluctuation at a fluctuation point P when two intermediate time points are set within a predetermined period T. It is a graph which shows a mode that a dynamic range further expands by setting two intermediate | middle time points. It is a graph which shows the waveform of the reset pulse useful in reducing thermal noise.

Explanation of symbols

A1, A10... Differential amplifiers B1, B10... 1 bit memory C1... Capacitance element (parasitic capacitance of photodiode PD)
C2: Capacitance element C10: Capacitance element (parasitic capacitance of photodiode PD and transistor T40)
C20: Capacitance elements E1, E10: Output terminals G1-G6: Graphs I1, I2, I3 showing potential drop at fluctuation point P ... Light intensity J ... Current sources L1, L10 ... Reset voltage setting lines Lx, Ly ... Signal level Lmax ... Maximum signal levels M1, M2 ... Intermediate time OUT ... Signal output line P ... Variation point PD ... Photodiode Q ... Detection point (floating diffusion terminal)
RST ... Reset signal line RST1, RST2 ... Reset pulse SEL ... Selection signal line SW ... Polarity switching signal T ... Predetermined period T1-T4 ... N-type MOS transistors T5-T7 ... Transistors T10-T40 ... N-type MOS transistors T50-T70 ... Transistor TNS: Transfer signal line t0 to t4: Timing on time axis (having time width)
V0 to V6 ... potential value VDD ... power supply line Vmin ... lowest potential level Vref that detection point Q can take ... reference voltages Vx, Vx ', Vy ... reference potential ΔV ... potential difference ΔVmax ... maximum value of potential difference

Claims (11)

A solid-state imaging device configured by arranging a large number of pixels having a function of outputting an electrical signal corresponding to the amount of received light,
Individual pixels
A photodiode whose one end is fixed at a constant potential and whose other end functions as a variation point P that generates a potential variation according to the amount of received light;
A reset MOS transistor for resetting the variation point P to a predetermined potential;
A reading MOS transistor for reading out the potential of the fluctuation point P to the outside;
In addition,
Reset means for periodically resetting each pixel with a predetermined period T so that the variation point P becomes a predetermined initial potential higher than the constant potential by giving a signal to the reset MOS transistor ;
By applying a signal to the readout MOS transistor, the potential at the variation point P immediately before the periodic reset by the resetting unit is read from each pixel, and the difference between the read potential and the initial potential is received by light reception for the pixel. A potential reading means for outputting an electric signal indicating the quantity;
With
The potential reading means has a function of reading the potential at the fluctuation point P at an intermediate time point of the predetermined period T as an intermediate potential;
It said reset means, when the intermediate potential is lower than a predetermined reference potential, so that the potential of the change point P is the reference potential, the have rows intermediate reset at an intermediate point, the intermediate potential is the reference A solid-state imaging device having a function of performing an intermediate reset at the intermediate point so that the potential at the fluctuation point P becomes the intermediate potential when the potential is equal to or higher than the potential . The solid-state imaging device according to claim 1,
A solid-state imaging device, wherein the potential reading means reads the potential at the fluctuation point P at the time of periodic reset by the resetting means, and uses this as the initial potential value. The solid-state imaging device according to claim 1 or 2,
  A solid-state imaging device characterized in that the reset means performs feedback control based on a read value by the potential reading means, so that the changing point P is reset to an initial potential, a reference potential, or an intermediate potential. The solid-state imaging device according to claim 3,
  When the reset means performs the feedback control so that the difference between the read value by the potential read means and the reference value set corresponding to the reference potential is zero when the intermediate potential is less than the reference potential. If an intermediate reset is performed and the intermediate potential is equal to or higher than the reference potential, feedback control is performed so that the difference between the read value immediately before the intermediate reset by the potential reading means and the read value at the intermediate reset is zero. A solid-state imaging device that performs resetting. In the solid-state imaging device according to any one of claims 1 to 4,
  A solid-state imaging device, wherein a plurality of intermediate time points are defined within a predetermined period T, and different reference potentials are set for each intermediate time point so that a lower reference potential is set for subsequent intermediate time points. A solid-state imaging device configured by arranging a large number of pixels having a function of outputting an electrical signal corresponding to the amount of received light,
  Individual pixels
  A photodiode whose one end is fixed at a constant potential and whose other end functions as a variation point P that generates a potential variation according to the amount of received light;
  A detection MOS transistor having one end connected to the variation point P and the other end serving as a detection point Q;
  A reset MOS transistor for resetting the variation point P to a predetermined potential;
  A reading MOS transistor for reading out the potential of the detection point Q to the outside;
  In addition,
  By controlling the gate voltage of the detection MOS transistor, for each pixel, the detection MOS transistor is periodically turned on periodically at a predetermined period T, and the negative charge accumulated at the fluctuation point P is detected. Charge transfer means for performing periodic transfer processing to transfer to the point Q;
  Resetting means for performing a primary reset for each pixel by giving a signal to the reset MOS transistor so that the detection point Q becomes a predetermined initial potential higher than the constant potential at an intermediate time point of the predetermined period T; ,
  By applying a signal to the readout MOS transistor, the potential of the detection point Q at the time when the periodic transfer processing by the charge transfer means is performed is read from each pixel, and the difference between the read potential and the initial potential A potential reading means for outputting as an electric signal indicating the amount of light received for the pixel;
  With
  The charge transfer means has a function of performing an intermediate transfer process for transferring negative charges accumulated at the fluctuation point P to the detection point Q immediately after the primary reset,
  The potential reading means has a function of reading the potential at the detection point Q at the time when the intermediate transfer process is performed as an intermediate potential,
  The reset means performs a secondary reset immediately after the intermediate transfer process so that the potential of the detection point Q becomes the reference potential when the intermediate potential is less than a predetermined reference potential, and the intermediate potential A solid-state imaging device having a function of performing a secondary reset immediately after the intermediate transfer process so that the potential of the detection point Q becomes the intermediate potential when is equal to or higher than the reference potential. The solid-state imaging device according to claim 6,
  A solid-state imaging device characterized in that the potential reading means reads the potential of the detection point Q at the time of the primary reset by the reset means and uses this as the value of the initial potential. The solid-state imaging device according to claim 6 or 7,
  A solid-state imaging device characterized in that the reset means performs feedback control based on a read value by the potential reading means, thereby resetting the detection point Q to an initial potential, a reference potential, or an intermediate potential. The solid-state imaging device according to claim 8,
  When the reset means performs the feedback control so that the difference between the read value by the potential read means and the reference value set corresponding to the reference potential is zero when the intermediate potential is less than the reference potential. When the secondary reset is performed and the intermediate potential is equal to or higher than the reference potential, the feedback control is performed so that the difference between the read value immediately before the secondary reset by the potential reading unit and the read value at the secondary reset becomes zero. A solid-state imaging device, wherein a secondary reset is performed. The solid-state imaging device according to any one of claims 6 to 9,
  A plurality of intermediate time points are determined within a predetermined period T, and different reference potentials are set for each intermediate time point so that lower reference potentials are set in subsequent intermediate time points, and the primary reset is performed only at the first intermediate time point. A solid-state imaging device characterized in that, at the second and subsequent intermediate points, a secondary reset is performed as necessary based on the readout result of the intermediate potential.   In the solid-state imaging device according to any one of claims 1 to 10,
  The potential reading means includes a first MOS transistor and a second MOS transistor connected in series to each other, and a current source for causing a current to flow through a current path formed by the pair of MOS transistors, Reading is performed by connecting the fluctuation point P or the detection point Q to the gate of one MOS transistor and giving a selection signal for selecting the reading operation for the pixel to the gate of the second MOS transistor. A solid-state imaging device.