JP5460248B2 - Solid-state image sensor - Google Patents

Description

  The present invention relates to a CMOS (Complementary Metal Oxide Semiconductor) type solid-state imaging device.

  A conventional solid-state imaging device will be described with reference to FIG.

  FIG. 11 shows a circuit configuration of one pixel in a conventional solid-state imaging device. As shown in FIG. 11, the pixel includes a switching circuit 200 and a photodiode 210. The switching circuit includes a transfer (transfer) transistor TRt, a capacitor C, a reset transistor TRr, a sense amplifier transistor TRa, and a switching transistor TRs. Composed.

  An address line A1, a transfer control line T, and a reset line R are arranged along the pixel row. The transfer control line T and the reset line R are connected to a vertical scanning circuit (not shown). A signal line L1 and a bias line B are arranged along the pixel column.

  Next, the operation of the conventional solid-state imaging device will be described with reference to FIG. As shown in FIG. 12, when the global shutter input mode of the short exposure method is assumed, the vertical scanning circuit simultaneously sets the H (high) level to the reset line R for all the rows according to the input of the trigger signal. Send all reset signals for a moment. At the same time, the vertical scanning circuit sends all transfer signals of H level to the transfer control lines T of all rows for a moment. As a result, the pixel signals stored in the photodiodes 210 and the capacitors C of all the pixels are emitted through the reset transistor TRr, and the photodiodes 210 and the capacitors C of all the pixels are reset.

  Subsequently, the vertical scanning circuit retransmits all H level transfer signals for a moment before negating (invalidating) the vertical synchronization signal. As a result, the transfer transistor TRt is turned off for a short time, and the photodiodes 210 of all the pixels are simultaneously exposed in the meantime. In all pixels, the pixel signal is transferred from the photodiode 210 to the capacitor C through the transfer transistor TRt at the time when all the transfer signals are retransmitted, and the pixel signal is temporarily stored in these capacitors C.

  Subsequently, the vertical scanning circuit transmits an address line selection signal for each row. As a result, the pixel signal obtained by simultaneous exposure of all pixels is sent to the sense amplifier transistor TRa and amplified. Further, the amplified pixel signal can be sent to the signal line L1 through the switching transistor TRs to obtain an image signal.

JP 2004-159155 A

  However, in the conventional solid-state imaging device, the capacitor C disposed between the photodiode 210 and the sense amplifier transistor TRa is a so-called FD (floating diffusion) portion and has a large dark current. For this reason, there is a problem that a pixel that retains electric charge for a time corresponding to one frame causes white defects and deteriorates image quality.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to obtain a solid-state imaging device capable of global operation while suppressing deterioration in image quality.

  In order to achieve the above object, a solid-state imaging device according to the present invention is arranged in a matrix, each provided with a plurality of pixels that output an electrical signal corresponding to the amount of received light, and for each column. A plurality of column signal lines that sequentially transfer electrical signals output from the plurality of pixels, and a first holding circuit that is provided for each column and holds the electrical signals transferred from the pixels through the column signal lines of the corresponding columns; And a second holding circuit for holding an output signal from the first holding circuit.

  According to the solid-state imaging device of the present invention, during a global operation, an electrical signal corresponding to the amount of received light is transferred from the pixel circuit to the first holding circuit, then transferred to the second holding circuit and held, and then the frame An electrical signal can be output from the second holding circuit to the outside of the solid-state imaging device after a predetermined waiting time corresponding to an external request such as a rate has elapsed. In this way, two types of holding circuits that hold the electric signals output from each pixel are arranged outside the pixel that is not easily restricted by the circuit area, and a relatively large capacitor is used for each holding circuit. For example, it is possible to hold an electric signal with lower noise than a pixel for a long time.

  In the solid-state imaging device of the present invention, the first holding circuit receives the first capacitor that holds the first electric signal in the initialization state of the corresponding pixel, and the second electric signal after receiving light from the corresponding pixel. The solid-state imaging device is provided for each column, and is held in the first capacitor and the second capacitor of the first holding circuit in the corresponding column. It is preferable to further include a difference circuit that takes a difference between the second electric signal and the second electric signal, and the second holding circuit holds the difference electric signal in the difference circuit.

  In this case, a plurality of electric signals in an initialization state in a pixel corresponding to one period are output, and then a plurality of electric signals after light reception in a pixel corresponding to another period are output. In addition, since the difference between the initialization signal of the corresponding pixel and the signal after light reception can be obtained, the area of each holding circuit can be obtained by holding it in the second holding circuit constituted by the capacity of one pixel unit. Can be reduced.

  In the solid-state imaging device of the present invention, each pixel is generated by a photodiode that generates a charge corresponding to the amount of received light, a transfer transistor connected to the output side of the photodiode, and transferred via the transfer transistor. The floating diffusion part that converts the generated charge into a voltage, the reset transistor that sets the floating diffusion part to the initialized state, and the gate is connected to the floating diffusion part, and an electric signal corresponding to the voltage converted by the floating diffusion part Each pixel is grouped into a plurality of predetermined rows, and the gates of the reset transistor and the transfer transistor included in the pixels of each group are commonly connected to each group. It may be.

  In this way, it is possible to output a plurality of electrical signals in the initialized state in the pixels corresponding to one period, and then output a plurality of electrical signals after light reception in the pixels corresponding to other periods.

  In the solid-state imaging device of the present invention, the first holding circuit has a capacity for holding an electrical signal in an initialization state of the corresponding pixel, and the solid-state imaging device is provided for each column, and the corresponding column A difference circuit for taking a difference between the first electric signal in the initialization state of the corresponding pixel held in the capacitor of the first holding circuit and the first electric signal after receiving light from the corresponding pixel; The second holding circuit preferably holds a difference electric signal in the difference circuit.

  In this case, even when the electrical signal in the initialization state in the corresponding pixel and the electrical signal after light reception in the corresponding pixel are alternately output, the initialization signal of the corresponding pixel and the signal after light reception are Therefore, the area of each holding circuit can be reduced by holding in the second holding circuit configured by the capacity of one pixel unit.

  In the solid-state imaging device of the present invention, each pixel is generated by a photodiode that generates a charge corresponding to the amount of received light, a transfer transistor connected to the output side of the photodiode, and transferred via the transfer transistor. The floating diffusion part that converts the generated charge into a voltage, the reset transistor that sets the floating diffusion part to the initialized state, and the gate is connected to the floating diffusion part, and an electric signal corresponding to the voltage converted by the floating diffusion part Each pixel has a temporally overlapping signal applied to the gates of the reset transistors in a plurality of rows, and a temporally overlapping signal applied to the gates of the transfer transistors in the plurality of rows. Have It may be.

  By doing this, it is possible to alternately output the electrical signal in the initialized state in the corresponding pixel and the electrical signal after light reception in the corresponding pixel.

  In the solid-state imaging device of the present invention, the first holding circuit and the second holding circuit may hold the electrical signal as an analog value.

  In this way, it is possible to hold a signal that maintains a gradation with a small capacity.

  In the solid-state imaging device of the present invention, the capacitance value of the first holding circuit may be larger than the capacitance value of the second holding circuit.

  In this way, noise generated in the first holding circuit can be made smaller than noise generated in the second holding circuit.

  According to the solid-state imaging device according to the present invention, it is possible to obtain a solid-state imaging device capable of global operation while suppressing deterioration in image quality.

It is a block diagram which shows the structure of the solid-state image sensor which concerns on one Embodiment of this invention. It is a circuit diagram which shows the structural example for 1 column 2 rows of the pixel in the solid-state image sensor which concerns on one Embodiment of this invention. It is a timing chart which shows the time change of the main signal in the solid-state image sensing device concerning the 1st example of one embodiment of the present invention. It is a timing chart which shows the time change of the main signal in the solid-state image sensing device concerning the 2nd example of one embodiment of the present invention. (A) is a timing chart which shows the output form of the solid-state image sensor which concerns on 1st Example of one Embodiment of this invention. (B) is a timing chart which shows the output form of the solid-state image sensor which concerns on 2nd Example of 1 embodiment of this invention. FIG. 9 is a circuit diagram illustrating a holding circuit of the solid-state imaging device according to the first example of the first embodiment of the present invention. It is a drive timing chart of the holding circuit and difference circuit which concern on 3rd Example of one Embodiment of this invention. It is a drive timing chart of the holding circuit and difference circuit which concern on 3rd Example of one Embodiment of this invention. FIG. 14 is a circuit diagram illustrating a holding circuit of the solid-state imaging device according to the second example, which is a fourth example of the embodiment of the present invention. It is a drive timing chart of the holding circuit which concerns on 4th Example of one Embodiment of this invention. It is a circuit diagram which shows the structure of 1 pixel in the conventional solid-state image sensor. It is a timing chart explaining operation | movement of the conventional solid-state image sensor.

(One embodiment)
An embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a block configuration of a solid-state imaging device according to the present embodiment.

  As shown in FIG. 1, the solid-state imaging device according to this embodiment includes, for example, a pixel circuit 1 in which a plurality of pixels are arranged in a matrix, a first holding circuit 2, a first difference circuit 3, A second holding circuit 4, a second difference circuit 5, an output line 6, a horizontal scanning circuit 7, and a vertical scanning circuit 8 are provided.

  A reference output and a signal output are output from the pixel circuit 1. The first holding circuit 2 holds the reference output and the signal output or only the reference output. The first difference circuit 3 is output from the difference output between the reference output and the signal output held in the first holding circuit 2 or the reference output and the pixel circuit 1 held in the first holding circuit 2. The difference output with the signal output is output. The second holding circuit 4 holds the difference output output from the first difference circuit 3. The second difference circuit 5 makes a difference between the difference output held in the second holding circuit 4 and the reference voltage, and this difference signal is output to the output line 6 in synchronization with the output of the horizontal scanning circuit 7. . The vertical scanning circuit 8 outputs a pulse signal to the pixel circuit 1, the first holding circuit 2, and the second holding circuit 4.

  FIG. 2 shows a specific example of pixels for one column and two rows in the pixel circuit 1. In FIG. 2, reference numerals 1-1 and 1-2 each indicate a pixel unit, and the pixel unit 1-1 includes a photodiode 10, a transfer transistor 11, a reset transistor 12, and an output transistor 13. Similarly to the pixel unit 1-1, the pixel unit 1-2 includes a photodiode 15, a transfer transistor 16, a reset transistor 17, and an output transistor 18.

  In the pixel unit 1-1, the photodiode 10 has an anode grounded and a cathode connected to the drain of the transfer transistor 11. The transfer transistor 11 has a source connected to the source of the reset transistor 12 and the gate of the output transistor 13, and a gate connected to the terminal 23. A region including the source of the transfer transistor 11, the source of the reset transistor 12, and the gate of the output transistor 13 forms a diffusion capacitance called a floating diffusion portion (hereinafter referred to as an FD portion). The reset transistor 12 has a drain connected to the power supply and a gate connected to the terminal 22. The output transistor 13 has a drain connected to the power supply and a source connected to the drain of the row selection transistor 14. The current source 20 is connected to the column signal line 21. The row selection transistor 14 forms a source follower by the output transistor 13 and the current source 20 when the gate is connected to the terminal 24 and is conductive.

  Also in the pixel unit 1-2, the photodiode 15 has an anode grounded and a cathode connected to the drain of the transfer transistor 16. The transfer transistor 16 has a source connected to the source of the reset transistor 17 and the gate of the output transistor 18, and a gate connected to the terminal 26. A region including the source of the transfer transistor 16, the source of the reset transistor 17, and the gate of the output transistor 18 forms a diffusion capacitance called an FD portion. The reset transistor 17 has a drain connected to the power supply and a gate connected to the terminal 25. The output transistor 18 has a drain connected to the power supply and a source connected to the drain of the row selection transistor 19. The row selection transistor 19 forms a source follower by the output transistor 18 and the current source 20 when the gate is connected to the terminal 27 and is conductive.

  The output signals of the pixel units 1-1 and 1-2 are output to the column signal line 21 via the row selection transistor 14 and the row selection transistor 19, respectively. The column signal line 21 is input to the first holding circuit 2 shown in FIG.

(First example of one embodiment)
FIG. 3 is a timing chart showing temporal changes of main signals in the solid-state imaging device according to the first example of the present embodiment.

  FIG. 3 shows control signals applied to the terminals shown in FIG. Each control signal is represented by a symbol with S added to the symbol of an applied terminal.

  A signal S22 shown in FIG. 3 is applied to the terminal 22 and input to the gate of the reset transistor 12. The signal S23 is applied to the terminal 23 and input to the gate of the transfer transistor 11. The signal S24 is applied to the terminal 24 and input to the gate of the row selection transistor 14. The signal S25 is applied to the terminal 25 and input to the gate of the reset transistor 17. The signal S26 is applied to the terminal 26 and input to the gate of the transfer transistor 16. The signal S27 is applied to the terminal 27 and input to the gate of the row selection transistor 19. The signal SV is output to the column signal line 21.

  Below, the 1st drive method of the solid-state image sensor which concerns on 1st Example is demonstrated, referring FIG.2 and FIG.3.

  As shown in FIG. 3, first, in a period t1, the signals S22, S24, and S25 are set to “HIGH (high)”, and the gates of the reset transistors 12 and 17 of each pixel unit are set to “HIGH” to be turned on. The unit's FD section is simultaneously connected to the power source to be in the initial state. Further, the gate of the row selection transistor 14 is also set to “HIGH” to make it conductive. As a result, the potential of the FD portion in the initial state of the pixel unit 1-1 is output to the column signal line 21 via the source follower including the output transistor 13 and the current source 20 (period of signal SV in FIG. 3). Vref value at t1).

  Next, in a period t2, the signals S22, S25, and S27 are set to “HIGH”, the gates of the reset transistors 12 and 17 for each pixel unit are set to “HIGH”, and the FD unit for each pixel unit is simultaneously connected to the power source. To maintain the initial state. Further, the gate of the row selection transistor 19 becomes “HIGH” and becomes conductive, and the potential of the FD portion in the initial state of the pixel unit 1-2 is a column signal via the source follower including the output transistor 18 and the current source 20. It is output to the line 21 (Vref value in the period t2 of the signal SV in FIG. 3).

  Next, in a period t3, the signals S22 and S25 maintain “HIGH”, and the signals S24 and S27 become “LOW”. Note that in FIG. 2, pixels for two rows are taken as an example, and in fact, when the pixel unit has three or more rows, the Vref value is output to the signal SV even in the period t3. Nor.

  Next, in the period t4, all signals are “LOW”.

  Next, in the period t5, the signals S23, S24, and S26 become “HIGH”, the gates of the transfer transistors 11 and 16 for each pixel unit are set to “HIGH”, and the transistors 10 and 15 for each pixel unit are turned on. The accumulated charge is transferred to the FD unit. A voltage is generated at each gate of the output transistors 13 and 18 by the transferred charge and the capacitance of the FD portion. In addition, the gate of the row selection transistor 14 is also set to “HIGH” to conduct, and the potential of the FD portion of the pixel unit 1-1 is output to the column signal line 21 via the source follower constituted by the output transistor 13 and the current source 20. (V1 value during the period t5 of the signal SV in FIG. 3).

  Next, in the period t6, the signals S23 and S26 maintain “HIGH”, and voltage continues to be generated at the gates of the output transistors 13 and 18 due to the transferred charges and the capacitance of the FD portion. In addition, the row selection transistor 19 is turned on by “HIGH” of the signal S27, and the potential of the FD portion of the pixel unit 1-2 is changed to the column signal line 21 via the source follower including the output transistor 18 and the current source 20. (V2 value in period t6 of signal SV in FIG. 3).

  As described above, the period T1 during which the reset transistors 12 and 17 of the pixel units 1-1 and 1-2 are simultaneously turned on to output the signal output (Vref) corresponding to the initial state of the FD unit, and the pixel unit 1- The first and second transfer transistors 11 and 16 are simultaneously turned on, and a first period of the pixel circuit 1 having a period T2 in which signal outputs (V1 and V2) corresponding to the charges accumulated in the photodiodes 10 and 15 are output. The driving method has been described.

(Second example of one embodiment)
FIG. 4 is a timing chart showing temporal changes of main signals in the solid-state imaging device according to the second example of the present embodiment.

  FIG. 4 shows control signals applied to the terminals shown in FIG. Each control signal is represented by a symbol with S added to the symbol of an applied terminal. The signals S22 to S27 and SV shown in FIG. 4 are the same as the signals shown in FIG.

  Hereinafter, a second driving method of the solid-state imaging device according to the second embodiment will be described with reference to FIGS.

  A signal S22 shown in FIG. 4 is a signal applied to the terminal 22, and is applied to the gate of the reset transistor 12 of the pixel unit 1-1 to make the reset transistor 12 conductive during the periods t1, t2, and t3. . The signal S23 is a signal applied to the terminal 23, and is applied to the gate of the transfer transistor 11 of the pixel unit 1-1 to make the transfer transistor 11 conductive during the periods t7 and t8. The signal S24 is a signal applied to the terminal 24, and is applied to the gate of the row selection transistor 14 of the pixel unit 1-1 to make the row selection transistor 14 conductive during the periods t3 and t9. The signal S25 is applied to the terminal 25 and is applied to the gate of the reset transistor 17 of the pixel unit 1-2 to make the reset transistor 17 conductive during the periods t2, t3, t4, and t5. The signal S26 is a signal applied to the terminal 26, and is applied to the gate of the transfer transistor 16 of the pixel unit 1-2 to make the transfer transistor 16 conductive during the periods t8, t9, and t10. The signal S27 is a signal applied to the terminal 27, and is applied to the gate of the row selection transistor 19 of the pixel unit 1-2 to make the row selection transistor 19 conductive during the periods t5 and t11. The signals S22 and S25 applied to the reset transistor 12 in the pixel unit 1-1 and the reset transistor 17 in the pixel unit 1-2 are simultaneously “HIGH” during the periods t2 and t3. The periods t1 and t4 + t5 , The signal S25 has the same “HIGH” period as the signal S22, and is therefore a signal delayed by the period t1. Similarly, the signals S23 and S26 applied to the transfer transistor 11 of the pixel unit 1-1 and the transfer transistor 15 of the pixel unit 1-2 are “HIGH” at the same time, the period t8, and the periods t7 and t9 + t10. , The signal S26 has the same “HIGH” period as the signal S23, and is therefore a signal delayed by the period t7.

  First, the pixel unit 1-1 will be described.

  As shown in FIG. 4, in the periods t1, t2 and t3, the signal S22 becomes “HIGH”, the gate of the reset transistor 12 becomes “HIGH” and becomes conductive, and the FD portion is connected to the power source to be in the initial state. . In the period t3, since the signal S24 becomes “HIGH”, the gate of the row selection transistor 14 becomes “HIGH” and becomes conductive. As a result, the potential of the FD portion in the initial state is output to the column signal line 21 via the source follower constituted by the output transistor 13 and the current source 20 (Vref value in the period t3 of the signal SV in FIG. 4).

  Subsequently, in the periods t7 and t8, the signal S23 becomes “HIGH”, and the gate of the transfer transistor 11 is set to “HIGH” to be conducted. Thereby, the electric charge accumulated in the photodiode 10 of the pixel unit 1-1 is transferred to the FD portion. A voltage is generated at the gate of the output transistor 13 by the transferred charge and the capacitance of the FD portion. In the period t9, since the signal 24 becomes “HIGH” again, the gate of the row selection transistor 14 becomes “HIGH” and becomes conductive. The potential of the FD portion is output to the column signal line 21 via the source follower including the output transistor 13 and the current source 20 (V1 value in the period t9 of the signal SV in FIG. 4).

  Next, the pixel unit 1-2 will be described.

  In periods t2, t3, t4, and t5, the signal S25 becomes “HIGH”, the gate of the reset transistor 17 becomes “HIGH”, and the FD portion is connected to the power source to be in an initial state. In the period t5, since the signal 27 becomes “HIGH”, the gate of the row selection transistor 19 becomes “HIGH” and becomes conductive. As a result, the potential of the FD portion in the initial state is output to the column signal line 21 via the source follower constituted by the output transistor 18 and the current source 20 (Vref value in the period t5 of the signal SV in FIG. 4).

  Subsequently, in the periods t8, t9, and t10, the signal S26 becomes “HIGH”, and the gate of the transfer transistor 16 is set to “HIGH” to be conducted. Thereby, the electric charge accumulated in the photodiode 15 of the pixel 1-2 is transferred to the FD portion. A voltage is generated at the gate of the output transistor 18 due to the transferred charge and the capacitance of the FD portion. In the period t11, since the signal S27 becomes “HIGH” again, the gate of the row selection transistor 19 becomes “HIGH” and becomes conductive. The potential of the FD portion is output to the column signal line 21 via the source follower including the output transistor 18 and the current source 20 (V2 value in the period t11 of the signal SV in FIG. 4).

  Here, if the time widths of the periods t1, t4 + t5, t7, and t9 + t10 are the same (this time width is assumed to be t), the output signal SV output from the pixel unit 1-1 to the column signal line 21 is in the period t3. Vref and V1 in the period t9, and the output signal SV output from the pixel unit 1-2 to the column signal line 21 becomes Vref in the period t5 and V2 in the period t11. Accordingly, the output of the pixel unit 1-2 has an output format delayed by the time width t from the output of the pixel unit 1-1.

  As described above, the second driving method of the pixel circuit 1 in which the signals applied to the reset transistors 12 and 17 and the transfer transistors 11 and 16 in the pixel units in different rows are applied with a delay by the same time width t has been described.

  5A and 5B show output waveforms output to the column signal line 21 when the pixel unit is arranged in three or more rows in the row direction.

  FIG. 5A corresponds to the first driving method shown in FIG. 3, and shows an output waveform when the reset transistors of the pixel units in a plurality of rows are simultaneously turned on and then the transfer transistors are turned on simultaneously. . After a plurality of signal outputs Vref corresponding to the initial state of the FD section are output, signal outputs V1, V2, V3, V4 and V5 corresponding to the charges accumulated in the photodiode are output.

  FIG. 5B corresponds to the second driving method shown in FIG. 4, and an output waveform when signals applied to the reset transistor and the transfer transistor in units of pixels are applied with a delay of the same time width. It is. After the signal output Vref corresponding to the initial state of the FD portion is output for one pixel, the signal output V1 for one pixel corresponding to the charge accumulated in the photodiode is output. After that, Vref, V2, Vref, V3, Vref, V4, Vref and V5, and a signal output corresponding to the initial state of the FD section and a signal output for one pixel corresponding to the charge accumulated in the photodiode are alternately output. Is done.

(Third example of one embodiment)
FIG. 6 shows a third embodiment corresponding to the first embodiment, in which a plurality of signal outputs Vref corresponding to the initial state of the FD section shown in FIG. 2 shows one column and two rows of the first holding circuit, the difference circuit, and the second holding circuit when the signal outputs V1, V2, V3, V4, and V5 corresponding to the charges accumulated in are output.

  As shown in FIG. 6, the gates of the transistors 30, 31, 32, 33, 36, 40, 41, 42, 43, 46, 48, 51, 52, 54, 801, 802, 803, 804, 816 and 815 Are connected to terminals 61, 64, 62, 63, 60, 66, 69, 67, 68, 65, 70, 71, 73, 74, 822, 821, 824, 823, 825 and 826, respectively.

  The capacitor 34 is connected to the transistors 30 and 32, the capacitor 35 is connected to the transistors 31 and 33, the capacitor 44 is connected to the transistors 40 and 42, the capacitor 45 is connected to the transistors 41 and 43, and the capacitors 49 and 50 are output. Connected to the line 56, the capacitor 53 is connected to the transistor 52, and the capacitor 55 is connected to the transistor 54. The capacitors 813 and 814 are connected to the output line 805.

  The transistors 37 and 47 form a source follower together with the current source 38 when the transistors 36 and 46 are turned on, respectively.

  Here, reference numeral 75 indicates a first holding circuit, reference numeral 76 indicates a first difference circuit, reference numeral 77 indicates a second holding circuit, and reference numeral 820 indicates a second difference circuit.

  FIG. 7 is a timing chart showing temporal changes of main signals in the first holding circuit, the first difference circuit, and the second holding circuit of the solid-state imaging device according to the third embodiment. FIG. 8 is a timing chart showing temporal changes between the second holding circuit and the second difference circuit.

  FIG. 7 shows control signals applied to the terminals shown in FIG. Each control signal is represented by a symbol with S added to the symbol of an applied terminal.

  A signal S21 illustrated in FIG. 7 indicates an output signal output to the column signal line 21. The signal S60 is applied to the terminal 60 and input to the gate of the transistor 36. The signal S61 is applied to the terminal 61 and input to the gate of the transistor 30. The signal S64 is applied to the terminal 64 and input to the gate of the transistor 31. The signal S62 is applied to the terminal 62 and input to the gate of the transistor 32. The signal S63 is applied to the terminal 63 and input to the gate of the transistor 33. The signal S65 is applied to the terminal 65 and input to the gate of the transistor 46. The signal S66 is applied to the terminal 66 and input to the gate of the transistor 40. The signal S69 is applied to the terminal 69 and input to the gate of the transistor 41. The signal S67 is applied to the terminal 67 and input to the gate of the transistor 42. The signal S68 is applied to the terminal 68 and input to the gate of the transistor 43. The signal S70 is applied to the terminal 70 and input to the gate of the transistor 48. The signal S71 is applied to the terminal 71 and input to the gate of the transistor 51. The signal S73 is applied to the terminal 73 and input to the gate of the transistor 52. The signal S74 is applied to the terminal 74 and input to the gate of the transistor 54.

  Below, the 1st drive method of the solid-state image sensor which concerns on 3rd Example is demonstrated, referring FIG.6 and FIG.7.

  In FIG. 7, a signal S21 is a signal output to the column signal line 21, and after a plurality of signal outputs Vref corresponding to the initial state of the FD section are output, a signal output corresponding to the charge accumulated in the photodiode is output. V1, V2, V3, V4 and V5 are sequentially output.

  First, in a period t1, the signal S61 becomes “HIGH” and the transistor 30 is turned on. Since the Vref signal for each pixel in the first row is output to the column signal line 21, the Vref value is held in the capacitor 34.

  In the period t2, the signal S66 becomes “HIGH” and the transistor 40 is turned on. Since the Vref signal for each pixel in the second row is output to the column signal line 21, the Vref value is held in the capacitor 44.

  In the period t3, the Vref signal for each pixel of the third row, the fourth row, and the fifth row is sequentially output to the column signal line 21, so that the Vref value is held in a corresponding capacitor (not shown). The

  In a period t5 after the period t4, the signal S64 becomes “HIGH” and the transistor 31 is turned on. Since the column signal line 21 outputs the signal output V1 of the pixel unit in the first row, the V1 value is held in the capacitor 35.

  In the periods t6 and t7, the signal 69 becomes “HIGH” and the transistor 41 is turned on. Since the column signal line 21 outputs the signal output V2 of the pixel unit in the second row, the V2 value is held in the capacitor 45.

  On the other hand, in the period t6 in the first half of the periods t6 and t7, the signals S60, S62, S70, and S71 are “HIGH”, and the transistors 36, 32, 48, and 51 are turned on. When the transistors 32, 36, and 48 are turned on, the Vref value of the unit pixel in the first row held in the capacitor 34 is transferred to the upper portion of the capacitor 49 via the source follower formed by the transistor 37 and the current source 38. Guided to the electrode. A bias voltage Vb is applied to the terminal 72, and the bias voltage Vb is guided to the lower electrode of the capacitor 49 when the transistor 51 is turned on. Accordingly, a voltage ((Vref−Vt) −Vb) is held between the electrodes of the capacitor 49. Here, Vt is a threshold voltage of the transistor 37. As a result, the Vb value is held in the capacitor 50 and the Vb value is also output to the output line 56 of the first difference circuit 76.

  In the subsequent period t7, the signals S60, S63, S70, and S73 are “HIGH”, and the transistors 36, 33, 48, and 52 are turned on. When the transistors 33, 36, and 48 are turned on, the V1 value of the unit pixel in the first row held in the capacitor 35 is passed through the source follower formed by the transistor 37 and the current source 38 to the upper portion of the capacitor 49. A voltage (V1-Vt) value is introduced to the electrodes. The upper electrode of the capacitor 49 becomes (V1-Vt) in the period t7 with respect to the (Vref-Vt) value in the period t6, and the voltage change becomes (Vref-V1). Further, this voltage change is applied to the output line 56 of the first difference circuit 76 by dividing the voltage 49 (capacitance value C49) and the capacitance 50 (capacitance value C50) by the divided voltage value {(Vref−V1) × (C50 / ( C49 + C50))} changes from the Vb value. Since the transistor 52 is conductive, the capacitor 53 holds the voltage value [Vb − {(Vref−V1) × (C50 / (C49 + C50))}].

  Next, in the periods t8 and t9, as in the periods t6 and t7, first, in the period t8, the signals S65, S67, S70, and S71 are “HIGH”, and the transistors 46, 42, 48, and 51 are turned on. . When the transistors 42, 46, and 48 are turned on, the Vref value of the unit pixel in the second row held in the capacitor 44 is transferred to the upper portion of the capacitor 49 via the source follower formed by the transistor 47 and the current source 38. Guided to the electrode. A bias voltage Vb is applied to the terminal 72. When the transistor 51 is turned on, the bias voltage Vb value is guided to the lower electrode of the capacitor 49. Therefore, the voltage ((Vref−Vt) −Vb) is held between the electrodes of the capacitor 49, the Vb value is held in the capacitor 50, and the Vb value is also in the output line 56 of the first difference circuit 76. Is output.

In the subsequent period t9, the signals S65, S68, S70, and S74 are “HIGH”, and the transistors 46, 43, 48, and 54 are turned on. When the transistors 43, 46, and 48 are turned on, the V2 value of the unit pixel in the second row held in the capacitor 45 passes through the source follower formed by the transistor 47 and the current source 38 to the upper part of the capacitor 49. It is guided to the electrode as a voltage (V2-Vt) value. The upper electrode of the capacitor 49 becomes (V2−Vt) in the period t9 with respect to the (Vref−Vt) value in the period t8, and the voltage change becomes (Vref−V2). In addition, this voltage change is applied to the output line 56 of the first difference circuit 76 by dividing the divided value {(Vref−V2) × (C50 / (C50) (capacitance value C49) and capacitance 50 (capacitance value C50). C49 + C50))} changes from the Vb value and is output. Further, since the transistor 54 is conductive, the capacitor 55 holds the voltage value [Vb − {(Vref−V2) × (C50 / (C49 + C50))}]. That is, in the first holding circuit 75 including the capacitors 34, 35, 44, and 45 and a plurality of transistors, the signal output Vref corresponding to the initial state of the FD portion and the charge accumulated in the photodiode are supported. While two capacitors per unit pixel are used for the signal outputs V1, V2, V3, V4, and V5, the first difference circuit 76 outputs those difference signals, and one capacitor per unit pixel. It is held in the second holding circuit 77 using the capacity of.

  Next, the description after the period t10 will be described with reference to FIG.

  As shown in FIG. 8, the signal accumulated in the capacitor 53 of the second holding circuit 77 is read in the period t11 and the period t12. First, in the period t11, the signal S821, the signal S825, and the signal S826 are set to “HIGH”, and the transistor 802, the transistor 816, and the transistor 815 are turned on. Accordingly, the signal accumulated in the capacitor 53 is transmitted to the upper electrode of the capacitor 813 through the transistor 802, the transistor 806, and the transistor 816. At the same time, the voltage set at the terminal 827 is transmitted to the lower electrode of the capacitor 813 through the transistor 815.

  In the subsequent period t12, since the signal S822 becomes “HIGH” and the signal S826 becomes “LOW”, the voltage value Vref2 is transmitted to the upper electrode of the capacitor 813 through the transistor 801. Thereafter, the first difference circuit 76 of the first difference circuit 76 described above. Similarly to the description, the divided values of the capacitors 813 and 814 are output to the signal line 805.

  In the subsequent period t13 and period t14, the divided value of the capacitor 813 and the capacitor 814 in the signal of the capacitor 55 is output to the signal line 805. By operating the second difference circuit 820, variations in threshold voltage values of the transistors 806 and 807 can be compensated.

  Note that the capacitance value of the capacitor constituting the first holding circuit 75 is larger than the capacitance value of the capacitor constituting the second holding circuit 77. This is because the number of capacitors of the first holding circuit 75 is smaller than the number of capacitors of the second holding circuit 77, and the kTC noise (thermal noise) becomes smaller as the capacitance value is larger.

(Fourth example of one embodiment)
FIG. 9 shows a fourth embodiment corresponding to the second embodiment, in which a signal output Vref corresponding to the initial state of the FD section shown in FIG. A signal output V1 for one pixel corresponding to the electric charge accumulated in the diode is output, and then the initial state of the FD section, such as signal outputs Vref, V2, Vref, V3, Vref, V4, Vref and V5, etc. When the corresponding signal output and the signal output for one pixel corresponding to the charge accumulated in the photodiode are alternately output, the first holding circuit, the first difference circuit, and the second holding circuit One column and two rows are shown.

  As shown in FIG. 9, transistors 80, 81, 82, 83, 84, 89, 90, 91, 48, 51, 52, and 54 have their gates connected to terminals 100, 101, 102, 104, 103, and 105, respectively. , 107, 106, 108, 109, 111 and 112, respectively.

  The capacitor 85 is connected to the transistors 83 and 84, the capacitor 92 is connected to the transistors 90 and 91, the capacitors 49 and 50 are connected to the output line 56, the capacitor 53 is connected to the transistor 52, and the capacitor 55 is connected to the transistor 54. Has been.

  The transistors 86 and 93 form a source follower together with the current source 87 when the transistors 86 and 93 are turned on.

  Here, reference numeral 95 denotes a first holding circuit, reference numeral 96 denotes a first difference circuit, and reference numeral 97 denotes a second holding circuit. The second differential circuit similar to that of the third embodiment is connected to the subsequent stage of the second holding circuit 97. However, since the operation is the same as that of the third embodiment, the circuit configuration and circuit operation thereof are the same. Is omitted.

  In the first holding circuit 95, the column signal line 21 is branched into a first signal line 21A and a second signal line 21B, and the transistors 80, 84, and 91 are connected to the first signal line 21A. The transistors 81, 82, and 89 are connected to the second signal line 21B.

  FIG. 10 is a timing chart illustrating temporal changes of main signals in the first holding circuit, the first difference circuit, and the second holding circuit of the solid-state imaging device according to the fourth embodiment.

  FIG. 10 shows control signals applied to the terminals shown in FIG. Each control signal is represented by a symbol with S added to the symbol of an applied terminal.

  A signal S21 illustrated in FIG. 10 indicates an output signal output to the column signal line 21. The signal S100 is applied to the terminal 100 and input to the gate of the transistor 80. The signal S101 is applied to the terminal 101 and input to the gate of the transistor 81. The signal S102 is applied to the terminal 102 and input to the gate of the transistor 82. The signal S103 is applied to the terminal 103 and input to the gate of the transistor 84. The signal S104 is applied to the terminal 104 and input to the gate of the transistor 83. The signal S105 is applied to the terminal 105 and input to the gate of the transistor 89. The signal S106 is applied to the terminal 106 and input to the gate of the transistor 91. The signal S107 is applied to the terminal 107 and input to the gate of the transistor 90. The signal S108 is applied to the terminal 108 and input to the gate of the transistor 48. The signal S109 is applied to the terminal 109 and input to the gate of the transistor 51. The signal S111 is applied to the terminal 111 and input to the gate of the transistor 52. The signal S112 is applied to the terminal 112 and input to the gate of the transistor 54.

  Hereinafter, a second driving method of the solid-state imaging device according to the fourth embodiment will be described with reference to FIGS. 9 and 10.

  In FIG. 10, a signal S21 is a signal output to the column signal line 21, and a plurality of signal outputs Vref corresponding to the initial state of the FD section, and signal outputs V1, V2, corresponding to charges accumulated in the photodiodes, V3, V4 and V5 are output alternately.

  First, the Vref signal of the unit pixel in the first row is output in the period t1, and the V1 signal is output in the period t4. Further, it is assumed that the Vref signal of the unit pixel in the second row is output in the period t3, the V2 signal is output in the period t6, and the signals of the unit pixels in the third row and thereafter are similarly output in the following order. To do.

  First, in a period t1, the signals S100 and S103 are “HIGH” and the transistors 80 and 84 are turned on. When the transistor 80 is turned on, the Vref signal of the pixel unit in the first row is transmitted from the column signal line 21 to the first signal line 21A, and the transistor 84 is turned on, so that the Vref value is held in the capacitor 85.

  Next, in the period t2, when the signal S101 becomes “HIGH” and the transistor 81 is turned on, the signal of the column signal line 21 is transmitted to the second signal line 21B.

  Next, in the period t <b> 3, the signals S <b> 100, S <b> 104, S <b> 106, S <b> 108, and S <b> 109 are “HIGH”, and the transistors 80, 83, 91, 48, and 51 are turned on. When the transistors 80 and 91 are turned on, the Vref value of the pixel unit in the second row of the column signal line 21 is held in the capacitor 92. On the other hand, when the transistors 83, 48, and 51 are turned on, the Vref signal of the pixel unit in the first row held in the capacitor 85 passes through the source follower including the transistor 86 and the current source 87. Guided to the upper electrode. A bias voltage Vb is applied to the terminal 110, and the transistor 51 is turned on, whereby the bias voltage Vb is guided to the lower electrode of the capacitor 49. Therefore, a voltage ((Vref−Vt) −Vb) is held between the electrodes of the capacitor 49. Here, Vt is a threshold voltage of the transistor 86. As a result, the Vb value is held in the capacitor 50 and the Vb value is also output to the output line 56 of the first difference circuit 96.

  Next, in a period t <b> 4, the signals S <b> 101, S <b> 102, S <b> 108, and S <b> 111 are “HIGH” and the transistors 81, 82, and 52 are turned on. When the transistors 81 and 82 are turned on, the V1 value of the unit pixel in the first row is led from the column signal line 21 to the second signal line 21B, and the source follower formed by the transistor 86 and the current source 87 is used. Thus, a voltage (V1-Vt) value is introduced to the upper electrode of the capacitor 49. The upper electrode of the capacitor 49 becomes (V1-Vt) in the period t4 with respect to the (Vref-Vt) value in the period t3, and the voltage change becomes (Vref-V1). Further, this voltage change is applied to the output line 56 of the first difference circuit 96 by dividing the divided value {(Vref−V1) × (C50 / (capacitance value C49) and the capacitance 50 (capacitance value C50). C49 + C50))} changes from the Vb value and is output. Further, since the transistor 52 is conductive, the capacitor 53 holds the voltage value [Vb − {(Vref−V1) × (C50 / (C49 + C50))}]. That is, the capacitor 53 holds a value corresponding to the difference between the Vref value and the V1 value for each pixel in the first row.

  Hereinafter, in the period t5, the Vref value of the unit pixel in the third row is held in a capacitor (not shown), and the Vref of the pixel unit in the second row held in the capacitor 92 is guided to the upper electrode of the capacitor 49. .

  In the period t6, the V2 value of the column signal line 21 is led to the upper electrode of the capacitor 49 by the same operation as in the period t4, and the voltage value [Vb − {(Vref−V2) × (C50 / (C49 + C50))}] is held. That is, the capacitor 55 holds a value corresponding to the difference between the Vref value and the V2 value for each pixel in the second row.

  Thus, according to the fourth embodiment, similarly to the third embodiment, the signal output Vref corresponding to the initial state of the FD portion and the signal outputs V1, V2, V3 corresponding to the charges accumulated in the photodiodes. , V4 and V5 are output by the first difference circuit 96, and are held in the second holding circuit 97 using one capacitor per unit pixel.

  As described above, the capacitors 34, 35, 44, 45, 49, 53 and 55 described in FIG. 6 of the third embodiment, and the capacitors 85, 92, 49, 53 and described in FIG. 9 of the fourth embodiment. In 55, the signal voltage is held as an analog value.

  Note that the capacitance value of the capacitor constituting the first holding circuit 95 according to this embodiment shown in FIG. 9 is larger than the capacitance value of the capacitor constituting the second holding circuit 97. This is because the number of capacitors of the first holding circuit 95 is smaller than the number of capacitors of the second holding circuit 97, and the kTC noise (thermal noise) becomes smaller as the capacitance value is larger.

  As described above, according to the present embodiment, since the holding circuit that holds the electric signal output from each pixel is arranged outside the pixel circuit that is not easily restricted by the circuit area, the holding circuit is relatively By using a large capacity (capacitor), an electric signal can be held for a long time with lower noise than the pixel circuit. In addition, the holding circuit is divided into a first holding circuit and a second holding circuit, and further, a first difference circuit is provided between the first holding circuit and the second holding circuit, and the first holding circuit is provided. The circuit and the first difference circuit can obtain a difference electric signal between the electric signal in the initialization state of the corresponding pixel and the electric signal after the light reception of the corresponding pixel, and the difference electric signal is supplied to the second holding circuit. By holding, the area of the holding circuit can be reduced.

  As described above, the solid-state imaging device according to the present embodiment has been described based on examples. However, the present invention is not limited to the present embodiment and each example. Unless it deviates from the meaning of the present invention, those in which various modifications conceived by those skilled in the art are applied to the present embodiment and each example are also included in the scope of the present invention.

  According to the solid-state imaging device according to the present invention, a solid-state imaging device capable of global operation with suppressed deterioration in image quality can be obtained, which is useful for a C-type solid-state imaging device and the like.

1 pixel circuit 1-1 pixel unit 1-2 pixel unit 2 first holding circuit 3 first difference circuit 4 second holding circuit 5 second difference circuit 6 output line 7 horizontal scanning circuit 8 vertical scanning circuit 10 photo Diode 11 Transfer transistor 12 Reset transistor 13 Output transistor 14 Row selection transistor 15 Photodiode 16 Transfer transistor 17 Reset transistor 18 Output transistor 19 Row selection transistor 20 Current source 21 Column signal line 21A First signal line 21B Second signal line 22 , 23, 24, 25, 26, 27 Terminals 30, 31, 32, 33, 36, 37 Transistors 34, 35 Capacity 38 Current sources 40, 41, 42, 43, 46, 47, 48 Transistors 44, 45, 49, 50, 53, 55 Capacitance 51, 52, 54 Transistor 56 Output line 0 to 74 Terminal 75 First holding circuit 76 First difference circuit 77 Second holding circuit 80, 81, 82, 83, 84, 86 Transistor 85, 92 Capacity 87 Current source 89, 90, 91, 93 Transistor 95 First holding circuit 96 First difference circuit 97 Second holding circuit 100 to 112 Terminals 801, 802, 803, 804, 815, 816 Transistor 805 Output line 813, 814 Capacitance 820 Second difference circuit 821 to 827 terminal

Claims (7)

A plurality of pixels arranged in a matrix and each outputting an electrical signal corresponding to the amount of received light;
A plurality of column signal lines provided for each column and sequentially transferring electrical signals output from the plurality of pixels in the corresponding column;
A first capacitor which is provided for each column and holds a first electric signal in an initialization state of the corresponding pixel; and a second capacitor which holds a second electric signal after light reception of the corresponding pixel. A first holding circuit that holds the first and second electric signals transferred from the pixel through the column signal line of the corresponding column;
The first electric signal provided in each column and held in the first capacitor of the first holding circuit in the corresponding column and the second electric signal held in the second capacitor A first difference circuit that takes the difference between
A second holding circuit for holding an electric signal of the first differential circuit or RaIzuru force is the difference,
A solid-state imaging device, comprising: a second difference circuit that obtains a difference between the difference electric signal held in the second holding circuit and a reference voltage . Each of the pixels includes a photodiode that generates a charge according to the amount of light received;
A transfer transistor connected to the output side of the photodiode;
A floating diffusion section that converts the charge generated by the photodiode and transferred through the transfer transistor into a voltage;
A reset transistor for setting the floating diffusion portion to an initialized state;
A gate connected to the floating diffusion portion, and an output transistor that outputs an electrical signal corresponding to a voltage converted by the floating diffusion portion,
The pixels are grouped into a plurality of predetermined rows, and the gates of the reset transistor and the transfer transistor included in the pixels of each group are connected in common to the groups. The solid-state imaging device according to claim 1 . A plurality of pixels arranged in a matrix and each outputting an electrical signal corresponding to the amount of received light;
A plurality of column signal lines provided for each column and sequentially transferring electrical signals output from the plurality of pixels in the corresponding column;
Provided for each column , having a capacity for holding the first electric signal in the initialization state of the corresponding pixel, and holding the first electric signal transferred from the pixel through the column signal line of the corresponding column A first holding circuit that
Provided for each column, is held in the capacitor of the first holding circuit in the corresponding column has a first electrical signal in the initial state of the corresponding pixel, after reception of the corresponding pixels a first differential circuit which takes the difference between the second electrical signal,
A second holding circuit for holding a differential electric signal output from the first difference circuit;
A solid-state imaging device, comprising: a second difference circuit that obtains a difference between the difference electric signal held in the second holding circuit and a reference voltage . Each of the pixels includes a photodiode that generates a charge according to the amount of light received;
A transfer transistor connected to the output side of the photodiode;
A floating diffusion section that converts the charge generated by the photodiode and transferred through the transfer transistor into a voltage;
A reset transistor for setting the floating diffusion portion to an initialized state;
A gate connected to the floating diffusion portion, and an output transistor that outputs an electrical signal corresponding to a voltage converted by the floating diffusion portion,
In each of the pixels, signals applied to the gates of the reset transistors in a plurality of rows have temporal overlap, and signals applied to the gates of the transfer transistors in a plurality of rows have temporal overlap. The solid-state imaging device according to claim 3 , wherein It said first holding circuit and a second holding circuit, solid-state imaging device according to any one of claims 1 to 4, characterized in that for holding the electrical signal in an analog value. The capacitance value of the first holding circuit, solid-state imaging device according to any one of claims 1 to 5, wherein greater than the capacitance value of the second hold circuit.   The solid-state imaging device according to claim 1, wherein the second holding circuit has one capacitor for the pixel.

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