JP2012156967A - Solid-state image pickup element and driving method of solid-state image pickup element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup element capable of realizing a circuit (storage section) with a small area for holding an electrical signal from a pixel, and further to provide a driving method of the solid-state image pickup element.SOLUTION: A solid-state image pickup element 100 comprises: a plurality of pixels 1a; a column signal line 21; and a first storage section 2a that is disposed on each column signal line 21 and stores an electrical signal transmitted from the plurality of pixels 1a of a corresponding column. The first storage section 2a comprises: a first transistor 31, of which a gate is connected to a row selection line 40, one of a source and a drain is connected to an input signal line 21 and the other one of the source and the drain is connected to a storage node; and a second transistor 32, of which a gate is connected to the storage node, one of a source and a drain is connected to a row power source line 41 and the other one of the source and the drain is connected to an output signal line 34.

Description

  The present invention relates to a solid-state imaging device which is a CMOS (Complementary Metal Oxide Semiconductor) type area image sensor incorporated in a digital camera or the like, and a driving method of the solid-state imaging device.

  In recent years, a technique such as Patent Document 1 has been proposed in order to realize a global shutter operation with a CMOS image sensor.

  FIG. 15 is a block diagram showing a configuration of a conventional solid-state imaging device 1200. As illustrated in FIG. 15, the solid-state imaging device 1200 includes a pixel cell 1201 that converts an optical signal into an electric signal, a pixel unit 1202 in which the pixel cells 1201 are arranged in a two-dimensional manner, and a vertical direction (row) of the pixel unit 1202. A vertical scanning unit 1203 for selecting a pixel, a noise suppressing unit 1231 for suppressing noise of a pixel signal from the selected row, and a memory unit 1222 in which memory cells 1221 for accumulating output signals of the noise suppressing unit 1231 are arranged in a two-dimensional manner, The memory vertical scanning unit 1223 for selecting the vertical direction (memory row) of the memory unit 1222, the horizontal selection unit 1205 for selecting the signal of the selected memory row, and the horizontal for sequentially selecting the horizontal selection unit 1205 in the horizontal direction The scanning unit 1206 includes an output amplifier 1212.

  FIG. 16 is a circuit diagram showing a configuration of noise suppression unit 1231 and memory unit 1222 shown in FIG. The memory cell 1221 provided in the memory unit 1222 includes a memory capacitor C31 that stores the output signal of the noise suppression unit 1231, a memory write transistor M31 that writes an output signal to the memory capacitor C31, and a memory capacitor C31. The memory amplifier A31 amplifies the signal and the memory read transistor M32 that reads the output of the memory amplifier A31.

JP 2008-072188 A

  However, the technique disclosed in Patent Document 1 has a configuration in which each memory cell includes a memory capacity and a memory amplifier (amplifying transistor) independently, which increases the circuit area of the memory cell. As the circuit area increases, a decrease in the aperture of the light receiving portion in the pixel cell becomes a problem.

  The present invention has been made in view of the above problems, and can realize a circuit (storage unit) for holding a signal from a pixel with a small area and a driving method of the solid-state image sensor. The purpose is to provide.

  In order to solve the above-described problem, a solid-state imaging device according to the present invention includes a plurality of pixels arranged in a matrix and outputting an electrical signal corresponding to the amount of received light, and a column signal provided for each column of the plurality of pixels. And a first storage unit that is provided for each column signal line and stores an electrical signal transferred from the plurality of pixels in the corresponding column through the column signal line, the first storage unit including a gate Is connected to a row selection line to which a control signal for selecting a row is applied, one of a source or a drain is connected to the column signal line of the corresponding column, and the other is connected to a storage node for storing an electrical signal The first transistor and the gate connected to the storage node, one of the source and the drain connected to a row power supply line for supplying a power supply voltage to the selected row, and the other connected to the output signal line Second transistor Equipped with a.

  With such a configuration, the first storage unit necessary for recording information (electric signal) of one pixel can be configured with only two transistors. Thereby, the 1st memory | storage part which memorize | stores the information (electric signal) of a pixel is realizable with a small area.

  In addition, a pulse power supply voltage is applied to the row power supply line, and a stored electrical signal is output to the output signal line from the storage node of the second transistor in the row to which the pulse power supply voltage is applied. Also good.

  With such a configuration, it is possible to read the memory from the first memory portion of the row selected from the plurality of first memory portions without providing a transistor for row selection. Thereby, the 1st memory | storage part which memorize | stores the information (electric signal) of a pixel is realizable with a small area.

  The solid-state imaging device further includes a first difference circuit that is provided for each of the output signal lines and outputs a voltage difference between an electric signal transferred through the column signal line of a corresponding column and a reset signal. It is good.

  With such a configuration, even if the electrical signal stored in the storage node includes noise, an electrical signal from which the influence of noise has been removed can be obtained.

  The first difference circuit reads the difference between the source and drain currents of the second transistor caused by the voltage difference of the storage node when the pixel signal is held in the storage node and when the reset signal is held. It is good.

  The first differential circuit may read a voltage change generated in the output signal line when the source-drain current is charged and discharged to the output signal line as a difference between the source-drain currents.

  Further, the solid-state imaging device may include the same number of the first storage units as the number of the plurality of pixels.

  With such a configuration, an electrical signal can be stored for each pixel.

  The solid-state imaging device may include the first storage unit as a multiple of the number of the plurality of pixels.

  With such a configuration, an electrical signal and a reset signal can be stored for each pixel.

  Further, a load transistor may be connected to the output signal line, and a source follower circuit may be configured by the second transistor and the load transistor.

  Further, a load transistor may be connected to the output signal line, and the second transistor and the load transistor may constitute an inverter circuit.

  With such a configuration, the stored electrical signal can be read without being reduced.

  The solid-state imaging device is further provided for each column, connected to each of the first difference circuits, and stores a difference between the electrical signal transferred from the first difference circuit in the corresponding column and the reset signal. A second storage unit may be provided.

  The solid-state imaging device may further include a second difference circuit that is provided for each column and connected to each of the second storage units.

  With such a configuration, stored electrical signals can be sequentially and efficiently read out.

  In addition, in order to solve the above-described problems of the prior art, the solid-state imaging device driving method of the present invention provides a control signal for selecting a row when reading an electrical signal stored from a storage node of a storage unit. A pulse power supply voltage is applied to the row power supply line, and the stored electrical signal is output to the output signal line from the storage node of the storage unit in the row to which the pulse power supply voltage is applied.

  With such a driving method, it is possible to read the memory from the first memory portion of the row selected from the plurality of first memory portions without providing a transistor for row selection. Thereby, the 1st memory | storage part which memorize | stores the information (electric signal) of a pixel is realizable with a small area.

  According to the present invention, it is possible to provide a solid-state imaging device and a driving method of the solid-state imaging device that can realize a circuit (storage unit) for holding an electrical signal from a pixel with a small area.

It is a block diagram which shows the structure of the solid-state image sensor which concerns on Embodiment 1 of this invention. FIG. 2 is a circuit diagram illustrating an example of a configuration of a pixel circuit portion for one column and two rows of the solid-state imaging device illustrated in FIG. 1. It is a timing chart which shows the time change of the main signal in the solid-state image sensor shown in FIG. FIG. 2 is a circuit diagram illustrating an example of a configuration of a holding circuit unit and a difference circuit unit in the solid-state imaging device illustrated in FIG. 1. It is a timing chart which shows the time change of the main signal in the solid-state image sensor shown in FIG. It is a timing chart which shows the time change of the main signal in the solid-state image sensor shown in FIG. It is a block diagram which shows the structure of the solid-state image sensor which concerns on Embodiment 2 of this invention. It is a circuit diagram for 1 column 2 rows of the pixel circuit which concerns on Embodiment 2 of this invention. 6 is a circuit diagram of a first holding circuit according to Embodiment 2 of the present invention for one column and two rows, and a circuit diagram of a differential circuit. FIG. It is a circuit diagram for 1 column 1 line of the 2nd holding | maintenance circuit which concerns on Embodiment 2 of this invention. It is a circuit diagram which shows the modification for 1 column 1 line of the 2nd holding | maintenance circuit which concerns on Embodiment 2 of this invention. It is a circuit diagram which shows the modification for 1 column 1 line of the 2nd holding | maintenance circuit which concerns on Embodiment 2 of this invention. It is a circuit diagram which shows the modification for 1 column 1 line of the 2nd holding | maintenance circuit which concerns on Embodiment 2 of this invention. It is a circuit diagram which shows an example of a structure of the pixel circuit part which shares FD with several photoelectric conversion elements. It is a circuit which shows an example of a structure of the pixel circuit part which shares FD with several photoelectric conversion elements. It is a block diagram which shows the structure of the conventional solid-state image sensor. It is a circuit diagram which shows the structure of the noise suppression part of the solid-state image sensor shown in FIG. 15, and a memory part.

  Hereinafter, embodiments of a solid-state imaging device according to the present invention will be described with reference to the drawings. In addition, although this invention is demonstrated using the following embodiment and attached drawing, this is for the purpose of illustration and this invention is not intended to be limited to these.

(Embodiment 1)
FIG. 1 is a block diagram illustrating a configuration of a solid-state imaging device 100 according to the present embodiment.

  As shown in FIG. 1, the solid-state imaging device 100 includes a pixel circuit unit 1, a holding circuit unit 2, a difference circuit unit 3, an output line 4, a horizontal scanning circuit 5, and a vertical scanning circuit 6.

  The pixel circuit unit 1 includes a plurality of pixel circuits 1a that are unit pixels in a matrix. The holding circuit unit 2 includes a plurality of holding circuits 2a that are unit holding circuits in a matrix. The pixel circuit unit 1 and the holding circuit unit 2 are connected to each other by a column signal line 21. The difference circuit unit 3 includes a plurality of difference circuits 3a, which are unit difference circuits, in a matrix. The holding circuit unit 2 and the difference circuit unit 3 are connected to each other by a read column signal line 34.

  A reference output and a signal output are output from the pixel circuit unit 1. The reference output refers to an electrical signal output from the pixel circuit unit 1 when the pixel circuit unit 1 is not irradiated with light, that is, an electrical signal (reset signal) in an initial state. The signal output refers to an electrical signal output from the pixel circuit unit 1 according to the amount of light received by the pixel circuit unit 1 when the pixel circuit unit 1 is irradiated with light.

  The holding circuit unit 2 holds the reference output and the signal output output from the pixel circuit unit 1. The holding circuits 2 a that are unit holding circuits of the holding circuit unit 2 are provided twice as many as the pixel circuits 1 a that are unit pixels of the pixel circuit unit 1. Specifically, two holding circuits 2a are provided for one pixel circuit 1a. Each holding circuit 2a holds the reference output and the signal output.

  The difference circuit unit 3 detects a difference output signal that is a difference between the reference output held in the holding circuit unit 2 and the signal output. The difference circuit 3a which is a unit difference circuit of the difference circuit unit 3 is provided for each column. A difference between the reference output held in the holding circuit unit 2 and the signal output is detected by the difference circuit 3a, and the difference output signal output from the difference circuit 3a is output in synchronization with the output signal of the horizontal scanning circuit 5. Output to line 4.

  The vertical scanning circuit 6 applies a pulse signal for reading signals from the pixel circuit unit 1 and the holding circuit unit 2 to the column signal line 21 and the readout column signal line 34.

  FIG. 2 is a circuit diagram illustrating an example of a configuration of pixels for one column and two rows of the pixel circuit unit 1. The broken lines in FIG. 2 indicate pixel circuits 1 a and 1 b that are unit pixels constituting the pixel circuit unit 1.

  The pixel circuit 1a includes a photodiode 10, a transfer MOS transistor 11, a reset MOS transistor 12, and an output MOS transistor 13. Similar to the pixel circuit 1a, the pixel circuit 1b includes a photodiode 15, a transfer MOS transistor 16, a reset MOS transistor 17, and an output MOS transistor 18.

  In the pixel circuit 1a, the photodiode 10 converts the received optical signal into an electrical signal, and generates an electrical signal corresponding to the amount of received light. The anode of the photodiode 10 is grounded, and the cathode is connected to the drain of the transfer MOS transistor 11. The source of the transfer MOS transistor 11 is connected to the source of the reset MOS transistor 12 and the gate of the output MOS transistor 13, and the gate is connected to the terminal 23. A region from the source of the transfer MOS transistor 11 to the source of the reset MOS transistor 12 and the gate of the output MOS transistor 13 forms a diffusion capacitance called floating diffusion (hereinafter referred to as FD). The drain of the reset MOS transistor 12 is connected to the power supply, and the gate is connected to the terminal 22. The drain of the output MOS transistor 13 is connected to the power supply, and the source is connected to the drain of the row selection MOS transistor 14. The current source 20 is connected to the column signal line 21. The gate of the row selection MOS transistor 14 is connected to the terminal 24, and when it is conductive, the output MOS transistor 13 and the current source 20 form a source follower.

  Also in the pixel circuit 1b, the photodiode 15 converts the received optical signal into an electrical signal, and generates an electrical signal corresponding to the amount of received light. The anode of the photodiode 15 is grounded, and the cathode is connected to the drain of the transfer MOS transistor 16. The source of the transfer MOS transistor 16 is connected to the source of the reset MOS transistor 17 and the gate of the output MOS transistor 18, and the gate is connected to the terminal 25. A region from the source of the transfer MOS transistor 16 to the source of the reset MOS transistor 17 and the gate of the output MOS transistor 18 forms a diffusion capacitor called FD. The drain of the reset MOS transistor 17 is connected to the power supply, and the gate is connected to the terminal 25. The drain of the output MOS transistor 18 is connected to the power supply, and the source is connected to the drain of the row selection MOS transistor 19. The gate of the row selection MOS transistor 19 is connected to the terminal 27, and when it is conductive, the output MOS transistor 18 and the current source 20 form a source follower.

  The outputs of the pixel circuits 1a and 1b are both connected to the column signal line 21 via the row selection MOS transistor 14 and the row selection MOS transistor 19. The column signal line 21 is connected to the holding circuit unit 2 in FIG. 1, and output signals from the pixel circuits 1 a and 1 b are input to the holding circuit unit 2.

  FIG. 3 is a timing chart showing temporal changes of main signals in the solid-state imaging device 100 according to the present embodiment.

  FIG. 3 shows control signals applied from the vertical scanning circuit 6 to the terminals 22, 23 and 24 in FIG. The control signal is represented by a name with S added to the sign of the applied terminal.

  That is, the signal S22 is a signal input to the gate of the reset MOS transistor 12 applied to the terminal 22. The signal S23 is a signal input to the gate of the transfer MOS transistor 11 applied to the terminal 23. The signal S24 is a signal input to the gate of the row selection MOS transistor 14 applied to the terminal 24. A signal SV represents an output signal output to the column signal line 21. The control signals applied to the terminals 25, 26, and 27 are the same as the control signals applied to the terminals 22, 23, and 24, and thus detailed description thereof is omitted.

  Next, the operation of the pixel circuit unit 1 of the solid-state imaging device 100 according to the present embodiment will be described with reference to FIGS.

  At time t1 in FIG. 3, the signal S22 becomes “HIGH”, and the vertical scanning circuit 6 applies a “HIGH” level pulse signal to the gate of the reset MOS transistor 12 of the pixel circuit 1a to make the reset MOS transistor 12 conductive. Then, the FD of the pixel circuit 1a is connected to a power source to obtain an initial state. At time t2, the signal S22 becomes “LOW”, and the MOS transistor 12 becomes non-conductive. As a result, the pixel circuit 1a is in an initial (reset) state.

  At time points t3 to t4, the signal S24 becomes “HIGH”, and the vertical scanning circuit 6 applies a “HIGH” level pulse signal to the gate of the row selection MOS transistor 14 to make the row selection MOS transistor 14 conductive, and the pixel circuit 1a. The reference output (reset signal) corresponding to the potential of the FD in the initial state is output to the column signal line 21 via the source follower constituted by the output MOS transistor 13 and the current source 20 (at the time of the signal SV in FIG. 3). Vref value of t3: reference output).

  At time t5 to t6, the signal S23 becomes “HIGH”, and the vertical scanning circuit 6 applies the pulse signal of “HIGH” level to the gate of the transfer MOS transistor 11 of the pixel circuit 1a to make the transfer transistor 11 conductive, and the pixel circuit. The charges accumulated in the photodiode 10a of 1a are transferred to the FD. A voltage (FD potential) generated by the transferred charge and the capacitance of the FD is applied to the gate of the output MOS transistor 13.

  From time t7 to time t8, the signal S24 becomes “HIGH”, and the vertical scanning circuit 6 applies a pulse signal of “HIGH” level to the gate of the row selection MOS transistor 14 to make the row selection MOS transistor 14 conductive, and the pixel circuit 1a. The signal output corresponding to the FD potential is output to the column signal line 21 via the source follower composed of the output MOS transistor 13 and the current source 20 (V1 value at time t7 of the signal SV in FIG. 3: signal output) ).

  After time t8, the pixel circuit 1b is also driven in the same manner as described above.

  FIG. 4 specifically shows the configuration of one column and two rows of the holding circuit unit 2 shown in FIG. FIG. 4 is a circuit diagram showing an example of the configuration of the holding circuit unit 2 and the difference circuit unit 3 in the solid-state imaging device 100 shown in FIG. Dashed lines 2a and 2b in FIG. 4 indicate holding circuits 2a and 2b corresponding to the pixel circuit 1a in FIG. A broken line 3a is the difference circuit 3a corresponding to the column in which the pixel circuit 1a of FIG. 2 is provided. The difference circuit unit 3 outputs a difference signal between the reference output (reset signal) output from the holding circuit unit 2 and the electrical signal.

  The holding circuits 2 a and 2 b include write row selection MOS transistors 31 and 36 and storage MOS transistors 32 and 37. One of the storage nodes 2a and 2b holds the reference output and the other holds the signal output. Here, the storage node means the gate capacitance of the storage MOS transistors 32 and 37 in detail.

  As shown in FIG. 4, the terminals 41 and 43 are connected to the drains of the storage MOS transistors 32 and 37. The terminals 41 and 43 are connected to a power source through a read row selection power line only for the row to be read. That is, a pulse voltage is applied from the power source to the terminals 41 and 43 in the row to be read at the timing at which the reading is desired. The sources of the storage MOS transistors 32 and 37 are connected to the read column signal line 34 driven by the drive MOS transistor 35. The storage MOS transistors 32 and 37 and the drive MOS transistor 35 operate as a source follower circuit. To do. That is, the storage MOS transistors 32 and 37 share the drive MOS transistor 35, and the storage MOS transistor 32 and the drive MOS transistor 35, and the storage MOS transistor 37 and the drive MOS transistor 35 form a source follower circuit, respectively. Yes.

  A bias voltage is applied to the terminal 44 connected to the gate of the drive MOS transistor 35 when the reference output or the signal output is read from the holding circuits 2a and 2b to the read column signal line 34. At this time, the terminals 41 and 43 in the non-selected rows are open, that is, not connected to the power supply, so that only the memory MOS transistors 32 and 37 in the selected row have a current corresponding to the gate voltage between the source and drain. become. The stored signal can be read out by detecting the difference between the currents (source-drain currents) by the difference circuit 3a. As a result, only the signal of the selected row is output to the read column signal line 34. At this time, by setting the read column signal line 34 to an arbitrary voltage in advance and connecting the read row selection power supply line of the selected row to the power supply or ground for an arbitrary period, the source − As a drain current difference, a voltage change that occurs in the read column signal line 34 when this current is charged to and discharged from the read column signal line 34 may be read.

  Here, the holding circuit 2a corresponds to the first storage unit in the present embodiment. The write row selection MOS transistors 31 and 36 correspond to the first transistor in this embodiment, and the storage MOS transistors 32 and 37 correspond to the second transistor.

  Further, the read column signal line 34 is connected to a difference circuit 3a provided in the difference circuit unit 3 shown in FIG. As shown in FIG. 4, the difference circuit 3a includes a sample capacitor 50, a divided capacitor 51, and a bias MOS transistor 52. The gate of the bias MOS transistor 52 is connected to a terminal 53, and the source or drain is The terminal 54 is connected. From the difference circuit 3a, a difference output signal that is the difference between the reference output output from the holding circuits 2a and 2b and the signal output is output. The difference output signal is output from the difference circuit 3a to the output signal line 55.

  FIG. 5 is a timing chart showing temporal changes of main signals in the solid-state imaging device 100 according to the present embodiment.

  FIG. 5 shows control signals applied from the vertical scanning circuit 6 to the terminals 22, 23, 24, 40, 41, 42, 43 in FIGS. 2 and 4. The control signal is represented by a name with S added to the sign of the applied terminal.

  Note that control signals applied to the terminals 25, 26, and 27 are the same as those of the terminals 22, 23, and 24, and thus are omitted. Further, the signal S22, the signal S23, the signal S24, and the signal SV are the same as those described in FIG.

  The signal S40 is a signal input to the gate of the write row selection MOS transistor 31 applied to the terminal 40. The signal S42 is a signal input to the gate of the write row selection MOS transistor 36 applied to the terminal 42. The signal S41 is a signal input to the drain of the storage MOS transistor 32 applied to the terminal 41. The signal S43 is a signal input to the drain of the storage MOS transistor 37 applied to the terminal 43.

  Hereinafter, the operation of the holding circuit unit 2 of the solid-state imaging device 100 according to the present embodiment will be described with reference to FIGS. 4 and 5.

  At time points t3 to t4 in FIG. 5, the reference output: Vref is output from the pixel circuit 1a to the column signal line 21. At this time, when the signal S40 and the signal S41 become “HIGH”, the vertical scanning circuit 6 gives a “HIGH” level pulse signal to the gate of the write row selection MOS transistor 31 and the drain of the storage MOS transistor 32, The write row selection MOS transistor 31 and the storage MOS transistor 32 are made conductive. Since the write row selection MOS transistor 31 is turned on, the reference output Vref of the column signal line 21 is held in the storage node (gate capacitance). Specifically, it is guided to the gate of the storage MOS transistor 32 and held in the gate capacitance of the storage MOS transistor 32. At this time, since the drain of the storage MOS transistor 32 is connected to the power supply, the source follower composed of the storage MOS transistor 32 and the drive MOS transistor 35 also operates. Therefore, an output signal corresponding to the reference output: Vref accumulated in the gate capacitance of the storage MOS transistor 32 is output to the read column signal line 34 at time t9 described later.

  Thus, when the write row selection MOS transistor 31 is turned on, the storage MOS transistor 32 operates as a source follower, that is, an amplifier, together with the drive MOS transistor 35. Therefore, the output signal corresponding to the electrical signal accumulated in the gate capacitance of the storage MOS transistor 32 can be amplified and output to the read column signal line 34 efficiently.

  Further, when the electric signal is held in the holding circuit 2a, the drain of the storage MOS transistor 32 is connected to the power source, as in the case of reading the electric signal held in the holding circuit 2a. That is, when the storage MOS transistor 32 holds an electrical signal in the holding circuit 2a, the storage MOS transistor 32 is connected to the power source in the same manner as when reading the electrical signal held in the holding circuit 2a, and then opened. The value of the reference output or signal output can be accurately held and read out.

  From time t7 to t8 in FIG. 5, the signal output V1 is output from the pixel circuit 1a to the column signal line 21. At this time, when the signal S42 and the signal S43 become “HIGH”, the vertical scanning circuit 6 applies a “HIGH” level pulse signal to the gate of the write row selection MOS transistor 36 and the drain of the storage MOS transistor 37, The write row selection MOS transistor 36 and the storage MOS transistor 37 are turned on. When the write row selection MOS transistor 36 is turned on, the signal output V1 of the column signal line 21 is guided to the gate of the storage MOS transistor 37 and held in the gate capacitance of the storage MOS transistor 37. At this time, since the drain of the storage MOS transistor 37 is connected to the power supply, the source follower composed of the storage MOS transistor 37 and the drive MOS transistor 35 also operates. For this reason, at time point t10 to be described later, an output corresponding to the signal output: V1 accumulated in the gate capacitance of the storage MOS transistor 37 is output to the read column signal line 34.

  Thus, when the write row selection MOS transistor 36 is turned on, the storage MOS transistor 37 operates as a source follower, that is, an amplifier, together with the drive MOS transistor 35. Therefore, the output signal corresponding to the electric signal accumulated in the gate capacitance of the storage MOS transistor 37 can be amplified and output to the read column signal line 34 efficiently.

  Further, when the electric signal is held in the holding circuit 2b, the drain of the storage MOS transistor 37 is connected to the power source in the same manner as when the electric signal held in the holding circuit 2b is read out, and then opened. Therefore, the value of the reference output or the signal output can be accurately held and read out.

  At time t9, the signal S41 becomes “HIGH”, the drain of the storage MOS transistor 32 is connected to the power supply, and an output signal corresponding to the reference output: Vref is output to the read column signal line 34.

  At time t10, the signal S43 becomes “HIGH”, the drain of the storage MOS transistor 37 is connected to the power supply, and an output signal corresponding to the signal output: V1 is output to the read column signal line 34.

  Next, the operation of the difference circuit unit 3 of the solid-state imaging device 100 according to the present embodiment will be described with reference to FIG.

  FIG. 6 is a timing chart showing temporal changes of main signals in the solid-state imaging device 100 according to the present embodiment, and is applied to the difference circuit 3a in addition to the operations of the pixel circuit 1a and the holding circuit 2a. It shows the time change of the control signal. Therefore, signals other than the signal S53 applied to the difference circuit 3a are the same as the signals shown in FIG. S 53 is a control signal applied to the gate of the bias MOS transistor 52 via the terminal 53.

  At time t9 in FIG. 6, the reference output: Vref is output from the holding circuit 2a to the read column signal line 34 as described above. At the same time, since the signal S 53 becomes “HIGH”, a pulse signal of “HIGH” level is applied to the gate of the bias MOS transistor 52, so that the bias MOS transistor 52 becomes conductive and the bias MOS transistor 52 is turned on via the terminal 54. A bias voltage applied to the drain of the MOS transistor 52 is transmitted to point M in FIG. When this bias voltage is VB, the potential on the read column signal line 34 side of the capacitor 50 is Vref, the potential on the M point side is VB, and a voltage of (Vref−VB) is applied to the capacitor 50. On the other hand, the voltage VB is applied to the M point side of the divided capacitor 51.

  At time t <b> 10, the signal S <b> 53 becomes “LOW”, the bias MOS transistor 52 is non-conductive, and the signal output: V <b> 1 is output to the read column signal line 34. At this time, the potential on the read column signal line side of the capacitor 50 is (Vref−V1), the potential on the M point side is (Vref−V1) * C1 / (C1 + C2), and the reference output: Vref and the signal output: V1 A capacity-divided differential voltage is obtained. That is, even if noise is included in V1 and Vref, the differential voltage is obtained from the above (Vref−V1) and (Vref−V1) * C1 / (C1 + C2). Is obtained.

  As described above, by combining the difference circuit unit 3, it is possible to suppress noise output in the solid-state imaging device 100.

  As described above, in the holding circuits 2a and 2b of the solid-state imaging device according to the present embodiment, the storage MOS transistors 32 and 37 have both a role as a holding capacitor and a role as an amplifier (amplifying transistor). The circuit area can be reduced as compared with the solid-state imaging device according to the prior art which is provided with a storage capacitor and an amplifier independently. Further, the drains of the storage MOS transistors 32 and 37 are connected to a power source when the reference output or the signal output is held or read, so that row selection is performed. Therefore, it is not necessary to provide a row selection MOS transistor for performing row selection, and the circuit area can be simplified and the storage area can be reduced.

(Embodiment 2)
Next, a second embodiment of the present invention will be described. The present embodiment is different from the first embodiment in that the solid-state imaging device according to the present embodiment includes a plurality of holding circuit units and a plurality of difference circuit units. Further, the difference circuit is provided with a column selection MOS transistor in addition to the configuration of the difference circuit of the first embodiment.

  FIG. 7 is a block diagram showing the configuration of the solid-state imaging device of the present embodiment.

  As illustrated in FIG. 7, the solid-state imaging device 300 includes a pixel circuit unit 301, a first holding circuit unit 302, a first difference circuit unit 303, a second holding circuit unit 304, and a second difference circuit unit 305. , An output line 306, a horizontal scanning circuit 307, and a vertical scanning circuit 308.

  A reference output and a signal output are output from the pixel circuit unit 301. The first holding circuit unit 302 stores the reference output and the signal output or only the reference output. The first difference circuit unit 303 outputs the difference output signal between the reference output and the signal output stored in the first holding circuit unit 302, or the reference output and the pixel circuit 1a stored in the first holding circuit unit 302. A differential output signal that is a difference in signal output is output. The second holding circuit unit 304 stores the differential output signal output from the first differential circuit unit 303. The second difference circuit unit 305 makes a difference between the difference output stored in the second holding circuit unit 304 and the reference voltage, and outputs the difference to the output line 306 in synchronization with the output of the horizontal scanning circuit 307. The vertical scanning circuit 308 applies a pulse voltage that is a control signal to the pixel circuit unit 301, the first holding circuit unit 302, and the second holding circuit unit 304.

  FIG. 8 is a circuit diagram illustrating an example of the configuration of pixels for one column and two rows of the pixel circuit unit 301. Broken lines 301a and 301b in FIG. 8 indicate unit pixels.

  The pixel circuit 301 a includes a photodiode 310, a transfer MOS transistor 311, a reset MOS transistor 312, and an output MOS transistor 313. Similar to the pixel circuit 301a, the pixel circuit 301b includes a photodiode 315, a transfer MOS transistor 316, a reset MOS transistor 317, and an output MOS transistor 318.

  In the pixel circuit 301a, the photodiode 310 converts the received optical signal into an electrical signal, and generates an electrical signal corresponding to the amount of received light. The anode of the photodiode 310 is grounded, and the cathode is connected to the drain of the transfer MOS transistor 311. The source of the transfer MOS transistor 311 is connected to the source of the reset MOS transistor 312 and the gate of the output MOS transistor 313, and the gate is connected to the terminal 323. A region from the source of the transfer MOS transistor 311 to the source of the reset MOS transistor 312 and the gate of the output MOS transistor 313 forms a diffusion capacitance called a floating diffusion (hereinafter referred to as FD). The drain of the reset MOS transistor 312 is connected to the power supply, and the gate is connected to the terminal 322. The drain of the output MOS transistor 313 is connected to the power supply, and the source is connected to the drain of the row selection MOS transistor 314. The current source 320 is connected to the column signal line 321. The gate of the row selection MOS transistor 314 is connected to the terminal 324, and when it is conductive, the output MOS transistor 313 and the current source 320 form a source follower.

  Also in the pixel circuit 301b, the photodiode 315 converts the received optical signal into an electrical signal, and generates an electrical signal corresponding to the amount of received light. The anode of the photodiode 315 is grounded, and the cathode is connected to the drain of the transfer MOS transistor 316. The source of the transfer MOS transistor 316 is connected to the source of the reset MOS transistor 317 and the gate of the output MOS transistor 318, and the gate is connected to the terminal 325. A region from the source of the transfer MOS transistor 316 to the source of the reset MOS transistor 317 and the gate of the output MOS transistor 318 forms a diffusion capacitor called FD. The drain of the reset MOS transistor 317 is connected to the power supply, and the gate is connected to the terminal 325. The drain of the output MOS transistor 318 is connected to the power supply, and the source is connected to the drain of the row selection MOS transistor 319. The gate of the row selection MOS transistor 319 is connected to the terminal 327, and when it is conductive, the output MOS transistor 318 and the current source 320 form a source follower.

  The outputs of the pixel circuits 301 a and 301 b are both connected to the column signal line 321 via the row selection MOS transistor 314 and the row selection MOS transistor 319. The column signal line 321 is connected to the first holding circuit unit 302 in FIG.

  FIG. 9 specifically shows the configuration of one column and two rows of the first holding circuit unit 302 and the configuration of the first difference circuit unit 303 shown in FIG. FIG. 9 is a circuit diagram illustrating an example of a configuration of the first holding circuit unit 302 and the first difference circuit unit 303 in the solid-state imaging device 300 illustrated in FIG. 7. Dashed lines 302a and 302b in FIG. 9 indicate first holding circuits 302a and 302b corresponding to the respective pixel circuits 301a and 301b in FIG. A broken line 303a is the first difference circuit 303a. The first difference circuit unit 303 outputs a difference signal between the reference output (reset signal) output from the first holding circuit unit 302 and the electrical signal. In the present embodiment, the first holding circuit unit 302 is provided with the same number of first holding circuits 302a and 302b as the pixel circuits 301a and 301b. One first difference circuit 303a is provided for each column.

  The first holding circuit 302a corresponding to the pixel circuit 301a and the first holding circuit 302b corresponding to the pixel circuit 301b include write row selection MOS transistors 331 and 336, and storage MOS transistors 332 and 337. The signal output of the pixel circuit 301a is held in the storage node of the first holding circuit 302a. The signal output of the pixel circuit 301b is held in the storage node of the first holding circuit 302b. Here, the storage node specifically refers to the gate capacitance of the storage MOS transistors 332 and 337. The first holding circuit 302a reads the reference output from the pixel circuit 301a, and the first holding circuit 302b reads the reference output from the pixel circuit 301b.

  Further, as shown in FIG. 9, the terminals 341 and 343 are connected to the drains of the storage MOS transistors 332 and 337. The terminals 341 and 343 are connected to a power source through a read row selection power line only for the row to be read. That is, a pulse voltage is applied from the power source to the terminals 341 and 343 in the row to be read at the timing at which reading is desired. The sources of the storage MOS transistors 332 and 337 are connected to the read column signal line 334 driven by the drive MOS transistor 335, and operate as a source follower circuit. That is, the storage MOS transistors 332 and 337 share the drive MOS transistor 335, and the storage MOS transistor 332 and the drive MOS transistor 335, and the storage MOS transistor 337 and the drive MOS transistor 335 form a source follower circuit, respectively. Yes.

  A bias voltage is applied to the terminal 344 connected to the gate of the drive MOS transistor 335 when the reference output or the signal output is read from the first holding circuits 302a and 302b to the read column signal line 334. At this time, the terminals 341 and 343 of the non-selected rows are open, that is, not connected to the power supply, so that only the signal of the selected row is output to the read column signal line 334.

  Here, the first holding circuit 302a corresponds to the first storage unit in the present embodiment. The write row selection MOS transistors 331 and 336 correspond to the first transistor in this embodiment, and the storage MOS transistors 332 and 337 correspond to the second transistor.

  Further, the read column signal line 334 is connected to a first difference circuit 303a provided in the first difference circuit unit 303 shown in FIG. As shown in FIG. 9, the first difference circuit 303a includes a column selection MOS transistor 345, a sample capacitor 350, a divided capacitor 351, and a bias MOS transistor 352, and the gate of the bias MOS transistor 352 is a terminal. The source or drain is connected to the terminal 354. The gate of the column selection MOS transistor 345 is connected to the terminal 355. A pulse voltage is applied to the terminal 355 at a desired timing, whereby a pulse voltage is applied to the column selection MOS transistor 345 to be conducted, thereby selecting a row. From the first difference circuit 303a in the selected row, a difference output signal that is the difference between the reference output and the signal output output from the first holding circuits 302a and 302b is output. The difference output signal is output from the first difference circuit 303a to the output line 356.

  With such a configuration, signal outputs (signals corresponding to the amount of received light) output from the pixel circuit 301a and the pixel circuit 301b in FIG. 8 have different timings for the first holding circuit 302a and the first holding circuit 302b, respectively. Is stored (held). Furthermore, the outputs of the first holding circuit 302a and the first holding circuit 302b are respectively output from the first holding circuit 302a and the first holding circuit 302b in the first difference circuit 303a connected via the read column signal line 334. Is output to the output line 356 as a voltage (difference output signal) proportional to the difference between the reference output (reset signal) and the signal output. The difference output signal output from the first difference circuit 303 a is held in the second holding circuit unit 304.

  Note that the configuration of the first difference circuit 303a is not limited to the configuration described above, and may be a configuration that does not include the column selection MOS transistor 345 like the configuration of the difference circuit 3a described in the first embodiment.

  Next, the second holding circuit unit 304 will be described.

  FIG. 10 shows an example of the configuration of one column and one row of the second holding circuit unit 304 shown in FIG. The second holding circuit unit 304 includes the same number of second holding circuits 304a as unit holding circuits constituting the second holding circuit unit 304 as the number of pixel circuits 301a provided in the pixel circuit unit 301. ing.

  As shown in FIG. 10, the second holding circuit 304a is connected to the column signal line 321 and the read column signal line 334, and includes a write row selection MOS transistor 441, a storage MOS transistor 442, and a read row selection MOS transistor 443. And. The gate of the write row selection MOS transistor 441 is connected to the power supply line 454. The drain of the storage MOS transistor 442 is connected to the power supply. Further, the gate of the read row selection MOS transistor 443 is connected to the read row selection power supply line 453.

  The storage MOS transistor 442 forms a source follower with the read row selection MOS transistor 443 and a current source (not shown). The second holding circuit 304 a holds and outputs the signal output input from the column signal line 321 to the storage node (gate capacitance) of the storage MOS transistor 442. That is, the second holding circuit 304a has both a role as a holding capacitor and a role as an amplifier (amplifying transistor).

  Here, the second holding circuit 304a corresponds to the second storage unit in this embodiment. The write row selection MOS transistor 441 corresponds to the first transistor in this embodiment, and the storage MOS transistor 442 corresponds to the second transistor.

  Further, the read column signal line 334 is connected to a second difference circuit 305a provided in the second difference circuit unit 305 shown in FIG. Since the second difference circuit 305a has the same configuration as the first difference circuit 303a described above, the description thereof is omitted.

  The configuration of the second difference circuit 305a is not limited to the configuration similar to the first difference circuit 303a, and may be the same configuration as the difference circuit 3a shown in the first embodiment.

  The configuration of the second holding circuit 304a may be as shown below. FIG. 11 shows an example of the configuration of the second holding circuit.

  As shown in FIG. 11, the second holding circuit 504 a includes a write row selection MOS transistor 551 and a storage MOS transistor 552. The gate of the write row selection MOS transistor 551 is connected to the power supply line 554. The drain of the storage MOS transistor 552 is connected to the read row selection power line 553.

  In the second holding circuit 504a, only the read row selection power supply line 553 of the selected row to be read is connected to the power source, and the read row selection power supply line 553 of the other non-selected rows is opened, thereby storing the selected row. Only in the MOS transistor 552, a current corresponding to the gate voltage flows between the source and the drain. The stored signal can be read by detecting the difference between the currents (source-drain currents) by the difference circuit 305a. At this time, the read column signal line 334 is set to an arbitrary voltage in advance, and the read row selection power supply line 553 of the selected row is connected to the power supply or the ground for an arbitrary period, whereby the source-drain flowing in the storage MOS transistor 552 As a difference in current, a voltage change that occurs in the read column signal line 334 when this current is charged to and discharged from the read column signal line 334 may be read.

(Modification)
Hereinafter, modifications of the present invention will be described. The holding circuit according to the present invention is not limited to the configuration of the holding circuit (first holding circuit, second holding circuit) described in the first embodiment and the second embodiment, and has the following configuration. Also good.

  FIG. 12 shows a first modification of the holding circuit according to the present invention. As shown in FIG. 12, the holding circuit 604a according to this modification includes a write row selection MOS transistor 651 and a storage MOS transistor 652. The gate of the write row selection MOS transistor 651 is connected to the power supply line 654. The drain of the storage MOS transistor 652 is connected to the read row selection power line 653.

  In addition, drive MOS transistor 660 is connected to the output line, and the memory MOS transistor 652 and drive MOS transistor 660 in the selected row form a source follower circuit. An output signal corresponding to the gate voltage of storage MOS transistor 652 is output to the output line. It is output to 654.

  Further, an inverter circuit may be configured instead of the source follower circuit by changing the connection and power supply of the drive MOS transistor 660 shown in FIG.

  FIG. 13 shows a second modification of the holding circuit according to the present invention. As shown in FIG. 13, the holding circuit 704 a according to the present modification includes a write row selection MOS transistor 751, a storage MOS transistor 752, and a storage capacitor 755. By adding the storage capacitor 755, the holding capacity of the holding circuit 704a is increased, noise can be reduced, and image quality can be improved. The gate of the write row selection MOS transistor 751 is connected to the power supply line 754. The drain of the storage MOS transistor 752 is connected to the read row selection power line 753.

  As described above, the series of pixel signal readout and storage operations according to the present embodiment enables readout that is close to a global shutter operation that reads out pixel signals almost simultaneously at a very low power consumption and is stable with little fluctuation in capacitance. This can be done at the signal level. Further, in this embodiment, the area of the storage device can be reduced.

  The present invention is not limited to the above-described embodiment, and various improvements and modifications may be made without departing from the gist of the present invention.

  For example, in the above-described embodiment, the case where one unit includes one photoelectric conversion element has been described. However, the present invention is not limited thereto, and each unit pixel includes a plurality of photoelectric conversion elements, and a plurality of FDs. The present invention can also be applied to a case where it is shared by photoelectric conversion elements. For example, pixel configurations as shown in FIGS. 14A and 14B are possible.

  In FIG. 14A, the unit pixel 811 includes photodiodes 860 and 865 that are photoelectric conversion elements, transfer transistors 861 and 866, a reset transistor 862, and an SF transistor 863. That is, it is composed of two photoelectric conversion elements, one FD for two transfer transistors, one reset transistor (shared reset transistor), and one SF transistor (shared SF transistor). A signal is read through the transfer transistors 561 and 566 and read out to the FD.

  In FIG. 14B, the unit pixel 811 includes a selection transistor 864 in the unit pixel 811 in addition to the configuration in FIG. 14A. Thus, by sharing the FD by the plurality of photoelectric conversion elements, the aperture of the light receiving portion in the pixel cell is further improved.

  Further, the solid-state imaging device according to the present invention is not limited to the configuration shown in the first and second embodiments, and may be configured to include the second holding circuit and not the second difference circuit, for example. . In this case, a differential output signal that is a difference between the signal output held in the second holding circuit and the reference output may be directly output to the output line (horizontal transfer line).

  Further, the number of holding circuits is not limited to the same number as the number of pixel circuits and twice the number, but may be other multiples. The number is not limited to a multiple, and may be other numbers. Further, the number of difference circuits is not limited to one for each column, but may be other numbers.

  Each transistor used in the present invention may be either p-type or n-type, and the drain and source of the transistor may be connected in reverse.

  In addition, the solid-state imaging device according to the present invention is applicable to other embodiments realized by combining arbitrary components in the above-described embodiments and to the embodiments without departing from the gist of the present invention. Modifications obtained by various modifications conceived by a trader, various devices including the solid-state imaging device according to the present invention, and the like are also included in the present invention. For example, a movie camera including the solid-state imaging device according to the present invention is also included in the present invention.

  The solid-state imaging device of the present invention can be used for surveillance cameras, network cameras, vehicle-mounted cameras, digital cameras, mobile phones, and the like, and can reduce the size of these devices and improve the quality of captured images.

DESCRIPTION OF SYMBOLS 1,301 Pixel circuit part 1a, 1b, 301a, 301b Pixel circuit (pixel)
2 holding circuit unit 2a, 2b holding circuit (storage unit)
3 Difference circuit section 3a Difference circuit 21, 321 Column signal line (input signal line)
31, 36, 331, 336, 441, 551, 651, 751 Write row selection MOS transistor (first transistor)
32, 37, 332, 337, 442, 552, 652, 752 Memory MOS transistor (second transistor)
34, 334 Read column signal line (output signal line)
35, 335, 660 Drive MOS transistor (load transistor)
40, 42, 340, 342 terminals (row selection lines)
41, 43, 341, 343 terminals (row power line)
100, 1200 Solid-state imaging device 302 First holding circuit unit 302a, 302b First holding circuit (first storage unit)
303 1st difference circuit part 303a 1st difference circuit (difference circuit)
304 Second holding circuit section 304a, 504a Second holding circuit (second storage section)
305 Second difference circuit unit 305a Second difference circuit 604a, 704a Holding circuit (first storage unit, second storage unit)

Claims (12)

A plurality of pixels arranged in a matrix and outputting an electrical signal corresponding to the amount of received light;
A column signal line provided for each column of the plurality of pixels;
A first storage unit that is provided for each column signal line and stores an electrical signal transferred from the plurality of pixels in the corresponding column through the column signal line;
The first storage unit
A gate is connected to a row selection line to which a control signal for selecting a row is applied, one of a source and a drain is connected to the column signal line of a corresponding column, and the other is a storage node for storing an electrical signal A connected first transistor;
A solid-state transistor including a second transistor having a gate connected to the storage node, one of a source and a drain connected to a row power supply line for supplying a power supply voltage to a selected row, and the other connected to an output signal line Image sensor. The pulse power supply voltage is applied to the row power supply line, and the stored electrical signal is output to the output signal line from the storage node of the second transistor in the row to which the pulse power supply voltage is applied. The solid-state image sensor described in 1. The solid-state imaging device further includes:
3. The solid-state imaging according to claim 1, further comprising a first difference circuit that is provided for each of the output signal lines and outputs a voltage difference between an electric signal transferred through the column signal line of a corresponding column and a reset signal. element. The first difference circuit is
4. The solid-state imaging device according to claim 3, wherein a difference between a source-drain current of the second transistor caused by a voltage difference of the storage node when a pixel signal is held in the storage node and when a reset signal is held is read. . The first difference circuit is
The solid-state imaging device according to claim 4, wherein a voltage change generated in the output signal line when the source-drain current is charged / discharged to / from the output signal line is read as a difference between the source-drain currents. The solid-state imaging device is
6. The solid-state imaging device according to claim 1, wherein the number of the first storage units is the same as the number of the plurality of pixels. The solid-state imaging device is
The solid-state imaging device according to claim 1, wherein the first storage unit includes a multiple of the number of the plurality of pixels. A load transistor is connected to the output signal line,
The solid-state imaging device according to claim 1, wherein a source follower circuit is configured by the second transistor and the load transistor. A load transistor is connected to the output signal line,
The solid-state imaging device according to claim 1, wherein the second transistor and the load transistor constitute an inverter circuit. The solid-state imaging device further includes:
2. A second storage unit that is provided for each column, is connected to each of the first difference circuits, and stores a difference between an electric signal transferred from the first difference circuit of the corresponding column and a reset signal. The solid-state image sensor of any one of -9. The solid-state imaging device further includes:
The solid-state imaging device according to claim 10, further comprising a second difference circuit provided for each column and connected to each of the second storage units. A method of driving a solid-state imaging device that outputs an electrical signal corresponding to the amount of received light,
When reading the stored electrical signal from the storage node of the storage unit, a pulse power supply voltage is applied to the row power supply line to which a control signal for selecting a row is applied,
A method for driving a solid-state imaging device in which a stored electrical signal is output to an output signal line from the storage node of the storage unit in a row to which the pulse power supply voltage is applied.

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