JP4730389B2 - Display device - Google Patents

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JP4730389B2
JP4730389B2 JP2008097779A JP2008097779A JP4730389B2 JP 4730389 B2 JP4730389 B2 JP 4730389B2 JP 2008097779 A JP2008097779 A JP 2008097779A JP 2008097779 A JP2008097779 A JP 2008097779A JP 4730389 B2 JP4730389 B2 JP 4730389B2
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connection terminal
output connection
semiconductor chip
line
substrate
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JP2008262197A (en
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千寿 外山
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Casio Computer Co Ltd
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Description

この発明は液晶表示装置等の表示装置に関する。   The present invention relates to a display device such as a liquid crystal display device.

従来の液晶表示装置は、例えば図７に示すように、互いに対向して配置された一対の基板１０１、１０２を備え、基板間のシール材１０３によって囲まれた領域内に液晶が充填されて表示領域が形成され、表示領域において、一方の基板１０１に複数の信号ライン１０４および複数の走査ライン１０５が直交して形成され、複数の信号ライン１０４と複数の走査ライン１０５の各交点近傍に表示画素が形成される。この信号ライン１０４および走査ライン１０５が形成された基板１０１は他方の基板１０２に対して、例えば表示領域の右側および下側に突出部１０６を有し、該突出部１０６に信号ライン駆動用の半導体チップ１０８および走査ライン駆動用の半導体チップ１０７が配設され、それぞれ信号ライン１０４および走査ライン１０５に接続されるように構成されている。すなわち、一方の基板１０１は表示領域に対して２方向に突出されて半導体チップが設けられるように構成されていたため、表示領域の周囲の額縁領域が大きくなるという問題があった。また、基板１０１の外形が表示領域に対して左右非対象となっているため、例えばこの表示装置を携帯電話に搭載しようとした場合に、表示画面の位置を機器の左右均等な位置に設けるようにすることが難しくなるという問題があった。   For example, as shown in FIG. 7, a conventional liquid crystal display device includes a pair of substrates 101 and 102 arranged to face each other, and a liquid crystal is filled in a region surrounded by a sealing material 103 between the substrates. An area is formed, and in the display area, a plurality of signal lines 104 and a plurality of scanning lines 105 are formed orthogonal to each other on one substrate 101, and a display pixel is near each intersection of the plurality of signal lines 104 and the plurality of scanning lines 105. Is formed. The substrate 101 on which the signal lines 104 and the scanning lines 105 are formed has protrusions 106 on the right side and the lower side of the display area, for example, with respect to the other substrate 102, and a semiconductor for driving signal lines is provided on the protrusions 106. A chip 108 and a semiconductor chip 107 for driving a scanning line are disposed, and are configured to be connected to the signal line 104 and the scanning line 105, respectively. That is, since one substrate 101 is configured to protrude in two directions with respect to the display area and to be provided with a semiconductor chip, there is a problem that a frame area around the display area becomes large. Further, since the outer shape of the substrate 101 is not subject to the left and right with respect to the display area, for example, when this display device is to be mounted on a mobile phone, the position of the display screen should be provided at the left and right positions of the device. There was a problem that it was difficult to make.

このような問題に対して、表示装置の一方の基板の列方向の一辺部のみが他方の基板から突出され、該突出部に走査ラインおよび信号ラインが引き廻されて、該突出部上に信号ラインを駆動するための１個の半導体チップと走査ラインを駆動するための１個の半導体チップとを搭載するようにして、少なくとも表示領域左右の額縁領域を小さくするようにしたのがある（例えば、特許文献１参照）。   For such a problem, only one side of the display device in the column direction protrudes from the other substrate, and a scanning line and a signal line are routed around the protruding portion, and a signal is output on the protruding portion. One semiconductor chip for driving a line and one semiconductor chip for driving a scanning line are mounted so that at least the frame areas on the left and right sides of the display area are reduced (for example, , See Patent Document 1).

特開２００１−９１９６７号公報JP 2001-91967 A

しかしながら、上記の一方の基板の列方向の一辺部のみが他方の基板から突出され、該突出部上に信号ラインを駆動用の１個の半導体チップと走査ラインを駆動用の１個の半導体チップとを搭載するようにした液晶表示装置では、行方向に配置された走査ラインと走査ライン駆動用の１個の半導体チップとを接続するための引き廻し線を表示領域の行方向一方側にのみ配置しているため、一方の基板の突出部上において、比較的狭い領域に多くの走査ライン引き廻し線が集中するため、各ラインを走査ライン駆動用の１個の半導体チップと接続するために要する配線の配置領域が列方向にある程度必要となる。このため、一方の基板の突出部の突出長が比較的大きくなってしまうという問題があった。
そこで、この発明は、一方の基板の突出部の突出長を小さくすることができる表示装置を提供することを目的とする。 However, only one side of the one substrate in the column direction protrudes from the other substrate, and one semiconductor chip for driving the signal line and one semiconductor chip for driving the scanning line on the protruding portion. In the liquid crystal display device in which a scanning line arranged in the row direction and one semiconductor chip for driving the scanning line are connected, a lead-out line is connected only to one side in the row direction of the display area. Since many scanning line routing lines are concentrated in a relatively narrow region on the protruding portion of one substrate, each line is connected to one semiconductor chip for driving the scanning line. Necessary wiring arrangement regions are required to some extent in the column direction. For this reason, there has been a problem that the protruding length of the protruding portion of one substrate becomes relatively large.
Accordingly, an object of the present invention is to provide a display device that can reduce the protruding length of the protruding portion of one substrate.

請求項１に記載の発明は、第１の基板と第２の基板とが対向配置され、表示領域の行方向に延びる複数の第１ラインの何れかを前記行方向における一方の側から前記表示領域外に引き出すとともに他の第１ラインを前記行方向における他方の側から前記表示領域外に引き出し、前記表示領域の列方向に延びる第２ラインを前記列方向における所定の側から前記表示領域外に引き出す表示装置において、前記第２ラインを前記表示領域外に引き出す側の前記第１の基板上に、前記一方の側から引き出される第１ラインに電気的に接続される第１の出力用接続端子と、前記他方の側から引き出される第１ラインに電気的に接続される第２の出力用接続端子と、前記第２ラインに電気的に接続される第３の出力用接続端子と、を有し、前記第１の出力用接続端子、前記第２の出力用接続端子及び前記第３の出力用接続端子は、それぞれ前記行方向に沿って配列され、前記第１の出力用接続端子は、前記第２の出力用接続端子よりも前記表示領域側に配置され、前記第２の出力用接続端子は、前記第１の出力用接続端子よりも前記第３の出力用接続端子側に配置されるとともに、前記第３の出力用接続端子側から引き廻されてくる配線を介して前記他方の側から引き出される第１ラインに電気的に接続され、前記第３の出力用接続端子側から引き廻されてくる配線は、前記複数の第１ラインを駆動する第１の半導体チップを搭載する第１の搭載領域内に配置されていることを特徴とするものである。
請求項２に記載の発明は、請求項１に記載の発明において、前記第１の出力用接続端子及び前記第２の出力用接続端子は、前記複数の第１ラインを駆動する第１の半導体チップを搭載する第１の搭載領域に配置され、前記第３の出力用接続端子は、前記第２ラインを駆動する第２の半導体チップを搭載する第２の搭載領域に配置されていることを特徴とするものである。
請求項３に記載の発明は、請求項１または２に記載の発明において、前記第１の出力用接続端子及び前記第２の出力用接続端子は、前記第１の基板の端部から延伸される所定の配線上に形成されていることを特徴とするものである。
そして、この発明によれば、基板の突出部の突出長を小さくすることができる。 According to the first aspect of the present invention, any one of a plurality of first lines extending in the row direction of the display region is displayed from one side in the row direction in which the first substrate and the second substrate are arranged to face each other. The first line is drawn out of the display area and the other first line is drawn out of the display area from the other side in the row direction, and the second line extending in the column direction of the display area is drawn out of the display area from a predetermined side in the column direction. A first output connection electrically connected to the first line drawn from the one side on the first substrate on the side to draw the second line out of the display area. A terminal, a second output connection terminal electrically connected to the first line drawn from the other side, and a third output connection terminal electrically connected to the second line. Having the first output The connection terminal for output, the second connection terminal for output, and the third connection terminal for output are arranged along the row direction, respectively, and the first output connection terminal is connected to the second output connection terminal. The second output connection terminal is disposed closer to the third output connection terminal than the first output connection terminal, and the third output connection terminal is disposed closer to the display area than the terminal. The wiring that is electrically connected to the first line drawn from the other side through the wiring routed from the output connection terminal side, and that is routed from the third output connection terminal side, The first semiconductor chip is disposed in a first mounting region on which a first semiconductor chip for driving the plurality of first lines is mounted .
According to a second aspect of the present invention, in the first aspect of the invention, the first output connection terminal and the second output connection terminal are a first semiconductor that drives the plurality of first lines. It is arranged in a first mounting area for mounting a chip, and the third output connection terminal is arranged in a second mounting area for mounting a second semiconductor chip for driving the second line. It is a feature.
According to a third aspect of the present invention, in the first or second aspect of the invention, the first output connection terminal and the second output connection terminal are extended from an end portion of the first substrate. It is formed on a predetermined wiring.
And according to this invention, the protrusion length of the protrusion part of a board | substrate can be made small.

この発明によれば、基板の突出部の突出長を小さくすることができる。 According to this invention, the protrusion length of the protrusion part of a board | substrate can be made small.

図１はこの発明の第１実施形態としての液晶表示装置の一例の、要部の平面図を示したものである。この液晶表示装置は、基板１と該基板１の上方に位置する対向基板２とがほぼ方形枠状のシール材（図示せず）を介して貼り合わされ、シール材の内側における両基板１、２間に液晶（図示せず）が封入されたものからなっている。   FIG. 1 is a plan view of the main part of an example of a liquid crystal display device as a first embodiment of the present invention. In this liquid crystal display device, a substrate 1 and a counter substrate 2 positioned above the substrate 1 are bonded to each other via a substantially rectangular frame-shaped sealing material (not shown), and both substrates 1 and 2 inside the sealing material. A liquid crystal (not shown) is enclosed between them.

この場合、基板１の下辺部は対向基板２から突出されている。以下、この突出部を突出部１ａという。また、シール材は、二点鎖線で示す表示領域３の外側の対向基板２の４辺の側縁部に沿って配置されている。そして、基板１の行方向中央部は表示領域３とされ、その行方向両側は引き廻し線配置領域４、５とされている。   In this case, the lower side portion of the substrate 1 protrudes from the counter substrate 2. Hereinafter, this protrusion part is called protrusion part 1a. Moreover, the sealing material is arrange | positioned along the side edge part of 4 sides of the opposing board | substrate 2 outside the display area 3 shown with a dashed-two dotted line. A central portion in the row direction of the substrate 1 is a display region 3, and both sides in the row direction are lead line arrangement regions 4 and 5.

基板１上の表示領域３には、それぞれ、代表的に各２本づつのみが図示されているが、周知の如く、複数の走査ライン６および複数のデータライン７が行方向および列方向に延びて設けられている。両ライン６、７の各交点近傍には、図示していないが、両ライン６、７に接続された薄膜トランジスタおよびこの薄膜トランジスタによって駆動される画素電極がマトリクス状に配置されている。   In the display area 3 on the substrate 1, only two of each are shown in the figure, but as is well known, a plurality of scanning lines 6 and a plurality of data lines 7 extend in the row and column directions. Is provided. Near the intersections of the two lines 6 and 7, although not shown, thin film transistors connected to the two lines 6 and 7 and pixel electrodes driven by the thin film transistors are arranged in a matrix.

基板１の突出部１ａの上面（対向基板２との対向面）の左側の所定の箇所には走査ライン６を駆動するための１個の第１の半導体チップ１１が搭載されている。基板１の突出部１ａの上面の中央部およびその右側の所定の箇所にはデータライン７を駆動するための第２の半導体チップ１２が搭載されている。すなわち、突出部１ａ上には２個の半導体チップ１１、１２が行方向に直列的に搭載されている。   A first semiconductor chip 11 for driving the scanning line 6 is mounted at a predetermined position on the left side of the upper surface of the protruding portion 1a of the substrate 1 (the surface facing the counter substrate 2). A second semiconductor chip 12 for driving the data line 7 is mounted on the central portion of the upper surface of the protruding portion 1a of the substrate 1 and a predetermined portion on the right side thereof. That is, two semiconductor chips 11 and 12 are mounted in series in the row direction on the protruding portion 1a.

走査ライン６のうちのほぼ上半分の左端部は、その左側の引き廻し線配置領域４に設けられた引き廻し線１３（第１の引き廻し線）を介して、後述の如く、第１の半導体チップ１１の出力端子の一部（第１の出力端子）（ここでは図示せず）に接続されている。走査ライン６のうちのほぼ下半分の右端部は、その右側の引き廻し線配置領域５に設けられた引き廻し線１４（第２の引き廻し線）および基板１の突出部１ａ上の第２の半導体チップ１２の列方向中央部下の所定の箇所に設けられた引き廻し線１５（第３の引き廻し線）を介して、後述の如く、第１の半導体チップ１１の、残りの出力端子（第２の出力端子）（ここでは図示せず）に接続されている。   As will be described later, the left end of the upper half of the scanning line 6 is connected to the first end as shown below via a lead line 13 (first lead line) provided in the lead line arrangement region 4 on the left side. The semiconductor chip 11 is connected to a part of the output terminal (first output terminal) (not shown here). The right end portion of the substantially lower half of the scanning line 6 has a lead line 14 (second lead line) provided in the lead line arrangement region 5 on the right side thereof and a second end on the protruding portion 1 a of the substrate 1. As will be described later, the remaining output terminals of the first semiconductor chip 11 (the third routing line) are provided via a routing line 15 (third routing line) provided at a predetermined position below the central portion of the semiconductor chip 12 in the column direction. (Second output terminal) (not shown here).

なお、図１においては、上記のように、走査ライン６の上半分が、引き廻し線１３を介して、第１の半導体チップ１１の出力端子に接続され、走査ライン６の下半分が、引き廻し線１４および引き廻し線１５を介して、第１の半導体チップ１１の出力端子に接続されるものとしたが、これに限るものではなく、走査ライン６の下半分が、引き廻し線１３を介して、第１の半導体チップ１１の出力端子に接続され、走査ライン６の上半分が、引き廻し線１４および引き廻し線１５を介して、第１の半導体チップ１１の出力端子に接続されるようにしてもよく、更に、走査ライン６の偶数行、又は、奇数行のいずれか一方が、引き廻し線１３を介して、第１の半導体チップ１１の出力端子に接続され、走査ライン６の偶数行、又は、奇数行の他方が、引き廻し線１４および引き廻し線１５を介して、第１の半導体チップ１１の出力端子に接続されるようにしてもよい。   In FIG. 1, as described above, the upper half of the scanning line 6 is connected to the output terminal of the first semiconductor chip 11 via the lead line 13, and the lower half of the scanning line 6 is pulled. Although it is assumed that it is connected to the output terminal of the first semiconductor chip 11 via the turning line 14 and the drawing line 15, the present invention is not limited to this, and the lower half of the scanning line 6 connects the drawing line 13. The upper half of the scanning line 6 is connected to the output terminal of the first semiconductor chip 11 via the lead line 14 and the lead line 15. Further, either the even-numbered row or the odd-numbered row of the scanning line 6 is connected to the output terminal of the first semiconductor chip 11 via the lead line 13, and The other of the even or odd rows , Via a pull turning line 14 and pull turning line 15, it may be connected to the output terminal of the first semiconductor chip 11.

データライン７の下端部は、その下側に設けられた引き廻し線１６を介して、後述の如く、第２の半導体チップ１２の出力端子（ここでは図示せず）に接続されている。ここで、引き廻し線１３、引き廻し線１４、引き廻し線１５および引き廻し線１６は、それぞれ、その両端部についてのみ図示されており、その内側のものは全て図示が省略されている。   The lower end of the data line 7 is connected to an output terminal (not shown here) of the second semiconductor chip 12 through a lead wire 16 provided below the data line 7 as will be described later. Here, each of the lead line 13, the lead line 14, the lead line 15 and the lead line 16 is shown only at both ends thereof, and the illustrations of all the inner parts thereof are omitted.

基板１の突出部１ａ上において第１の半導体チップ１１搭載領域の左半分の下側には外部接続端子１７が設けられている。基板１の突出部１ａ上において第２の半導体チップ１２搭載領域の下側には外部接続端子１８が設けられている。ここで、外部接続端子１７、１８は、それぞれ、その両端部についてのみ図示されており、その内側のものは全て図示が省略されている。   An external connection terminal 17 is provided below the left half of the first semiconductor chip 11 mounting region on the protruding portion 1 a of the substrate 1. External connection terminals 18 are provided below the second semiconductor chip 12 mounting region on the protruding portion 1 a of the substrate 1. Here, each of the external connection terminals 17 and 18 is shown only at both ends thereof, and the illustrations of all the internal connection terminals are omitted.

外部接続端子１７の上端部は、後述の如く、第１の半導体チップ１１の入力端子（ここでは図示せず）に接続されている。外部接続端子１８の上端部は、後述の如く、第２の半導体チップ１２の入力端子（ここでは図示せず）に接続されている。外部接続端子１７、１８の下端部にはフレキシブル配線板１９の一端部が接続されている。   The upper end portion of the external connection terminal 17 is connected to an input terminal (not shown here) of the first semiconductor chip 11 as will be described later. The upper end portion of the external connection terminal 18 is connected to an input terminal (not shown here) of the second semiconductor chip 12 as will be described later. One end of a flexible wiring board 19 is connected to the lower ends of the external connection terminals 17 and 18.

次に、図２（Ａ）は基板１の第１の半導体チップ１１搭載領域の部分の一例の拡大平面図を示す。基板１の突出部１ａの上面において一点鎖線で囲まれた領域２１は、第１の半導体チップ１１が搭載される第１の半導体チップ搭載領域である。第１の半導体チップ搭載領域２１内の下辺部のほぼ左半分には、複数の外部接続端子１７の一端部からなる入力用接続端子２２が設けられている。   Next, FIG. 2A shows an enlarged plan view of an example of a portion of the substrate 1 where the first semiconductor chip 11 is mounted. A region 21 surrounded by an alternate long and short dash line on the upper surface of the protruding portion 1 a of the substrate 1 is a first semiconductor chip mounting region on which the first semiconductor chip 11 is mounted. An input connection terminal 22 composed of one end portions of a plurality of external connection terminals 17 is provided on substantially the left half of the lower side portion in the first semiconductor chip mounting region 21.

第１の半導体チップ搭載領域２１内の上辺部のほぼ左半分には、複数の引き廻し線１３の一端部からなる出力用接続端子２３（第１の出力端子）が設けられている。出力用接続端子２３には、図１において走査ライン６のうちのほぼ上半分を陽極酸化するための陽極酸化ライン２４の一端部が接続されている。陽極酸化ライン２４の他端部は、第１の半導体チップ搭載領域２１内を引き廻された後に、第１の半導体チップ搭載領域２１の左側に延出されて基板１の左端面まで延ばされている。   An output connection terminal 23 (first output terminal) composed of one end portions of a plurality of lead wires 13 is provided on substantially the left half of the upper side portion in the first semiconductor chip mounting region 21. One end of an anodizing line 24 for anodizing the upper half of the scanning line 6 in FIG. 1 is connected to the output connection terminal 23. The other end of the anodic oxidation line 24 is routed through the first semiconductor chip mounting region 21, and then is extended to the left side of the first semiconductor chip mounting region 21 to the left end surface of the substrate 1. ing.

第１の半導体チップ搭載領域２１内の下辺部のほぼ右半分には、複数の引き廻し線１５の一端部からなる出力用接続端子２５（第２の出力端子）が設けられている。この場合、引き廻し線１５の他端部側は、第１の半導体チップ搭載領域２１内を引き廻された後に、第１の半導体チップ搭載領域２１の右側に延出されている（この延出部分については後で説明する。）。出力用接続端子２５には、図１において走査ライン６のうちのほぼ下半分を陽極酸化するための陽極酸化ライン２６の一端部が接続されている。陽極酸化ライン２６の他端部は、突出部１ａの突出端面まで延ばされている。   An output connection terminal 25 (second output terminal) consisting of one end of a plurality of lead wires 15 is provided on the almost right half of the lower side in the first semiconductor chip mounting region 21. In this case, the other end side of the lead wire 15 is routed in the first semiconductor chip mounting region 21 and then extended to the right side of the first semiconductor chip mounting region 21 (this extension). The part will be explained later.) One end of an anodizing line 26 for anodizing the lower half of the scanning line 6 in FIG. 1 is connected to the output connection terminal 25. The other end portion of the anodizing line 26 extends to the protruding end surface of the protruding portion 1a.

次に、図２（Ｂ）は第１の半導体チップ１１の端子位置を示すための透過拡大平面図を示す。第１の半導体チップ１１の下面の下辺部のほぼ左半分には複数の入力端子２７が設けられ、同下面の上辺部のほぼ左半分には複数の出力端子２８が設けられ、同下面の下辺部のほぼ右半分には複数の出力端子２９が設けられている。そして、第１の半導体チップ１１を第１の半導体チップ搭載領域２１上に搭載した状態では、端子２７、２８、２９はそれぞれ対応する接続端子２２、２３、２５に接続されている。   Next, FIG. 2B shows a transparent enlarged plan view for showing the terminal positions of the first semiconductor chip 11. A plurality of input terminals 27 are provided in substantially the left half of the lower side portion of the lower surface of the first semiconductor chip 11, and a plurality of output terminals 28 are provided in substantially the left half of the upper side portion of the lower surface of the first semiconductor chip 11. A plurality of output terminals 29 are provided in almost the right half of the section. In a state where the first semiconductor chip 11 is mounted on the first semiconductor chip mounting region 21, the terminals 27, 28, and 29 are connected to the corresponding connection terminals 22, 23, and 25, respectively.

次に、図３（Ａ）は基板１の第２の半導体チップ１２搭載領域の部分の拡大平面図を示す。基板１の突出部１ａの上面において一点鎖線で囲まれた領域３１は、第２の半導体チップ１２が搭載される第２の半導体チップ搭載領域である。第２の半導体チップ搭載領域３１内の下辺部には、複数の外部接続端子１８の一端部からなる入力用接続端子３２が設けられている。第２の半導体チップ搭載領域３１内の上辺部には、複数の引き廻し線１６の一端部からなる出力用接続端子３３が設けられている。   Next, FIG. 3A shows an enlarged plan view of a portion of the substrate 1 where the second semiconductor chip 12 is mounted. A region 31 surrounded by an alternate long and short dash line on the upper surface of the protruding portion 1 a of the substrate 1 is a second semiconductor chip mounting region on which the second semiconductor chip 12 is mounted. An input connection terminal 32 including one end portions of the plurality of external connection terminals 18 is provided on the lower side portion in the second semiconductor chip mounting region 31. On the upper side of the second semiconductor chip mounting region 31, an output connection terminal 33 composed of one end of a plurality of lead wires 16 is provided.

第２の半導体チップ搭載領域３１内の幅方向（列方向）中央部には、図２（Ａ）に示すように、第１の半導体チップ搭載領域２１の右側に延出された引き廻し線１５が配置されている。この引き廻し線１５の他端部は、第２の半導体チップ搭載領域３１の右辺において引き廻し線１４に接続されている。   At the center in the width direction (column direction) in the second semiconductor chip mounting region 31, as shown in FIG. 2A, the lead line 15 extending to the right side of the first semiconductor chip mounting region 21 is provided. Is arranged. The other end of the lead wire 15 is connected to the lead wire 14 on the right side of the second semiconductor chip mounting region 31.

次に、図３（Ｂ）は第２の半導体チップ１２の端子位置を示すための透過拡大平面図を示す。第２の半導体チップ１２の下面の下辺部には複数の入力端子３４が設けられ、同下面の上辺部には複数の出力端子３５が設けられている。そして、第２の半導体チップ１２を第２の半導体チップ搭載領域３１上に搭載した状態では、端子３４、３５はそれぞれ対応する接続端子３２、３３に接続されている。   Next, FIG. 3B is a transparent enlarged plan view for showing the terminal positions of the second semiconductor chip 12. A plurality of input terminals 34 are provided on the lower side portion of the lower surface of the second semiconductor chip 12, and a plurality of output terminals 35 are provided on the upper side portion of the lower surface. In the state where the second semiconductor chip 12 is mounted on the second semiconductor chip mounting region 31, the terminals 34 and 35 are connected to the corresponding connection terminals 32 and 33, respectively.

以上のように、この液晶表示装置では、図１に示すように、走査ライン６のほぼ上半分を表示領域３の左側に設けられた引き廻し線１３を介して第１の半導体チップ１１の下面に設けられた出力端子２８（図２（Ｂ））に接続し、走査ライン６のほぼ下半分を表示領域３の右側に設けられた引き廻し線１４および突出部１ａ上の第２の半導体チップ１２下に設けられた引き廻し線１５を介して第１の半導体チップ１１の下面に設けられた出力端子２９（図２（Ｂ））に接続している。   As described above, in this liquid crystal display device, as shown in FIG. 1, the lower surface of the first semiconductor chip 11 is provided on the substantially upper half of the scanning line 6 via the lead line 13 provided on the left side of the display region 3. 2 is connected to the output terminal 28 (FIG. 2B), and the lower half of the scanning line 6 is connected to the lead line 14 provided on the right side of the display area 3 and the second semiconductor chip on the protruding portion 1a. 12 is connected to an output terminal 29 (FIG. 2 (B)) provided on the lower surface of the first semiconductor chip 11 through a lead wire 15 provided below.

このような構造であると、特に、表示領域３の左側に設けられた引き廻し線１３の突出部１ａ上における配置領域を比較的小さくすることができる。また、突出部１ａ上の引き廻し線１５は第２の半導体チップ１２下に設けられているため、引き廻し線１５の配置領域を列方向に専用に設ける必要がない。これにより、基板１の突出部１ａの突出長を小さくすることができる。   With such a structure, in particular, the arrangement area on the protruding portion 1a of the lead line 13 provided on the left side of the display area 3 can be made relatively small. Further, since the lead line 15 on the projecting portion 1a is provided under the second semiconductor chip 12, it is not necessary to provide a dedicated region for the lead line 15 in the column direction. Thereby, the protrusion length of the protrusion part 1a of the board | substrate 1 can be made small.

なお、上記実施形態では、図２（Ａ）に示すように、第１の半導体チップ搭載領域２１内の下辺部のほぼ左半分に入力用接続端子２２を設け、上辺部のほぼ左半分と下辺部のほぼ右半分とに出力用接続端子２３、２５を設けているが、これに限定されるものではない。   In the above embodiment, as shown in FIG. 2A, the input connection terminal 22 is provided in the substantially left half of the lower side portion in the first semiconductor chip mounting area 21, and the substantially left half and the lower side of the upper side portion are provided. Although the output connection terminals 23 and 25 are provided in almost the right half of the section, the present invention is not limited to this.

例えば、図４（Ａ）に示すこの発明の第２実施形態のように、第１の半導体チップ搭載領域２１内の下辺部のほぼ左半分に入力用接続端子２２を設け、上辺部のほぼ左半分と上辺部のほぼ右半分とに出力用接続端子２３、２５を設けるようにしてもよい。この場合、図４（Ｂ）に示すように、第１の半導体チップ１１の下面の下辺部のほぼ左半分に入力端子２７を設け、上辺部のほぼ左半分と上辺部のほぼ右半分とに出力端子２８、２９を設ければよい。   For example, as in the second embodiment of the present invention shown in FIG. 4A, the input connection terminal 22 is provided in the substantially left half of the lower side portion in the first semiconductor chip mounting region 21, and the upper left side is substantially left. The output connection terminals 23 and 25 may be provided on the half and almost the right half of the upper side. In this case, as shown in FIG. 4B, an input terminal 27 is provided in the substantially left half of the lower side portion of the lower surface of the first semiconductor chip 11, and is provided in the substantially left half of the upper side portion and the substantially right half of the upper side portion. The output terminals 28 and 29 may be provided.

また、図５（Ａ）に示すこの発明の第３実施形態のように、第１の半導体チップ搭載領域２１内の下辺部のほぼ右半分に入力用接続端子２２を設け、上辺部のほぼ左半分と上辺部のほぼ右半分とに出力用接続端子２３、２５を設けるようにしてもよい。この場合、図５（Ｂ）に示すように、第１の半導体チップ１１の下面の下辺部のほぼ右半分に入力端子２７を設け、上辺部のほぼ左半分と上辺部のほぼ右半分とに出力端子２８、２９を設ければよい。   Further, as in the third embodiment of the present invention shown in FIG. 5A, the input connection terminal 22 is provided in the substantially right half of the lower side portion in the first semiconductor chip mounting region 21, and the left side of the upper side portion is substantially left. The output connection terminals 23 and 25 may be provided on the half and almost the right half of the upper side. In this case, as shown in FIG. 5B, an input terminal 27 is provided on the substantially right half of the lower side of the lower surface of the first semiconductor chip 11 so that the upper half is substantially the left half and the upper side is substantially the right half. The output terminals 28 and 29 may be provided.

さらに、例えば、図１に示す状態に対して、左右を逆にして配置した形態としてもよい。すなわち、基板１の突出部１ａ上の右側に第１の半導体チップ１１を搭載し、中央部および左側に第２の半導体チップ１２を搭載するようにして、図６（Ａ）に示すこの発明の第４実施形態のように、第１の半導体チップ搭載領域２１内の下辺部のほぼ右半分に入力用接続端子２２を設け、下辺部のほぼ左半分と上辺部のほぼ右半分とに出力用接続端子２３、２５を設けるようにしてもよい。この場合、図６（Ｂ）に示すように、第１の半導体チップ１１の下面の下辺部のほぼ右半分に入力端子２７を設け、下辺部のほぼ左半分と上辺部のほぼ右半分とに出力端子２８、２９を設ければよい。   Furthermore, for example, a configuration in which the left and right are reversed with respect to the state illustrated in FIG. That is, the first semiconductor chip 11 is mounted on the right side on the protruding portion 1a of the substrate 1 and the second semiconductor chip 12 is mounted on the central portion and the left side, so that the present invention shown in FIG. As in the fourth embodiment, the input connection terminal 22 is provided in the substantially right half of the lower side portion in the first semiconductor chip mounting area 21, and the output connection terminal is provided in the substantially left half of the lower side portion and the substantially right half of the upper side portion. Connection terminals 23 and 25 may be provided. In this case, as shown in FIG. 6B, an input terminal 27 is provided in the substantially right half of the lower side of the lower surface of the first semiconductor chip 11, and is provided in the substantially left half of the lower side and the right half of the upper side. The output terminals 28 and 29 may be provided.

この発明の第１実施形態としての液晶表示装置の要部の平面図。The top view of the principal part of the liquid crystal display device as 1st Embodiment of this invention. （Ａ）は第１の半導体チップ搭載領域の部分の拡大平面図、（Ｂ）は第１の半導体チップの端子位置を示すための透過拡大平面図。(A) is an enlarged plan view of a portion of the first semiconductor chip mounting region, and (B) is a transparent enlarged plan view for showing terminal positions of the first semiconductor chip. （Ａ）は第２の半導体チップ搭載領域の部分の拡大平面図、（Ｂ）は第２の半導体チップの端子位置を示すための透過拡大平面図。(A) is an enlarged plan view of a portion of the second semiconductor chip mounting region, and (B) is a transparent enlarged plan view for showing terminal positions of the second semiconductor chip. （Ａ）、（Ｂ）はそれぞれこの発明の第２実施形態を説明するために示す図２（Ａ）、（Ｂ）同様の拡大平面図および透過拡大平面図。FIGS. 2A and 2B are respectively an enlarged plan view and a transmission enlarged plan view similar to FIGS. 2A and 2B for explaining a second embodiment of the present invention. （Ａ）、（Ｂ）はそれぞれこの発明の第３実施形態を説明するために示す図２（Ａ）、（Ｂ）同様の拡大平面図および透過拡大平面図。FIGS. 2A and 2B are respectively an enlarged plan view and a transmission enlarged plan view similar to FIGS. 2A and 2B for explaining a third embodiment of the present invention. （Ａ）、（Ｂ）はそれぞれこの発明の第４実施形態を説明するために示す図２（Ａ）、（Ｂ）同様の拡大平面図および透過拡大平面図。FIGS. 2A and 2B are respectively an enlarged plan view and a transmission enlarged plan view similar to FIGS. 2A and 2B for explaining a fourth embodiment of the present invention. 従来の液晶表示装置の構成の一例の要部を示す平面図。The top view which shows the principal part of an example of a structure of the conventional liquid crystal display device.

符号の説明Explanation of symbols

１ 基板
１ａ 突出部
２ 対向基板
３ 表示領域
４、５ 引き廻し線配置領域
６ 走査ライン
７ データライン
１１ 第１の半導体チップ
１２ 第２の半導体チップ
１３〜１６ 引き廻し線
１７、１８ 外部接続端子
１９ フレキシブル配線板 DESCRIPTION OF SYMBOLS 1 Board | substrate 1a Protrusion part 2 Opposite board | substrate 3 Display area 4, 5 Leading line arrangement | positioning area | region 6 Scan line 7 Data line 11 1st semiconductor chip 12 2nd semiconductor chips 13-16 Leading line 17, 18 External connection terminal 19 Flexible wiring board

Claims (3)

第１の基板と第２の基板とが対向配置され、
表示領域の行方向に延びる複数の第１ラインの何れかを前記行方向における一方の側から前記表示領域外に引き出すとともに他の第１ラインを前記行方向における他方の側から前記表示領域外に引き出し、
前記表示領域の列方向に延びる第２ラインを前記列方向における所定の側から前記表示領域外に引き出す表示装置において、
前記第２ラインを前記表示領域外に引き出す側の前記第１の基板上に、
前記一方の側から引き出される第１ラインに電気的に接続される第１の出力用接続端子と、
前記他方の側から引き出される第１ラインに電気的に接続される第２の出力用接続端子と、
前記第２ラインに電気的に接続される第３の出力用接続端子と、を有し、
前記第１の出力用接続端子、前記第２の出力用接続端子及び前記第３の出力用接続端子は、それぞれ前記行方向に沿って配列され、
前記第１の出力用接続端子は、前記第２の出力用接続端子よりも前記表示領域側に配置され、
前記第２の出力用接続端子は、前記第１の出力用接続端子よりも前記第３の出力用接続端子側に配置されるとともに、前記第３の出力用接続端子側から引き廻されてくる配線を介して前記他方の側から引き出される第１ラインに電気的に接続され、
前記第３の出力用接続端子側から引き廻されてくる配線は、前記複数の第１ラインを駆動する第１の半導体チップを搭載する第１の搭載領域内に配置されていることを特徴とする表示装置。 The first substrate and the second substrate are arranged to face each other,
One of a plurality of first lines extending in the row direction of the display area is pulled out of the display area from one side in the row direction, and the other first line is drawn out of the display area from the other side in the row direction. drawer,
In the display device that pulls out the second line extending in the column direction of the display region from the predetermined side in the column direction to the outside of the display region,
On the first substrate on the side where the second line is drawn out of the display area,
A first output connection terminal electrically connected to a first line drawn from the one side;
A second output connection terminal electrically connected to the first line drawn from the other side;
A third output connection terminal electrically connected to the second line,
The first output connection terminal, the second output connection terminal, and the third output connection terminal are each arranged along the row direction,
The first output connection terminal is disposed closer to the display area than the second output connection terminal,
The second output connection terminal is disposed closer to the third output connection terminal than the first output connection terminal, and is routed from the third output connection terminal side. Electrically connected to a first line drawn from the other side via wiring ,
The wiring routed from the third output connection terminal side is disposed in a first mounting region on which a first semiconductor chip for driving the plurality of first lines is mounted. Display device. 前記第１の出力用接続端子及び前記第２の出力用接続端子は、前記複数の第１ラインを駆動する第１の半導体チップを搭載する第１の搭載領域に配置され、
前記第３の出力用接続端子は、前記第２ラインを駆動する第２の半導体チップを搭載する第２の搭載領域に配置されていることを特徴とする請求項１に記載の表示装置。 The first output connection terminal and the second output connection terminal are disposed in a first mounting region on which a first semiconductor chip that drives the plurality of first lines is mounted.
2. The display device according to claim 1, wherein the third output connection terminal is disposed in a second mounting region on which a second semiconductor chip for driving the second line is mounted . 前記第１の出力用接続端子及び前記第２の出力用接続端子は、前記第１の基板の端部から延伸される所定の配線上に形成されていることを特徴とする請求項１または２に記載の表示装置。 Said first output connection terminal and the second output connection terminal according to claim 1 or 2, characterized in that it is formed on a predetermined wiring to be extended from an end portion of said first substrate The display device described in 1.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002328390A (en) * 2001-02-23 2002-11-15 Citizen Watch Co Ltd Liquid crystal display device and scanning electrode driving ic
JP2003075861A (en) * 2001-09-07 2003-03-12 Casio Comput Co Ltd Liquid crystal display device
JP2004101863A (en) * 2002-09-10 2004-04-02 Hitachi Displays Ltd Liquid crystal display

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002328390A (en) * 2001-02-23 2002-11-15 Citizen Watch Co Ltd Liquid crystal display device and scanning electrode driving ic
JP2003075861A (en) * 2001-09-07 2003-03-12 Casio Comput Co Ltd Liquid crystal display device
JP2004101863A (en) * 2002-09-10 2004-04-02 Hitachi Displays Ltd Liquid crystal display

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