JP4725810B2 - Serial controller and serial control method - Google Patents

Description

  The present invention relates to a serial controller and a serial control method, and more particularly, to serial control of different types of devices with different update cycles applied under an instruction from a host device.

  In general, a gaming machine such as a pachinko machine is equipped with a display for displaying an image, a speaker for generating sound effects, a stepping motor for rotating an accessory, a lamp arranged on a board, and the like. These are highly controlled in such a manner that the image display and the sound output are synchronized with the progress of the game, and further, the lighting of the lamps is also synchronized, thereby producing various effects. Improving the production effect has become one of the main issues for enhancing the appeal to players.

  As the control of these output devices becomes complicated, the processing load of a CPU (Central Processing Unit) also increases significantly. Therefore, in gaming machines, systems that reduce the load on the CPU by widely sharing the functions originally performed by the CPU, which is the host device, with the lower units are widely used. For example, graphic processing for displaying an image on an LCD (Liquid Crystal Display) is assigned to the graphic LSI, and audio processing for outputting sound from a speaker is assigned to the audio LSI.

  On the other hand, Patent Document 1 discloses a system in which lamp control of LEDs (Light Emitting Diodes) or the like is shared by a controller and lamp control is performed using a single serial port. The controller converts the signal from the CPU into serial data, and outputs this as serial data to the serial data line. The driver IC cascade-connected to the serial data line takes in the serial data to which identification data for itself is assigned, converts it into parallel data, and controls the lighting state of the light emitter connected to itself based on this. .

  Further, Patent Document 2 includes an integrated CPU that operates under the control of a host CPU, and a gaming machine system that performs graphic processing, audio processing, lamp control, and motor control in an integrated manner using this integrated CPU. It is disclosed. Note that this Patent Document 2 also mentions that a plurality of types of devices such as LEDs and motors are serially controlled by one port.

JP 2006-218137 A JP 2006-255337 A

  By the way, in serial control, data is supplied in time series to a plurality of devices connected to the same port, so that the number of devices that can be connected to the same port is limited.

  Therefore, an object of the present invention is to relax the upper limit of the number of devices that can be connected to the same port in the serial control of devices based on an instruction from a host device.

In order to solve such a problem, the first invention has a storage unit, an update cycle generation circuit, and an output control circuit, and outputs data according to an instruction from a host device to a serial data line. A serial controller for serially controlling a plurality of devices connected to the same serial data line is provided. Storage unit, a data set for each of the plurality of devices by the host system, for storing control data including a valid count value that specifies the fundamental period to allow data output to the device. The update cycle generation circuit can generate a plurality of different update cycles set based on an integer multiple of the basic cycle, and generates an update cycle specified by the host device as a time unit for updating the control data. At the same time, the temporal transition of the basic period in this update period is counted. The output control circuit outputs to the device in a basic cycle in which the count value counted with respect to the update cycle applied to a device matches the valid count value included in the control data of the device read from the storage unit. It performs data output, the fundamental period the count value does not match a valid count value, skipping a data output to this device. Of the plurality of devices connected to the same serial data line, at least one device is set to a different update cycle from other devices.

  Here, in the first invention, the storage unit may store cycle selection data for designating an update cycle as data set for each device by the host device. In this case, the update cycle generation circuit generates an update cycle specified by the cycle selection data read from the storage unit. The output control circuit selects an update cycle to be applied to each device based on the cycle selection data read from the storage unit, and determines whether or not the basic cycle matches the valid count value. Do it every time.

  In the first invention, in the case of a serial controller connected to a serial driver that drives a plurality of devices via a serial data line, the output control circuit uses identification data unique to the serial driver as a serial data header. It is preferable to add. In the case of a serial controller that performs serial control in synchronization with image display, the update cycle generation circuit preferably synchronizes the update cycle with the vertical synchronization signal by referring to the vertical synchronization signal used for image display.

The second invention has a storage unit, an update cycle generation circuit, and an output control circuit, and outputs data in accordance with an instruction from the host device to the serial data line, so that the same serial data line A serial controller for serially controlling a plurality of connected devices is provided. Storage unit, a data set for each of the plurality of devices by the upper apparatus, the includes a first effective count value that specifies the fundamental period to allow data output to the first device of the plurality of devices 1 control data, first cycle selection data that designates an update cycle that is a time unit for updating the first control data, and a basic that allows data output to the second device among the plurality of devices Second control data including a second effective count value that designates a period and second period selection data that designates an update period serving as a time unit for updating the second control data are stored. The update cycle generation circuit can generate a plurality of different update cycles set based on an integer multiple of the basic cycle, and m times the basic cycle based on the first cycle selection data read from the storage unit A first update cycle (m is an integer) is generated, and a second cycle that is n times the basic cycle (n is an integer different from m) based on the second cycle selection data read from the storage unit. Are updated, and the transition of the basic period over time in each of the first update period and the second update period is counted. The output control circuit includes a first count value counted with respect to the first update period in a basic period in which the first valid count value included in the first control data read from the storage unit coincides with the first count value. The data output to the first device is performed, and in the basic cycle that does not coincide with the first valid count value, the data output to the first device is skipped and the second count value counted with respect to the second update cycle However, in a basic cycle that matches the second valid count value included in the second control data read from the storage unit, data is output to the second device and does not match the second valid count value. In the basic period, data output to the second device is skipped. Of the plurality of devices connected to the same serial data line, at least one device is set to a different update cycle from other devices.

  Here, in the second invention, the second update cycle is preferably an integer multiple of the first update cycle. The first device is a time-division control device whose on / off is controlled by the first control data, and the second device is a current control whose current value is variably controlled by the second control data. It may be a device. The first control data may specify the on / off state of the first device in the first update period by designating the position of the basic period for turning on the first device. The second control data may define a current value supplied to the second device by a plurality of bits.

The third invention provides a serial control method for serially controlling a plurality of devices connected to the same serial data line by outputting data corresponding to an instruction from a host device to the serial data line. This control method is set to the first step and a different value for each of the plurality of devices for setting the control data including a valid count value that specifies the fundamental period to allow data output to the device for each of the plurality of devices are possible, are set based on integral multiples of the fundamental period, or Tsu system while generating the update period comprising a temporal unit of updating the control data, and counts the temporal course of the basic period in the update cycle In the second step and the basic cycle in which the count value counted with respect to the update cycle applied to a certain device matches the valid count value included in the control data of this device, data is output to this device, and In the basic cycle that does not coincide with the valid count value, a third step of skipping data output is included. Of the plurality of devices connected to the same serial data line, at least one device is set to a different update cycle from other devices.

  Here, in the third invention, the first step has a step of setting cycle selection data for designating a device update cycle, and the second step generates an update cycle designated by the cycle selection data. The third step selects an update period to be applied to each device based on the period selection data, and determines whether or not the basic period matches the valid count value for each device. You may have the step to perform.

  In the third invention, in the case of serial control connected to a serial driver that drives a plurality of devices via a serial data line, the third step includes identification data unique to the serial driver as a header of the serial data. It is preferable to have a step of adding. In the case of serial control in which serial control is performed in synchronization with image display, the second step includes a step of synchronizing the update cycle with the vertical synchronization signal by referring to the vertical synchronization signal used for image display. Is preferred.

According to a fourth aspect of the present invention, there is provided a serial control method for serially controlling a plurality of devices connected to the same serial data line by outputting data corresponding to an instruction from a host device to the serial data line. This control method includes a first effective count value that specifies a basic period in which data output to a first device among the plurality of devices is permitted as data set for each device by a host device. Control data, first cycle selection data that designates an update cycle that is a time unit for updating the first control data, and a basic cycle that permits data output to the second device among the plurality of devices The second control data including the second effective count value for designating the second control data and the second cycle selection data for designating the update cycle that is a time unit for updating the second control data are set. A first update period that is m times the basic period (m is an integer) is generated based on the step and the first period selection data, and n times the basic period based on the second period selection data ( n is different from m A second step of generating a second update cycle that is an integer) and counting the time course of the fundamental cycle in each of the first update cycle and the second update cycle, and the first update cycle In the basic cycle in which the counted first count value coincides with the first valid count value included in the first control data, data is output to the first device and coincides with the first valid count value. In the basic cycle, the data output to the first device is skipped, and the second count value counted for the second update cycle matches the second valid count value included in the second control data In the basic cycle, data output to the second device is performed, and in the basic cycle that does not match the second valid count value, data output to the second device is skipped. And a step. Of the plurality of devices connected to the same serial data line, at least one device is set to a different update cycle from other devices.

  Here, in the fourth invention, it is preferable that the second update cycle is an integer multiple of the first update cycle. The first device is a time-division control device whose on / off is controlled by the first control data, and the second device is a current control whose current value is variably controlled by the second control data. It may be a device. In this case, the first control data may specify the on / off state of the first device in the first update period by designating the position of the basic period for turning on the first device. The second control data may define a current value supplied to the second device by a plurality of bits.

  According to the present invention, the basic period for permitting data output can be individually set for each device by the effective count value. As a result, unnecessary data output can be skipped for devices that do not need to output data every basic period. As a result, when devices that require data output for each basic cycle and devices that do not require data output for each basic cycle are mixed in the same port, the upper limit on the number of devices that can be connected to the same port can be relaxed. Become.

  FIG. 1 is a block diagram of an integrated processing system that integrally controls image display, audio output, rotation of an accessory by a stepping motor, and lighting of a lamp in a gaming machine. This integrated processing system includes a CPU 1 that is a host device, an integrated LSI 2, a display device 7 such as an LCD, a speaker 8, a serial driver 9, and a device 10. The CPU 1 and the integrated LSI 2 are connected via an external bus, and commands and parameters issued by the CPU 1 (hereinafter simply referred to as “commands”) are stored in the register 3 in the integrated LSI 2. This command includes three graphics commands that define the processing content of the graphic processing unit 4, audio commands that specify the processing content of the audio processing unit 5, and serial control commands that specify the processing content of the serial controller 6. There are types. The integrated LSI 2 includes a graphic processing unit 4, an audio processing unit 5, and a serial controller 6 in addition to the register 3 serving as a storage unit. The graphic processing unit 4 reads a graphic command stored in the register 3 and performs graphic processing instructed by this command. The graphic processing is basically performed by fetching image data stored in an external ROM (not shown) via an external bus, performing drawing processing on the image data, and writing the image data in a frame memory (not shown). Then, the image for one frame read from the frame memory is displayed on the display device 7 via the bus connected to the integrated LSI 2 under the synchronization control by the vertical synchronization signal Vsnc.

The audio processing unit 5 reads an audio command stored in the register 3 and performs audio processing instructed by this command. The audio processing is basically performed by fetching audio data stored in the external ROM through an external bus and performing signal processing on the audio data. The sound generated by this audio processing is output to the speaker 8 via the bus connected to the integrated LSI 2.

  On the other hand, a plurality of serial drivers 9 are connected to the serial data lines connected to the integrated LSI 2, and a plurality of devices 10 are connected in parallel to each serial driver 9. The serial controller 6 in the integrated LSI 2 reads the serial control system command stored in the register 3 and outputs serial data corresponding to the command to the serial data line, thereby serially controlling the plurality of devices 10. In this embodiment, since the device 10 itself does not have a function of analyzing serial data, the device 10 is driven via the serial driver 9 having this function. Each serial driver 9 receives the serial data supplied to the serial data line, and drives the device 10 connected thereto in response thereto. The synchronization with the serial driver 9 is performed when the serial controller 6 supplies the clock CLK to the serial driver 9 via the clock line. Various devices 10 including a light emitting body such as an LED and a lamp, or motors such as a synchronous motor (stepping motor), a commutator motor, and an induction motor exist as devices 10 to be serially controlled. Then, as an example, two types of LED, a stepping motor that rotates an accessory and the like, which are arranged on the board surface of the gaming machine are used.

  The graphic processing unit 4, the audio processing unit 5, and the serial controller 6 are controlled so that their processes are synchronized with each other. By these controls, the moving image displayed on the gaming machine, the output sound, the lighting state of the lamp, and the movement of the accessory are synchronized, and a high performance effect is exhibited by these mutual effects. Note that a vertical synchronization signal Vsnc used for image display is supplied to the serial controller 6 in order to synchronize image display and serial control.

  FIG. 2 is a block configuration diagram of the serial controller 6. In order to simplify the description, attention is focused on the serial driver 9a to which the LED 10a and the stepping motor 10b (hereinafter simply referred to as “motor 10b”) are connected, and the serial driver 9b to which the LED 10c is connected. In this embodiment, two types of serial drivers 9 are mixed, one being a time division control driver 9a and the other being a current control driver 9b.

  The time division control driver 9a drives the devices 10a and 10b to be driven by time division control. FIG. 3 is a schematic explanatory diagram of the time division control driver 9a. Serial data is supplied to the driver 9a every basic cycle CB. When the driver 9a accepts serial data addressed to the driver 9a, the decoder 20 interprets the data (1-bit data) and selectively turns the switch 21 on and off. When the switch 21 is on, a current flows from the power supply potential to the ground potential, the LED 10a emits light (on), and when the switch 21 is off, it does not emit light (off). The gradation of the LED is determined by the ratio of the ON time of the LED 10a to one frame (for example, 1/60 sec), that is, the ON duty. For example, when one frame is divided into k basic periods CB and serial data (“0” = off, “1” = on) is supplied for each basic period CB, the lowest order is obtained if all the basic periods CB are off. Tone (black) (ON duty = 0%). Then, as the number of basic cycles CB to be turned on increases, the gradation increases, and when all the basic cycles CB are turned on, the maximum luminance (white) is obtained (on duty = 100%). Basically, in the time division control, the LED 10a is controlled with binary values of on and off, but it is possible to express intermediate gradation by adjusting the on duty. In the time-sharing control, it is only necessary to set on / off, so that the circuit configuration can be simplified. On the other hand, since the control is performed in fine time division, the control is complicated, and since one control unit (basic cycle CB) is short, there is a demerit that the number of devices that can be controlled by one port is limited. As shown in FIG. 2, the LED 10a (time division control LED) is controlled by the output destination D0, and is off (not lit) when D0 = 0, and is on (lit) when D0 = 1. On the other hand, the motor 10b is controlled by output destinations D1 to D4, the supply pulse to the motor phase A is D1, the supply pulse to the motor phase B is D2, the supply pulse to the motor phase A 'is D3, and the motor phase B'. The supply pulse to D4 is D4.

  On the other hand, the current control driver 9b drives the device 10c to be driven by current control. The driver 9b does not need to supply serial data for each basic cycle CB like the time division control driver 9a described above, and it is sufficient to supply data only when changing the output. FIG. 4 is a schematic explanatory diagram of the current control driver 9b. When the driver 9b receives serial data addressed to the driver 9b, the decoder 22 interprets the data (multi-bit data) and selects a resistance value in the variable resistor 23. The LED 10a emits light according to the resistance value set by this selection. The gradation of the LED changes continuously according to the set resistance value. In current control, since one control unit (update cycle) is long, the number of devices that can be controlled by one port can be increased, and control is easier compared to time division control. On the other hand, since it is necessary to change the current value by allocating a resistor after decoding serial data on the driver side, there is a demerit that the circuit on the driver side becomes complicated and the cost increases. As shown in FIG. 2, the LED 10c (current control LED) is controlled by an output destination D5 (for example, 3 bits). In this specification, “current control” includes control by voltage. This is because if the voltage is variably controlled, the current also changes as a result.

  Hereinafter, the register 3 shown in FIG. 1 is handled as a part of the serial controller 6. The serial controller 6 is mainly composed of a register 3, a basic cycle generation circuit 11, an update cycle generation circuit 12, and an output control circuit 13. As described above, the serial control system command issued by the CPU 1 is stored in the register 3. FIG. 5 is a diagram illustrating an example of register settings for serial control commands. Serial control commands are roughly classified into period selection data SEL and control data. The cycle selection data SEL specifies the update cycle of each device 10a to 10c. In the case of the figure, the update cycle CRa should be applied to the LEDs 10a and 10c operated by the output destinations D0 and D5, and the update cycle CRb (CRa ≠ CRb) should be applied to the motor 10b operated by the output destinations D1 to D4. Show. These update periods CRa and CRb are defined by m and n times (m and n are integers and m ≠ n) of a basic period CB, which will be described later, and the values of m and n are specified by the period selection data SEL. At this time, if the update cycles CRa and CRb are set so as to have an integer multiple relationship, it is possible to avoid complication of control related to the different devices 10a to 10c. In the following description, as an example, the update cycle CRa is 64 basic cycles (m = 64), and the update cycle CRb is 8 basic cycles (n = 8).

  On the other hand, control data prescribes | regulates the operation | movement content of each device 10a-10c. The control data includes a valid count value setting signal Sc, a valid count value CNTv, an offset value Tofs, an on-state time Ton, and a control value d. The valid count value setting signal Sc sets validity / invalidity of the valid count value CNTv. When this is “invalid”, data is output in all the basic cycles CB within the update cycle CR applied to the output destination D. Therefore, the setting signal Sc is set to “invalid” with respect to the output destination D0 (time division control LED 10a) and the output destinations D1 to D4 (motor 10b) to be subjected to time division control. On the other hand, when the setting signal Sc is “valid”, data is output only in a part of the update cycle CR applied to the output destination D. Therefore, the setting signal Sc is set to “valid” for the output destination D 5 (current control LED 10 c) that performs current control.

  When the valid count value setting signal Sc is “invalid”, that is, when the output destination D is time-division controlled, the offset value Tofs and the on-state time Ton are used as control data. The offset value Tofs indicates an offset time based on the start timing of the update cycle CR provided to the output destination D, and the on-state time Ton is the duration of the on-state based on the end timing of the off-state Indicates. These durations are defined by i, j times (i, j are integers) of the basic period CB, and the values of i, j are specified by the control data. For example, the output destination D3 in the case of FIG. 5 is turned on at a timing offset by four basic periods (i = 4) from the start timing of the update period CRb, and this is set to two basic periods (j = 2). It seems to continue. In this way, by specifying the position of the basic cycle CB for turning on the devices 10a and 10b in the update cycle CR applied to the output destination D, the devices 10a and 10b can be turned on / off in the entire update cycle CR. It is prescribed.

When the valid count value setting signal Sc is “valid”, that is, when the output destination D is current-controlled, the valid count value CNTv and the control value d are used as control data. The effective count value CNTv designates a basic cycle CB for outputting data (multiple designation is also possible). The control value d defines the value (3 bits) of data supplied to the output destination D. In the case of Figure 5, with respect to the output destination D 5 (current control LED 10c), the update period CR a first basic cycle CB (effective count value CNTv = 0), 3-bit data (the gradation value of the current control LED 10c ) Is output.

The basic cycle generation circuit 11 generates a one-shot pulse at each start timing as a basic cycle CB that defines the minimum unit of the update cycle. This basic cycle CB is output to the update cycle generation circuit 12 and the output control circuit 13. On the other hand, the update cycle generation circuit 12 can generate a plurality of update cycles (variable values) set based on an integer multiple of the basic cycle CB. The update cycle CR defines a time unit for updating the control data described above. The update cycle generation circuit 12 reads all the cycle selection data SEL stored in the register 3 and generates all the update cycles CR specified by these data. The update cycle CR is output as a count value CNT obtained by counting the time-series transition (number) of the basic cycle CB with reference to the start timing. The count value CNTa of the update cycle CRa is in the range of 0 to 63, and the update cycle. The count value CNTb of CRa is in the range of 0-7. The reason for setting the update periods CRa and CRb based on an integer multiple of the basic period CB is to clearly reflect the time-series transition of the basic period CB in each update period CRa and CRb as the count value CNT. Therefore, as long as there is no problem in synchronizing the basic period CB and the count value CNT, at the end of the time domain having a length that is an integral multiple of the basic period CB, or between adjacent basic periods CB, A temporal redundant area may be added. These update periods CRa and CRb are output to the output control circuit 13.

  The update cycle generation circuit 12 refers to the vertical synchronization signal Vsnc and synchronizes the update cycles CRa and CRb with the vertical synchronization signal Vsnc. This synchronization is realized by resetting the count values CNTa and CNTb of the update periods CRa and CRb in accordance with the vertical synchronization signal Vsnc. By synchronizing the periods in this way, it is possible to easily and highly interactively perform image display, lamp lighting on the board surface, and movement of the accessory.

  Based on the cycle selection data SEL and control data read from the register 3, the output control circuit 13 selects the update cycle of the devices 10 a to 10 c and performs time-sharing control based on the selected update cycle. . FIG. 6 is a block diagram of the output control circuit 13, and FIG. 7 is a timing chart of output control. The output control circuit 13 is mainly composed of a control unit 13a, an update cycle selection unit 13b, an operation determination unit 13c, and a data output unit 13d. Note that the serial data finally output to the serial data line is data in which the operating states of the devices 10a to 10c are arranged in time series. As a header, the serial data is specific to the serial drivers 9a and 9b. Identification data (ID) is added. This ID is used in the protocol between the serial controller 6 and the serial drivers 9a and 9b for the serial controller 6 to individually specify the serial drivers 9a and 9b, and for the serial drivers 9a and 9b to be self-addressed data. Used to identify if there is. The serial data output process is repeated every basic period CB, and the process is started at the start timing of the basic period CB.

  First, the control unit 13a grasps the current connection status of the serial driver 9 with reference to the database stored in the register 3 or other storage device at the start timing of the basic cycle CB. As a result of referring to the database shown in FIG. 6, it is found that the serial drivers 9 with ID = Drv (1) to Drv (x) are connected. In this database, in addition to the connection status of the serial driver 9, the connection status of the device 10 driven by each serial driver 9 is described and managed by the CPU 1. As a result of referring to the database, when the ID of the currently connected serial driver 9 is Drv (1) to Drv (x), in principle, data output to all x serial drivers 9 within the period of one basic cycle CB Are sequentially performed in units of drivers (however, data output may be skipped for the current control driver 9b).

First, data output to the time division control driver 9a (ID = Drv (1)) is performed. First, the output destination D connected to Drv (1) is specified by referring to the database. As a result of referring to the database shown in FIG. 6 , it is found that the output destinations connected to Drv (1) are D0 to D4. The control unit 13a requests the register 3 as a reading source to read the cycle selection data SEL and the control data regarding the output destinations D0 to D4. At the same time, the control unit 13a outputs the header (1) including the ID (= Drv (1)) of the serial driver 9a that is the current output target to the data output unit 13d. Receiving this, the data output unit 13d outputs the header (1) (including ID = Drv (1)) to the serial data line as the head data of the serial data.

  When the cycle selection data SEL is read from the register 3, the update cycle selection unit 13b sequentially selects the update cycle CR to be applied to each of the output destinations D0 to D4 under the control of the control unit 13a. In the case of FIG. 5, the update cycle CRa is selected for the output destination D0, and the current count value CNTa related to this update cycle CRa is output to the operation determination unit 13c. As shown in FIG. 7, since the update cycle CRa corresponds to 64 basic cycles, the count value CNTa is sequentially counted up within a range from 0 to 63. On the other hand, the update cycle CRb is selected for the output destinations D1 to D4, and the current count value CNTb related to the update cycle CRb is output to the operation determination unit 13c. Since the update cycle CRb corresponds to eight basic cycles, the count value CNTb is sequentially counted up within a range from 0 to 7.

  Each time the selected count value CNT (CNTa or CNTb) is input, the operation determination unit 13c determines the operation of the output destination D (any one of D0 to D4) associated with the input count value CNT. . In determining this operation, first, the valid count value setting signal Sc is read.

  In the case of FIG. 5, the valid count value setting signal Sc of the output destinations D0 to D4 is set to “invalid”. In this case, the data output to each of the output destinations D0 to D4 includes the count value CNT of the update period CR applied to the output destination D, the offset value Tofs of the output destination D, and the ON state of the output destination D Based on the following setting rule with the time Ton as an input, it is uniquely identified.

(Setting rules)
Count value CNT Operation status of output destination D CNT <Tofs Off (= 0)
Tofs ≦ CNT <(Tofs + Ton) ON (= 1)
(Tofs + Ton) ≤ CNT off (= 0)

  In the case of FIG. 5, the offset value Tofs of the output destination D0 is 0, and the on-state time Ton is 32. Therefore, when the count value CNTa = 0, the output destination D0 is set to ON. The output destinations (D1, D2, D3, D4) subsequent to the output destination D0 are sequentially set to (on, off, off, off). The operation determination unit 13c outputs (1, 1, 0, 0, 0) in which the operation states of the output destinations D0 to D4 are arranged in time series as data (1) to the data output unit 13d. Receiving this, the data output unit 13d uses (1, 1, 0, 0, 0) as the data (1) following the header (1) (including ID = Drv1) as the serial data line in units of the basic cycle CB. Output. The serial data constituted by the header (1) and the data (1) is data for the time division control driver 9a with ID = Drv1.

Next, data output to the current control driver 9b (ID = Drv (2)) is performed. By referring to the database, the output destination D connected to Drv (2) is specified. As a result of referring to the database shown in FIG. 6 , it is found that the output destination connected to Drv (2) is D5. The control unit 13a requests the register 3 as a reading source to read the cycle selection data SEL and the control data regarding the output destination D5. At the same time, the control unit 13a outputs the header (2) including the ID (= Drv (2)) of the serial driver 9b to be output this time to the data output unit 13d. Receiving this, the data output unit 13d outputs the header (2) (including ID = Drv (2)) to the serial data line as the head data of the serial data.

  When the cycle selection data SEL is read from the register 3, the update cycle selection unit 13b selects the update cycle CR to be applied to the output destination D5 under the control of the control unit 13a. In the case of FIG. 5, the update cycle CRa is selected for the output destination D5, and the current count value CNTa related to this update cycle CRa is output to the operation determination unit 13c.

  The operation determination unit 13c reads the valid count value setting signal Sc of the output destination D5. In the case of FIG. 5, the valid count value setting signal Sc of the output destination D5 is set to “valid”. In this case, whether or not to output data to the output destination D5 in the current basic cycle CB depends on the count value CNTa of the update period CRa applied to the output destination D5 and the valid count value CNTv of the output destination D5. Judgment based on. Then, in the basic cycle CB where the count value CNTa matches the valid count value CNTv, data output to the output destination D5 is performed. In this case, data to be output to the output destination D5 is generated based on the control value d (3 bits) of the output destination D5 read from the register 3. On the other hand, in the basic cycle CB where the count value CNTa does not coincide with the valid count value CNTv, the data is skipped without outputting the data to the output destination D5. In the case of FIG. 5, since the valid count value CNTv of the output destination D5 is 0, data corresponding to the control value d is output in the head basic cycle CB (CNTa = 0).

  The above device-by-device processing is similarly repeated for the serial driver 9 with ID = Drv (3), Drv (4),..., Drv (x). Then, the processing within one basic cycle is completed when the processing related to all the serial drivers 9 is completed. Such processing within one basic period is repeated every basic period CB. It should be noted that data output to the output destinations D0 to D4 is repeated every basic cycle CB, but data output to the output destination D5 is performed only in the first basic cycle CB in the update cycle CRa. This is a point to be skipped in the second to 63rd basic cycles (CNTa ≠ 0).

  As a result of the above process being repeated, the output destinations D0 to D5 change as shown in FIG. First, the output destination D0 (SEL = CRa, Tofs = 0, Ton = 32) rises to 1 level at the count value CNTa = 0, which is the start timing of the update cycle CRa, and this state reaches the count value CNTa = 32. Continue until Then, when it reaches the count value CNTa = 32, it falls to 0 level and continues until the count value CNTa = 63, which is the end timing of the update cycle CRa. As a result, the time-division control LED 10a connected to the output destination D0 emits light with an on-duty of 50% within a period in which the update cycle CRa is one frame (unit for driving the device). The gradation control of the LED 10a is performed by adjusting the on-duty. The output destination D1 (SEL = CRb, Tofs = 0, Ton = 2) rises to 1 level when the count value CNTb = 0, which is the start timing of the update cycle CRb, and this state reaches the count value CNTb = 2. Continue until When the count value CNTb = 2 is reached, it falls to 0 level and continues until the count value CNTa = 7, which is the end timing of the update cycle CRb. With respect to the output destinations D2 to D4, the waveforms of the output destination D1 are sequentially shifted by two basic periods. As a result, when the motor 10b connected to the output destinations D1 to D4 is a one-phase excitation stepping motor, the motor 10b rotates forward by 4 pulses within the update period CRb (the step angle per pulse is 1 degree). If so, 4 degrees). The rotation control of the motor 10b is performed by adjusting the pulse. When the motor 10b is rotated in the reverse direction, the waveform shift direction at the output destinations D1 to D4 may be set in reverse.

  On the other hand, for the output destination D5 (SEL = CRa, CNTv = 0, control value d), the control value d (3 bits) corresponding to the gradation data is serial data as the head basic cycle CB (CNTa = CNTv). After that, data is not output at least within the same update cycle CRa. As a result, the current control LED 10a connected to the output destination D5 emits light corresponding to the control value d at least until the next data is supplied.

  FIG. 8 is a diagram illustrating an output example of serial data. A protocol related to data exchange between the serial controller 6 and the serial driver 9 is determined in advance. The serial data output to the serial data line is supplied to all the serial drivers 9a and 9b connected to the serial data line. Each serial driver 9a, 9b refers to the ID (= Drv (1), Drv (2)) included in the header of the serial data and determines whether or not it matches the ID assigned to itself. . Then, the time division control driver 9a (ID = Drv (1)) takes in the serial data addressed to Drv (1), converts the data D0 to D4 contained in this data into parallel data, and based on this, the time The division control LED 10a and the motor 10b are driven. On the other hand, the current control driver 9b (ID = Drv (2)) takes in the serial data addressed to Drv (2), converts the data D5 included in this data into parallel data, and based on this converts the current control LED 10c. Drive. The timing for fetching the bits in the serial data is defined by the rising timing of the clock CLK supplied to the clock line.

  As described above, according to the present embodiment, by providing the valid count value CNTv as data set for each device by the CPU 1, the basic cycle CB permitting data output can be individually set for each device 10a to 10c. . As a result, unnecessary data output can be skipped for the device 10c that does not need to output data every basic cycle CB. As a result, when the devices 10a and 10b that require data output for each basic cycle CB and the devices 10c that do not require data output for each basic cycle CB are mixed in the same port, the upper limit of the number of devices that can be connected to the same port is increased. It can be mitigated.

  Further, according to the present embodiment, the processing load on the CPU 1 can be reduced. The serial controller 6 generates a plurality of update periods CRa and CRb having different periods based on the period selection data SEL set by the CPU 1. At the same time, the serial controller 6 individually selects the update cycle CR applied to the different devices 10a to 10c connected to the same port on the basis of the control data set by the CPU 1, and selects the selected update cycle CR. Performs time-sharing control as a reference. Therefore, the CPU 1 only needs to set the cycle selection data SEL and the control data in the register 3, and the CPU 1 itself does not need to generate the update cycle CR or always manage them. Further, it is sufficient for the CPU 1 to set the output of the devices 10a to 10c with an update cycle CR that is relatively longer than the basic cycle CB.

  Further, according to the present embodiment, it is possible to optimize serial control related to different types of devices 10a to 10c having different update cycles CR to be applied. Here, as a comparative example, consider a case where the update cycle of all the devices 10a to 10c is constant. In this case, when the update cycle of the LEDs 10a and 10c having a long cycle is uniformly applied, the rotational resolution per unit time of the motor 10b having a short cycle is lowered, so that high-speed rotation becomes difficult. On the other hand, when the update cycle of the motor 10b having a short cycle is uniformly applied, the gradation control of the LEDs 10a and 10c having a long cycle becomes more complicated than necessary. On the other hand, in the present embodiment, different devices 10a to 10c operating at different update periods CRa and CRb can be arranged in the same port without disturbing the characteristics of the other, and And optimal device control can be performed in an integrated manner.

  Further, according to the present embodiment, a plurality of different update periods are set as integer multiples of the basic period CB. This facilitates the generation and management of the update cycle CR. In particular, if the longer update cycle CRa is set to an integral multiple of the shorter update cycle CRb, the start / end timing of the long update cycle CRa coincides with that of the short update cycle CRb, so that the heterogeneous devices 10a to 10c are controlled. It is easy to synchronize when performing the operation, and the operation setting of the devices 10a to 10c is facilitated.

  Further, according to the present embodiment, the control data such as the offset value Tofs and the on-state time Ton are defined by the number (multiple) of the basic period CB, so that the control data defining the operation contents of the devices 10a and 10b can be interpreted. It becomes easy and the circuit configuration of the serial controller 6 can be simplified.

  Furthermore, according to the present embodiment, by using the update periods CRa and CRb synchronized with the vertical synchronization signal Vsnc, it is possible to easily produce a mutual and high-dimensional effect between the image display and the operation of the different devices 10a to 10c. Can be done.

  In the above-described embodiment, the serial controller 6 performs serial control of the devices 10a to 10c via the serial drivers 9a and 9b compliant with a predefined protocol. Of course, the serial drivers 9a and 9b are not necessary when they are compatible. In this case, the devices 10a to 10c are directly connected to the serial data line.

  In the above-described embodiment, the effective count value setting signal Sc, the effective count value CNTv, the control value d, the offset value Tofs, and the on-state time Ton are used as the control data. However, any data may be used as long as at least the presence / absence of data output can be specified in units of the basic cycle CB. From this point of view, for example, as shown in FIG. 9, the offset value Tofs and the on-state time Ton may be omitted, and these may be expressed by the effective count value CNTv. In the case of FIG. 5, for example, the offset value Tofs = 0 for the output destination D0 and the on-state time Ton = 32 are equivalent to the valid count value CNTv = 0 to 31 (in this case, when Sc = “invalid” is set, It is determined that the valid count CnTv coincides with “ON” and the mismatch does not coincide with “OFF”). Therefore, the offset value Tofs and the on-state time Ton are not essentially different from the valid count value CNTv on condition that a plurality of valid count values CNTv can be designated. The “valid count value” in the present invention is any form including the combination of the offset value Tofs and the on-state time Ton as long as the basic period permitting data output to the device can be uniquely specified. (It is not necessary to be the direct value CNTv itself as in the above-described embodiment).

  Furthermore, in the embodiment described above, 1 bit (ON / OFF) is assigned to each of the output destinations D0 to D4, but a plurality of bits (ON / OFF / intermediate level) are assigned using the control value d. May be. This makes it possible to realize device control using both time-division control and current control.

Block diagram of integrated system Block diagram of serial controller Schematic illustration of time-sharing control driver Schematic illustration of current control driver The figure which shows an example of the register setting of the serial control system command Block diagram of output control circuit Output control timing chart Figure showing an example of serial data output The figure which shows another example of the register setting of a serial control system command

Explanation of symbols

1 CPU
2 Integrated LSI
3 Register 4 Graphic Processing Unit 5 Audio Processing Unit 6 Serial Controller 7 Display Device 8 Speaker 9 Serial Driver 9a Time Division Control Driver 9b Current Control Driver 10 Device 10a LED (Time Division Control LED)
10b Motor 10c LED (Current control LED)
DESCRIPTION OF SYMBOLS 11 Basic period generation circuit 12 Update period generation circuit 13 Output control circuit 13a Control part 13b Update period selection part 13c Operation determination part 13d Data output part 20,22 Decoder 21 Switch 23 Variable resistance

Claims (26)

In a serial controller that serially controls a plurality of devices connected to the same serial data line by outputting data corresponding to an instruction from the host device to the serial data line,
As data to be set for each of the plurality of devices by the host system, and a storage unit for storing control data including a valid count value that specifies the fundamental period to allow data output to the device,
It is capable of generating a plurality of different update period that is an integral multiple of the fundamental period based, as time units of updating the control data, as well as generate a designated update cycle by the host system, the update period An update cycle generator that counts the transition of the fundamental cycle over time in
In the basic cycle in which the count value counted for the update cycle applied to a device matches the valid count value included in the control data of the device read from the storage unit, data is output to the device. in the fundamental period the count value does not match the valid count value, possess an output control circuit for skipping the data output,
A serial controller, wherein at least one device among the plurality of devices connected to the same serial data line is set to an update cycle different from that of other devices . The storage unit, as the data set for each device by the host device, stores the cycle selection data specifying the update cycle,
The update cycle generation circuit generates an update cycle specified by cycle selection data read from the storage unit,
The output control circuit selects an update cycle to be applied to each device based on the cycle selection data read from the storage unit, and determines whether or not the basic cycle matches the valid count value. The serial controller according to claim 1, which is performed for each device. In the serial controller connected to a serial driver that drives the plurality of devices via a serial data line,
The serial controller according to claim 1, wherein the output control circuit adds identification data unique to a serial driver as a header of serial data. In the serial controller that performs the serial control in synchronization with image display,
4. The serial controller according to claim 1, wherein the update cycle generation circuit synchronizes the update cycle with the vertical synchronization signal by referring to a vertical synchronization signal used for image display .   5. The serial controller according to claim 1, wherein the at least one device and the other device have different device types. 6. The LED used in the gaming machine and the motor used in the gaming machine are included as the plurality of devices, and the update period different for the LED and the motor is set. The serial controller of any one of items. By outputting the data according to an instruction from the upper level device to the serial data line, a plurality of devices connected to the same said serial data line in the serial controller for serial control,
As data to be set for each of the plurality of devices by the host system, the first control including a first effective count value that specifies the fundamental period to allow data output to the first device of the plurality of devices Data, first cycle selection data for specifying an update cycle as a time unit for updating the first control data, and a basic cycle for permitting data output to the second device among the plurality of devices. A storage unit for storing second control data including a second effective count value to be specified, and second cycle selection data for specifying an update cycle as a time unit for updating the second control data;
A plurality of different update cycles set based on an integer multiple of the basic cycle can be generated, and m times the basic cycle (m is an integer) based on the first cycle selection data read from the storage unit And a second update cycle that is n times the basic cycle (n is an integer different from m) based on the second cycle selection data read from the storage unit. An update cycle generator that generates and counts the temporal transition of the basic cycle in each of the first update cycle and the second update cycle;
In the basic period in which the first count value counted with respect to the first update period coincides with the first effective count value included in the first control data read from the storage unit, to the first device In the basic period that does not match the first valid count value, the data output to the first device is skipped, and the second count value counted with respect to the second update period is In a basic cycle that matches the second effective count value included in the second control data read from the storage unit, data is output to the second device, and the basic does not match the second effective count value. the cycle, possess an output control circuit for skipping data output to the second device,
A serial controller, wherein at least one device among the plurality of devices connected to the same serial data line is set to an update cycle different from that of other devices .   The serial controller according to claim 7, wherein the second update cycle is an integral multiple of the first update cycle. The first device is a time-division control device that is controlled to be turned on / off by first control data, and the second device is a current control in which a current value is variably controlled by second control data. 9. The serial controller according to claim 7 , wherein the serial controller is a device. The first control data defines an on / off state of the first device in a first update period by designating a position of a basic period for turning on the first device. Item 10. The serial controller according to item 9 . The serial controller according to claim 9 , wherein the second control data defines a current value supplied to the second device by a plurality of bits . The serial controller according to any one of claims 7 to 11, wherein the at least one device and the other device have different device types.   The LED used in a gaming machine and a motor used in the gaming machine are included as the plurality of devices, and the update period different for the LED and the motor is set. The serial controller of any one of items. By outputting the data according to an instruction from the upper level device to the serial data line, a plurality of devices connected to the same said serial data line in the serial control method for serial control,
A first step of setting, for each of the plurality of devices, control data including an effective count value that specifies a basic period for permitting data output to the device;
A second step that is set based on an integral multiple of the basic period and that generates an update period that is a unit of time for updating the control data, and that counts the temporal transition of the basic period in the update period; ,
In the basic cycle in which the count value counted for the update cycle applied to a device matches the valid count value included in the control data of the device, data is output to the device and matches the valid count value. the fundamental period not, have a third step of skipping the data output,
A serial control method characterized in that at least one device among the plurality of devices connected to the same serial data line is set to a different update cycle from other devices . The first step includes the step of setting cycle selection data that specifies the device update cycle,
The second step includes generating an update period specified by the period selection data,
The third step includes a step of selecting, based on the cycle selection data, an update cycle to be applied to each device, and determining for each device whether or not the basic cycle matches the valid count value. 15. The serial control method according to claim 14 , further comprising: In the serial control method connected to a serial driver that drives the plurality of devices via a serial data line,
16. The serial control method according to claim 14, wherein the third step includes a step of adding identification data unique to a serial driver as a header of serial data. In the serial control method for performing the serial control in synchronization with image display,
17. The method according to claim 14, wherein the second step includes a step of synchronizing an update period with a vertical synchronization signal by referring to a vertical synchronization signal used for image display. Serial control method. The serial control method according to any one of claims 14 to 17, wherein the at least one device and the other device have different device types.   The LED used for the gaming machine and the motor used for the gaming machine are included as the plurality of devices, and the update period different for the LED and the motor is set. The serial control method according to any one of the above items. In a serial control method for serially controlling a plurality of devices connected to the same serial data line by outputting data corresponding to an instruction from a host device to a serial data line, a first of the plurality of devices is provided . First control data including a first effective count value that designates a basic period in which data output to the device is permitted, and a first period that designates an update period that is a time unit for updating the first control data Update cycle selection data, second control data including a second effective count value designating a basic cycle in which data output to a second device among the plurality of devices is permitted, and second control data. A first step of setting second cycle selection data for specifying an update cycle as a time unit;
Based on the first cycle selection data, a first update cycle that is m times the basic cycle (m is an integer) is generated, and on the basis of the second cycle selection data, n times the basic cycle (n is m A second step of generating a second update period that is a different integer) and counting the temporal transition of the fundamental period in each of the first update period and the second update period;
In the basic cycle in which the first count value counted with respect to the first update cycle matches the first valid count value included in the first control data, data is output to the first device, and the first In the basic cycle that does not coincide with the effective count value, the data output to the first device is skipped, and the second count value counted with respect to the second update cycle is included in the second control data. In a basic cycle that coincides with the effective count value, a data output to the second device is performed, and in a basic cycle that does not coincide with the second effective count value, a data output to the second device is skipped. It has a door,
A serial control method characterized in that at least one device among the plurality of devices connected to the same serial data line is set to a different update cycle from other devices . The serial control method according to claim 20 , wherein the second update cycle is an integral multiple of the first update cycle. The first device is a time-division control device that is controlled to be turned on / off by first control data, and the second device is a current control in which a current value is variably controlled by second control data. The serial control method according to claim 20 or 21 , wherein the serial control method is a device. The first control data defines an on / off state of the first device in a first update period by designating a position of a basic period for turning on the first device. Item 23. The serial control method according to Item 22 . 23. The serial control method according to claim 22 , wherein the second control data defines a current value supplied to the second device by a plurality of bits. 25. The serial control method according to claim 20, wherein the at least one device and the other device have different device types.   The LED used for a gaming machine and a motor used for the gaming machine are included as the plurality of devices, and the update period different for the LED and the motor is set. The serial control method according to any one of the above items.

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