JP4725809B2 - Serial controller and serial control method - Google Patents

Description

  The present invention relates to a serial controller and a serial control method, and more particularly, to serial control of different types of devices with different update cycles applied under an instruction from a host device.

  In general, a gaming machine such as a pachinko machine is equipped with a display for displaying an image, a speaker for generating sound effects, a stepping motor for rotating an accessory, a lamp arranged on a board, and the like. These are highly controlled in such a manner that the image display and the sound output are synchronized with the progress of the game, and further, the lighting of the lamps is also synchronized, thereby producing various effects. Improving the production effect has become one of the main issues for enhancing the appeal to players.

  As the control of these output devices becomes complicated, the processing load of a CPU (Central Processing Unit) also increases significantly. Therefore, in gaming machines, systems that reduce the load on the CPU by widely sharing the functions originally performed by the CPU, which is the host device, with the lower units are widely used. For example, graphic processing for displaying an image on an LCD (Liquid Crystal Display) is assigned to the graphic LSI, and audio processing for outputting sound from a speaker is assigned to the audio LSI.

  On the other hand, Patent Document 1 discloses a system in which lamp control of LEDs (Light Emitting Diodes) or the like is shared by a controller and lamp control is performed using a single serial port. The controller converts the signal from the CPU into serial data, and outputs this as serial data to the serial data line. The driver IC cascade-connected to the serial data line takes in the serial data to which identification data for itself is assigned, converts it into parallel data, and controls the lighting state of the light emitter connected to itself based on this. .

  Further, Patent Document 2 includes an integrated CPU that operates under the control of a host CPU, and a gaming machine system that performs graphic processing, audio processing, lamp control, and motor control in an integrated manner using this integrated CPU. It is disclosed. Note that this Patent Document 2 also mentions that a plurality of types of devices such as LEDs and motors are serially controlled by one port.

JP 2006-218137 A JP 2006-255337 A

  The LED and the stepping motor are common in that they are controlled by switching the voltage at a certain cycle (update cycle). However, each update cycle is almost different, and in general, a stepping motor has a shorter update cycle than an LED. Although Patent Document 2 conceptually discloses that a plurality of devices having different update cycles are serially controlled, such a difference in update cycles is not considered and there is no suggestion thereof. . Here, let us consider a case where the update cycle of all devices is constant regardless of the type of device. When the update cycle of the LED having a long cycle is uniformly applied, the rotation resolution per unit time of the stepping motor having a short cycle is lowered, so that high-speed rotation becomes difficult. On the other hand, when the renewal cycle of the motor having a short cycle is uniformly applied, the gradation control of the LED having a long cycle becomes more complicated than necessary. Therefore, when various devices with different update cycles are connected to the same port, a technical problem still remains regarding how to optimize the device control.

  Accordingly, an object of the present invention is to optimize device control while reducing the processing load of a host device when serially controlling different types of devices having different update cycles.

In order to solve this problem, the first invention serially controls a plurality of devices connected to the same serial data line by outputting serial data according to an instruction from the host device to the serial data line. Provide a serial controller. The controller includes a storage unit, an update cycle generation circuit, and an output control circuit. The storage unit stores data set for each of the plurality of devices by the host device. This data includes control data that defines the operation content of the device and cycle selection data that specifies an update cycle that is a time unit for updating the control data. The update cycle generation circuit can generate a plurality of different update cycles set based on an integer multiple of the basic cycle, and generates an update cycle specified by cycle selection data read from the storage unit. The output control circuit selects an update cycle to be applied to each device based on the cycle selection data read from the storage unit. In addition, the output control circuit determines the operation state of each device for each basic period constituting the selected update period for the device based on the control data read from the storage unit. Thus, the serial data to be output to the serial data line is generated. Here, at least one device among the plurality of devices connected to the same serial data line is set to an update period different from that of the other devices.

  Here, in the first invention, the storage unit includes first cycle selection data that specifies an update cycle of the first device, first control data that defines an operation content of the first device, and second Second cycle selection data for designating the update cycle of the second device and second control data for defining the operation content of the second device may be stored. In this case, the update cycle generation circuit generates a first update cycle that is m times the basic cycle (m is an integer) based on the first cycle selection data read from the storage unit. Based on the second cycle selection data read from, a second update cycle that is n times the basic cycle (n is an integer different from m) is generated. The output control circuit selects the first update cycle as the update cycle of the first device based on the first cycle selection data read from the storage unit, and the first control cycle is read from the storage unit. Based on the control data, the operation state of the first device in each of the basic periods constituting the first update period is determined. At the same time, the output control circuit selects the second update cycle as the update cycle of the second device based on the second cycle selection data read from the storage unit, and the second control cycle is read from the storage unit. Based on the control data of 2, the operation state of the second device in each of the basic periods constituting the second update period is determined.

  In the first invention, the second update cycle is preferably an integral multiple of the first update cycle. The control data may include an on-state time that defines the device operation time according to the number of basic periods, and an offset that defines an offset time based on the start timing of the update period according to the number of basic periods. It may contain a value. In the case of a serial controller connected to a serial driver that drives a plurality of devices via serial data lines, the output control circuit preferably adds identification data unique to the serial driver as a header of the serial data. Further, in the case of a serial controller that performs serial control in synchronization with image display, the update cycle generation circuit preferably synchronizes the update cycle with the vertical synchronization signal by referring to the vertical synchronization signal used for image display.

The second invention provides a serial control method for serially controlling a plurality of devices connected to the same serial data line by outputting serial data according to an instruction from a host device to the serial data line. This control method sets, for each of the plurality of devices, control data that defines the operation content of the device and cycle selection data that specifies an update cycle that is a time unit for updating the control data. A first step for generating a plurality of different update cycles specified by the set cycle selection data, and a second step for selecting an update cycle to be applied to each device based on the set cycle selection data. And the operation state of each device is determined for each basic period constituting the selected update period for the device based on the control data set in step 3 and the serial data to be output to the serial data line And a fourth step of generating data. Here, at least one device among the plurality of devices connected to the same serial data line is set to an update period different from that of the other devices.

  Here, in the second invention, in the first step, the first cycle selection data that specifies the update cycle of the first device, the first control data that defines the operation content of the first device, Second cycle selection data for specifying the update cycle of the second device and second control data for defining the operation content of the second device are set, and in the second step, the first cycle selection data is set. Based on, a first update period that is m times the basic period (m is an integer) is generated, and n times the basic period (n is an integer different from m) based on the second period selection data. A second update cycle may be generated. In this case, the third step includes selecting the first update cycle as the update cycle of the first device based on the first cycle selection data, and selecting the second update cycle based on the second cycle selection data. Preferably, the second update cycle is selected as the device update cycle. The fourth step is based on the second control data and the step of determining the operating state of the first device in each of the basic periods constituting the first update period based on the first control data. And determining the operation state of the second device in each of the basic periods constituting the second update period.

  In the second invention, the second update cycle is preferably an integral multiple of the first update cycle. In addition, the control data may include an on-state time that defines the operation time of the device according to the number of basic periods, and an offset time based on the start timing of the update period is defined according to the number of basic periods. An offset value may be included. In the case of a serial control method connected to a serial driver that drives a plurality of devices via a serial data line, the fourth step includes a step of adding identification data unique to the serial driver as a serial data header. It is preferable to have. Further, in the case of a serial control method in which serial control is performed in synchronization with image display, the second step includes a step of synchronizing the update cycle with the vertical synchronization signal by referring to the vertical synchronization signal used for image display. It is preferable.

  According to the present invention, the host device only needs to set the update period and the operation content for each device, so that the processing load on the host device can be reduced. In addition, for each device, an update cycle to be applied is selected based on data set by the host device, and an operation state of each basic cycle in the selected update cycle is also determined. Then, serial data indicating the operation state of each device is output to the serial data line. This makes it possible to perform optimal integrated control of a plurality of devices connected to the same port regardless of the difference in update cycle.

  FIG. 1 is a block diagram of an integrated processing system that integrally controls image display, audio output, rotation of an accessory by a stepping motor, and lighting of a lamp in a gaming machine. This integrated processing system includes a CPU 1 that is a host device, an integrated LSI 2, a display device 7 such as an LCD, a speaker 8, a serial driver 9, and a device 10. The CPU 1 and the integrated LSI 2 are connected via an external bus, and commands and parameters issued by the CPU 1 (hereinafter simply referred to as “commands”) are stored in the register 3 in the integrated LSI 2. This command includes three graphics commands that define the processing content of the graphic processing unit 4, audio commands that specify the processing content of the audio processing unit 5, and serial control commands that specify the processing content of the serial controller 6. There are types. The integrated LSI 2 includes a graphic processing unit 4, an audio processing unit 5, and a serial controller 6 in addition to the register 3 serving as a storage unit. The graphic processing unit 4 reads a graphic command stored in the register 3 and performs graphic processing instructed by this command. The graphic processing is basically performed by fetching image data stored in an external ROM (not shown) via an external bus, performing drawing processing on the image data, and writing the image data in a frame memory (not shown). Then, the image for one frame read from the frame memory is displayed on the display device 7 via the bus connected to the integrated LSI 2 under the synchronization control by the vertical synchronization signal Vsnc.

The audio processing unit 5 reads an audio command stored in the register 3 and performs audio processing instructed by this command. The audio processing is basically performed by fetching audio data stored in the external ROM through an external bus and performing signal processing on the audio data. The sound generated by this audio processing is output to the speaker 8 via the bus connected to the integrated LSI 2.

  On the other hand, a plurality of serial drivers 9 are connected to the serial data lines connected to the integrated LSI 2, and a plurality of devices 10 are connected in parallel to each serial driver 9. The serial controller 6 in the integrated LSI 2 reads the serial control system command stored in the register 3 and outputs serial data corresponding to the command to the serial data line, thereby serially controlling the plurality of devices 10. In this embodiment, since the device 10 itself does not have a function of analyzing serial data, the device 10 is driven via the serial driver 9 having this function. Each serial driver 9 receives the serial data supplied to the serial data line, and drives the device 10 connected thereto in response thereto. The synchronization with the serial driver 9 is performed when the serial controller 6 supplies the clock CLK to the serial driver 9 via the clock line. Various devices 10 including a light emitting body such as an LED and a lamp, or motors such as a synchronous motor (stepping motor), a commutator motor, and an induction motor exist as devices 10 to be serially controlled. Then, as an example, two types of LED, a stepping motor that rotates an accessory and the like, which are arranged on the board surface of the gaming machine are used.

  The graphic processing unit 4, the audio processing unit 5, and the serial controller 6 are controlled so that their processes are synchronized with each other. By these controls, the moving image displayed on the gaming machine, the output sound, the lighting state of the lamp, and the movement of the accessory are synchronized, and a high performance effect is exhibited by these mutual effects. Note that a vertical synchronization signal Vsnc used for image display is supplied to the serial controller 6 in order to synchronize image display and serial control.

  FIG. 2 is a block configuration diagram of the serial controller 6. In order to simplify the description, attention is focused on one serial driver 9 to which the LED 10a and the stepping motor 10b (hereinafter simply referred to as “motor 10b”) are connected. The light emitting state of the LED 10a is controlled by the output destination D0, and is off (not lit) when D0 = 0, and is on (lit) when D0 = 1. On the other hand, the motor 10b is driven and controlled by the output destinations D1 to D4, the supply pulse to the motor phase A is D1, the supply pulse to the motor phase B is D2, the supply pulse to the motor phase A 'is D3, the motor The supply pulse to phase B ′ is D4.

  Hereinafter, the register 3 shown in FIG. 1 is handled as a part of the serial controller 6. The serial controller 6 is mainly composed of a register 3, a basic cycle generation circuit 11, an update cycle generation circuit 12, and an output control circuit 13. As described above, the serial control system command issued by the CPU 1 is stored in the register 3. FIG. 3 is a diagram illustrating an example of setting the serial control command in the register 3. Serial control commands are roughly classified into period selection data SEL and control data. The cycle selection data SEL specifies the update cycle of each device 10a, 10b. The case shown in the figure indicates that the update cycle CRa should be applied to the LED 10a operated by the output destination D0, and the update cycle CRb (CRa ≠ CRb) should be applied to the motor 10b operated by the output destinations D1 to D4. These update periods CRa and CRb are defined by m and n times (m and n are integers and m ≠ n) of a basic period CB, which will be described later, and the values of m and n are specified by the period selection data SEL. At this time, if the update cycles CRa and CRb are set so as to have an integer multiple relationship, it is possible to avoid complication of control related to the different types of devices 10a and 10b. In the following description, as an example, the update cycle CRa is 64 basic cycles (m = 64), and the update cycle CRb is 8 basic cycles (n = 8).

  On the other hand, the control data defines the operation content of each device 10a, 10b, which includes an offset value Tofs and an on-state time Ton. Although details will be described later, the offset value Tofs indicates an offset time based on the start timing of the update cycle CRa (or CRb), and the on-state time Ton is an on-state based on the end timing of the off-state. Indicates the duration of. These durations are defined by i, j times (i, j are integers) of the basic period CB, and the values of i, j are specified by the control data. For example, the output destination D3 in the case of FIG. 3 is turned on at a timing that is offset by four basic cycles (i = 4) from the start timing of the update cycle CRb, and this is turned on for two basic cycles (j = 2). It seems to continue. In this way, by specifying the position of the basic cycle CB for turning on the devices 10a and 10b in the update cycles CRa and CRb, on / off of the devices 10a and 10b in the entire update cycles CRa and CRb is specified.

The basic cycle generation circuit 11 generates a one-shot pulse at each start timing as a basic cycle CB that defines the minimum unit of the update cycle. This basic cycle CB is output to the update cycle generation circuit 12 and the output control circuit 13. On the other hand, the update cycle generation circuit 12 can generate a plurality of update cycles (variable values) set based on an integer multiple of the basic cycle CB. The update cycle CR defines a time unit for updating control data such as the offset value Tofs and the on-state time Ton. The update cycle generation circuit 12 reads all the cycle selection data SEL stored in the register 3 and generates all the update cycles CR specified by these data. The update cycle CR is output as a count value CNT obtained by counting the time-series transition (number) of the basic cycle CB with reference to the start timing. The count value CNTa of the update cycle CRa is in the range of 0 to 63, and the update cycle. The count value CNTb of CRa is in the range of 0-7. The reason for setting the update periods CRa and CRb based on an integer multiple of the basic period CB is to clearly reflect the time-series transition of the basic period CB in each update period CRa and CRb as the count value CNT. Therefore, as long as there is no problem in synchronizing the basic period CB and the count value CNT, a time interval between the end of the time region having an integral multiple of the basic period CB or between adjacent basic periods CB A redundant area may be added. These update periods CRa and CRb are output to the output control circuit 13.

  The update cycle generation circuit 12 refers to the vertical synchronization signal Vsnc and synchronizes the update cycles CRa and CRb with the vertical synchronization signal Vsnc. This synchronization is realized by resetting the count values CNTa and CNTb of the update periods CRa and CRb in accordance with the vertical synchronization signal Vsnc. By synchronizing the periods in this way, it is possible to easily and highly interactively perform image display, lamp lighting on the board surface, and movement of the accessory.

  The output control circuit 13 selects the update cycle of the devices 10a and 10b based on the cycle selection data SEL read from the register 3, the offset value Tofs, and the ON state time Ton, and uses the selected update cycle as a reference. Perform time-sharing control. FIG. 4 is a block diagram of the output control circuit 13, and FIG. 5 is a timing chart of output control. The output control circuit 13 is mainly composed of a control unit 13a, an update cycle selection unit 13b, an operation determination unit 13c, and a data output unit 13d. Note that the serial data finally output to the serial data line is data in which the operation states of the devices 10a and 10b are arranged in time series, and the identification data unique to the serial driver 9 is used as the header. (ID) is added. This ID is used in the protocol between the serial controller 6 and the serial driver 9 for the serial controller 6 to individually specify the serial driver 9 and to identify whether the serial driver 9 is data addressed to itself. Used for. The serial data output process is repeated every basic period CB, and the process is started at the start timing of the basic period CB.

  First, the control unit 13a grasps the current connection status of the serial driver 9 with reference to the database stored in the register 3 or other storage device at the start timing of the basic cycle CB. As a result of referring to the database shown in FIG. 4, it is found that the serial drivers 9 with ID = Drv (1) to Drv (x) are connected. In this database, in addition to the connection status of the serial driver 9, the connection status of the devices 10a and 10b driven by each serial driver 9 is described and managed by the CPU 1. As a result of referring to the database, when the ID of the currently connected serial driver 9 is Drv (1) to Drv (x), the data output for all x serial drivers 9 is in units of drivers within one basic period CB. Are performed sequentially.

This time, the output destination (device) connected to Drv (1) is specified by referring to the database focusing on one serial driver 9 (for example, ID = Drv (1)) that is the output target of serial data. The As a result of referring to the database shown in FIG. 4 , it is found that the output destinations connected to Drv (1) are D0 to D4. The control unit 13a requests the register 3 as a reading source to read the cycle selection data SEL, the offset value Tofs, and the on-state time Ton related to these output destinations D0 to D4. At the same time, the control unit 13a outputs the header (1) including the ID (= Drv (1)) of the serial driver to be output this time to the data output unit 13d. Receiving this, the data output unit 13d outputs the header (1) (including ID = Drv (1)) to the serial data line as the head data of the serial data.

  When the cycle selection data SEL is read from the register 3, the update cycle selection unit 13b sequentially selects the update cycle (CRa or CRb) to be applied to each of the output destinations D0 to D4 under the control of the control unit 13a. In the case of FIG. 3, the update cycle CRa is selected for the output destination D0, and the current count value CNTa related to this update cycle CRa is output to the operation determination unit 13c. As shown in FIG. 5, since the update cycle CRa corresponds to 64 basic cycles, the count value CNTa is sequentially counted up within a range from 0 to 63. On the other hand, the update cycle CRb is selected for the output destinations D1 to D4, and the current count value CNTb related to the update cycle CRb is output to the operation determination unit 13c. Since the update cycle CRb corresponds to eight basic cycles, the count value CNTb is sequentially counted up within a range from 0 to 7.

  Each time the selected count value CNT (CNTa or CNTb) is input, the operation determination unit 13c determines the operation of the output destination D (any one of D0 to D4) associated with the input count value CNT. . The data to be output to the output destination D is uniquely defined based on the following setting rule using the count value CNT of the update cycle CR applied to the output destination D, its offset value Tofs, and its on-state time Ton as inputs. Specific.

(Setting rules)
Count value CNT Operation status of output destination D CNT <Tofs Off (= 0)
Tofs ≦ CNT <(Tofs + Ton) ON (= 1)
(Tofs + Ton) ≤ CNT off (= 0)

  In the case of FIG. 3, the offset value Tofs of the output destination D0 is 0, and the on-state time Ton is 32. Therefore, when the count value CNTa = 0, the output destination D0 is set to ON. The output destinations (D1, D2, D3, D4) subsequent to the output destination D0 are sequentially set to (on, off, off, off). The operation determination unit 13c outputs (1, 1, 0, 0, 0) in which the operation states of the output destinations D0 to D4 are arranged in time series as data (1) to the data output unit 13d. Receiving this, the data output unit 13d uses (1, 1, 0, 0, 0) as the data (1) following the header (1) (including ID = Drv1) as the serial data line in units of the basic cycle CB. Output. The serial data constituted by the header (1) and the data (1) is data for the serial driver 9 with ID = Drv1.

  The series of processes as described above are similarly repeated for the serial driver 9 with ID = Drv (2), Drv (3),..., Drv (x). Then, the processing in the current basic cycle CB ends when the processing related to all the serial drivers 9 ends. Such processing within one basic period is repeated every basic period CB. As a result, the output destinations D0 to D4 change as shown in FIG. First, the output destination D0 (SEL = CRa, Tofs = 0, Ton = 32) rises to 1 level at the count value CNTa = 0, which is the start timing of the update cycle CRa, and this state reaches the count value CNTa = 32. Continue until Then, when it reaches the count value CNTa = 32, it falls to 0 level and continues until the count value CNTa = 63, which is the end timing of the update cycle CRa. Thus, the LED 10a connected to the output destination D0 emits light with an on-duty of 50% within a period in which the update cycle CRa is one frame (unit for driving the device). The gradation control of the LED 10a is performed by adjusting the on-duty. The output destination D1 (SEL = CRb, Tofs = 0, Ton = 2) rises to 1 level when the count value CNTb = 0, which is the start timing of the update cycle CRb, and this state reaches the count value CNTb = 2. Continue until When the count value CNTb = 2 is reached, it falls to 0 level and continues until the count value CNTa = 7, which is the end timing of the update cycle CRb. With respect to the output destinations D2 to D4, the waveforms of the output destination D1 are sequentially shifted by two basic periods. As a result, when the motor 10b connected to the output destinations D1 to D4 is a one-phase excitation stepping motor, the motor 10b rotates forward by 4 pulses within the update period CRb (the step angle per pulse is 1 degree). If so, 4 degrees). The rotation control of the motor 10b is performed by adjusting the pulse. When the motor 10b is rotated in the reverse direction, the waveform shift direction at the output destinations D1 to D4 may be set in reverse.

  FIG. 6 is a diagram illustrating an example of serial data output. A protocol related to data exchange between the serial controller 6 and the serial driver 9 is determined in advance. The serial data output to the serial data line is supplied to all the serial drivers 9 connected to the serial data line. Each serial driver 9 refers to the ID (= Drv (1)) included in the header of the serial data and determines whether or not it matches the ID assigned to itself. Then, the serial driver 9 (ID = Drv (1)) that coincides with its own ID converts the data D0 to D4 included in the serial data into parallel data, and drives the LED 10a and the motor 10b based on this. The timing for fetching the bits in the serial data is defined by the rising timing of the clock CLK supplied to the clock line.

  Thus, according to the present embodiment, the processing load on the CPU 1 can be reduced. The serial controller 6 generates a plurality of update periods CRa and CRb having different periods based on the period selection data SEL set by the CPU 1. At the same time, the serial controller 6 individually selects the update periods CRa and CRb applied to the different devices 10a and 10b connected to the same port based on the control data set by the CPU 1, and selects the selected update period. Time-division control is performed based on CRa (or CRb). Therefore, the CPU 1 only needs to set the cycle selection data SEL, the offset value Tofs, and the on-state time Ton in the register 3, and it is necessary for the CPU 1 itself to generate the update cycles CRa and CRb or to constantly manage them. Absent. The CPU 1 only needs to set the output of the devices 10a and 10b with the update periods CRa and CRb that are relatively longer than the basic period CB.

  Further, according to the present embodiment, it is possible to optimize serial control related to the different devices 10a and 10b having different update cycles CRa and CRb to be applied. Here, as a comparative example, consider a case where the update cycle of all the devices 10a and 10b is constant. In this case, when the update cycle of the LED 10a having a long cycle is uniformly applied, the rotational resolution per unit time of the motor 10b having a short cycle is lowered, so that high-speed rotation becomes difficult. On the other hand, when the update cycle of the motor 10b having a short cycle is uniformly applied, gradation control of the LED 10a having a long cycle becomes more complicated than necessary. On the other hand, in the present embodiment, different devices 10a and 10b operating at different update periods CRa and CRb can be arranged in the same port without disturbing the other characteristic, and And optimal device control can be performed in an integrated manner.

  Further, according to the present embodiment, the update periods CRa and CRb are both set as an integral multiple of the basic period CB. This facilitates the generation and management of the update cycles CRa and CRb. In particular, if the longer update cycle CRa is set to an integral multiple of the shorter update cycle CRb, the start / end timing of the long update cycle CRa coincides with that of the short update cycle CRb, so that the heterogeneous devices 10a and 10b are controlled. This makes it easy to synchronize, and the operation settings of the devices 10a and 10b are facilitated.

  Further, according to the present embodiment, the control data such as the offset value Tofs and the on-state time Ton are defined by the number (multiple) of the basic period CB, so that the control data defining the operation contents of the devices 10a and 10b can be interpreted. It becomes easy and the circuit configuration of the serial controller 6 can be simplified.

  Furthermore, according to the present embodiment, by using the update periods CRa and CRb synchronized with the vertical synchronization signal Vsnc, it is possible to easily produce a mutual and high-dimensional effect between the image display and the operation of the different devices 10a and 10b. Can be done.

  In the above-described embodiment, the serial controller 6 performs serial control of the devices 10a and 10b via the serial driver 9 conforming to a predefined protocol, but the devices 10a and 10b themselves correspond to the protocol. Of course, the serial driver 9 is unnecessary. In this case, the devices 10a and 10b are directly connected to the serial data line.

  In the embodiment described above, 1 bit (on / off) is assigned to each of the output destinations D0 to D4, but multiple bits (on / off / intermediate level) may be assigned.

Block diagram of integrated system Block diagram of serial controller The figure which shows the example of setting to the register of the serial control system command Block diagram of output control circuit Output control timing chart Figure showing an example of serial data output

Explanation of symbols

1 CPU
2 Integrated LSI
3 Register 4 Graphic processing unit 5 Audio processing unit 6 Serial controller 7 Display device 8 Speaker 9 Serial driver 10 Device 10a LED
10b Motor 11 Basic cycle generation circuit 12 Update cycle generation circuit 13 Output control circuit 13a Control unit 13b Update cycle selection unit 13c Operation determination unit 13d Data output unit

Claims (18)

In a serial controller that serially controls a plurality of devices connected to the same serial data line by outputting serial data according to an instruction from the host device to the serial data line,
As data to be set for each of the plurality of devices by the host system, the control data defining the operation contents of the device, and a cycle selection data designating the updating period of the temporal unit for updating the control data A storage unit for storing;
Is capable of generating a plurality of different said update period is an integral multiple of the fundamental period based, the update period generating circuit for generating the update period designated by the period selection data read from said storage unit ,
On the basis of the storage unit from the read the cycle selection data, along with selecting an update cycle to apply to each said device, based on the control data read from the storage unit, the operating state of each of said devices and by determining for each of the basic period constituting the selected update cycle for the device, it has a an output control circuit for generating the serial data to be output to the serial data line,
Among the plurality of devices connected to the same said serial data line, at least one device, a serial controller, characterized in Rukoto set to different update periods with other devices. The plurality of devices connected to the same serial data line include a first device and a second device,
The storage unit, the a first cycle selection data designating the updating period of the first device, the first control data defining the operation content of the first device, updating period of the second device storing a second cycle selection data designating, a second control data defining the operation content of the second devices,
The update cycle generating circuit, based on the first cycle selection data read from the storage unit, together with the (m is an integer) m multiple of the basic period for generating a first update cycle is, the storage said read from parts on the basis of the second cycle selection data, n times the fundamental period (n is an integer different from the m) to generate a second update cycle is,
The output control circuit, the read out from the storage unit based on the first cycle selection data, select the first update cycle as the update period of the first device, read out from the storage unit based on said first control data, and determines the operating state of the first device in each of the basic period constituting the first update cycle, the second of said read from storage unit based on the cycle selection data, the second selecting the second update cycle as an update cycle of the device, on the basis of the read out from the storage unit the second control data, said second update The serial controller according to claim 1, wherein an operation state of the second device in each of the basic periods constituting the period is determined.   The serial controller according to claim 2, wherein the second update period is an integer multiple of the first update period.   The serial controller according to claim 1, wherein the control data includes an on-state time that defines an operation time of the device according to the number of basic periods.   5. The serial controller according to claim 4, wherein the control data includes an offset value that defines an offset time based on a start timing of an update cycle according to the number of basic cycles. In the serial controller connected to a serial driver that drives the plurality of devices via a serial data line,
The serial controller according to claim 1, wherein the output control circuit adds identification data unique to a serial driver as a header of serial data. In the serial controller that performs the serial control in synchronization with image display,
The serial controller according to claim 1, wherein the update cycle generation circuit synchronizes the update cycle with the vertical synchronization signal by referring to a vertical synchronization signal used for image display. The serial controller according to claim 1, wherein the at least one device and the other device are different in device type. The LED used in the gaming machine and the motor used in the gaming machine are included as the plurality of devices, and the update cycle different for the LED and the motor is set. 9. The serial controller according to any one of 8. In a serial control method for serially controlling a plurality of devices connected to the same serial data line by outputting serial data according to an instruction from a host device to the serial data line,
For each of the devices of said plurality of devices, a first step of setting the control data defining the operation contents of the device, and a cycle selection data designating the updating period of the temporal unit for updating the control data When,
A second step of generating a plurality of different said updating period specified by the set cycle selection data,
On the basis of the set period selection data, a third step of selecting the update period to be applied to each device,
On the basis of the set control data, the operation status of each device, the serial data by determining for each of the basic period constituting the selected update cycle for the device, to be output to the serial data line have a fourth step of generating a
Among the plurality of devices connected to the same said serial data line, at least one device, a serial control method according to claim Rukoto set to different update periods with other devices. The plurality of devices connected to the same serial data line include a first device and a second device,
The first step includes
Second specifying the first cycle selection data designating the updating period of the first device, the first control data defining the operation content of the first device, the update cycle of the second device and cycle selection data, a step of setting the second control data defining the operation content of the second device,
The second step includes
Generating a first update period that is m times the basic period (m is an integer) based on the set first period selection data;
Generating a second update period that is n times the basic period (n is an integer different from m) based on the set second period selection data;
The third step includes
A step based on the first cycle selection data, selects the first update cycle as the update period of the first device the set,
Based on the second cycle selection data the set, and a step of selecting the second update cycle as the update period of the second device,
The fourth step includes
Determining an operating state of the first device in each of the fundamental period on the basis of the first control data to which the set, forming the first update cycle,
Based on the second control data the set, according to claim 10, characterized in that a step of determining the operating state of the second device in each of the basic cycle constituting the second update period Serial control method described in 1. The serial control method according to claim 11 , wherein the second update period is an integer multiple of the first update period. The serial control method according to claim 10 , wherein the control data includes an on-state time that defines an operation time of the device according to the number of basic periods. The serial control method according to claim 13 , wherein the control data includes an offset value that defines an offset time based on a start timing of an update cycle according to the number of basic cycles. In the serial control method connected to a serial driver that drives the plurality of devices via a serial data line,
The serial control method according to claim 10 , wherein the fourth step includes a step of adding identification data unique to a serial driver as a header of serial data. In the serial control method in which the serial control is performed in synchronization with image display,
The serial control method according to claim 10 , wherein the second step includes a step of synchronizing an update period with a vertical synchronization signal by referring to a vertical synchronization signal used for image display. The serial control method according to any one of claims 10 to 16, wherein the at least one device and the other device have different device types. The LED used in a gaming machine and a motor used in the gaming machine are included as the plurality of devices, and the update periods different from each other are set for the LED and the motor. The serial control method according to claim 17.

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