JP2015163246A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a processing load of a microcomputer for performance control processing.SOLUTION: A game machine includes emission drive signal output means (driver) of a first system and a second system each for outputting an emission drive signal to light-emitting means (an LED or the like) to execute an operation; and performance control means for supply to the emission drive signal output means of the first and second systems as serial data. Each of the emission drive signal output means includes a plurality of driver circuits. The performance control means outputs a slave address designating a driver circuit to acquire light emission drive data, a data setting start register address designating the top of registers for fetching light emission drive data in the driver circuits and each of light emission drive data designating an emission mode of each of light-emitting means set to registers after the data setting start register address in order for the unit of one transmission. The driver circuits designated by the slave address acquire each of the light emission drive data in the registers after the register designated by the data setting start register address.

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine, and more particularly to a data transmission operation for controlling a rendering operation or the like in the gaming machine.

Japanese Patent No. 4613191

In pachinko machines, slot machines, etc., lighting and flashing operations using light emitting parts using LEDs (Light Emitting Diodes), etc., and driving of movable objects provided on the game board, etc. There are some that perform error notification, guidance display, etc. by lighting or blinking operation of the light emitting unit.
For the operation of the light emitting unit and the movable body accessory, for example, a microcomputer functioning as an effect control unit supplies drive data to an LED driver circuit or the like. For example, a large number of LEDs are connected to the LED driver, and the LED driver causes each LED to perform a light emission operation by flowing a light emission drive current according to drive data.

  In the above-mentioned patent document 1, the production control unit outputs drive data for light emission driving of a plurality of LEDs to the LED driver as serial data, and the LED driver converts the serial data into parallel data and is connected. Further, a technique for supplying current to each LED is disclosed.

In such a gaming machine, various presentation control, error control, and the like are performed in addition to the control of the original game operation. For this reason, the control load of the microcomputer for the presentation control tends to increase.
Therefore, an object of the present invention is to reduce the control load of a production control microcomputer or the like.

The gaming machine according to the present invention includes a plurality of light emitting means for performing a light emitting operation according to a gaming state, and each of which outputs a light emission driving signal corresponding to the supplied light emission driving data to the connected light emitting means. Effect control for supplying the first and second systems of light emission drive signal output means, and serial data including the light emission drive data to the first system and second systems of light emission drive signal output means Means.

  In this case, each of the light emission drive signal output means of the first system and the second system includes a plurality of driver circuits each outputting a drive signal to one or a plurality of light emission means. The driver circuit is configured to transmit the serial data from the effect control means in parallel.

  The effect control means includes a slave address for designating a driver circuit for obtaining light emission drive data, a data setting start register address for designating a head of a register for capturing light emission drive data in the driver circuit, and a data setting start register address and thereafter Each light emission drive data specifying the light emission mode of each light emitting means set in each register is sequentially output one transmission unit, and each driver circuit specified by the slave address is a register specified by the data setting start register address Each light emission drive data is acquired in the subsequent registers.

According to the present invention, transmission processing of serial data as effect drive data to the light emission drive signal output means of the first system and the second system by the effect control means is made efficient, thereby reducing the processing load of the effect control means. .

1 is a perspective view of a pachinko gaming machine according to an embodiment of the present invention. It is a front view of the board surface of the pachinko game machine of an embodiment. It is a block diagram of a control configuration of the pachinko gaming machine of the embodiment. 3 is a block diagram of a connection configuration of a driver unit according to the first embodiment. FIG. It is a block diagram of an example of an internal configuration of a driver unit according to the first embodiment. It is a flowchart of the main control main process of an embodiment. It is a flowchart of the main control timer interruption process of an embodiment. It is a flowchart of an effect control main process of the embodiment. It is a flowchart of 1 ms timer interruption processing of effect control of an embodiment. It is a flowchart of the command analysis process in presentation control of an embodiment. It is a flowchart of the command corresponding | compatible process in presentation control of embodiment. It is a flowchart of the scenario registration process in presentation control of an embodiment. It is a flowchart of the scenario deletion process in presentation control of an embodiment. It is a flowchart of the scenario update process in presentation control of an embodiment. It is a flowchart of the subscenario update process in presentation control of an embodiment. It is explanatory drawing of scenario registration information, lamp data registration information, and motor data registration information of embodiment. It is explanatory drawing of the sound data registration information of embodiment. It is explanatory drawing of the main scenario table of embodiment. It is explanatory drawing of the sub scenario table of embodiment. It is a flowchart of the LED drive data update process in presentation control of an embodiment. It is a flowchart of the LED output process in the production control of the first embodiment. It is explanatory drawing of the registration information of the lamp data of embodiment. It is explanatory drawing of the address table of the lamp data and mask data of embodiment. It is explanatory drawing of the lamp data table and mask data table of embodiment. It is explanatory drawing of the update of lamp data of an embodiment, and an output. It is explanatory drawing of the serial data transmitted to the driver of embodiment. It is explanatory drawing of the serial data transmission to each channel of embodiment. It is explanatory drawing of the serial data transmission operation | movement of the production | presentation control part of embodiment. It is explanatory drawing of 8-bit conversion of the 4-bit lighting data of embodiment. It is a flowchart of the LED driver initialization process of an embodiment. It is a flowchart of the LED driver initialization process of an embodiment. It is a block diagram of the connection structure of the driver part of 2nd Embodiment. It is a block diagram of an example of an internal configuration of a driver unit according to the second embodiment. It is a flowchart of the LED output process in the production control of the second embodiment.

Hereinafter, a pachinko gaming machine will be exemplified as an embodiment of a gaming machine according to the present invention, and will be described in the following order.
<1. Pachinko machine structure>
<2. Control configuration of pachinko gaming machine and driver configuration of first embodiment>
<3. Processing of main control unit>
<4. Processing of production control unit>
[4-1: Main processing]
[4-2: 1ms timer interrupt processing]
[4-3: Command analysis processing]
[4-4: Scenario registration / deletion processing]
[4-5: Scenario update processing]
[4-6: LED drive data update process]
[4-7: LED output processing of the first embodiment]
[4-8: LED driver initialization processing]
<5. Second Embodiment>
<6. Modification>

<1. Pachinko machine structure>

First, with reference to FIG. 1 and FIG. 2, the structure of the pachinko gaming machine 1 as an embodiment of the present invention will be schematically described.
FIG. 1 is a front perspective view showing the appearance of a pachinko gaming machine 1 according to the embodiment, and FIG. 2 is a front view of the game board.
The pachinko gaming machine 1 shown in FIGS. 1 and 2 mainly includes a “frame portion” and a “game board portion”.
The “frame portion” includes a front frame 2, an outer frame 4 , a glass door 5, and an operation panel 7 described below. The “game board part” comprises the game board 3 of FIG. In the following description, “frame part” and “frame side” are a general term for the front frame 2, the outer frame 4 , the glass door 5, and the operation panel 7. “Board” and “board side” indicate the game board 3.

As shown in FIG. 1, the pachinko gaming machine 1 has a frame-shaped front frame 2 attached to the front surface of a wooden outer frame 4 so as to be opened and closed. Although not shown, a game board storage frame is formed on the rear surface of the front frame 2, and the game board 3 shown in FIG. 2 is mounted in the game board storage frame. As a result, the gaming area 3a formed on the surface of the gaming board 3 faces the front side of the gaming machine in FIG.
A glass door 5 supporting transparent glass is provided on the front side of the game area 3a, and the game area 3a is exposed to the player on the front side through the transparent glass.

The glass door 5 is attached to the front frame 2 by a shaft support mechanism 6 so as to be opened and closed. Then, by operating a door lock release key cylinder (not shown) provided at a predetermined position of the glass door 5, the glass door 5 is unlocked from the front frame 2, and the glass door 5 can be opened to the front side. ing. Further, the lock state of the front frame 2 with respect to the outer frame 4 can be released by operating the door lock releasing key cylinder.
On the front side of the glass door 5, decorative lamps 20w are provided in various places as light emitting means on the frame side. The decorative lamp 20w performs, for example, a light emitting operation for effects, a light emitting operation for error notification, and a light emitting operation according to an operation state as a light emitting operation by an LED.

An operation panel 7 is provided below the glass door 5. The operation panel 7 can also be opened and closed with respect to the front frame 2 by a shaft support mechanism (not shown).
The operation panel 7 is provided with an upper tray unit 8, a lower tray unit 9, and a firing operation handle 10.

The upper tray unit 8 is formed with an upper tray 8a for storing game balls to be used as bullets. The lower tray unit 9 is formed with a lower tray 9a that stores game balls that cannot be stored in the upper tray 8a.
The upper tray unit 8 is provided with a ball removal button 16 for removing the game balls stored in the upper tray 8a toward the lower tray 9a. The lower tray unit 9 is provided with a ball pulling lever 17 for pulling out the game balls stored in the lower tray 9a below the gaming machine.
Further, the upper tray unit 8 has a ball lending button 14 for requesting a game ball lending device to a game ball lending device (not shown) and a card for requesting the return of the valuable medium inserted in the game ball lending device. A return button 15 is provided.
Further, the upper tray unit 8 is provided with an effect switch 11, an effect button 12, and a cross key 13. The effect switch 11 and the effect button 12 are push buttons that can be operated by turning on the built-in lamp during a predetermined input reception period and can be changed when the built-in lamp is turned on. Further, the cross key 13 is an operator for the player to perform an operation for an operation or an effect setting according to the effect situation.

The firing operation handle 10 is provided on the right end side of the operation panel 7 and is an operator for operating the launching device 56 shown in FIG.
In addition, speakers 25 that sound production effects are provided on both sides of the upper portion of the front frame 2 and in the vicinity of the firing operation handle 10.

  Next, the configuration of the game board 3 will be described with reference to FIG. The game board 3 is mainly composed of a substantially square wooden plywood or resin board. The game board 3 is provided with a ball guide rail 31 for guiding the launched game ball in a ring shape as a board surface partition member, and a substantially circular area surrounded by the ball guide rail 31 is a game area 3a. It has become.

A main liquid crystal display device 32M (LCD: Liquid Crystal Display) is provided at a substantially central portion of the game area 3a, and a sub liquid crystal display device 32S is provided on the right side of the main liquid crystal display device 32M.
In the main liquid crystal display device 32M, under the control of the effect control unit 51, which will be described later, for example, three decorative symbols of left, middle and right are displayed in a variable manner on the background image. Various effect images such as a normal effect, a reach effect, and a super reach effect are also displayed. Similarly, the sub liquid crystal display device 32S performs display according to various effects.

A center decoration 35C is provided in the game area 3a so as to surround the display surfaces of the main liquid crystal display device 32M and the sub liquid crystal display device 32S.
The center decoration 35C not only exhibits a decorative effect due to its design, but also has an action of protecting the display surfaces of the main liquid crystal display device 32M and the sub liquid crystal display device 32S from surrounding game balls. Furthermore, the center decoration 35C also functions as a member that enables the right and left shots of the flow path of the game ball depending on the strength or stroke length of the game ball. That is, the flow path of the game ball launched to the upper part of the game area 3a via the ball guide rail 31 flows down either the left game area 3b or the right game area 3c divided by the center decoration 35C. In the case of so-called left hit, the game ball flows down the left game area 3b, and in the case of right hit, the game ball flows down the right game area 3c.

In addition, a lower left decoration 35L is provided below the left game area 3b to exhibit a decorative effect and define a range as the left game area 3b.
Similarly, a lower right decoration 35R is provided below the right game area 3c, which exhibits a decorative effect and defines a range as the left game area 3b.
In the game area 3a (the left game area 3b and the right game area 3c), nails 49 and windmills 47 are provided at various places to form various flow paths for game balls.
Further, a center stage 35S is provided below the main liquid crystal display device 32M, which exhibits a decorative effect and functions as a play area for a game ball.
Although not shown in the drawing, the center ornament 35C is provided with a movable body accessory that provides a visual effect in an appropriate place.

In the vicinity of the upper right edge of the game area 3a, a symbol display unit 33 is provided by a dot display formed by arranging a plurality of LEDs.
In the symbol display unit 33, a first special symbol display unit, a second special symbol display unit, and a normal symbol display unit are formed by a predetermined dot area, and the first special symbol, the second special symbol, and the normal symbol are displayed. Each variation display operation (variation display operation for setting variation start and variation stop as one set) is performed.
The main liquid crystal display device 32M described above variably displays the decorative symbol by the image in time synchronization with the variable display of the first and second special symbols by the symbol display unit 33.

A winning device having an upper start port 41 (first special symbol start port) is provided below the center ornament 35C, and a lower start port 42a (second special symbol start port) is further provided below that. A variable winning device 42 is provided.
Inside the upper start opening 41 and the lower start opening 42a, detection sensors (upper start opening sensor 71 and lower start opening sensor 72 shown in FIG. 3) for detecting the passage of the game ball are formed.

  The upper starting port 41 is a winning port related to the starting condition of the variable display operation of the first special symbol in the symbol display unit 33, and does not have a starting port opening / closing means (means for opening or expanding the starting port). It is a type winning device.

The normal variation winning device 42 having the lower starting port 42a is configured as a winning rate variation type winning device capable of changing the winning rate of the game ball at the starting port by the starting port opening / closing means. That is, it is a so-called electric tulip type winning device including a pair of left and right movable blades (movable members) 42b that can open or enlarge the lower start port 42a.
The lower start opening 42 a of the normal variation winning device 42 is a winning opening relating to the start condition of the variable display operation of the second special symbol in the symbol display unit 33. The winning rate of the lower start port 42a varies depending on the operating state of the movable blade piece 42b. That is, it is configured such that winning is easy when the movable blade piece 42b is open, and winning is difficult or impossible when the movable blade piece 42b is closed.

In addition, a plurality of general winning ports 43 are provided on the left and right sides of the normal variation winning device 42. A detection sensor (general winning opening sensor 74 shown in FIG. 3) for detecting the passage of the game ball is formed inside each general winning opening 42.
In addition, a normal symbol start port 44 including a gate (specific passage region) through which a game ball can pass is provided on the lower side of the right game region 3c. The normal symbol start port 44 is a winning port relating to the normal symbol variation display operation in the symbol display unit 33, and a sensor (gate sensor 73 shown in FIG. 3) for detecting a passing game ball is formed therein. Has been.

A first special variable winning device 45 (special electric accessory) is provided along the flow path from the normal symbol starting port 44 to the normal variable winning device 42 in the right game area 3c.
The first special variable winning device 45 is configured to close / open the first big winning opening 45a by a retractable opening door 45b. In addition, a sensor for detecting the passage of the game ball to the first big prize opening 45a (the first big prize port sensor 75 in FIG. 3) is formed inside.
The lower right decoration 35R bulges from the surface of the game board 3 around the first grand prize winning opening 45a, and the upper side of the bulged portion and the upper surface of the open door 45b guide downstream of the right flow path 3c. Forming part. Therefore, when the opening door 45b is drawn into the board, the game ball that has reached the downstream guide portion easily enters the first big winning opening 45a.

A second special variable winning device 46 (special electric accessory) is provided below the normal variable winning device 42. The second special variable winning device 46 is configured to close / open the second large winning port 46a on the inside by an open door 46b that is pivotally supported at the lower part and can be opened and closed. In addition, a sensor (second big prize port sensor 76 in FIG. 3) for detecting the passage of the game ball to the second big prize port 46a is formed therein.
The second big prize opening 46a is opened by opening the open door 46b. In this state, the game balls that have flowed down the left game area 3b or the right game area 3c will enter the second big prize opening 50 with a high probability.

As described above, the upper starting port 41, the lower starting port 42a, the normal symbol starting port 44, the first large winning port 45a, the second large winning port 46a, and the general winning port 43 are formed in the game area of the board as winning ports. Has been.
In the pachinko gaming machine 1 according to the present embodiment, when a winning is made to a winning port other than the normal symbol starting port 44 among these winning ports, per winning ball set for each winning port. The number of prize balls is paid out from the game ball payout device 55 (see FIG. 3).
For example, the upper start opening 41 and the lower start opening 42a are set to three, the first big winning opening 45a and the second big winning opening 46a are set to 13, the general winning opening 43 is set to 10 and the like.
Note that the game balls that have not won the prize holes are discharged from the game area 3 a through the out port 48.
Here, “winning” means that the winning opening takes the game ball inside, or the game ball passes through the gate. Actually, when a game ball is detected by a sensor (each winning detection switch) formed for each winning opening, it is treated that a “winning” has occurred in that winning opening. The game ball related to the winning is also referred to as “winning ball”.

On the board as described above, the center ornament 35C, the lower left ornament 35L, the lower right ornament 35R, the center stage 35S, the first special variable winning device 45, the second special variable winning device 46, and a movable object not shown in the figure. Although not shown in detail, decorative lamps 20b are provided as light emitting means on the panel side at various places.
The decorative lamp 20b performs, for example, a light emitting operation for effects, a light emitting operation for error notification, and a light emitting operation according to the operation state as a light emitting operation by an LED.

<2. Control configuration of pachinko gaming machine and driver configuration of first embodiment>

Next, the configuration of the control system of the pachinko gaming machine 1 according to the present embodiment will be described. FIG. 3 is a schematic block diagram of the internal configuration of the pachinko gaming machine 1.
The pachinko gaming machine 1 of the present embodiment mainly has a main control board 50, an effect control board 51, a liquid crystal control board 52, a payout control board 53, a launch control board 54, and a power supply board 58 as the boards forming the control configuration. Is provided.

The main control board 50 is equipped with a microcomputer or the like, and performs overall control related to the entire game operation of the pachinko gaming machine 1. In the following description, a component of the main control board 50 including a microcomputer mounted on the main control board 50 is referred to as a “main control unit 50”.
The effect control board 51 is equipped with a microcomputer or the like, and receives an effect control command from the main control unit 50 and performs control for executing various effect operations using image display, light emission, and sound output. Hereinafter, the structure of the effect control board 51 including the microcomputer mounted on the effect control board 51 is referred to as an “effect control unit 51”.

The liquid crystal control board 52 is equipped with a microcomputer, a video processor, etc., and receives display control commands from the effect control unit 51 to control display operations by the main liquid crystal display device 32M and the sub liquid crystal display device 32S.
Note that the main liquid crystal control substrate and the sub liquid crystal control substrate may be provided independently as the liquid crystal control substrate for controlling the display operation by the main liquid crystal display device 32M and the sub liquid crystal display device 32S.
The payout control board 53 performs payout control of prize balls by the game ball payout device 55 connected to the pachinko gaming machine 1.
Launch control board 54 controls the firing operation of the game ball by launching apparatus 56 provided in the pachinko game machine 1.
The power supply board 58 performs AC / DC conversion and further DC / DC conversion from an external power supply (for example, AC 24 V), and supplies an operation power supply voltage Vcc to each unit. The power supply path is not shown.

First, the main controller 50 and its peripheral circuits will be described.
The main control unit 50 includes a microprocessor incorporating a CPU 100 (hereinafter referred to as “main control CPU 100”), a ROM 101 (hereinafter referred to as “main control ROM 101”), and a RAM 102 (hereinafter referred to as “main control RAM 102”). A microcomputer is configured.
The main control CPU 100 executes various calculations and control processes according to the progress of the game based on the control program.
The main control ROM 101 stores a game operation control program by the main control CPU 100 and various data necessary for game operation control.
The main control RAM 102 is used as a work area used by the main control CPU 100 for various arithmetic processing, and as a buffer area for various input / output data and processing data.
Although not shown, the main control unit 50 includes an interface circuit with each unit, a random number generation circuit that generates random numbers for lottery related to special symbol variation display, a CTC (Counter Timer Circuit) for various time counting, An interrupt controller circuit for giving an interrupt signal to the control CPU 100 is also provided.

As described above, the main control unit 50 receives each winning means in the game area on the board (upper start port 41, lower start port 42a, normal symbol start port 44, first big win port 45a, second big win port 46a, general It is configured to receive a detection signal of a sensor provided at the winning opening 43).
That is, the detection signals of the upper start opening sensor 71, the lower start opening sensor 72, the gate sensor 73, the general winning opening sensor 74, the first large winning opening sensor 75, and the second large winning opening sensor 76 are sent to the main control unit 50. Supplied.
These sensors (71 to 76) are configured by detection switches that detect a game ball that has entered, but specifically, contactless switches such as photoswitches and proximity switches, and contact points such as microswitches. It can consist of switches.

  The main control unit 50 receives the detection signals of the upper start opening sensor 71, the lower start opening sensor 72, the gate sensor 73, the general winning opening sensor 74, the first large winning opening sensor 75, and the second large winning opening sensor 76. Depending on the process. For example, lottery processing, symbol variation control, prize ball payout control, effect control command transmission control, external data transmission processing, and the like are performed.

The main control unit 50 is connected to a normal electric accessory solenoid 77 that opens and closes the movable wing piece 42b of the lower start port 42, and the main control unit 50 transmits a control signal according to the progress of the game to perform normal electric operation. The driving operation of the accessory solenoid 77 is executed, and the opening / closing operation of the movable blade piece 42b is executed.
Further, the main control unit 50 has a first grand prize opening solenoid 78 that opens and closes the opening door 45b of the first big prize opening 45 and a second big prize that opens and closes the opening door 46b of the second big prize opening 46. A mouth solenoid 79 is connected. The main control unit 50 drives and controls the first big prize opening solenoid 78 or the second big prize opening solenoid 79 in accordance with the so-called jackpot situation, and opens the first big prize opening 45 or the second big prize opening 46. Is executed.

  In addition, a symbol display unit 33 is connected to the main control unit 50, and a control signal is transmitted to the symbol display unit 33 to execute various symbol displays (LED OFF / ON / flashing). Thereby, the display operation in the 1st special symbol display part 80 in the symbol display part 33, the 2nd special symbol display part 81, and the normal symbol display part 82 is performed.

  The main control unit 50 is connected to a frame external terminal board 57. The main control unit 50 can transmit information related to game progress to a hall computer (not shown) via the frame external terminal board 57. The information related to the game progress is information such as jackpot winning information, prize ball number information, symbol variation display execution number information, and the like. The hall computer is a management computer that comprehensively manages pachinko hall gaming machines, and is installed outside the gaming machine.

In addition, a payout control board 53 is connected to the main control unit 50. Connected to the payout control board 53 are a launch control board 54 for controlling the launch device 56 and a game ball payout device 55 for paying out game balls.
The main control unit 50 transmits a payout control command (payout control command for designating the number of prize balls) to the payout control board 53. The payout control board 53 controls the game ball payout device 55 in accordance with the control command to cause the game ball to be paid out.
The payout control board 53 can transmit information (payout state signal) regarding the payout operation state to the main control unit 50. The main controller 50 monitors whether or not the game ball payout device 55 is functioning normally based on this payout state signal. Specifically, it is monitored whether or not a problem such as clogged balls or insufficient payout of prize balls has occurred during the prize ball payout operation.

  The main control unit 50 transmits an effect control command including information related to the special symbol variation display to the effect control unit 51. The transmission of the effect control command from the main control unit 50 to the effect control unit 51 is executed by one-way communication. This is to prevent an unauthorized signal due to an illegal act from the outside from being input to the main control unit 50 via the effect control unit 51.

Next, the production control unit 51 and its peripheral circuits will be described.
The effect control unit 51 includes a microprocessor incorporating a CPU 200 (hereinafter referred to as “effect control CPU 200”), a ROM 201 (hereinafter referred to as “effect control ROM 201”), and a RAM 202 (hereinafter referred to as “effect control RAM 202”). A microcomputer is configured.
The effect control CPU 200 performs arithmetic processing for various effect operations and controls each effect means based on the effect control program and the effect control command received from the main control unit 50. In the case of the pachinko gaming machine 1 according to the present embodiment, the effect means are the main liquid crystal display device 32M, the sub liquid crystal display device 32S, the decorative lamps 20w and 20b, and the movable object that is not shown.
The effect control ROM 201 stores a control program of the effect operation by the effect control CPU 200 and various data necessary for effect operation control.
The effect control RAM 202 is used as a work area used by the effect control CPU 200 for various arithmetic processes, a table data area, a buffer area for various input / output data and processing data, and the like.
Although illustration is omitted, the production control unit 51 gives an interrupt signal to the interface circuit with each unit, a random number generation circuit for generating random numbers for lottery for production, CTC for various time counting, and the production control CPU 200. An interrupt controller circuit and a sound source IC for sound production are also provided.
The main roles of the effect control unit 51 are to receive an effect control command from the main control unit 50, to select an effect based on the effect control command, and to provide an effect control command to the main liquid crystal display device 32M and the sub liquid crystal display device 32S. , Output sound control of the speaker 45, light emission control of the decoration lamps 20w and 20b (LED), operation control of the movable body accessory, and the like.

  The effect control unit 51 transmits an effect control command to the main liquid crystal display device 32M and the sub liquid crystal display device 32S, and the effect control command is sent to the liquid crystal control substrate 52 via the liquid crystal interface substrate 66.

The liquid crystal control board 52 performs display control of the main liquid crystal display device 32M and the sub liquid crystal display device 32S. Although not shown, the liquid crystal control board 52 includes a VDP (Video Display Processor), an image ROM, a VRAM (Video RAM), a liquid crystal control CPU, a liquid crystal control ROM, and a liquid crystal control RAM.
The VDP performs overall control of video output processing such as image development processing and image drawing.
The image ROM stores image data (effect image data) on which the VDP performs image expansion processing.
The VRAM is an image memory area that temporarily stores image data developed by the VDP.
The liquid crystal control CPU outputs control data necessary for the VDP to perform display control.
The liquid crystal control ROM stores a program describing the display control operation procedure of the liquid crystal control CPU and various data necessary for the display control.
The liquid crystal control RAM functions as a work area and a buffer memory.

  With these configurations, the liquid crystal control board 52 generates various image data based on the effect control command from the effect control board 51, and outputs it to the main liquid crystal display device 32M and the sub liquid crystal display device 32S. As a result, various effect images are displayed on the main liquid crystal display device 32M and the sub liquid crystal display device 32S.

The production control unit 51 controls the light production and the sound production. For this reason, a frame driver unit 61 and a panel driver unit 62 are connected to the effect control unit 51.
The frame driver unit 61 performs light emission driving for the LEDs of the decorative lamp unit 63 on the frame side. Note that the decorative lamp portion 63 is a general view of the decorative lamp 20w provided on the frame side as shown in FIG.
The panel driver unit 62 performs light emission driving for the LEDs of the decorative lamp unit 64 on the panel side. In addition, the decorative lamp part 64 is a general view of the decorative lamp 20b provided on the panel side as shown in FIG. In the case of the present embodiment, the panel driver unit 62 also drives the movable body accessory motor 65 that drives the movable body accessory formed on the board side. As the movable body accessory motor 65, for example, a stepping motor is used.

In the case of the present embodiment, the frame driver unit 61 is a first-system drive signal output unit, and the panel driver unit 62 is a second-system drive signal output unit. Although details will be described later with reference to FIG. 4, the effect control unit 51 (effect control CPU 200) uses the serial data transmission channels ch <b> 1 and ch <b> 2 and uses the drive data for the first and second systems with the effect drive data as serial data. The output means (the frame driver unit 61 and the panel driver unit 62) is supplied.
In this example, the board driver unit 62 also drives the movable body accessory motor 65 that drives the movable body accessory formed on the board side. However, each LED of the decorative lamp unit 64 is driven to emit light. The driver unit and the driver unit that drives the movable body accessory motor 65 may be provided separately.

  The effect control unit 51 outputs a sound signal generated by the sound source IC to the speaker unit 59. The speaker unit 59 is shown as a part including the speaker 25 described in FIG. 1 and a driving circuit (power amplifier or the like) of the speaker. The production control unit 51 outputs audio signals such as music, character voices, sound effects, and message sounds to the speaker unit 59 in correspondence with the game progress status and the display of the main / sub liquid crystal display devices 32M and 32S. Sound output.

The effect control unit 51 is connected to an operation unit 60 that can be operated by the player, and can receive an operation detection signal from the operation unit 60. The operation unit 60 refers to the effect switch 11, the effect button 12, the cross key 13, and the operation detection mechanism thereof described with reference to FIG.
The effect control unit 51 can perform various effect controls according to the operation detection signal from the operation unit 60.

  The production control unit 51 determines a production pattern by lottery or uniquely from a plurality of types of production patterns prepared in advance based on the production control command sent from the main control unit 50, and performs various productions at necessary timing. Control means. Thereby, the display of the effect image by the main / sub liquid crystal display devices 32M and 32S corresponding to the effect pattern, the reproduction of the sound from the speaker unit 59 (the speaker 25), and the decoration lamp units 63 and 64 (the decoration lamps 20w and 20b). LED lighting and blinking drive and the operation of the movable body accessory by the movable body accessory motor 65 are realized, and various production patterns are developed in time series. Thereby, the “production scenario” is realized.

The effect control command defines a function by a 2-byte structure consisting of a 1-byte length mode (MODE) and a 1-byte length event (EVENT).
In order to distinguish between MODE and EVENT, MODE Bit 7 is ON, and EVENT Bit 7 is OFF.
When these pieces of information are transmitted as valid, a strobe signal is output corresponding to each of the mode (MODE) and the event (EVENT). That is, when there is a command to be transmitted, the main control CPU 100 sets and outputs mode (MODE) information for transmitting the command to the effect control unit 51, and the first strobe signal after a predetermined time has elapsed from this setting. Send. Furthermore, event (EVENT) information is set and output after the elapse of a predetermined time from the transmission of the strobe signal, and the second time of the strobe signal is transmitted after the elapse of the predetermined time from this setting.
The strobe signal is controlled by the main control CPU 100 to be in an active state for a predetermined period during which the effect control CPU 200 can reliably receive a command.
The effect control unit 51 (effect control CPU 200) generates an interrupt based on the input of the strobe signal and executes a control program for command reception interrupt processing, and the effect control command is acquired in this interrupt processing. .

Next, the driver configuration as the first embodiment will be described. It is the structure of the drive signal output means (the frame driver unit 61 and the panel driver unit 62) of the first system and the second system described above.
FIG. 4 shows the frame driver unit 61 and the panel driver unit 62 connected to the effect control unit 51.

In the frame driver unit 61 which is the first-system drive signal output means, n LED drivers 90 are connected in parallel to the serial data output channel ch1 of the effect control CPU 200.
As a signal line of the serial data output channel ch1, a reset signal line for supplying a reset signal RESET, a clock line for supplying a clock signal CLK, a data line for supplying serial data DATA as effect drive data, and an enable signal ENABLE are supplied. An enable signal line is provided. Each of these signal lines is connected so as to supply each signal in parallel to n LED drivers 90 constituting the frame driver unit 61.
In each LED driver 90 of the frame driver unit 61, a device ID used as a slave address by the effect control CPU 200 is set. That is, the identifier of each LED driver 90. For the sake of explanation, the device IDs (slave addresses) of the LED drivers 90 are denoted as w1 to w (n) as illustrated.

In the panel driver unit 62 which is the second-system drive signal output means, m LED drivers 90 are connected in parallel to the serial data output channel ch2 of the effect control CPU 200.
Similarly to channel ch1, the signal line of serial data output channel ch2 is a reset signal line for supplying reset signal RESET, a clock line for supplying clock signal CLK, a data line for supplying serial data DATA as effect drive data, and an enable signal ENABLE. An enable signal line for supplying is provided. Each of these signal lines is connected so as to supply each signal in parallel to m LED drivers 90 constituting the panel driver unit 62.
In each LED driver 90 of the panel driver unit 62, a device ID (identifier of each LED driver 90) used as a slave address by the effect control CPU 200 is set. For the sake of explanation, the device ID (slave address) of each LED driver 90 is represented as b1 to b (m) as shown in the figure.

As each LED driver 90 in the frame driver unit 61 and the panel driver unit 62, for example, “LV5236V (manufactured by Sanyo Semiconductor Co., Ltd.)” which is a 24-channel LED driver can be used, and 24 current output terminals are provided. Therefore, one LED driver 90 can output a maximum of 24 LED drive currents. Specifically, for example, 8 series of R (red) LED drive current outputs, 8 series of G (green) LED drive current outputs, and 8 series of B (blue) LED drive current outputs, and light emission of 8 full-color LEDs. It can be driven. Here, one “series” means one LED connected to one current output terminal, or a group of a plurality of LEDs connected in series or in parallel to one current output terminal. pointing.
The number n of LED drivers 90 in the frame driver unit 61 is determined by the number of LED series arranged on the frame side (the number of series of decorative lamps 20w). Therefore, n may be 1 or may be 2 or more. The frame driver unit 61 has one or a plurality of LED drivers 90.
Further, the number m of LED drivers 90 in the panel driver unit 62 is determined by the number of LED series (the number of series of decorative lamps 20b) arranged on the panel side. Accordingly, m may be 1 or may be 2 or more. The panel driver unit 62 has one or a plurality of LED drivers 90.

FIG. 5A shows a schematic configuration example of a main part of the LED driver 90.
The LED driver 90 includes a serial bus interface 91, an address setting unit 92, a data buffer / PWM controller 93, a D / A converter 94, and drive current source circuits 95-1 to 95-24.
The drive current source circuits 95-1 to 95-24 are current sources that perform the 24 series drive current outputs from the output terminals 96-1 to 96-24, respectively.

The LED driver 90 receives an enable signal ENABLE, a clock signal CLK, and serial data DATA from the effect control CPU 200 with respect to the serial bus interface 91. The serial bus interface 91 takes in the serial data DATA at the timing of the clock signal CLK during the period specified by the enable signal ENABLE. The serial bus interface 91 converts the captured serial data into parallel data and transfers the parallel data to the data buffer / PWM controller 93.
The serial data format will be described later with reference to FIG. 26, but the effect control CPU 200 transmits the LED drive data by designating the slave address.
The data buffer / PWM controller 93 performs slave address confirmation for the parallel data transferred from the serial bus interface 91. When it is confirmed that the slave address included in the parallel data matches the own slave address (either w1 to w (n) or b1 to b (m)) set in the address setting unit 92 The LED drive data included in the parallel data is stored as valid data in a designated register.

When the data buffer / PWM controller 93 fetches each series of LED drive data, the data buffer / PWM controller 93 sets the value corresponding to the luminance information (gradation value) indicated by the LED drive data as the 24 series drive control values as D / A. Output to the converter 94.
The D / A converter 94 converts a value corresponding to the luminance information into an analog signal, which is used as a control signal to each of the current source circuits 95-1 to 95-24.

24 series of LEDs 120 are connected to all (or part of) the output terminals 96-1 to 96-24. Although the drawing shows a simplified state in which one LED 120 is connected to one series of output terminals 96, a configuration in which a plurality of LEDs are connected to one series of output terminals 96 (for example, series connection) is also possible. Of course this is possible.
In each series (output terminals 96-1 to 96-24), the power supply voltage Vcc is applied to the series connection of the LED 120 and the resistor R. Current is supplied to each series of LEDs 120 by the current source circuits 95-1 to 95-24 to emit light.
That is, each of the current source circuits 95-1 to 95-24 operates so that a drive current having a current amount corresponding to the signal supplied from the D / A converter 94 flows through the corresponding series of LEDs 120.

Specifically, such LED drive control is described for one series. The data buffer / PWM controller 93 converts the digital data string corresponding to the pulse duty corresponding to the gradation value of the series to the D / A converter 94. The D / A converter 94 converts the digital data string into a pulse signal as an analog signal and supplies the pulse signal to the current source circuit 95 of the series. The output of the current source circuit 95 is controlled by the H / L of the pulse signal, and for example, outputs currents of 0 mA and 5 mA. For example, in such an operation, a driving current having an average current value corresponding to the gradation value flows to the LED 120 as a result.
In this embodiment, the current value is set to, for example, 0 mA and 5 mA by the PWM driving method, and gradation control is performed (integrally) in the time axis direction. Needless to say, the current value may actually be changed according to the gradation. Regardless of duty control or level control, appropriate gradation expression can be realized by setting the average current value per unit time to a level corresponding to the gradation.

In the case of the present embodiment, a movable body accessory motor 65 that drives the movable body accessory is connected to some of the LED drivers 90 in the panel driver unit 62. FIG. 5B shows an example in which, for example, the stepping motor 121 is connected to all (or a part) of the output terminals 96-1 to 96-24 of a certain LED driver 90. 5B shows only the portions of the output terminals 96-1 to 96-24, but the internal configuration of the LED driver 90 is the same as that of FIG. 5A.
The LED driver 90 is a circuit that outputs a current instructed by a given command (serial data) from the output terminals 96-1 to 96-24, and thus a driver for a physically movable body driving device such as a stepping motor or a solenoid. Can also be used. Therefore, some LED drivers 90 are used as drivers for the stepping motor 121 as shown in FIG. 5B. The operation of the movable body accessory is finely set according to the production scenario, and the production control unit 51 controls the driving direction, the driving amount, and the like accordingly. The movable body is operated using the LED driver 90 in the panel driver unit 62. By driving the accessory, the movable object accessory can be controlled by serial data together with each decoration lamp (LED 20b) of the decoration lamp unit 64, and the control processing and configuration can be made efficient.
In one LED driver 90, a method may be adopted in which some output terminals are used for LED driving and other part of the output terminals are used for driving a stepping motor, a solenoid, or the like.

As described above, each LED driver 90 is driven so that each LED 120 emits light with a designated luminance in accordance with the serial data DATA received from the effect control CPU 200. Alternatively, a part of the LED driver 90 drives the stepping motor 121 according to the serial data DATA.
Each of the first and second system drive signal output means (frame driver unit 61, board driver unit 62) includes a plurality of LED drivers 90 each outputting a drive signal to one or a plurality of effect means, The serial data from the effect control unit 51 is transmitted in parallel to each LED driver 90 in one system. Each LED driver 90 acquires effect drive data (serial data) including its own ID (slave address).
In such a driver configuration, as will be described later, in the present embodiment, the effect control unit 51 (effect control CPU 200) converts serial data of one transmission unit into drive signal output means (frame driver) of the first system and the second system. Unit 61 and board driver unit 62) are output almost simultaneously, and after the transmission of the serial data of the transmission unit to frame driver unit 61 and panel driver unit 62 is completed, the next serial data of one transmission unit is obtained. The frame driver unit 61 and the panel driver unit 62 perform transmission processing to output substantially simultaneously.

<3. Processing of main control unit>

Hereinafter, control processing according to the present embodiment will be described. First, main processing by the main control unit (main control board) 50 will be described here.
FIG. 6 is a flowchart showing main processing of the main control unit 50. The main process starts when the power is turned on without operating the initialization switch (not shown), such as when recovering from a power failure, and when the initialization switch is turned on. May turn on. In any case, when the pachinko gaming machine 1 is powered on, the power board 58 supplies a voltage to each control board. In this case, the main control unit 50 (main control CPU 100) starts the main process shown in FIG.

In the main control side main process, the main control CPU 100 first executes a necessary initial setting process before starting the game operation in step S11. For example, it first sets itself to an interrupt disabled state, sets it to a predetermined interrupt mode (interrupt mode 2), and initializes register values in the CPU including each part of the microcomputer.
Next, in step S12, the main control CPU 100 determines the state (ON, OFF) of a RAM clear signal that is an output signal of a RAM clear switch that is input via an input port (not shown). The RAM clear signal is a signal that determines whether or not to initialize all the areas of the RAM. The RAM clear signal usually has a value corresponding to the ON / OFF state of the initialization switch operated by the store clerk of the pachinko parlor.

When the RAM clear signal is in the ON state, the main control CPU 100 advances the process from step S12 to S16, and performs zero clear of the entire area of the RAM. Therefore, the value of the backup flag set at the time of power-off becomes zero together with other checksum values.
Subsequently, in step S17, the main control CPU 100 transmits a “RAM clear display command” for notifying that the RAM area has been cleared to zero to each control board as an initialization command. In step S18, for example, 30 seconds is stored in the RAM clear notification timer as a time for notifying that the RAM has been cleared.

Next, in step S19, the main control CPU 100 initializes a CTC that outputs an interrupt signal for starting a timer interrupt operation, and sets the CPU to an interrupt enabled state.
Thereafter, as the processing of steps S20, S21, and S22, the interrupt disabled state and the interrupt enabled state are repeated until an interrupt occurs, and various random number update processes are executed during that time. In the various random number update processing in step S21, random numbers used for changing initial values (start values) of various random numbers used for special symbol fluctuation display and normal symbol fluctuation display, and fluctuations used for selection of fluctuation patterns. Update pattern random numbers.
The various random numbers used for the special symbol variation display and the normal symbol variation display are, for example, random numbers related to jackpot lottery circulating through a predetermined numerical range by increment processing (special symbol determination random numbers used for symbol lottery). Or a random number related to a lottery per assistance (a random number for judging per assistance used in winning lottery per assistance). The random numbers used for changing the initial value include an initial value random number for special symbol determination, an initial value random number for auxiliary hit determination, and the like.

The main control RAM 102 has a special symbol determination random number counter initial value generation counter and a special symbol determination random number counter as various random number counters used for symbol lottery related to big hit lottery, auxiliary lottery, or variation pattern lottery. There are provided a counter for generating an initial value per auxiliary sub-counting counter, a random counter for sub-peripheral determining, a random number 1 counter for variation pattern, a random number 2 counter for variation pattern, and the like. These counters serve as random number generation means for generating random numbers in software.
In the various random number update processing in step S21, two initial value generation counters for generating initial values of the special symbol determination random number counter and the auxiliary hit determination random number counter, a variation pattern random number 1 counter, and a variation pattern random number 2 The counter is updated to generate the above various soft random numbers. For example, if the numerical value range that can be taken as the variation pattern random number 1 counter is 0 to 238, a value is acquired from the count value storage area for generating the value of the variation pattern random number 1 in the main control RAM 102, and the acquired value is changed to the acquired value. After adding 1, it is stored in the original count value storage area. At this time, if the result of adding 1 to the acquired value is 239, 0 is stored in the original random number counter storage area. Other initial value generation random number counters are updated in the same manner. The CPU 201 is configured to repeatedly execute various random number update processes except during a timer interrupt process that is executed intermittently.

The above describes the case where it is determined in step S12 that the RAM clear switch is ON. Next, the case where the RAM clear switch is OFF will be described. For example, at the time of recovery from a power failure state, the initialization switch (RAM clear signal) is in an OFF state. In such a case, the main control CPU 100 advances the process from step S12 to S13, and determines the backup flag value. The backup flag is set to the ON state when the power is shut off, and is reset to the OFF state in the first timer interrupt processing after the power is restored.
Therefore, when the power is turned on or when recovering from a power failure, the backup flag should normally be in the ON state. However, the backup flag is reset (OFF) if the predetermined processing is not completed before the power is cut off for some reason. Therefore, when the backup flag is in the OFF state, the main control CPU 100 advances the process from step S13 to S16, and returns the operation of the gaming machine to the initial state.

On the other hand, if the backup flag is in the ON state, the main control CPU 100 advances the process from step S13 to S14, and executes a checksum calculation for calculating a checksum value. Here, the checksum operation is an 8-bit addition operation for the work area of the main control RAM 102.
When the checksum value is calculated, the calculation result is compared with the stored value at the SUM address in the main control RAM 102. This SUM address stores a checksum value obtained by the same checksum calculation when the power is shut off. The stored calculation result is maintained by the backup power source together with other data of the main control RAM 102. Therefore, originally, both should match according to the determination in step S14.
However, there may be a case where the checksum operation cannot be executed when the power is turned off, or even if it can be executed, the data in the work area is damaged after the checksum operation of the main process is executed. In such a case, the determination result in step S14 is inconsistent.
If data corruption is detected due to the discrepancy of the determination results, the main control CPU 100 proceeds from step S14 to step S16, executes RAM clear processing, and returns the operating state of the gaming machine to the initial state.

If the checksum value obtained by the checksum calculation in step S14 matches the stored value at the SUM address, the main control CPU 100 proceeds to step S15, and returns the stack pointer before power-off based on the backup data. A game restoration process necessary for starting a game from the processing state at the time of power-off is executed.
When the game recovery process at step S15 is completed, the process proceeds to the process at step S19, the CTC is initialized and the CPU is set in the interrupt enabled state, and thereafter, the interrupt disabled state and the interrupt enabled state are generated until an interrupt occurs. In the meantime, various random number update processes described above are executed (steps S20 to S22).

  Next, timer interrupt processing of the main control CPU 100 will be described. FIG. 7 shows the timer interrupt process of the main control CPU 100. This main control timer interrupt process is activated by interruption every predetermined time (about 4 ms) from the CTC, and is interrupted and executed during execution of the main process described above.

  When a timer interrupt occurs, the main control CPU 100 saves the contents of the register in the stack area, and then first performs a power supply abnormality check process for monitoring the power supply state from the power supply board 58 in step S51 of FIG. In this power abnormality check process, it is mainly monitored whether the power is normally supplied. Here, for example, when an abnormality such as a power interruption occurs, a backup process is performed in which predetermined game information at the time of power interruption is stored in the RAM so that the game can be restored without any trouble when the power is restored.

  In step S52, the main control CPU 100 performs a timer management process for managing a timer used for gaming operation control. Timer values of various timers (for example, special symbol accessory operation timer) used for game operation control of the pachinko gaming machine 1 are managed (updated) by this processing.

In step S53, the main control CPU 100 performs input management processing. In this input management process, information detected by various sensors provided in the pachinko gaming machine 1 is stored in the winning counter. Here, the detection information by various sensors includes, for example, an upper start opening sensor 71, a lower start opening sensor 72, a gate sensor (normal pattern start opening sensor) 73, a first large winning opening sensor 75, and a second large winning opening sensor. 76, ON / OFF information (winning detection information) of a switch signal output from a winning detection switch such as the general winning opening sensor 74.
Through the processing in step S53, it is monitored for each interrupt whether or not a winning is detected (winning has occurred) at each winning opening. The “winning counter” is a counter provided corresponding to each winning opening and counting the number of game balls (winning balls) won. In the present embodiment, in a predetermined area of the main control RAM 102, an upper start opening winning counter for the upper starting opening 41, a lower starting opening winning counter for the lower starting opening 42a, a normal symbol starting opening winning counter for the gate 44, A first grand prize winning counter for the first grand prize winning opening 45a, a second big winning prize winning prize counter for the second big winning prize opening 46a, a general winning prize winning counter for the general winning opening 43, and the like are provided. .
Further, in this input management process, it is also monitored whether or not there is an illegal prize based on whether or not the detection information from the prize detection switch has won a prize during a period in which the prize should be allowed. For example, when the first and second big prize opening sensors 75 and 76 detect a game ball even though the big hit game is not being played, the prize detection information is invalidated by invalidating the prize detection information. In order to notify the outside of the fact, a predetermined error process is performed in an error management process in step S55 described later.

  In step S54, the main control CPU 100 performs a timer interrupt random number management process for periodically updating the random numbers related to each variation display. In this periodic random number update process, a special symbol determination random number or auxiliary per-subject determination random number is updated (+1 is added for each interrupt), and a process for changing the start value of the random number counter is performed each time the random number counter makes a round. For example, the value of the special symbol judgment random number counter is updated (added by +1) within a predetermined range, and the special symbol judgment random number counter initial value generation counter value is read each time the special symbol judgment random number counter makes one round. The value of the generation counter is stored in the special symbol determination random number counter. As a result, the start value of the special symbol determination random number counter is changed according to the value of the generation counter, so that the count value of the special symbol determination random number counter is random while the update cycle is constant.

In step S55, the main control CPU 100 performs an error management process for monitoring whether there is an abnormality in the gaming operation state. In this error management process, as abnormalities in the game operation state, these operational abnormalities (errors) occur, for example, by monitoring whether or not a break has occurred between the boards or whether or not there has been an illegal winning. If so, predetermined error processing corresponding to the error is performed.
As the error processing, for example, the progress of a predetermined game operation (for example, a game ball payout operation or a game ball launch operation) is stopped, or an error notification command is transmitted to the effect control unit 51 to generate the effect means. To notify that an error has occurred.

In step S56, the main control CPU 100 performs prize ball management processing. In this prize ball management process, the data stored in the input management process in step S53 is grasped, the above-mentioned prize counter is confirmed, and if there is a prize, a payout control command for designating the number of prize balls is issued. Transmit to the substrate 53.
Upon receiving this payout control command, the payout control board 53 controls the game ball payout device 55 to perform a payout operation for the designated number of prize balls. Thereby, the number of winning balls corresponding to each winning opening is paid out. The number of winning balls corresponding to a winning opening is the predetermined number of winning balls per winning ball set for each winning opening × the number of winning balls corresponding to the value of the winning counter.

  In step S57, the main control CPU 100 performs normal symbol management processing. In this normal symbol management process, a lottery per auxiliary in the normal symbol variation display is performed, and based on the lottery result, the variation pattern of the normal symbol and the stop display mode of the normal symbol are determined, or the blinking is repeated every predetermined time. Create symbol data (data for LED blinking display during normal symbol variation), or create data for stop display (data for LED blinking display during normal symbol stop display) if normal symbol is not varying Or

In step S <b> 58, the main control CPU 100 performs a normal electric accessory management process. In this ordinary electric accessory management process, generation of an excitation signal for solenoid control for the ordinary electric accessory solenoid 77 and its data (solenoid control data) based on the lottery result of the auxiliary symbol lottery in the normal symbol management process in step S57. Set up. Based on the data set here, an excitation signal is output to the ordinary electric utility solenoid 77 in a solenoid management process in step S64 described later, whereby the operation of the movable blade piece 42b is controlled.
In step S59, the main control CPU 100 performs special symbol management processing. In this special symbol management process, the big hit lottery in the special symbol variation display is mainly performed, and based on the lottery result, the variation pattern of the special symbol (look-ahead variation pattern, variation pattern at the start of variation), the special stop symbol, etc. decide.
In step S60, the main control CPU 100 performs a special electric accessory management process. In this special electric utility management process, when the big hit lottery result is “big hit” or “small win”, a setting process necessary to execute and control the hit game corresponding to the win is performed.

In step S61, the main control CPU 100 performs a right-handed notification information management process. In this right-handed notification information management process, for example, a right-handed instruction is given in situations where right-handed is advantageous, such as when the first and second winning holes 45a and 46a are opened or when the movable blade piece 42b is driven. A process for making a “launch position guidance effect (right-handed notification effect)” for performing the notification appears. Specifically, the right-handed instruction is an effect operation instructing the player to aim at the right game area 3c. For example, an image prompting the player to “right-hand” is displayed on the main liquid crystal display device 32M. Or a right-handed message sound is generated from the speaker 25.
When a right-handed notification effect is performed, in this right-handed notification information management process, a “right-handed instruction command” instructing execution of a right-handed notification effect is transmitted to the effect control unit 51 as an effect control command. Then, the production control unit 51 performs execution control of right-handed notification using an image or sound.
In step S62, the main control CPU 100 performs LED management processing. This LED management process is a process of outputting display data for normal symbol display and first and second special symbol displays to the symbol display unit 33. By this processing, normal symbol and special symbol change display and stop display are performed. The normal symbol display data created in the normal symbol management process in step S57 and the special symbol display data created in the special symbol display data update process in the special symbol management process in step S59 are the LED management process. Is output.

In step S63, the main control CPU 100 performs an external terminal management process. In this external terminal management process, the operation state information of the pachinko gaming machine 1 is output to an external device such as a hall computer or an island lamp through the frame external terminal board 57. The operating state information includes that a big hit game has occurred (condition device has been activated), that a small hit game has occurred, that a symbol variation display has been executed (a special symbol variation display game has started or ended) , Information such as winning information (information indicating that the player has won a winning opening or a big winning opening and information on the number of winning balls) is included.
In step S64, the main control CPU 100 performs solenoid management processing. In this solenoid management process, an excitation signal output process for the ordinary electric accessory solenoid 77 based on the solenoid control data created in the ordinary electric accessory management process in step S58, and a special electric accessory management process in step S60. Excitation signal output processing for the first and second big prize opening solenoids 78 and 79 based on the solenoid control data is performed. Thereby, the movable wing piece 42b and the open doors 45b and 46b operate in a predetermined pattern, and the lower start port 42a and the big winning ports 45a and 46b are opened and closed.

After completing the above steps S51 to S64, the main control CPU 100 restores the saved register contents and sets the interrupt permitted state in step S65. As a result, the timer interrupt process is ended, the process returns to the main process on the main control side in FIG. 6 before the interruption, and the main control main process is performed until the next timer interrupt occurs.

<4. Processing of production control unit>
[4-1: Main processing]

Then, the process of the production | presentation control part 51 is demonstrated. As the processing of the effect control unit 51, mainly processing performed every 16 ms on the main loop (hereinafter also referred to as “16 ms processing”) and interrupt processing performed every 1 ms (hereinafter referred to as “1 ms timer interrupt processing”). Say).
First, main processing including 16 ms processing will be described here.
FIG. 8 shows the main process of the effect control unit 51. The effect control unit 51 (effect control CPU 200) starts the main process of FIG. 8 when the gaming machine body is powered on.
In this main process, the effect control CPU 200 first performs a necessary initial setting process before starting the game operation in step S101. For example, as an initial setting process, command reception interrupt setting, movable object starting point return processing, CTC initial setting, timer interrupt permission, initial setting of CPU internal register values including each part of the microcomputer, and the like are performed.

When the initial setting process in step S101 is completed, the processes in steps S102 to S117 are repeated as a process during normal operation.
In other words, in this example, the effect control CPU 200 performs the ID check in step S102 and the random number update in step S117 every loop, and performs the processing of steps S105 to S116 (16 ms processing) every 16 ms.
In the ID check in step S102, the effect control CPU 200 confirms the ID of itself or each connected part set on the system. If an ID abnormality is detected for some reason, system stop processing is performed as step S103.
In normal times when there is no problem with the ID, the effect control CPU 200 performs the processing of step S104 and subsequent steps. That is, the effect control CPU 200 determines whether or not the value of the interrupt counter for determining whether to execute the 16 ms process is greater than “15”. This interrupt counter is a counter that is incremented in step S207 of the 1 ms timer interrupt process described later. Therefore, when the value of the interrupt counter is larger than “15”, it means that the processing timing is 16 ms.

When the value of the interrupt counter is “15” or less, the production control CPU 200 proceeds from step S104 to S117, performs the production soft random number update process, finishes one main process, and again performs the process from step S102. I do.
On the other hand, if the value of the interrupt counter is equal to or greater than “16”, the effect control CPU 200 executes the processes of steps S105 to S116, and then updates the effect soft random number in step S117 to perform one main process. The process from step S102 is performed again.

Thus, every 16 ms counted by the interrupt counter, the effect control CPU 200 performs the 16 ms processing from step S105.
In that case, first, in step S105, the interrupt counter is reset to zero. Thereafter, the counting up to the next 16 ms processing is performed again.
In step S106, the effect control CPU 200 performs error processing. The error processing includes error processing timer processing during a RAM clear error, an accessory error, a right-handed error, etc., scenario registration processing for error notification when various errors occur, error scenario after error notification Clearing processing will be performed.
Next, in step S107, the effect control CPU 200 performs a demo process. In this demonstration processing, processing such as playback sound control, demonstration movie execution, scenario registration of an accessory origin correction, and its command set are performed. In the customer waiting state or the like, the demonstration movie display is executed by executing the scenario set in the demonstration process.

In step S108, the effect control CPU 200 performs command analysis processing. In this command analysis process, the effect control CPU 200 monitors whether or not the effect control command supplied from the main control unit 50 is stored in the command reception buffer, and reads out this command if the effect control command is stored. . Then, an effect control process corresponding to the read effect control command is performed. Details will be described later with reference to FIGS.
In step S109, the effect control CPU 200 performs input detection processing. In this input detection process, an input is detected by operating the operation elements (the effect switch 11, the effect button 12, and the cross key 13) of the operation unit 60. When an input is detected, a process corresponding to the operation is performed.
In step S110, effect control CPU200 performs a scenario update process. In this process, the main scenario and subscenario are updated. At that time, lighting pattern registration of the decorative lamp units 64 and 65, registration of sound to be reproduced, registration of motor operation for driving the movable body accessory, and the like are also performed. Details will be described later with reference to FIGS.
In step S111, the effect control CPU 200 performs sound reproduction processing. The effect control CPU 200 outputs data such as a phrase number and volume to the sound source IC based on sound data registered as a sound channel in the work based on the scenario data. As a result, reproduction output of sound effects, music / sound, and the like from the speaker unit 59 is performed.
In step S112, the effect control CPU 200 performs an accessory error process. Here, a position error determination such as a return of the origin of the movable object is not performed.

In step S113, the effect control CPU 200 updates the LED drive data. Here, processing for creating LED output data (driving data) is performed based on the lamp data registered as a lamp channel in the workpiece based on the scenario data. Details will be described later with reference to FIG. The LED output data is output to each LED driver 90 at a predetermined timing in the 1 ms timer interrupt process.
In step S114, the effect control CPU 200 performs checksum calculation and storage for the work area of the effect control RAM 202, and in step S115, stores the backup data.
In step S116, the scenario update counter is reset to zero. The scenario update counter is a counter that is incremented by a 1 ms timer interrupt process described later.
The 16 ms processing as described above is performed every 16 ms in the main loop processing of FIG.

[4-2: 1ms timer interrupt processing]

Next, the 1 ms timer interrupt process will be described with reference to FIG. The effect control CPU 200 executes the 1 ms timer interrupt process of FIG. 9 in response to an interrupt request generated every 1 ms by the time count.
In this 1 ms timer interrupt process, first, in step S201, it is determined whether or not a checksum is being calculated according to a test command from the main control CPU 100. If the checksum is not being calculated, the effect control CPU 200 proceeds to the input process in step S202.

The input process in step S202 is a process for every 1 ms for performing input detection by operating the operator together with the input detection process in step S109 of FIG. For example, in this input process, when an edge is detected in the signal waveform of the operation detection signal of the operation element, the input counter is reset, and thereafter, the input counter is counted up during a period in which no edge occurs. In the 1 ms timer interrupt process, input information (H or L of the input signal waveform) is detected, and the input counter is reset or incremented depending on the presence or absence of an edge. In step S109 in the main loop process (16 ms process), when the input counter value is 16 or more and the input information has changed from the previous time, the input change is recognized.
Such input processing (S202) and input detection processing (S109) can prevent erroneous input recognition due to noise chattering. In addition, since an input counter is used and, in this embodiment, for example, a 16-bit counter can be used to count up to 65535 ms (about 65 seconds), so-called long press can be detected.

In step S203, the effect control CPU 200 performs a motor operation update process. In this case, the effect control CPU 200 performs a process of creating motor drive data based on the motor data registered as a motor channel in the work (motor data registration information described in FIG. 16C) based on the scenario data. This is motor drive data output to the LED driver of the panel driver unit 62 in order to drive and control the movable body accessory motor 65. In the present embodiment, the LED drive data is updated every 16 ms in step S113, while the motor data is updated every 1 ms.
In step S204, the effect control CPU 200 outputs motor drive data. As described above, the stepping motor 121 of the movable body accessory motor 65 and the like are connected to some of the LED drivers 90 of the panel driver unit 62. In this step S204, serial data as drive data for these stepping motors 121 is sent to a predetermined LED driver 90 of the panel driver unit 62 (LED driver 90 that drives the movable body accessory motor 65 such as the stepping motor 121). Will be output.

In step S205, the effect control CPU 200 executes each process according to the value of the interrupt counter. The interrupt counter is reset to zero in step S105 of the 16 ms process described above and incremented in step S207 of the 1 ms timer interrupt process. Therefore, when step S205 is executed in the 1 ms timer interrupt process, the value of the interrupt counter is 0-15.
According to the interrupt counter values 0 to 15, the process of step S205 is defined as case 0 to case 15. For example, in the present embodiment, in case 0, a WDT (watchdog timer) clear signal ON and an initialization process of the LED driver 90 are performed. In cases 1 to 3, the LED driver 90 is initialized. In case 8, the WDT clear signal is turned OFF. In cases 12 to 15, LED drive data is output to the LED driver 90.
The initialization of the LED driver 90 is a process of outputting a default value to a register that is not used in the LED driver 90. This initialization and LED drive data output are performed for a few LED drivers 90 in one 1 ms timer interrupt process.

In step S206, the effect control CPU 200 outputs an effect control command to the liquid crystal control board 52. For example, one command (2 bytes) is transmitted in one 1 ms timer interrupt process. That is, a 2-byte effect control command as a mode and an event is transmitted.
Thereafter, the effect control CPU 200 increments the interrupt counter in step S207, and increments the scenario update counter in step S208. If the value of the scenario update counter is less than 100, the 1 ms timer interrupt process ends.
Since the scenario update counter is reset to zero in step S116 of the 16 ms process as described above, the scenario update counter value does not normally exceed 100. The value of 100 or more is a case where the 16 ms process is not executed due to a calculation abnormality, a process response abnormality or the like, or the progress of a certain process in the 16 ms process is stopped. In such a case, an infinite loop is entered, and the time-up process is performed by WDT.

When it is determined that the checksum is being calculated in step S201 when entering the 1 ms timer interrupt process, the effect control CPU 200 advances the process to step S210 and clears the WDT. In step S211, an effect control command is transmitted to the liquid crystal control board 52. In step S212, the interrupt counter is incremented and the 1 ms timer interrupt process is completed.

[4-3: Command analysis processing]

Next, the command analysis processing performed in step S108 of FIG. 8 as 16 ms processing will be described with reference to FIGS. The effect control CPU 200 monitors whether or not the effect control command supplied from the main control unit 50 is stored in the command reception buffer as the command analysis processing in step S108, and if the effect control command is stored, this command Is read. As this specific process, the processes of steps S301 to S308 in FIG. 10 are performed.

In the effect control unit 51, a command reception buffer that captures the effect control command transmitted from the main control unit 50 is prepared in the effect control RAM 202, for example. In step S301 in FIG. 10, the effect control CPU 200 first checks the read pointer indicating the read address of the command reception buffer and the write pointer indicating the write address.
The light pointer is updated in response to the command reception, and the received effect control command is stored in the address indicated by the light pointer accordingly. The read pointer is updated when reading from the command reception buffer is performed (step S302). Therefore, if the read pointer is not the write pointer, the effect control command that has not been read is stored in the command reception buffer. Therefore, if the read pointer is not the write pointer, the process goes to step S302, and the effect control CPU 200 loads 1-byte command data from the address indicated by the read pointer in the command reception buffer. In this case, the read pointer is incremented for the next reading (loading).

As described above, one presentation control command is formed of two bytes, one byte as a mode and one byte as an event. In step S303, the effect control CPU 200 confirms whether the loaded 1-byte command data is a mode or an event. This confirmation is performed by the value of Bit 7 out of 8 bits (Bit 0 to Bit 7).
If it is the mode, the process proceeds to step S304 as a process for receiving the upper data of the command, and the read command data is saved in the register “command HI byte”. Also, the “command LO byte” register is cleared. Then, the process returns to step S301.
Even if the read pointer is not equal to the write pointer, the effect control command that has not yet been read is stored in the command reception buffer, and thus the process proceeds to step S302, where the effect control CPU 200 uses the read pointer in the command reception buffer. Load 1 byte of command data from the indicated address. In addition, the read pointer is incremented.
If the read command is an event, the process proceeds from step S303 to S305 as processing for receiving lower-order data of the command, and the read command data is saved in the register “command LO byte”.

The command data of the mode and the event is saved in the registers “command HI byte” and “command LO byte”, so that the effect control CPU 200 takes in one command.
Therefore, the effect control CPU 200 performs processing according to the fetched command in step S306. A specific example will be described later with reference to FIG.

  The read pointer = write pointer is when the effect control command that has not yet been captured by the effect control CPU 200 does not exist in the command reception buffer. Therefore, since new acquisition is unnecessary, the process proceeds to step S307. In this case, it is confirmed whether 100 ms has elapsed while waiting for a symbol command. If such a situation does not occur, the command analysis processing of FIG. 10 is finished. On the other hand, if 100 ms has elapsed while waiting for a symbol command, symbol fluctuation processing due to a missing command is performed in step S308.

An example of the command response process in step S306 will be described with reference to FIG.
FIG. 11A shows basic processing as command response processing. In response to the reception of the 2-byte effect control command, the effect control CPU 200 first checks in step S321 of FIG. 11A whether or not it is currently in the test mode. If it is in the test mode, all the production scenarios are cleared, the sound output is stopped, and the LEDs in the decorative lamp units 63 and 64 are turned off in step S322. In step S323, the test mode ends.
These processes are not performed unless in the test mode.
Then, the effect control CPU 200 performs a process for the acquired effect control command as step S330.

  As the effect control command, for example, a special symbol variation pattern designation command, a special symbol designation command, a holding ball subtraction command, a holding ball addition command, an error display designation command, a jackpot start designation command, etc. are variously set. In step S330, the effect control CPU 200 performs a process specified by the program in response to the received command. Here, in FIG. 11B, FIG. 11C, FIG. 11D, and FIG. 11E, specific processing is exemplified by giving four effect control commands.

FIG. 11B shows a process S330a when a variation pattern command is fetched as the command process in step S330.
In this case, the effect control CPU 200 performs a process of setting a symbol command waiting state in step S331. This is because the effect control CPU 200 controls the variation display of the symbols by sequentially receiving the variation pattern command and the symbol commands.
FIG. 11C shows a process S330b when a symbol command is fetched as the command process in step S330.
In this case, the effect control CPU 200 first confirms whether or not the variation pattern command has been received in step S332. If it has not been received, the process ends.
If a variation pattern command has already been received when the symbol command is received, the process proceeds to step S333, and first, scenario registration for the operation of correcting the accessory origin is performed. In step S334, variation start processing is performed. Thereafter, the change pattern command is deleted in step S335 in response to the start of change.

FIG. 11D shows a process S330c when a power-on command is captured as the command process in step S330.
In this case, the effect control CPU 200 clears the effect control RAM 202 in step S337. For example, the command reception / transmission buffer, the contents of the input information buffer for the operation unit 60, and the checksum storage area are cleared.
Then, in step S338, an error release command is transmitted, in step S339 the accessory error information is cleared, in step S340, the accessory operation is stopped, in step S341, a power-on scenario is registered, and in step S342, the power is transmitted to the liquid crystal control board 52. Perform a set of commands sequentially.

FIG. 11E shows a process S330d when a RAM clear command is fetched as the command process in step S330.
In this case, the effect control CPU 200 clears the effect control RAM 202 in step S343. For example, the command reception / transmission buffer, the contents of the input information buffer for the operation unit 60, and the checksum storage area are cleared.
In step S344, an error cancel command is transmitted, and in step S345, a RAM clear error set and an error notification timer are set. In step S346, information related to the lottery process in the effect control RAM 202 is cleared. In step S347, information related to the scenario is cleared. In step S348, an initial power-on display (RAM clear) command to be transmitted to the liquid crystal control board 52 is set.

[4-4: Scenario registration / deletion processing]

Next, scenario registration / deletion processing will be described. The scenario is data defining various operations to be executed such as production control and error processing. The scenario data to be executed is registered in the work area of the effect control RAM 202 as scenario registration information. The scenario registration information shown in FIG. 16A will be described later. As scenario registration information, 64 scenario channels from 0 to 63 are prepared. Scenarios registered in these 64 scenario channels can be executed simultaneously. Hereinafter, the scenario channel is indicated by “sCH”.
The scenario registration process is a process of registering a scenario having a scenario number requested to be registered in an arbitrary scenario channel in the scenario registration information. In principle, any scenario channel of sCH0 to sCH63 may be used.

  Scenario registration to be described below is called and executed when necessary, for example, in the process of error processing in step S106, demo processing in step S107, command analysis processing in step S108, and the like. For example, step S333 in FIG. 11C and step S341 in FIG. 11D described above are an example of the case where scenario registration is executed.

As the process of FIG. 12, the effect control CPU 200 performs a process of registering a scenario number and a standby time (delay) value corresponding to a scenario specified on a command or program in a work (scenario registration information).
In step S401, the effect control CPU 200 first checks whether or not the scenario number to be registered this time is normal. If the scenario number is not possible, the process ends without doing anything.

  If the scenario number is appropriate, effect control CPU 200 sets variable B to zero in step S402. The variable B is a variable used for sequentially searching for an empty channel among the scenario channels sCH0 to sCH63. Furthermore, the variable B also serves as a variable for determining whether or not there remains a scenario channel that has not yet been searched (confirmation of whether it is an empty channel).

In step S403, the effect control CPU 200 confirms whether or not the “additional pointer” + B scenario channel is empty. The additional pointer is a pointer set in step S407 described later when scenario registration is performed. At the time of starting the processing of FIG. 12, the value of the additional pointer is a value indicating the scenario channel next to the scenario channel registered last time. Note that the initial value of the additional pointer (the value when the processing in FIG. 12 is performed for the first time from the initial state) is zero.
If the “addition pointer” + B scenario channel is not empty, the effect control CPU 200 increments the variable B in step S404.
If B <64 is not satisfied in step S405, the processing in FIG. This is a case where all scenario channels have been searched but scenario registration is impossible because there are no free channels.
At a time point when all scenario channels have not been searched (confirmation of whether or not they are free channels), B <64 in step S405. In that case, the confirmation process of step S406 is performed, and if the value of “addition pointer” + B is not equal to or greater than the value “64” exceeding the maximum value of the scenario channel sCH, the process returns to step S403.
If the value of “addition pointer” + B is “64” or more, correction processing for the value of the addition pointer is performed in step S407. Specifically, when the value of “addition pointer” + B becomes “64”, a process of subtracting “64” from the value of the addition pointer is performed. Then, the process returns to step S403.

According to the processing in steps S403 to S407, it is sequentially confirmed from the scenario channel next to the previously registered scenario channel whether or not the scenario channel is empty.
That is, the scenario channel sCH that is confirmed every time step S403 is performed sequentially advances one by one due to the increment of the variable B in step S404.
Since variable B is zero-reset in step S402 and incremented in step S404, if B <64 is not satisfied in step S405 (that is, if variable B reaches 64), step S403 has already been performed. This process is performed 64 times. This is a case where all scenario channels sCH0 to sCH63 have been examined, but it is determined that there is no free space. For this reason, the processing of FIG.

Further, since the value of the “addition pointer” is a value indicating the next scenario channel of the scenario channel registered last time, the “addition pointer” + B even when B <64 when all the scenario channels are not yet confirmed. (That is, the number of the scenario channel sCH to be checked next) may be “64” or more. Specifically, the value of “addition pointer” + B is 63 at the time of immediately preceding step S403, and after confirming the scenario channel sCH63, the variable B is incremented in step S404. In this state, the scenario channel sCH64 that does not exist next is designated.
Therefore, this point is confirmed in step S406, and if the value of “addition pointer” + B is “64”, in step S407, correction of the addition pointer is performed to return the scenario channel to be confirmed next to “sCH0”. Do. That is, the value of “addition pointer” + B is set to “0” by setting the value of the addition pointer to −64. Thus, in the next step S403, it is confirmed whether or not the scenario channel sCH0 is empty.

If an empty scenario channel is found in the process of step S403 at a certain time, the presentation control CPU 200 proceeds to step S408, and sets a scenario number and a waiting time (delay) in the empty scenario channel. In addition, the data necessary for other scenario management is cleared to zero.
In step S409, the additional pointer is updated to the value of the registered scenario channel + 1. That is, the value of the scenario channel next to the scenario channel registered this time is stored as an additional pointer so that it can be used for the next registration process. In this embodiment, since the scenario channel is 64 channels sCH0 to sCH63, the maximum value of the additional pointer is 63.

  According to the processing of FIG. 12, at the time of scenario registration, an empty channel is searched from the scenario channel next to the scenario channel that was registered last time. The initial value of the additional pointer is “0”, and is subsequently updated in step S407 according to the registration. In many cases, according to this process, scenario registration is performed using the scenario channel sCH0 in order. . When the scenario is registered, the availability is confirmed from the scenario channel next to the previous registered channel. Therefore, in most cases, an empty channel can be found quickly, and the scenario registration process can be executed efficiently. As a result, the processing burden on the effect control CPU 200 is reduced.

  As a modification of the process, the value of the additional pointer updated in step S407 may be set as the number of the scenario channel that has been registered, and 1 may be substituted for variable B in step S402. In this case, however, it is determined in step S405 whether B ≦ 65.

Next, scenario deletion processing will be described. This is a process for deleting a scenario registered in a certain scenario channel of the work.
FIG. 13A shows processing of the effect control CPU 200 when a certain scenario is deleted from the scenario registration information.
The effect control CPU 200 starts the process of FIG. 13A based on the value of a scenario number to be deleted (a main scenario number (mcNo) described later) designated on the command or the programgram. First, in step S421, the effect control CPU 200 confirms whether or not the scenario number related to the deletion request is normal. If the scenario number is not possible, the process ends without being deleted.

  If the scenario number is appropriate, effect control CPU 200 sets variable B to zero in step S422. The variable B in this case is a variable used for searching for a channel in which the scenario to be deleted is registered among the scenario channels sCH0 to sCH63. Further, the variable B also serves as a variable for determining whether or not there remains a scenario channel that has not yet been searched (confirmation of whether or not a scenario to be deleted is registered).

In step S423, the effect control CPU 200 confirms whether or not the scenario registered in the B area, that is, the scenario channel sCH (B) is the scenario number to be deleted. If the scenario registered in the scenario channel sCH (B) is not the scenario number to be deleted, the variable B is incremented in step S424, and it is confirmed in step S425 that B <64, and the process of step S423 is performed. Do.
According to the processing of steps S423 and F424, the scenario to be deleted is searched in order from the scenario channel sCH0 to the scenario channel sCH63.
If the scenario registered in the scenario channel sCH (B) is the scenario number to be deleted in step S423, the process proceeds to step S426, and the scenario registered in the B area, that is, the scenario channel sCH (B) is deleted. Perform the process.
As described above, the process of deleting the scenario with the requested scenario number from the work (scenario registration information) is performed.
If it is determined in step S425 that B <64 is not satisfied, that is, if the variable B reaches 64, all the scenario channels sCH0 to sCH63 have been searched, but the scenario to be deleted has not been registered. Therefore, the process is finished.

FIG. 13B shows processing for deleting a certain range of scenarios. This process is performed when a deletion scenario is specified by a range.
The effect control CPU 200 first sets a variable B to zero in step S431 when a deletion is designated within a range of a certain scenario number on a command or program. The variable B in this case is a variable used to search for a channel in which a scenario corresponding to the deletion target range is registered among the scenario channels sCH0 to sCH63. Further, the variable B also serves as a variable for determining whether or not there remains a scenario channel that has not yet been searched (confirmation of whether or not a scenario corresponding to the deletion target range is registered).

In step S432, the effect control CPU 200 confirms whether or not the scenario registered in the B area, that is, the scenario channel sCH (B), is a scenario number within the range to be deleted. If the scenario registered in the scenario channel sCH (B) is a scenario number within the range to be deleted, the scenario registered in the scenario channel sCH (B) is deleted in step S433. Then, the process proceeds to step S434.
If the scenario registered in the scenario channel sCH (B) is not a scenario number within the range targeted for deletion, the process proceeds to step S434 without performing step S433.
The effect control CPU 200 increments the variable B in step S434, confirms that B <64 in step S435, and returns to step S432. If the variable B has reached 64, the processing has been completed for all scenario channels sCH0 to sCH63, and the scenario range deletion processing is completed.
As described above, one or more scenarios in the scenario number range are deleted from the work (scenario registration information).

FIG. 13C shows a process for deleting all registered scenarios. For example, it is a process called when a scenario is unavoidably deleted due to circumstances on the system. Do not delete scenarios that are targeted for protection.
When it is requested to delete all scenarios, the effect control CPU 200 first sets the variable B to zero in step S441. The variable B in this case is a variable used for confirming the scenario channel in which the scenario to be protected is registered among the scenario channels sCH0 to sCH63. Furthermore, the variable B also serves as a variable for determining whether or not there remains a scenario channel that has not yet been confirmed (confirmation of whether or not a scenario to be protected is registered).

In step S442, the effect control CPU 200 confirms whether or not the scenario registered in the B region, that is, the scenario channel sCH (B), is a scenario to be protected. If it is a scenario to be protected, it is not deleted. On the other hand, if it is not a scenario to be protected, the scenario registered in the scenario channel sCH (B) is deleted in step S443.
In step S444, the variable B is incremented. If B <64 in step S445, the process returns to step S442. If the variable B has reached 64, the processing has been completed for all the scenario channels sCH0 to sCH63, and thus the scenario all deletion processing ends.
As described above, all scenarios other than the scenario to be protected are deleted from the scenario registered as scenario registration information in the work.

[4-5: Scenario update processing]

Next, the scenario update process performed in step S110 of the 16ms process of the main process will be described. In the scenario update process, the main scenario and the sub-scenario are updated as described with reference to FIGS.

First, the structure of scenario registration information will be described with reference to FIGS. FIG. 16A shows the structure of scenario registration information as a main scenario and a sub-scenario. This scenario registration information is set using the work area of the effect control RAM 202.
In the present embodiment, as described above, the scenario registration information includes 64 channels of scenario channels sCH0 to sCH63. Scenarios registered in each scenario channel sCH can be executed simultaneously.

  As shown in the figure, information that can be registered in each scenario channel sCH includes sub-scenario timer (scTm) and previous time (scPrevTm) used in the sub-scenario update process, and sub-scenario execution line (sound / motor sub-scenario table execution line) scIx), sub-scenario execution line lmp (lmpIx) indicating the execution line of the ramp sub-scenario table, main scenario timer (msTm) used for scenario update processing, main scenario execution line (mcIx) indicating the execution line of the main scenario table, main There are a scenario number (mcNo), a main scenario option (mcOpt) that is optional data that can be added to the main scenario, a user option (userFn), a waiting time (delay), and a checksum (checkSum).

When a sound output by the speaker unit 59, light emission by the decorative lamp units 63 and 64, and production by driving the movable body accessory motor 65 are started, a standby time (delay) and a main scenario number (scNo) are set. It registers in an empty scenario channel among the scenario channels sCH0 to sCH63.
The waiting time (delay) indicates the time from registration to the scenario channel sCH until the scenario is started. The waiting time (delay) is decremented by 1 every 16 ms processing. When the waiting time (delay) is 0, processing corresponding to the registered data is executed.

FIG. 18 shows an example of scenario numbers 1, 2, and 3 as a part of the main scenario table. As the scenario of each scenario number, the main scenario timer (msTm) value is described as time data in each line (row) of the scenario, and the sub-scenario number (scNo) and option (OPT) can be described. . That is, in the main scenario table, a sub-scenario (and optional in some cases) to be executed is designated as the time by the main scenario timer (msTm). In the last line of the scenario, a scenario data end code D_SEEND or a scenario data loop code D_SELOP is described.
Since the value of the main scenario timer (msTm) is incremented by 1 in the scenario update process performed in the 16 ms process from the start of the main scenario, “1” indicates 16 ms. The scenario table of each scenario number advances to the next line when the time of the main scenario timer (msTm) in a certain line has elapsed. The time data of each line indicates the timing when the line ends.
For example, in the case of scenario number 2, the operation of sub-scenario number 2 is specified as a time of 1500 × 16 ms, the operation of sub-scenario number 20 is specified as the next time of 500 × 16 ms, and the operation is performed as the next time of 2000 × 16 ms. The operation of scenario number 21 is designated. The next line is the scenario data end code D_SEEND. In the case of the scenario data end code D_SEEND, this scenario is deleted from the scenario registration information (work) (see step S617 in FIG. 14 described later).

Next, the structure of the lamp data registration information will be described with reference to FIG. 16B. As the lamp data registration information, a scenario selected from the lamp sub-scenario table, that is, information indicating a rendering operation (lighting pattern) by the decorative lamp units 63 and 64 is registered. This lamp data registration information is also set using the work area of the effect control RAM 202.
In the present embodiment, the ramp data registration information has 16 channels of ramp channels dwCH0 to dwCH15. Priorities are set for each of the ramp channels dwCH0 to dwCH15, and the priority increases in order from the ramp channels dwCH0 to dwCH15. Therefore, the scenario (lamp sub-scenario) registered in the ramp channel dwCH15 is executed with the highest priority. For example, if a scenario is registered in the ramp channels dwCH3 and dwCH10, the scenario registered in the ramp channel dwCH10 is preferentially executed.
The ramp channel dwCH0 is mainly used for a lamp effect associated with BGM (Back Ground Music), the lamp channel dwCH15 is used for an error-related lamp effect, and the lamp channels dwCH1 to dwCH14 are used for a normal effect.

  As shown in the figure, information that can be registered in each lamp channel dwCH includes a registered lighting number (lmpNew) indicating the number of the registered lighting pattern, an execution lighting number (lmpNo) indicating the number of the lighting pattern to be executed, and a lamp sub-scenario. There are an offset indicating an execution line (offset), an execution time (time), and a checksum (checkSum).

  FIG. 19A shows an example of lamp sub-scenario numbers 1, 2, and 3 as a part of the lamp sub-scenario table. For each number of lamp sub-scenarios, time data (time) values are described in each line (row) of the scenario, and lamp channels and lamp numbers indicating various lighting patterns are described. In the last line, a lamp scenario data end code D_LSEND is described.

In this ramp sub-scenario table, the time data (time) of each line indicates the time at which the line is started after the sub-scenario is started.
When the main scenario timer (msTm) and the time data in the table are compared every 16 ms and they match, the lamp number of that line is registered in the lamp data registration information of FIG. 16B. The registered ramp channel dwCH is the channel indicated in the line.
For example, it is assumed that the scenario number 2 shown in FIG. 18 is registered and the sub-scenario number 2 is referred to in a certain scenario channel sCH described above. In the lamp sub-scenario number 2 shown in FIG. 19A, the lamp channel 5 (dwCH5) and the lamp number 5 are described as time data (time) = 0 on the first line. In this case, when the main scenario timer (msTm) = 0, the information on the first line is first registered in the lamp channel dwCH5 of the lamp data registration information in FIG. 16B as the registered lighting number (lmpNew) = 5. The value of the sub-scenario execution line lmp (lmpIx) in the scenario registration information is updated to the value of the next line (second line). This is a registration for performing the lighting pattern operation of the lighting number 5 with a relatively low priority of the lamp channel dwCH5.
For the second line, the same processing is performed when it becomes 500 × 16 ms. That is, the registered lighting number (lmpNew) = 6 (that is, the lighting pattern 6 lighting instruction) is registered in the lamp channel dwCH5 of the lamp data registration information.
If the time data (time) has the same value for two consecutive lines, the processing for each line is started simultaneously.
In the LED drive data update process to be described later, LED drive data is created based on the lamp data registration information updated in this way.

Next, the structure of the motor data registration information will be described with reference to FIG. 16C. As motor data registration information, information indicating a scenario selected from the sound / motor sub-scenario table is registered. This motor data registration information is also set using the work area of the effect control RAM 202.
In the present embodiment, the motor data registration information is assumed to have eight channels of motor channels mCH0 to mCH7.
Information that can be registered in each motor channel mCH includes execution operation number (no), registration operation number (noNew), operation count (lcnt), excitation counter (tcnt), execution step (step), operation line as shown in the figure. (Offset), parent (migration source) / child (migration destination) attribute (attribute), parent number (retNo), return address (retAddr), loop start point (roopAddr), loop count (roopCnt), error counter (errCnt) ), Current input information (currentSw), software switch information (softSw), and software count (softCnt).

FIG. 17 shows sound data registration information. As the sound data registration information, information indicating a scenario selected from the sound / motor sub-scenario table is registered. This sound data registration information is also set using the work area of the effect control RAM 202.
In the present embodiment, the sound data registration information has 16 channels of sound channels aCH0 to aCH15.
Information that can be registered in each sound channel aCH includes volume transition amount (frzVq), volume (frzVl), transition amount change (rsv2), volume change (rsv1), phrase change (rsv0), stereo (frzSt, as shown) ), Loop (frzLp), phrase number hi (frzHi), and phrase number low (frzLo).

FIG. 19B shows an example of sound / motor sub-scenario numbers 1 and 2 as a part of the sound / motor sub-scenario table. As the sound / motor sub-scenario of each number, the time data (time) value (ms) is described in each line (row) of the scenario, and BGM, warning sound, error sound, sound control, motor, solenoid / User option information is described. In the last line, a scenario data end code D_SEEND is described.
Regarding this sound / motor sub-scenario table, when the sub-scenario timer (scTm) becomes 0 (initially 0), the time data (time) value of this sound / motor sub-scenario table is set to the sub-scenario timer ( scTm). The time data (time) of each line indicates the timing when the line ends. The sub-scenario timer (scTm) describes the absolute time. Therefore, the time data value to be set is a value of (time data of the relevant line) − (time data of the previous line).
The BGM data of the line is composed of information registered in the sound data registration information such as the BGM phrase number and volume value, and is set in the sound channel aCH0 (aCH1 in the case of stereo) in the sound data registration information. .
The notice sound data of the line is composed of information registered in the sound data registration information such as the phrase number and volume value of the notice sound, and is set in the space where the sound channels aCH2 to aCH14 are vacant.
The error sound data of the line includes information registered in sound data registration information such as the error sound phrase number and volume value, and is set in the sound channel aCH15.
The sound control data is channel information in the lower 6 bytes and control information in the upper 2 bytes.
The motor data is configured to indicate the motor operation pattern number in one byte per motor. An operation pattern number is set in the motor channel corresponding to the motor number.

In the motor operation update process described as step S203 in FIG. 9, motor drive data is created based on the motor data registration information updated in the scenario update process in FIGS.
In the sound reproduction process in step S111 in FIG. 8, reproduction output is performed based on the sound data registration information updated in the scenario update process in FIGS.

Scenario update processing using the above information will be described with reference to FIGS.
In the scenario update process of FIG. 14 executed as step S110 of the 16 ms process of FIG. 8, the effect control CPU 200 performs the processes of steps S601 to S616 for each of the scenario channels sCH0 to sCH63 as the loop process LP1. The scenario channel to be processed each time in the loop processing will be described as “sCHn”.

  The effect control CPU 200 confirms the standby time (delay) of the scenario channel sCHn in step S601. If the standby time (delay) = 0 is not satisfied, the value of the standby time (delay) is decremented by −1 (decrement) in step S602. In step S615, a checksum of data related to the scenario channel sCHn is calculated and stored. In step S616, the scenario channel sCHn related data is backed up. This completes one process for the scenario channel sCHn.

On the other hand, if it is confirmed in step S601 that the standby time (delay) = 0, the effect control CPU 200 proceeds to step S603 and executes the main scenario number (mcNo) registered in the scenario channel sCHn and the main scenario execution. The address of the main scenario table corresponding to the line (mcIx) is specified.
In step S604, it is confirmed whether or not an execution line of a certain main scenario number in the main scenario table indicated by the specified address is a final line in which an end code D_SEEND (see FIG. 18) is described.
If the end code matches the last line in which the end code is described, the processing to be executed in the scenario registered in the scenario channel sCHn has been completed. Therefore, in step S617, the scenario registered in the scenario channel sCHn. Is deleted from the scenario registration information (work).
Note that the scenario registration deletion in this case is a normal deletion corresponding to the end of the scenario. It is added that the scenario deletion described above with reference to FIG. 13 is a process for deleting, for example, an unfinished scenario from the scenario registration information (work) other than the normal deletion.

If it is determined in step S604 that the line in the main scenario table is not an end code, the production control CPU 200 proceeds to step S605, and first sets the option (OPT) of the line in the main scenario option (mcOpt) of the scenario channel sCHn. To do. Next, in step S606, it is confirmed whether or not the scenario number is 0. If it is not 0, 0 is assigned to the user option (userFn) in step S607.
In step S608, the sub-scenario specified by the scenario channel sCHn is updated. The sub-scenario update will be described later with reference to FIG.

In step S609, the effect control CPU 200 increments the main scenario timer (msTm) by +1. In step S610, the value of the main scenario timer (msTm) is compared with the time data of the corresponding line in the main scenario table (see FIG. 18: described in msTm). As described above, the time data of each line in the main scenario table defines the end timing of the line. Therefore, if the value of the main scenario timer (msTm) is equal to or greater than the time data described in the relevant line of the main scenario table, the processing for that line ends and the next line is targeted. In that case, the process proceeds from step S610 to S611, and the main scenario execution line (mcIx) of the scenario channel sCHn is incremented by one. That is, next time, the next line is targeted.
In that case, it is checked in step S612 whether or not the next line is designated as a loop. In scenario number 1 in the main scenario table of FIG. 18, an example is shown in which the last line is the scenario data loop code D_SELOP. Set loop line to mcIx).

In step S614, the effect control CPU 200 performs a clear process according to the end of one line. That is, main scenario timer (msTm), sub-scenario timer (scTm), previous time (scPrevTm), sub-scenario execution line (scIx), sub-scenario execution line lmp (lmpIx), main scenario option (mcOpt), user option (userFn) Clear the delay time.
Then, the checksum process in step S615 and the backup process in step S616 are performed, and one process for the scenario channel sCHn is completed.
As the scenario update process, the above process is executed for each of the scenario channels sCH0 to sCH63 as the loop process LP1.

The sub-scenario update process performed in step S608 is shown in detail in FIG. 15A.
Based on the main scenario timer (msTm), the scenario channel sCHn, and the sub-scenario number (scNo) described in the main scenario table, the sub-scenario update process of FIG. 15A is performed.

First, in step S621, the effect control CPU 200 confirms whether or not the scenario channel sCHn indicates any of 0 to 63, that is, whether or not it is an appropriate value. If the scenario channel sCHn is 64 or more, the update process is impossible and the process of FIG. 15 ends.
If the scenario channel sCHn is an appropriate value, the effect control CPU 200 identifies the address of the lamp sub scenario table (see FIG. 19A) corresponding to the sub scenario number (scNo) and the sub scenario execution line lmp (lmpIx) in step S622. .

In step S623, the effect control CPU 200 first sets 0 to the lamp channel dwCH in order to update the lamp data registration information. That is, first, the lamp channel dwCH0 is designated.
In step S624, the main scenario timer (msTm) and the time data (time) in the lamp sub-scenario table are compared. The time data (time) in the lamp sub-scenario table indicates the time (ms) at which the line (the line indicated by the sub-scenario execution line lmp (lmpIx)) is started. Therefore, if the time of the main scenario timer (actually, the time of msTm × 16 ms) is equal to or greater than the time data (time), the processing for that line is performed. In that case, it is checked in step S625 whether the value of the ramp channel dwCH is normal (within the range of dwCH0 to dwCH15). If it is an abnormal value, the process ends. If it is a normal value, it is checked in step S626 if the current line is a line in which the lamp scenario data end code D_LSEND is described.

If it is not the line in which the lamp scenario data end code D_LSEND is described, the effect control CPU 200 acquires the lamp channel and lamp number described in the line in step S627. In step S628, the lighting pattern number is registered.
The lighting pattern number registration process is shown in FIG. 15B. In this case, first, in step S651, the effect control CPU 200 determines whether or not the value of the lamp channel dwCH described in the line is a normal value. If it is not a normal value, the process ends without performing registration.
If it is a normal value, it is determined in step S652 whether or not the ramp number described in the line is a normal value. If it is not a normal value, the process ends without performing registration.
If both the lamp channel dwCH and the lamp number are normal values, the registered lighting number (lmpNew) and the execution lighting number (lmpNo) are set in the area corresponding to the lamp channel dwCH in the lamp data registration information of the work in step S653. To do. That is, the lamp number acquired from the relevant line in the lamp sub-scenario table is set in the registered lighting number (lmpNew), and “0” is set in the execution lighting number (lmpNo).
15B is performed in step S628, the effect control CPU 200 increments the value of the sub-scenario execution line lmp (lmpIx) in step S629, increments the value of the ramp channel dwCH in step S630, and returns to step S624. .

When the time of the main scenario timer does not reach the time data (time) of the line indicated by the sub-scenario execution line lmp (lmpIx) in step S624, and the lamp scenario data end code D_LSEND is confirmed in step S626 The process of the effect control CPU 200 proceeds to step S631.
In step S631, it is confirmed whether or not the sub-scenario timer (scTm) is zero. If not 0, the process proceeds to step S639 without registering sound and motor. In this case, the value of the sub-scenario timer (scTm) is decremented in step S640, and the processing in FIG. 15A is completed.

If the sub-scenario timer (scTm) = 0 at the time of step S631, the effect control CPU 200 advances the process to step S632, and registers the sub-scenario number described in the main scenario table and the scenario channel sCHn currently being processed. The address of the sound / motor sub-scenario table corresponding to the executed sub-scenario execution line (scIx) is specified.
In step S633, the production control CPU 200 determines whether or not the line indicated by the sub-scenario execution line (scIx) in the corresponding sound / motor sub-scenario number table is a line describing the scenario data end code D_SEEND. If it is confirmed and the scenario data end code D_SEEND is described, the process ends.
If the scenario data end code D_SEEND is not described, the production control CPU 200 substitutes a value obtained by subtracting the previous time (scPrevTm) from the time data (time) of the line in step S634 in the sub-scenario timer (scTm). To do. Also, the time data (time) of the line is substituted for the previous time (scPrevTm).

Then, the effect control CPU 200 performs sound registration in step S635, and performs motor registration in step S636. Although not described in detail, the information on the corresponding line of the corresponding sub-scenario number in the sound / motor sub-scenario table illustrated in FIG. 19B, the arbitrary motor channel of the motor data registration information in FIG. The process of registering to an arbitrary sound channel is performed. In step S637, the solenoid / user option information described in the line is also registered in the scenario registration information.
In step S638, the value of the next line is set as the value of the sub-scenario execution line (scIx). If the sub-scenario timer (scTm) is not 0 in step S639, the sub-scenario timer (scTm) is decremented in step S640 and the process ends.

In step S110 in FIG. 8, the processes in FIGS. 14 and 15 are performed. In this process, the scenario registration information, lamp data registration information, motor data registration information, and sound data registration information on the workpiece are sequentially updated, and the rendering operation is performed in accordance with this, thereby performing the rendering operation according to the scenario. The

[4-6: LED drive data update process]

The LED drive data update process in step S113 of FIG. 8 will be described.
This process is a process for creating LED drive data with reference to the lamp data table corresponding to the lighting number (registered lighting number (lmpNew), execution lighting number (lmpNo)) registered in the lamp data registration information. . As described above, the lamp number indicating the lighting pattern originally set in the lamp sub-scenario table is set as the lighting number of the lamp data registration information. The lamp number has been described as the number indicating the lighting pattern, but specifically indicates the number of the lamp data in the lamp data table described in FIG. 24A.

FIG. 20 shows LED drive data update processing.
In step S701, the effect control CPU 200 clears the LED drive data that has been output data until then.
Then, as loop processing LP2, the processing of steps S702 to S720 is performed for each of the lamp channels dwCH0 to dwCH15 of the lamp data registration information. Hereinafter, the lamp channel to be processed will be described as “dwCHn”.

In step S702, the effect control CPU 200 checks whether or not the execution lighting number (lmpNo) and the registered lighting number (lmpNew) in the target lamp channel dwCHn match. Since the lighting pattern number is registered as in step S653 of FIG. 15B, they do not match at first. If they do not match, the lighting is started, and the value of the registered lighting number (lmpNew) is substituted into the execution lighting number (lmpNo) in step S703. In step S704, the execution line (ofset) is set to 0, and the execution time (time) is set to 0.
If the execution lighting number (lmpNo) matches the registered lighting number (lmpNew), the above steps S703 and S704 have already been performed, and these processes are unnecessary.

Regarding the information registered in a certain lamp channel dwCH, after the registration, the LED drive data to be output to each LED driver 90 is created for each occasion of the LED drive data update process.
FIG. 22A shows a state where registration is performed on the ramp channels dwCH0, dwCH5, and dwCH8 in the ramp data registration information of the workpiece shown in FIG. The state in this figure is an example of the state at time t0 in FIG. 22B.
That is, the information on the lamp channels dwCH0 and dwCH5 is reflected in the LED output data before time t0. For the lamp channel dwCH0, the execution lighting number (lmpNo) and the registered lighting number (lmpNew) have already been matched, and the execution line (ofset) has advanced to 3 (third line). Also, for the lamp channel dwCH5, the execution lighting number (lmpNo) and the registered lighting number (lmpNew) have already been matched, and the execution line (ofset) has advanced to 2 (second line). At time t0, the lamp channel dwCH8 is immediately after registration, and the execution lighting number (lmpNo) and the registration lighting number (lmpNew) are not matched. Thereafter, the processes in steps S703 and S704 are performed.

As described above, in the present embodiment, priority is set for the ramp channels dwCH0 to dwCH15, and the priority increases in order from the ramp channels dwCH0 to dwCH15. As shown in FIG. 22A, the lamp channel dwCH15 having a high priority is used for error notification. Lamp channels with high priority, such as the lamp channels dwCH12, dwCH13, dwCH14, etc. are used for relatively highly reliable performances such as continuous notices and final notices. The lamp channel with medium priority is used for moving body effects, and the lamp channel with relatively low priority is used for effects with relatively low reliability, such as conversation notices and step-up notices. Channels are used for ramp effects that are synchronized with normal fluctuations, reach, and the like.
Due to such priority setting, when operations of a plurality of lamp channels dwCH overlap as shown in FIG. 22B, a lighting operation of a lamp channel with a high priority is executed. For example, from time t0, the lighting operation based on the lamp channels dwCH0 and dwCH5 is limited, and the LED output data is generated so that lighting based on dwCH8 is performed. In order not to reflect the information of the lamp channel having a low priority, mask data described later is used.

Subsequently, in step S705 of FIG. 20, the effect control CPU 200 confirms whether or not the value of the execution lighting number (lmpNo) is within a normal range. The normal range is a range where numbers exist as lamp data in the lamp data table shown in FIG.
If the execution lighting number (lmpNo) is abnormal, the process proceeds to step S719. In the case of an empty channel in which the lamp channel dwCHn is not registered, the process proceeds to step S719 as abnormal here.

If the execution lighting number (lmpNo) is normal, the process proceeds to step S706. In step S706, the effect control CPU 200 specifies the address of the lamp data table corresponding to the execution lighting number (lmpNo) and execution line (ofset) registered in the lamp channel dwCHn.
In step S707, the execution lighting number (lmpNo) registered in the lamp channel dwCHn and the address of the mask data table are specified.
To specify the address, the effect control CPU 200 refers to a lamp data address table as shown in FIG. In this lamp data address table, the address of the lamp data number for realizing each lighting pattern, for example, entire flashing, right flashing, left flashing, and accessory lighting is shown. The numbers on the left side of FIG. 23 are the lamp numbers shown in the lamp sub-scenario table of FIG. 19A. For example, in the column of the lamp data address of lamp number 2, the lamp data numbers for performing the entire blinking lighting pattern are shown. The stored address is described.
In the address field of mask data, an address where mask data necessary for executing the lighting pattern of the lamp data number is stored is stored. For example, when a lighting pattern of blinking on the right side of the lighting number 5 is performed, a center case mask is required, but an address of mask data for performing the center case mask is described.

FIG. 24A shows lamp data 1 and 2 as part of the lamp data table.
Each line in each number of lamp data describes time data and lighting data as a timer (frame). The timer (frame) defines the time for generating the LED output data based on the lighting data of each line.
The lighting data is described corresponding to each LED driver 90. In FIG. 4, it is assumed that there are n LED drivers 90 in the frame driver unit 61 and m LED drivers 90 in the panel driver unit 62. However, in the following, as an example, four LED drivers 90 are included in the frame driver unit 61. The description will be made on the assumption that there are five LED drivers 90 in 62, that is, nine in total.
In this case, lighting data is described in each line of the lamp data corresponding to each of the nine LED drivers 90, as shown in FIG. 24A. In the figure, the correspondence with each LED driver 90 is indicated by w1 to w4 and b1 to b5 as slave addresses of the LED driver 90.
As the lighting data, 4 bits (0h to Fh) are assigned to one output terminal 96 (one series of LED drive current outputs) of the LED driver 90 described in FIGS. 4 and 5 (“h” is Hexadecimal notation is shown), and the luminance of 16 gradations is designated. As described in FIG. 5, the LED driver 90 has 24 output terminals 96-1 to 96-24. Therefore, one piece of lighting data is information of (4 × 24) bits as “FFFF000055550000AAAAAAAA (h)”. If the lighting data for the LED driver 90 (w1) is “FFFF00000000000000055550000 (h)” as shown in the first line of the lamp data 1 shown in the figure, the output terminals 96-1 to 96-96 of the LED driver 90 (w1). -4 outputs a driving current for emitting the maximum luminance “F”, the output terminals 96-5 to 96-16 and 96-21 to 96-24 are not emitting light (minimum luminance), and the output terminal 96-17. ... 96 to 20 is information for designating output of a drive current having a luminance of “5”.
In the lamp data, such lighting data is set for each of the LED drivers 90 (w1 to w4, b1 to b5), and is set for each line, so that time series. A predetermined light emission pattern that changes is shown. (In the figure, the lighting data is illustrated only in part. The blank portion is not shown, and the lighting data is actually described.)

FIG. 24B shows mask data 1 to 5 as an example of the mask data table. Each mask data includes a mask for driving the decorative lamp 20w on the frame side, a mask for driving the decorative lamp 20b on the board side, an entire mask, a mask for the center case, Necessary mask patterns are stored for masking and the like.
The mask data 1 to 5 are data indicating that the output terminals 96-5 to 96-24 of the LED drivers 90 (w1 to w4 and b1 to b5) are turned off by “0h” and no mask by “Fh”, respectively. It is said that.
For example, in the mask data 1, the LED driver 90 (w1 to w4) in the frame driver unit 61 is “0000... 00 (h)” and the output terminals 96-5 to 96-24 are turned off. Is set for the LED drivers 90 (b1 to b5) of the panel driver unit 62, and "FFFF... FF (h)" and no output masks are set for the output terminals 96-5 to 96-24. ing. That is, the data specifies that only the decorative lamp 20w on the frame side is masked. (Note that the mask data 4 and 5 are not shown with data values)

In steps S706 and S707 in FIG. 20, an address corresponding to the lamp channel dwCHn being processed is specified in the lamp data table and the mask data table.
Subsequently, in step S708, the effect control CPU 200 obtains a timer (frame) of the corresponding line (the line indicated by the execution line (offset) of the current target lamp channel dwCHn) in the lamp data table, and substitutes it for the variable Dtime. .

  In step S709, the effect control CPU 200 develops the corresponding lighting data and mask data specified in steps S706 and S707, and generates LED drive data. Although this process will be described later, the lighting data and mask data for the lamp channel dwCHn currently being processed are reflected in the LED drive data to be output.

In step S710, the execution time (time), which is information of the ramp channel dwCHn, is incremented by one.
In step S711, the variable Dtime is compared with the execution time (time). The timer (frame) of the currently executing line is assigned to the variable Dtime. The execution time (time) is incremented by 1 in step S710 for each LED drive data update process (every 16 ms). Therefore, if Dtime ≦ time, the current line end timing is reached. If Dtime ≦ time is not satisfied, it is determined that the end of the current line has not yet been reached, and the process proceeds from step S711 to S719. If Dtime ≦ time, the process proceeds from step S711 to S712 as the end of the current line.
The effect control CPU 200 resets the execution time (time) to 0 in step S712. In step S713, the execution line (offset) value is incremented by one. In other words, the next line is targeted.
In step S714, the effect control CPU 200 specifies the address of the lamp data table corresponding line corresponding to the execution line (offset). In steps S715 and S717, it is confirmed whether an end code (D_DTEND) or a loop code (LMP_LP) is described in the line.
If the end code (D_DTEND) is described, the registered lighting number of the lamp channel dwCHn is updated to 0 in step S716. In other words, it indicates that the processing corresponding to the registration of the lamp channel dwCH is completed on the work.
If the loop code (LMP_LP) has been described, the value of the execution line (offset) is updated to the loop destination address in step S718.

In step S719, the effect control CPU 200 calculates the checksum of the LED drive data at the time of the lamp channel dwCHn. In step S720, the backup data is saved.
This completes the LED data update for one lamp channel dwCHn. As the loop processing LP2, the above processing is sequentially performed up to the ramp channels dwCH0 to dwCH15.

The LED output data is updated in each lamp channel dwCHn in step S709, and this is the following process.
FIG. 25A schematically shows an output data buffer that develops lighting data and mask data to generate LED drive data.
The output data buffer is prepared corresponding to each LED driver 90 (w1 to w4, b1 to b5), similarly to the lamp data table and the mask data table. One square shown corresponds to one LED driver 90 and serves as a buffer of (4 × 24) bit information.

For such an output data buffer, in step S709, a process of developing the mask data with AND (logical product) and developing the lighting data with OR (logical sum) is performed. This is sequentially performed in step S709 for each of the lamp channels dwCH0 to dwCH15 by loop processing (LP2).
For example, at the time point t0 shown in FIG. 22, the output data buffer is AND-expanded with the mask data of the lamp data 2 (see FIG. 23: no mask), and the lighting data of the third line of the lamp data 2 is OR-expanded. After the state, the mask data of the lamp data 5 (see FIG. 23: center case mask) is AND expanded, and the lighting data of the second line of the lamp data 5 is OR expanded.
As described above, in the mask data, 0h (= 0000) is extinguished and Fh (= 1111) is no mask. Therefore, expanding the mask data with AND means that the bit to be extinguished (masked) is set to “0” in the output data buffer value up to that point, and the bits not masked are not changed.
Further, when the lighting data is expanded OR, the lighting data of the lamp channel dwCH being processed is reflected in the output data buffer after masking.
By sequentially performing this process for the lamp channels dwCH0 to dwCH15, the LED drive data that is prioritized for the higher-numbered lamp channels is formed on the output data buffer.

[4-7: LED output processing of the first embodiment]

The LED drive data generated by the LED data update process as described above is actually output to each LED driver 90 in step S205 of the 1 ms timer interrupt process of FIG. 9 (however, in the cases 12 to 15 described above). The
In the present embodiment, LED drive data is output to a few LED drivers 90 during one 1 ms timer interrupt process. Furthermore, in the present embodiment, the effect control CPU 200 sends serial data of one transmission unit of LED drive data to the first and second systems of drive signal output means (frame driver unit 61 and panel driver unit 62). Output almost simultaneously.
For example, as shown in FIG. 25B, in case 12 of step S205 of the 1 ms timer interrupt process, the LED driver 90 (w1, w2, w3) of the frame driver unit 61 and the LED driver 90 (b1, b2) of the panel driver unit 62 are displayed. , B3), the LED drive data is transmitted. Transmission of the LED driver 90 to w1 and b1, w2 and b2, and w3 and b3 is performed simultaneously.
In case 12, LED drive data is transmitted to the LED driver 90 (w4) of the frame driver unit 61 and the LED driver 90 (b4, b5) of the panel driver unit 62. The LED driver 90 transmits to w4 and b4 simultaneously.

FIG. 26 shows a serial data structure when transmitting LED drive data to the LED driver 90. For example, the serial data structure is transmitted to one LED driver 90 such as the LED driver 90 (w1).
For example, LED drive data is transmitted as serial data having the structure of FIG. 26 to each of the LED drivers 90 (w1 to w4, b1 to b5) shown in FIG. 25B. FIG. 26 shows the serial data DATA and the enable signal ENABLE described with reference to FIGS.
This serial data is sequentially transmitted byte by byte during a period when the enable signal ENABLE is turned on. In other words, each byte of serial data having this structure is a transmission unit.

The serial data DATA includes a 1-byte slave address, a 1-byte data setting start register address (SX), 1-byte write data to the address (SX), and write data to the address (SX + 1). -Consists of a total of 26 bytes of write data to address (SX + 23).
Such serial data DATA is taken into the LED driver 90 during a period defined by the enable signal ENABLE.

The “slave address” is a device ID of each LED driver 90, and is a 1-byte code that identifies w1 to w4 or b1 to b5.
“Data setting start register address (SX)” is information for designating the head of a register for fetching data in the LED driver 90. For example, it is the designation information of the internal register of the data buffer / PWM controller 93 of FIG. In the LED driver 90 employed in the present embodiment, for example, registers (8 bits each) of register addresses 00h to 2Ch are prepared for capturing serial data. Of these, 24 registers (8 bits each) of register addresses 15h to 2Ch are registers (gradation) for inputting lighting data (PWM gradation instruction data) corresponding to 24 output terminals 96-1 to 96-24. Value setting unit). Therefore, the register address 15h is designated as the “data setting start register address (SX)”.
As “write data to address (SX)”, write data to the register at the register address (“15h” in this embodiment) specified by “data setting start register address (SX)”, that is, an output terminal LED drive data corresponding to 96-1 is set.
As “write data to address (SX + 1)”, write data to the register at register address + 1 (“16h” in this embodiment) designated by “data setting start register address (SX)”, that is, output LED drive data corresponding to the terminal 96-2 is set.
The same applies to the following, and “write data to address (SX + 23)” is a register address +23 (“2Ch” in this embodiment) specified by “data setting start register address (SX)”. Write data, that is, LED drive data corresponding to the output terminals 96-24 is set.

These write data have an 8-bit structure, but as described above, one lighting data has a 4-bit structure of “0h (= 0000)” to “Fh (= 1111)”. Four bits represent 16 gradations of brightness. On the other hand, each register (8 bits each) of the register addresses 15h to 2Ch for inputting the PWM gradation instruction data can correspond to 256 gradations with 8 bits.
In the case of the present embodiment, since the lighting data is data of 16 gradations, the lighting data is set in the upper 4 bits as 8-bit write data to each register of the register addresses 15h to 2Ch. Yes. This point will be described later.
Further, in step S205 in FIG. 9, it has been described that the LED driver 90 is initialized in cases 0 to 3. Specifically, this is a transmission process in which default values are set in registers of unused register addresses 00h to 14h. It becomes. This point will also be described later.

The LED drive data output process performed in step S205 (cases 12 and 13) of the 1 ms timer interrupt process will be described with reference to FIG.
In step S801, the effect control CPU 200 specifies the head address of the LED drive data (output data buffer in FIG. 25A) of the serial data output channels ch1 and ch2 corresponding to the start value.
The start value is the value of the LED driver 90 that is transmitted first. For example, in case 12 of FIG. 25B, the start value is “1”, and transmission is first performed from the serial data output channels ch1 and ch2 to the LED driver 90 (w1) and the LED driver 90 (b1), respectively. Here, the head address where the LED drive data for w1 is stored in the output data buffer of FIG. 25A and the head address where the LED drive data for b1 are stored are specified.
In case 13, the start value is “4”, and in the same way, the start address where the LED drive data for w4 is stored in the output data buffer of FIG. 25A and the LED drive data for b4 are stored. Specify the first address.

  Next, in step S802, the effect control CPU 200 specifies the slave addresses of the serial data output channels ch1 and ch2 corresponding to the start value. In the case 12, the address code indicates “w1, b1”, and in the case 13, the address code indicates “w4, b4”.

Then, as loop processing LP3, the processing of steps S803 to S815 is executed in a loop for the number of driver numbers.
In the example of FIG. 25B, in case 12, the number of driver numbers is “3” (that is, transmission is performed to three LED drivers 90 for one serial data output channel), and thus the loop process is performed three times. In case 13, the number of driver numbers is “2” (because the serial data output channel ch2 transmits to two LED drivers 90).

In step S803, the effect control CPU 200 turns on the enable signal ENABLE in the serial data output channels ch1 and ch2.
In step S804, the production control CPU 200 transmits the data of the first transmission unit (1 byte) as the output of the serial data DATA of the serial data output channels ch1 and ch2, that is, the serial data structure shown in FIG. 26 in this case. Sends and outputs the slave address of the first byte. The serial data output channels ch1 and ch2 are simultaneously transmitted in parallel.
When the transmission of one transmission unit is performed, in steps S805 and S806, completion of transmission output for each serial data output channel ch1 and ch2 is waited.

When the transmission output completion for the serial data output channels ch1 and ch2 is confirmed, the effect control CPU 200, in step S807, sets the data setting start register address (SX) (this example) as the next one transmission unit (1 byte) data transmission. 15h) is transmitted and output. Also in this case, data transmission is performed simultaneously on the serial data output channels ch1 and ch2.
When the transmission in one transmission unit is performed, in steps S808 and S809, the completion of transmission output for each serial data output channel ch1 and ch2 is awaited.

When the transmission output completion for the serial data output channels ch1 and ch2 is confirmed in steps S808 and S809, the effect control CPU 200 performs register transmission (SX = 15h) to data transmission in one transmission unit (1 byte) in step S810. Write data (= LED drive data) to (SX + 23 = 2Ch) is transmitted and output.
First, 1-byte LED drive data transmission to the register address (15h) is simultaneously performed in parallel for the serial data output channels ch1 and ch2. In steps S811 and S812, the transmission output completion for the serial data output channels ch1 and ch2 is awaited.
If transmission completion is confirmed, transmission of step S810 will be performed byte by byte until it is confirmed in step S813 that a total of 24 bytes, that is, completion of LED drive data transmission from register addresses 15h to 2Ch is confirmed. Therefore, next, 1-byte LED drive data transmission to the register address (16h) is performed for the serial data output channels ch1 and ch2. Further, after confirming the transmission, LED drive data is transmitted to the register address (17h). Thereafter, transmission completion standby → LED drive data transmission to register address (18h) → transmission completion standby → LED drive data transmission to register address (19h) → transmission completion standby →→ LED to register address (2Ch) The process of driving data transmission → transmission completion waiting is performed.

When the transmission output of 24 bytes for the LED drive data is completed, the serial data output for one LED driver 90 having the structure of FIG. 26 is completed. Therefore, the enable signal ENABLE is turned off in step S814, and the target slave address is incremented by 1 in step S815. Then, one loop process is completed.
FIG. 27 shows data transmitted in the above one loop process. In the serial data output channels ch1 and ch2, a slave address, a data setting start register address, and LED drive data LPDT1, LPDT2,.
Such transmission is performed, and LED drive data is set in the LED driver 90. On the LED driver 90 side, each output terminal 96-1 is based on the light emission luminance (16 gradations from 0h to Fh) indicated by the LED drive data LPDT1, LPDT2,... LPDT24 written in the registers (15h to 2Ch). The amount of current from ˜96-24 is controlled, and the LEDs 120 of each series connected to the output terminals 96-1 to 96-24 emit light.

In the case 12, the processes of steps S803 to S815 are similarly performed for the LED driver 90 (w2) and the LED driver 90 (b2) as the second loop process. Further, thereafter, as the third loop process, the processes of steps S803 to S815 are similarly performed for the LED driver 90 (w3) and the LED driver 90 (b3). The LED drive data output of FIG. 21 is completed by the three loop processes.
In case 13, the processes of steps S803 to S815 are performed for the LED driver 90 (w4) and the LED driver 90 (b4) as the first loop process. Thereafter, in the second loop process, the processes of steps S803 to S815 are performed only for the LED driver 90 (b5). The LED drive data output of FIG. 21 is completed by the two loop processes.
As described above, serial data output to each of the nine LED drivers 90 as shown in FIG. 25B is executed. Of course, if the number of LED drivers 90 mounted or the number of LED drivers 90 transmitted in one 1 ms timer interrupt process is different, the number of loops may naturally be different.
In the above example, two serial data output channels ch1 and ch2 are used. However, when three or more serial data output channels are used, serial data transmission is performed simultaneously in parallel. You can do that.

As in the processing of FIG. 21 described above, in the present embodiment, the effect control CPU 200 performs drive signal output means (frame driver) for the first system (serial data output channel ch1) and the second system (serial data output channel ch2). The unit 61 and the panel driver unit 62) transmit serial data of one transmission unit simultaneously. Then, after the transmission is completed, the next serial data of one transmission unit is transmitted substantially simultaneously to the drive signal output means of the first system and the second system. Through such processing, LED drive data is transmitted to each LED driver 90.
As a result, the time required for the entire serial data transmission operation can be shortened, and the processing load on the rendering control CPU 200 can be reduced.

The reason for this will be explained.
FIG. 28 shows the write timing of the clock signal CLK, transmission data, TDRE (transmission data empty flag), and transmission data used by the effect control CPU 200 for serial data transmission to the transmission data register.
The transmission data corresponds to the above-described slave address, data setting start register address, and LED drive data LPDT1, LPDT2,. Here, 8 bits as one transmission unit are shown as data d0 to d7.

The effect control CPU 200 writes 8-bit transmission data in the transmission data registers in the serial data output channels ch1 and ch2 when transmitting 8-bit data in one transmission unit in each of steps S804, S807, and S810 of FIG. The transmission data written to the transmission data register is transmitted and output one bit at each timing of the clock signal CLK.
Here, TDRE becomes “0” when transmission data is written in the transmission data register, indicating that valid data exists in the transmission data register. When the data in the transmission data register is actually output for transmission (loading to the transmission shift register) and transmission is started, it becomes “1”, indicating that there is no valid data in the transmission data register.
Therefore, as the transmission process of the effect control CPU 200, after confirming that the TDRE is “1”, the 8-bit transmission data is written to the transmission data register, and the next 8-bit transmission data is written next. Wait until TDRE becomes “1”. That is, during the period indicated as the standby time TW in FIG. 28, the next transmission data cannot be processed.

Regarding serial data transmission, conventionally, serial data of one transmission unit (8 bits) is transmitted from one serial data output channel to, for example, the first-system drive signal output means, and after the transmission is completed, from the next transmission channel The transmission operation is performed such that serial data of one transmission unit (8 bits) is transmitted to the drive signal output means of the second system. For example, the processing corresponding to steps S804 to S806 in FIG.
(ST1) Slave address output from ch1 (write to transmission data register)
(ST2) Transmission output completion waiting (ST3) Data setting start register address output from ch1 (writing to transmission data register)
(ST4) Transmission output completion waiting (ST5) LED drive data LPDT1 output from ch1 (writing to transmission data register)
(ST6) Transmission output completion standby (ST7) LED drive data LPDT2 output from ch1 (ST8) Transmission output completion standby ... Omission ...
(ST51) LED drive data LPDT24 output from ch1 (ST52) Transmission output completion standby (ST53) Slave address output from ch2 (ST54) ch2 transmission output completion standby (ST55) Data setting start register address output from ch2 (ST56) Transmission output completion LED drive data LPDT1 output from standby (ST57) ch2 (ST58) Transmission output completion standby (ST59) LED drive data LPDT2 output (ST60) transmission output completion standby from ch2 ... Omission ...
(ST103) LED drive data LPDT24 output from ch2 (ST104) Transmission output completion waiting.
In this case, a waiting time is generated for each transmission of one transmission unit in each of the serial data output channels ch1 and ch2, and transmission processing efficiency is poor.
In contrast, in this embodiment,
(S804) Slave address output from ch1 and ch2 (write to transmission data register)
(S805, S806) By performing transmission processing on both serial data output channels ch1 and ch2 at the same time, such as ch1 and ch2 transmission output completion waiting, the processing becomes efficient.
The same applies to the processing in steps S807 to S809 and the processing in steps S810 to S812.

Then, transmission to one LED driver 90 is 26 bytes for each transmission channel in one loop process (26 writes to the transmission data register). If simultaneous processing is not executed for each of the serial data output channels ch1 and ch2, the total standby time is approximately (52 × TW) in one loop processing period. In the case of this embodiment, this can be remarkably shortened to approximately (26 × TW) in one loop processing period.
In the LED drive data output process performed in the 1 ms timer interrupt process, the serial data output process can be made more efficient in this way, so that the processing load on the effect control CPU 200 is greatly reduced.

In the present embodiment, the LED drive data transmitted as serial data is data indicating the light emission luminance (gradation), and realizes light emission drive of 16 gradations with, for example, 4 bits as described above. By making such gradation control possible, more various effects can be realized.
In this embodiment, an example of 16 gradations has been described, but it is needless to say that multiple gradations may be used.

The pachinko gaming machine 1 according to the present embodiment includes a frame (front frame 2, outer frame 4 and glass door 5) and a game board (game board 3) attached to the frame. The first-system drive signal output means (frame driver unit 61) includes a plurality of driver circuits (LEDs) that output LED drive signals to a decorative lamp unit 63 (decorative lamp 20w) that is a rendering means provided in the front frame 2. The second-system drive signal output means (panel driver section 62) outputs an LED drive signal to the decoration lamp section 64 (decoration lamp 20b), which is an effect means provided in the game board 3. It is composed of a plurality of driver circuits (LED drivers 90).
With this configuration, all the LED drivers 90 of the frame driver unit 61 correspond to the decorative lamp 20w on the frame side, and all the LED drivers 90 of the panel driver unit 62 correspond to the decorative lamp 20b on the panel side. Therefore, it is possible to realize the simplification of wiring, the efficiency improvement, the ease of production control setting, and the like.

By the way, in this embodiment, in step S810, the data obtained by converting the lighting data having the 4-bit structure as described above into 8 bits is output as serial data in one transmission unit.
This bit conversion will be described with reference to FIG. FIG. 29A shows an example of 4 × 24-bit lighting data transmitted to one LED driver 90. That is, this is an example of data corresponding to one square of the output data buffer of FIG. 25A. The first “F8h” (“h” is omitted in the figure) is lighting data to be transmitted to the register addresses 15h and 16h of the LED driver 90, that is, “Fh” is written to the register address 15h of the LED driver 90. The lighting data as the gradation value for the terminal 96-1, and “8h” is the lighting data as the gradation value for the output terminal 96-2 to be written to the register address 16h. The next “0Fh” similarly corresponds to the register addresses 17h and 18h. The same applies to the following, and the last “00h” corresponds to the register addresses 2Bh and 2Ch.

Here, when considered in the unit of 8 bits as the internal processing unit of the effect control CPU 200, such as “F8h” “0Fh”... “00h” in FIG. 29A, the upper 4 bits (for example, “F8h” "Fh" is lighting data for an odd register address (for example, register address 15h), and lower 4 bits (for example, "8h" for "F8h") is lighting data for an even register address (for example, register address 16h). It becomes.
Here, “odd register address” and “even register address” are examples according to the register design of the LED driver 90. For the sake of convenience, the transmission destination is merely assumed to be the register addresses 15h to 2Ch.
In this case, for the lighting data to the odd register addresses (15h, 17h... 2Bh), the effect control CPU 200 masks the lower 4 bits of the 8-bit data and transmits it to the LED driver 90. On the other hand, for the lighting data to the even register address (16h, 18h... 2Ch), the effect control CPU 200 masks the upper 4 bits of the 8-bit data and shifts the 4-bit shift to the LED driver 90. Send. That is, as a result, 4-bit lighting data is converted into 8-bit and transmitted.

As this bit conversion, the case of “F8h” is shown in FIGS. 29B and 29C.
FIG. 29B shows processing when the lighting data “Fh” is transmitted to the register address 15 h. The lighting data extracted from the output data buffer of FIG. 25A is “F8h” = “11111000”, which is two lighting data of 4 bits each. The lower 4 bits are masked for this data. For example, AND is performed using mask data “F0h” = “11110000”. As a result, serial data “11110000” = “F0h” to be transmitted to the register address 15h is obtained as illustrated. In this case, the drive current output of the maximum gradation value (F0h) is performed from the output terminal 96-1.
On the other hand, FIG. 29C shows a process when the lighting data “8h” is transmitted to the register address 16h. As described above, the lighting data extracted from the output data buffer in FIG. 25A is “F8h” = “11111000”. The upper 4 bits are masked for this data. For example, AND is performed using mask data “0Fh” = “00001111”. As a result, data “00001000” is obtained as illustrated. Further, in this case, serial data “10000000” = “80h” to be transmitted to the register address 16h is obtained by shifting the data by 4 bits. In this case, a drive current output having an intermediate gradation value (80h) is output from the output terminal 96-1.

As described above, in the present embodiment, the effect control unit 51 has, for example, the light emission luminance information of the second bit number (for example, 4 bits) that is smaller than the first bit number (for example, 8 bits) in the effect control ROM 201. (Lighting data) is stored in the form of a lamp data table or the like. Then, the production control CPU 200 converts the light emission luminance information of the second bit number into the first bit number to generate LED drive data, and the LED drive data is converted into serial data to the LED driver 90 which is a light emission drive signal output means. Send.
The fact that the 8-bit PWM data can be input to the register addresses 15h to 2Ch of the LED driver 90 enables LED light emission control of 256 gradations if it is 8-bit lighting data. However, 256 gradations are not necessary for the control of the decoration lamps 20w and 20b used for the light emission effect of the gaming machine of the present embodiment. Specifically, 16 gradations of “00h”, “10h”, “20h”,... “F0h” are sufficient.
Therefore, in this embodiment, the lighting data has a 4-bit structure, and 16 gradations are expressed. When outputting to the LED driver 90, 4 bits are converted into 8 bits and transmitted.

By doing in this way, the production control unit 51 can greatly reduce the data capacity of the lighting data stored in the internal ROM (production control ROM 201), and the memory capacity consumption can be suppressed.
Further, in recent years, general-purpose LED drivers of high-performance type such as 256 gradations have a higher production volume and are more advantageous in price. Therefore, for example, when 16 gradations are required, it is more cost-effective to use a 256 gradation LED driver than to use an LED driver having 16 gradation control capability, and is stable. Availability is also good. This provides manufacturing and cost advantages.
As described above, the effect control CPU 200 arranges the 4-bit lighting data in the upper 4 bits of the 8 bits, and generates 8-bit LED drive data (serial data to be transmitted).
As described above, the LED driving data of 16 gradations can be generated by the arrangement of the upper 4 bits, and the processing is very simple processing as in the examples of FIGS. 29B and 29C, for example. For this reason, the processing load of bit number conversion hardly poses a problem.

In the above example, the lighting data converted into 8 bits is assumed to be “00h”, “10h”, “20h”... “F0h”, but the following example is also conceivable.
In this case, when the 4-bit lighting data is “Fh”, the 8-bit serial data “F0h” has the maximum control brightness, but the LED driver 90 can handle “FFh”. Therefore, the lower 4 bits of “F0h” of the 8-bit serial data may be converted to “1111” and “FFh” (= 11111111) may be transmitted. That is, the serial data to be transmitted is “00h”, “10h”, “20h”,... “E0h”, “FFh”. In this way, it is possible to execute light emission with the maximum brightness on the light emission drive capability of the LED driver 90.
For “10h”, “20h”,... “F0h” other than “00h”, the lower 4 bits may be converted to “1111” and transmitted as “1Fh”, “2Fh”, “FFh”. . Thereby, the light emission brightness in each gradation can be increased, and the effect can be improved.
Further, the example in which the 4-bit lighting data is 8 bits has been described so far, but this is an example. The first bit number (for example, 8 bits) is determined according to the design on the LED driver side. The second bit number (for example, 4 bits) may be set according to the gradation to be expressed. For example, 1 bit may be used for 2 gradations, 2 bits for 4 gradations, 3 bits for 8 gradations, and so on.
In this embodiment, LED drive data is transmitted as serial data output. However, the process of converting the second bit number of lighting data into the first bit number and transmitting it to the light emission driver is performed in parallel. The present invention can also be applied to data output or wireless transmission output. In this case, when there is a difference between the gradation capability of the transmission destination and the desired gradation expression, the data storage capacity of the transmission source can be reduced.

[4-8: LED driver initialization processing]

In step S205 in FIG. 9, it is described that the LED driver 90 is initialized in cases 0 to 3 in which the interrupt counter value is “0” to “3”. This is because the register addresses 00h to 14h that are not used are registered. The default value is set in the transmission process.
Here, as described above, the register addresses 15h to 2Ch of the LED driver 90 are registers to which lighting data (gradation values) corresponding to the output terminals 96-1 to 96-24 are written, respectively. Data is written in the registers 00h to 14h as follows.

00h: PWM cycle setting data is set in 3 bits out of 8 bits, and master / slave setting data is set in 1 bit.
01h: Setting data of fade-in speed per gradation is set by 3 bits out of 8 bits and fade-out speed is set by 3 bits.
02h: Red LED current value data is set in 5 bits of 8 bits.
03h: Current value data of the green LED is set in 5 bits out of 8 bits.
04h: Current value data of blue LED is set in 5 bits out of 8 bits.
05h: Six bits out of eight bits set ON / OFF setting data of output terminals 96-1 to 96-6.
06h: Six bits out of eight bits set ON / OFF setting data of output terminals 96-7 to 96-12.
07h: Six bits out of eight bits set ON / OFF setting data of output terminals 96-13 to 96-18.
08h: Six bits out of eight bits set ON / OFF setting data of output terminals 96-19 to 96-24. The registers at the register addresses 05h to 08h serve as on / off setting units for the output terminals 96-1 to 96-24.
09h to 0Eh: For each of the four output terminals, any one of “PWM output priority”, “fade output priority”, and “forced on / off output priority” is selected and set for each of the four output terminals. The six registers from 09h to 0Eh correspond to the 24 output terminals 96-1 to 96-24.
0Fh to 11h: Three registers (24 bits in total) are set to enable / disable the fade function of 24 output terminals 96-1 to 96-24.
12h to 14h: Three registers (24 bits in total) are used to forcibly turn on / off the 24 output terminals 96-1 to 96-24.

In the initialization process of the LED driver 90, default values are set in these registers (00h to 14h). The default values are as follows: Note that “0x” represents hexadecimal notation as in “h”. In order to distinguish between the register address value and the data value (default value), “0x” and “h” are used separately.
00h: 0x00: Initial setting of PWM cycle 01h: 0x00: No fade-in / fade-out slope 02h: 0x1F: Initial setting of red LED current value 03h: 0x1F: Initial setting of green LED current value 04h: 0x1F ... Initial setting of blue LED current value 05h: 0x77 ... ON setting of output terminals 96-1 to 96-6 06h: 0x77 ... ON setting of output terminals 96-7 to 96-12 07h : 0x77 ... ON setting of output terminals 96-13 to 96-18 08h: 0x77 ... ON setting of output terminals 96-19 to 96-24 09h: 0x00 ... PWM output priority 0Ah: 0x00 ... PWM output priority 0Bh: 0x00 ... PWM output priority 0Ch: 0x00 ... PWM output priority 0Dh: 0x00 ... PWM Output priority 0Eh: 0x00 ... PWM output priority 0Fh: 0x00 ... Fade function disabled 10h: 0x00 ... Fade function disabled 11h: 0x00 ... Fade function disabled 12h: 0x00 ... Forced on / off setting All off 13h: 0x00 ... All forced on / off settings off 14h: 0x00 ... All forced on / off settings off

The default values as described above are set for each LED driver 90 (w1 to w4, b1 to b5) in step S205 (cases 0 to 3) of the 1 ms timer interrupt process of FIG.
FIG. 30 shows an example of the LED driver initialization process. This process is called when the interrupt counter = 0-3.
Further, initialization is performed for each LED driver 90 (w1 to w4, b1 to b5) in several times (for example, four times). For example, in step S205 of one 1 ms timer interruption process, initialization is performed for three or two LED drivers 90.

FIG. 30 shows the initialization process for one LED driver 90.
In step S901, the effect control CPU 200 performs processing according to the interrupt counter value (any of cases 0 to 15). If any of cases 0 to 3, the LED driver 90 to be initialized is specified, and the process proceeds to step S902 and subsequent steps for the LED driver 90. In cases other than Cases 0 to 3, since initialization is not performed, the processing after Step S902 is not performed.

When initialization is performed for a certain LED driver 90, the effect control CPU 200 turns on an enable signal (ENABLE) corresponding to the LED driver 90 in step S902. In step S902, the slave address of the target LED driver 90 is output.
Further, the effect control CPU 200 outputs a data setting start register address in step S904. In this case, since data is written to the register addresses “00h” to “14h”, the data setting start register address = 00h.
In step S905, the effect control CPU 200 sequentially transmits data of default values corresponding to the register addresses “00h” to “14h”. In this process, the above-described default values are written in the register addresses “00h” to “14h” of the target LED driver 90. That is, the LED driver 90 is initialized.
When the above is completed, the enable signal (ENABLE) is turned off in step S906, and the slave address is incremented by 1 in step S907. That is, the next LED driver 90 can be designated. Then, the initialization process for one LED driver 90 is completed.

In this embodiment, as described above, two systems of serial data output are performed as the serial data output channels ch1 and ch2.
FIG. 30 shows the initialization process for one LED driver 90. By the process of FIG. 30, for example, each of nine LED drivers 90 (w1 to w4, b1 to b5) is initialized sequentially one by one. May be. For example, LED driver 90 (w1, w2) in case 0 of the 1 ms timer interrupt process, LED driver 90 (w3, w4) in case 1, LED driver 90 (b1, b2) in case 2, and case In the case of 3, the processing can be assigned as the LED driver 90 (b3, b4, b5).

However, initialization processing for each LED driver 90 (w1 to w4, b1 to b5) of the frame driver unit 61 and the panel driver unit 62 is performed by performing substantially simultaneous transmission using the serial data output channels ch1 and ch2. Can be made more efficient. That is, the same method as the LED drive data transmission described above can be adopted. A processing example in that case is shown in FIG.
Assume that the timing of each LED driver 90 to be initialized is assigned, for example, as in the example of LED drive data output in FIG. 25B.
That is, the case 12 in FIG. 25B is considered as, for example, case 0, and in the case 0 in step S205 of the 1 ms timer interrupt process, the LED driver 90 (w1, w2, w3) of the frame driver unit 61 and the board driver unit 62 Initialization data is transmitted for the LED driver 90 (b1, b2, b3). Transmission of the LED driver 90 to w1 and b1, w2 and b2, and w3 and b3 is performed simultaneously.
Further, the case 13 in FIG. 25B is considered as, for example, the case 1. In the case 1, the initialization data is transferred to the LED driver 90 (w4) of the frame driver unit 61 and the LED driver 90 (b4, b5) of the panel driver unit 62. Send. The LED driver 90 transmits to w4 and b4 simultaneously.

  As the processing in FIG. 31, the effect control CPU 200 identifies the slave addresses of the serial data output channels ch1 and ch2 in step S951. According to the example similar to FIG. 25B above, in the case 0, the address code indicates “w1, b1”, and in the case 1, the address code indicates “w4, b4”. .

Then, as loop processing LP5, the processing of steps S952 to S964 is executed in a loop for the number of driver numbers.
In the case of the example similar to FIG. 25B, in case 0, the number of driver numbers is “3” (that is, transmission is performed to three LED drivers 90 for one serial data output channel). . In case 1, the number of driver numbers is “2” (because the serial data output channel ch2 transmits to two LED drivers 90).

In step S952, the effect control CPU 200 turns on the enable signal ENABLE in the serial data output channels ch1 and ch2.
In step S953, the production control CPU 200 transmits the data of the first transmission unit (1 byte) as the output of the serial data DATA of the serial data output channels ch1 and ch2, that is, in this case, the serial data structure shown in FIG. Sends and outputs the slave address of the first byte. The serial data output channels ch1 and ch2 are simultaneously transmitted in parallel.
When the transmission of one transmission unit is performed, in steps S954 and S955, the completion of transmission output for each serial data output channel ch1 and ch2 is waited.

When the transmission output completion for the serial data output channels ch1 and ch2 is confirmed, the effect control CPU 200 transmits and outputs the data setting start register address (SX) as data transmission of the next one transmission unit (1 byte) in step S956. To do. Since writing is performed to the register addresses 00h to 14h, SX = 00h is set. Also in this case, data transmission is performed simultaneously in parallel for the serial data output channels ch1 and ch2.
When the transmission in one transmission unit is performed, in steps S957 and S958, completion of transmission output for each serial data output channel ch1 and ch2 is awaited.

When it is confirmed in steps S957 and S958 that transmission output for the serial data output channels ch1 and ch2 is completed, the effect control CPU 200 performs register transmission (00h) to (14h) as data transmission of one transmission unit (1 byte) in step S959. Send default data to).
First, 1-byte default data transmission to the register address (00h) is simultaneously performed in parallel for the serial data output channels ch1 and ch2. In steps S960 and S961, the transmission output completion for the serial data output channels ch1 and ch2 is awaited.
If transmission completion is confirmed, transmission of step S959 is performed byte by byte until completion of transmission of default data from register addresses 00h to 14h is confirmed in step S962. Therefore, next, 1-byte default data transmission to the register address (01h) is performed for the serial data output channels ch1 and ch2. Further, after the transmission confirmation, default data transmission to the register address (02h) is performed. Thereafter, transmission completion standby → default data transmission to register address (03h) → transmission completion standby → default data transmission to register address (04h) → transmission completion standby— → default data transmission to register address (14h) → The process of waiting for transmission completion is performed.

  When the transmission output of default data to the register addresses 00h to 14h is completed, the enable signal ENABLE is turned off in step S963, and the target slave address is incremented by +1. Then, one loop process is completed.

In case 0, the processing of steps S952 to S964 is similarly performed for the LED driver 90 (w2) and the LED driver 90 (b2) as the second loop processing. Further, thereafter, as the third loop process, the processes of steps S952 to S964 are similarly performed for the LED driver 90 (w3) and the LED driver 90 (b3). The LED driver initialization process of FIG. 31 is completed by the three loop processes.
In Case 1, as the first loop process, the processes of steps S952 to S964 are performed for the LED driver 90 (w4) and the LED driver 90 (b4). Thereafter, in the second loop process, the processes of steps S952 to S964 are performed only for the LED driver 90 (b5). The LED driver initialization process of FIG. 31 is completed by the two loop processes.
As described above, the initialization by outputting the default data to each of the nine LED drivers 90 as shown in FIG. 25B is executed. Of course, if the number of LED drivers 90 mounted or the number of LED drivers 90 transmitted in one 1 ms timer interrupt process is different, the number of loops may naturally be different.
In the above example, two serial data output channels ch1 and ch2 are used. However, when three or more serial data output channels are used, serial data (default data) are simultaneously used in parallel. What is necessary is just to make it transmit.

  As in the process of FIG. 31 described above, also for the initialization process of the LED driver 90, the drive signal output means (frame driver unit) of the first system (serial data output channel ch1) and the second system (serial data output channel ch2) 61 and the board driver unit 62) transmit serial data of one transmission unit simultaneously. Then, after the transmission is completed, the next serial data of one transmission unit is transmitted substantially simultaneously to the drive signal output means of the first system and the second system. By performing the initialization process of the LED driver 90 in such a process, the time required for the entire initialization process can be shortened, and the processing load on the effect control CPU 200 can be reduced.

In the present embodiment, as described above, each LED driver 90 is initialized by serial data transmission of default data as initial setting data. As a result, each LED driver 90 has a gradation value indicated by the LED drive data. Accordingly, the LED 120 connected to the output terminals 96-1 to 96-24 is set to a state where the LED 120 is turned off, turned on, and a light emission driving signal for realizing the light emission luminance at the time of lighting is output.
That is, the above-mentioned default value (= ON data) is always set by the initialization process for the register addresses 05h to 08h which are the on / off setting units for the output terminals 96-1 to 96-24, and the output terminal 96- 1 to 96-24 are all turned on, and the PWM priority is set by setting default values of the register addresses 09h to 14h, and the fade function and the forced on / off function are invalidated. Therefore, each LED driver 90 performs PWM control based on the gradation values (lighting data values) written in the register addresses 15h to 2Ch, which are gradation value setting units, and outputs terminals 96-1 to 96-24. Then, a light emission drive current having a current amount corresponding to the gradation from the current is passed.

That is, in the LED drive data output processing of FIG. 21 performed in case S12 to case 15 of step S205 of FIG. 9, “00h” “10h” “20h” as LED drive data written to the register addresses 15h to 2Ch. ... Transmission of 16 gradation data of "F0h" is performed, but when transmitting this LED drive data, only transmission of 16 gradation data of "00h", "10h", "20h", "F0h" Thus, lighting (10h to F0h) in which gradation control is performed from turning off (00h) is executed.
When this is viewed from the production control CPU 200 side, it means that all of the light emission brightness control at the time of turning off, turning on, and turning on can be executed by the lighting data of 0h to Fh.
As a result, the effect control CPU 200 can realize the LED light emission control with simple lighting data setting, the processing load is small, and the data capacity required for the control can be reduced to only the lighting data. Reduction of consumption is also realized.

In summary, the effect control unit 51 performs a process in which the register addresses 05h to 08h, which are on / off setting units, are always set to on, and generates LED drive data including gradation values according to the gaming state. By transmitting to the LED driver 90 and setting the gradation values to the register addresses 15h to 2Ch which are gradation value setting units, 16 gradations of “00h”... “F0h” at the time of LED drive data transmission By simply transmitting the data, it is possible to execute control from turning off to lighting with gradation controlled.
In the above example, in the embodiment, the initialization process is performed every 16 ms as the process of setting the register addresses 05h to 08h, which are the on / off setting units, to be always on, but only the transmission of 16-gradation data is performed. In order to control from turn-off to gradation-controlled turn-on, register addresses 05h to 08h need only be always set to on. Therefore, for example, the effect control CPU 200 may perform initialization processing at the beginning of power-on, for example, and only set the register addresses 05h to 08h to ON. This is also an example of processing in which the on / off setting unit is always on.

  In the above embodiment, the LED driver 90 is a gaming state that defines the first register (register addresses 15h to 2Ch) in which the LED driving data that changes according to the gaming state is set, and the operation of the LED driver 90. And a second register (register addresses 00h to 14h) in which fixed data (initialization data) that does not change is set. Then, the production control unit 51 sets the LED drive data of the first register at every predetermined cycle (every occasion of the 1 ms timer interrupt processing cases 12 to 15), and at every predetermined cycle (the case of 1 ms timer interrupt processing). The fixed data of the second register is set every 0-3). From the viewpoint of each LED driver 90, initialization data is set in the second register every 16 ms, and LED drive data (gradation value) is set in the first register every 16 ms.

In the case of the present embodiment, the set values of the register addresses 00h to 14h are always the above-described default values during the game. Therefore, the process for setting the default value in the second register as the initialization process may be performed once at the time of startup. However, the set values of the register addresses 00h to 14h may be destroyed or lost due to noise or the like, and the operation of the LED driver 90 may not be the operation intended by the LED drive data. On the other hand, in the present embodiment, by performing the initialization process periodically, even if the set values of the register addresses 00h to 14h are destroyed, they can be restored immediately and become the original initialization state. Thereby, an accurate LED light emission operation based on LED drive data is always executed. Thus, the output operation of the light emission drive signal based on the LED drive data can be stably maintained in a normal state.

<5. Second Embodiment>

Next, the driver configuration as the second embodiment will be described. Note that configurations and processes that are the same as those in the first embodiment are omitted, and only different points will be described.
FIG. 32 shows the connection configuration of the effect control unit 51 (effect control CPU 200) and the LED driver 130 in the same format as in FIG. 4 in the first embodiment.
In this example, the effect control CPU 200 uses three serial data output channels ch1, ch2, and ch3. As the LED driver 130, three systems (frame driver unit 61, panel driver units 62A and 62B) are provided.
Serial data transmission to the plurality of LED drivers 130 as the frame driver unit 61 is performed by the serial data output channel ch1.
Serial data transmission to the plurality of LED drivers 130 as the panel driver unit 62A is performed by the serial data output channel ch2.
Serial data transmission to the plurality of LED drivers 130 as the panel driver unit 62B is performed by the serial data output channel ch3.

The signal lines of the serial data output channels ch1, ch2, and ch3 include a latch signal line that supplies a latch signal LATCH, a clock line that supplies a clock signal CLK, an enable signal line that supplies an enable signal ENABLE, and effect drive data. A data line for supplying serial data DATA is provided.
The latch signal LATCH, the clock signal CLK, and the enable signal ENABLE line are supplied in parallel to the plurality of LED drivers 130 constituting the frame driver unit 61 (or the panel driver units 62A and 62B). On the other hand, the serial data DATA is supplied to the first LED driver 130 among the plurality of LED drivers 130 constituting the frame driver unit 61 (or the panel driver units 62A and 62B), and sequentially transferred to the subsequent LED driver 130. To go.
That is, the input / output of serial data DATA is sequentially connected in series to each LED driver 130 in one system, and the serial data DATA from the presentation control CPU 200 is transmitted from the first LED driver 130 to the last LED in one system. The LED drivers 130 are sequentially transferred to the driver 130, and each LED driver 130 takes in the serial data DATA based on the latch signal from the effect control CPU 200.

As each LED driver 130 in the frame driver unit 61 and the panel driver units 62A and 62B, for example, “BD7851FP (manufactured by ROHM Co., Ltd.)” which is a 16-bit constant current LED driver can be used, for example, 16 constant current outputs. Provide terminals.
Therefore, a single LED driver 130 can output a maximum of 16 LED driving currents. One “series” refers to a group of one or more LEDs connected in series or in parallel to one current output terminal.
The number of LED drivers 130 in the frame driver unit 61 is determined by the number of LED series (the number of decorative lamps 20w) arranged on the frame side.
Further, the number of LED drivers 130 in the panel driver units 62A and 62B is determined by the number of LED sequences (the number of decorative lamps 20b) arranged on the panel side.

FIG. 33 shows a schematic configuration example of a main part of the LED driver 130.
The LED driver 90 includes a 16-bit shift register 131, a latch unit 132, an output gate unit 133, and constant current output terminals 139-1 to 139-16.
16 series of LEDs 120 are connected to all (or part of) the constant current output terminals 139-1 to 139-16. Note that the drawing shows a simplified state in which one LED 120 is connected to one series of constant current output terminals 139, but a configuration in which a plurality of LEDs are connected to one series of constant current output terminals 139 (for example, (Serial connection) is also possible.

In the LED driver 130, the serial data DATA is supplied to the terminal 134 and the clock signal CLK is input to the terminal 135 with respect to the shift register 131.
The serial data DATA from the effect control CPU 200 is supplied to the terminal 134 of the leading LED driver 130 of each system. The terminal 134 of the second and subsequent LED drivers 130 of each system is connected to the terminal 136 of the previous LED driver 130.
The shift register 131 is composed of, for example, 16 stages of D flip-flop circuits, and takes in the serial data DATA from the terminal 134 at the timing of the clock signal CLK and shifts the data held in each D flip-flop circuit to the subsequent stage. Go. The output of the 16th stage D flip-flop circuit is supplied from the terminal 136 to the shift register 131 from the terminal 134 of the next LED driver 130.

Each LED driver 130 is supplied with a latch signal LATCH from the effect control CPU 200 from the terminal 137 to the latch unit 132. The latch unit 132 latches the values of the 16 D flip-flop circuits in the shift register 131 at the timing when the latch signal LATCH is input. 16-bit data is latched.
The 16-bit data latched by the latch unit 132 is supplied to the output gate unit 133.
Note that the LED driver 130 of each system has a configuration in which serial data DATA is sequentially transferred. The effect control CPU 200 receives the LED drive data (16 bits) for the last LED driver 130, the LED drive data (16 bits) for the previous LED driver 130, ... the LED drive data (16 bits) for the first LED driver 130. Output sequentially. Each LED driver 130 is supplied to itself by outputting a latch signal LATCH in parallel to all LED drivers 130 in the system at the timing when 16-bit LED drive data is transferred to the first LED driver 130. Further, 16-bit LED drive data can be taken into the latch unit 132.

When the enable signal ENABLE from the terminal 138 is ON, the output gate unit emits light from the LED 120 from each of the constant current output terminals 139-1 to 139-16 based on the 16-bit data latched by the latch unit 132. Current output. Each latched 16-bit bit becomes a current output control value for each of the 16 constant current output terminals 139-1 to 139-16.
With such a configuration, each LED driver 130 drives a maximum of 16 connected LEDs 120.

In the second embodiment, the effect control CPU 200 converts the serial data of one transmission unit into drive signal output means (frame driver unit 61 and panel driver units 62A and 62B) of the first system, the second system, and the third system. ) Is output almost simultaneously.
The LED output processing as the second embodiment will be described with reference to FIG.
As in the case described in the first embodiment, the LED drive data generated by the LED data update process is output to each LED driver 130 at a predetermined timing.

In step S851, the effect control CPU 200 specifies the head address of the LED drive data (for example, the output data buffer corresponding to the output data buffer of FIG. 25A of the first embodiment) in each of the serial data output channels ch1, ch2, and ch3. . In the first embodiment, the LED drive data for one LED driver 90 is an example of 4 × 24 bits, but in the second embodiment, the LED drive data for one LED driver 130 is 16 bits, for example. Become.
In step S852, the effect control CPU 200 turns off the latch signal LATCH of all the serial data output channels ch1, ch2, and ch3. In step S853, the enable signals ENABLE of all the serial data output channels ch1, ch2, and ch3 are turned on.

Then, as the loop process LP4, the processes of steps S854 to S859 are repeated as many times as necessary.
For explanation, it is assumed that the number of LED drivers 130 is five for the frame driver 61, three for the panel driver 62A, and six for the panel driver 62B. That is, serial data output channel ch1 transmits to five LED drivers 130, serial data output channel ch2 transmits to three LED drivers, and serial data output channel ch3 transmits to six LED drivers 130. Shall.
Note that writing to the transmission data register is performed 8 bits at a time, while 16-bit data is transmitted to one LED driver 130. Therefore, two transmissions are required for one LED driver 130. Therefore, writing to the transmission data register is 10 times for the serial data output channel ch1, 6 times for the serial data output channel ch2, and 12 times for the serial data output channel ch3.
As the loop processing LP4, the loop is performed as many times as the number of LED drivers 130 (six) and the number of transmissions of the serial data output channel ch3 (= 12 times).

As the loop process LP4, the effect control CPU 200 outputs serial data DATA (8-bit writing to the transmission data register) as transmission in one transmission unit of the serial data output channel ch1 in step S854.
At substantially the same time, the serial data DATA of the serial data output channel ch2 is output (8-bit writing to the transmission data register) at step S855, and at the same time, the serial data DATA of the serial data output channel ch3 is output (at step S856). 8-bit write to the transmission data register).
As described above, the serial data output channels ch1, ch2, and ch3 simultaneously transmit the serial data DATA (16 bits × the number of LED drivers) of each system.
In steps S857, S858, and S859, the effect control CPU 200 waits for the completion of transmission of serial data DATA in each serial data output channel ch1, ch2, and ch3.
When the transmission is completed, the processes of steps S854, S855, and S856 are performed again.

Note that due to the difference in the number of LED drivers 130, a serial data output channel is generated that completes the output of all data before others. In the case of the above example, the serial data output channel ch1 is completed by performing step S854 10 times, the serial data output channel ch2 is completed by performing step S855 six times, and the serial data output channel ch3 is completed by performing step S856 12 times. Complete by doing.
Therefore, in this example, for the serial data output channels ch1 and ch2, the serial data output in steps S854 and S855 may not be performed at the number of loops after completion.
Note that it is natural to control the clock signal CLK (for example, mask) so that data shift in the shift register 136 is not performed except during actual serial data transmission.

When the transmission is completed (in the above example, the loop processing LP4 is completed 12 times), the latch signal LATCH of all the serial data output channels ch1, ch2, and ch3 is turned on in step S860. As a result, serial data DATA (16-bit LED drive data) is captured in all the LED drivers 130. When the latch is performed, in step S861, the latch signal LATCH of all the serial data output channels ch1, ch2, and ch3 is turned off.
At this point, the enable signal ENABLE is on. For example, the output gate unit 133 of each LED driver 130 drives the constant current output terminals 139-1 to 139-16 by the LED drive data latched in the latch unit 132 when the enable signal ENABLE from the terminal 138 is OFF. It is supposed to be. Therefore, the effect control CPU 200 turns off the enable signal ENABLE in step S862. Accordingly, each LED driver 130 performs light emission driving of the connected LED 120 based on the LED driving data written this time.

In the second embodiment, the effect control CPU 200 outputs drive signals for the first system (serial data output channel ch1), the second system (serial data output channel ch2), and the third system (serial data output channel ch3). Serial data is simultaneously transmitted to the means (the frame driver unit 61 and the panel driver units 62A and 62B).
Then, after the transmission is completed, each LED driver 130 is caused to execute a latch.
As a result, the time required for the entire serial data transmission operation can be shortened, and the processing load on the rendering control CPU 200 can be reduced.

For example, conventionally, the processing corresponding to steps S854 to S860 in FIG.
(ST1) Serial data transmission of ch1 (writing to transmission data register)
(ST2) Ch1 transmission output completion waiting ... The above is the required number of loops (STx) ch1 latch signal LATCH is on

(STx + 1) ch2 serial data transmission (writing to transmission data register)
(STx + 2) ch2 transmission output completion waiting ... The above is a required number of loops (STy) ch2 latch signal LATCH on (STy + 1) ch3 serial data transmission (writing to transmission data register)
(STx + 2) ch3 transmission output completion waiting ... The above is performed as the required number of loops (STz) ch3 latch signal LATCH on.
In this case, a waiting time occurs in each of the serial data output channels ch1, ch2, and CH3, and the transmission processing efficiency is poor.
In contrast, in this embodiment,
(S854, S855, S856) Serial data transmission start from ch1, ch2, ch3 (S857, S858, S859) Transmission output completion waiting of ch1, ch2, ch3 (S860) All channel latch signal LATCH on simultaneously By performing transmission processing on both serial data output channels ch1, ch2, and ch3, the processing efficiency is improved.

Particularly in the case of the second embodiment, serial data for one system of drive signal output means (frame driver unit 61, panel driver units 62A and 62B) is the number of LED drivers 130 included in the system × 16. A unit of bits.
Therefore, the entire standby time is until the serial data transfer to the drive signal output means having the largest number of LED drivers 130 is completed. That is, in the above example, data transmission to all the serial data output channels ch1, ch2, and ch3 can be completed within the time required for the serial data output channel ch3 having the largest number of LED drivers 130.
Thereby, the total time required for serial data transmission can be remarkably shortened as compared with the case of performing output to individual drive signal output means and standby.

Desirably, the number of LED drivers 130 in the drive signal output means of each system should be the same. Alternatively, the same number may be provided by providing dummy drivers. Then, the effect control CPU 200 can start serial data transmission from the three serial data output channels ch1, ch2, and ch3 at the same time, complete the transmission at the same time, can be latched at the timing immediately thereafter, and the processing becomes easy.
In FIG. 34, after confirming the completion of transmission in all the serial data output channels in steps S857 to S859, the latches of all the systems are executed in step S860. The channel may be latched on.

In the second embodiment, the first-system drive signal output means (frame driver section 61) sends an LED drive signal to the decorative lamp section 63 (decorative lamp 20w), which is an effect means provided in the front frame 2. Is composed of a plurality of driver circuits (LED drivers 90). The second-system drive signal output means (board driver section 62A) and the third-system drive signal output means (board driver section 62B) are decoration lamp sections 64 (decoration lamps) that are presentation means provided in the game board 3. 20b) includes a plurality of driver circuits (LED drivers 90) that output LED driving signals.
With this configuration, all the LED drivers 90 of the frame driver unit 61 correspond to the decorative lamp 20w on the frame side, and all the LED drivers 90 of the panel driver units 62A and 62B correspond to the decorative lamp 20b on the panel side. As a result, it is possible to realize the simplification and efficiency of wiring, the ease of setting the production control, and the like.

<6. Modification>

Although the embodiment has been described above, the present invention is not limited to the example given in the embodiment, and various modifications and application examples are conceivable.
As the decorative lamp portions 63 and 64 using LEDs or the like, an example of one system (one serial data output channel) on the frame side and one system or two systems on the panel side is given, but it is of course not limited thereto. A plurality of systems may be provided for the decorative lamp section 63 on the frame side, and three or more systems may be provided in the decorative lamp section 64 on the panel side.
Further, the panel-side decorative lamp 20b and the frame-side decorative lamp 20w may be mixed in one system.

The present invention can be applied not only to LED light emission driving but also to serial data transmission for other driving control, for example, serial data transmission to a driver of a driving motor of a movable body such as a stepping motor or a solenoid.
Moreover, although the present invention has been shown as being applied to a ball game machine such as the pachinko gaming machine 1, it can also be applied to a spinning-type game machine (so-called slot machine).

DESCRIPTION OF SYMBOLS 1 Pachinko machine 2 Front frame 3 Game board 3a Game area 4 Outer frame 5 Glass door 6 Axle support mechanism 7 Operation panel 8 Upper tray unit 9 Lower tray unit 10 Launching operation handle 11 Effect switch 12 Effect button 13 Cross key 14 Ball lending Button 15 Card return button 20w, 20b Decorative lamp 25 Speaker 31 Sphere guide rail 32M Main liquid crystal display device 32S Sub liquid crystal display device 33 Symbol display section 41 Upper start opening 42 Ordinary variable winning device 42a Lower start opening 43 General winning opening 44 Gate 45 First special variable winning device 46 Second special variable winning device 50 Main control board 51 Production control board 52 Liquid crystal control board 53 Dispensing control board 54 Launching control board 58 Power supply board 59 Speaker unit 60 Operation unit 61 Frame driver unit 62 Panel driver unit 63,64 Decorative lamp part 90,1 30 LED driver 120 LED
200 Production control CPU
201 Production control ROM
202 Production control RAM

Claims (1)

A plurality of light emitting means for performing a light emitting operation according to a gaming state;
A first system and a second system of light emission drive signal output means, each of which outputs a light emission drive signal corresponding to the supplied light emission drive data to the connected light emission means to execute the light emission operation of the light emission means;
Effect control means for supplying serial data including the light emission drive data to the light emission drive signal output means of the first system and the second system;
Have
Each light emission drive signal output means of the first system and the second system includes a plurality of driver circuits each outputting a drive signal to one or a plurality of light emission means, and each driver circuit in one system includes The serial data from the production control means is configured to be transmitted in parallel.
The production control means
A slave address that specifies a driver circuit that acquires light emission drive data, a data setting start register address that specifies the head of a register for capturing light emission drive data in the driver circuit, and a register that is set after the data setting start register address Each light emission drive data that designates the light emission mode of the light emitting means is sequentially output one transmission unit at a time,
Each driver circuit specified by the slave address acquires each light emission drive data in a register after the register specified by the data setting start register address.
A gaming machine characterized by that .

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