JP4721851B2 - Circuit board and circuit board manufacturing method - Google Patents

Description

  The present invention relates to a circuit board, and more particularly to a circuit board using an insulating layer containing a particulate filler.

  2. Description of the Related Art In recent years, circuit devices included in electronic devices and the like have increased in heat generation density per unit volume in order to reduce size, increase density, and increase functionality. Therefore, in recent years, a metal substrate having high heat dissipation is used as a circuit device substrate, and an IC (Integrated Circuit) or an LSI (Large Scale Integrated Circuit) is used on the metal substrate. Are mounted (for example, refer to Patent Document 1). Conventionally, a structure in which a hybrid IC (Hybrid Integrated Circuit) is formed on a metal substrate is also known. Here, the hybrid IC means a circuit device in which circuit elements such as an IC chip, a capacitor, and a resistor are integrated on one substrate.

FIG. 4 is a cross-sectional view schematically showing the structure of the conventional circuit device disclosed in Patent Document 1. Referring to FIG. 4, in a conventional circuit device, a resin layer 102 which functions as an insulating layer and is added with silica (SiO ₂ ) as a filler is formed on a metal substrate 101 made of aluminum. . An IC chip 104 is attached to a predetermined region on the resin layer 102 via an adhesive layer 103 made of resin. A metal wiring 105 made of copper is formed via an adhesive layer 103 in a region on the resin layer 102 that is spaced from the end of the IC chip 104 by a predetermined distance. The metal wiring 105 and the metal substrate 101 are insulated by the resin layer 102. The metal wiring 105 and the IC chip 104 are electrically connected by a wire 106.

In the conventional circuit device shown in FIG. 4, a metal substrate 101 made of aluminum is used, and a large amount of heat is generated from the IC chip 104 by mounting the IC chip 104 on the metal substrate 101 via the resin layer 102. Even if this occurs, the heat can be dissipated by the metal substrate 101.
JP-A-8-288605

  Conventionally, thermal conductivity has been increased by filling an insulating layer with a particulate filler such as silica. However, when the filling amount of the filler is large (typically about 70 to 80 Vol%), there is a problem that the thermal conductivity is rapidly increased, but cracks are easily generated on the circuit board including the insulating layer. Further, in the conventional circuit device shown in FIG. 4, when the circuit element generates heat, the temperature of the entire circuit device rises, and the resin layer 102 having a large thermal expansion coefficient tends to expand. For this reason, in the structure in which the resin layer (insulating layer) 102 having a large thermal expansion coefficient is attached on the metal substrate 101 as in the conventional circuit device, there is a problem that the circuit device is deformed due to thermal strain. Depending on the situation, there is a problem that the resin layer (insulating layer) 102 peels from the metal substrate 101.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a circuit board capable of suppressing the occurrence of peeling and cracking of an insulating layer.

  In order to solve the above problems, a circuit board according to an aspect of the present invention includes a substrate, an insulating layer provided on the substrate, and a particulate filler having thermal conductivity filled in the insulating layer, And a conductive layer provided on the insulating layer, the insulating layer having a void inside.

  According to this aspect, when a load is applied to the circuit board, the voids in the insulating layer are deformed, so that the load can be absorbed and relaxed. Generation of cracks at the interface between the material and the insulating layer can be prevented.

  In addition, even when heat is applied to the circuit board, the expansion of the insulating layer due to temperature rise is absorbed and alleviated by the deformation and contraction of the internal voids, so the coefficient of thermal expansion between the wiring layer and the insulating layer Peeling resulting from the difference can be prevented.

  As a result, a highly reliable circuit board can be provided.

  In the above structure, it is desirable that the filler has higher rigidity than the insulating layer, and a plurality of fillers are exposed in the gap. By doing so, when the load is applied to the circuit board or heat is applied, the gap is deformed, so the filler is highly rigid and hard, so the filler exposed in the gap is in contact with each other. And since it can suppress that a space | gap collapses and lose | disappears, deterioration of the buffer function by the space | gap in an insulating layer can be prevented.

  ADVANTAGE OF THE INVENTION According to this invention, the circuit board which can suppress that peeling and a crack of an insulating layer generate | occur | produce can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view showing a configuration of a circuit board 10 according to an embodiment of the present invention. The circuit board 10 includes a first wiring layer 20, an insulating layer 30, a filler 40, a gap 50, a via hole 60, and a second wiring layer 70.

  The first wiring layer 20 and the second wiring layer 70 constitute a part of the multilayer wiring, and each has a predetermined wiring pattern. Although the material of the 1st wiring layer 20 and the 2nd wiring layer 70 is not specifically limited, For example, metals, such as copper (Cu), are suitable.

  The insulating layer 30 is provided between the first wiring layer 20 and the second wiring layer 70. The insulating layer 30 electrically insulates between the first wiring layer 20 and the second wiring layer 70. Examples of the material used for the insulating layer 30 include epoxy resin, melamine derivatives such as BT resin, liquid crystal polymer, PPE resin, polyimide resin, fluororesin, phenol resin, polyamide bismaleimide, and the like. The thickness of the insulating layer 30 is not particularly limited, but is typically 25 to 60 μm. However, the lower limit of the film thickness of the insulating layer 30 needs to be at least larger than the particle size of the filler 40 described later. Further, a filler 40 is added to the insulating layer 30 in order to increase the thermal conductivity of the insulating layer 30.

The filler 40 is made of a particulate inorganic material having good thermal conductivity. Examples of the filler include alumina (Al ₂ O ₃ ), silica (SiO ₂ ), aluminum nitride (AlN), silicon nitride (SiN), and boron nitride (BN). Although the filler 40 of this embodiment is spherical, the filler 40 may be in the form of particles, and may be in the shape of an ellipse, an indeterminate shape, a needle shape, or the like.

  The filling rate (volume filling rate) of the filler 40 in the insulating layer 30 is preferably 50 to 90 Vol%, and more preferably 65 to 75 Vol%. When the filling rate of the filler 40 is less than 50 Vol%, sufficient thermal conductivity cannot be obtained. On the other hand, when the filling rate of the filler 40 is more than 90 Vol%, the insulating layer 30 becomes brittle and durability is impaired. In order to set the filling rate of the filler 40 to 50 to 90 Vol%, it is preferable to mix a group having a relatively large particle size distribution and a group having a relatively small particle size distribution. As a result, the particles having a small particle size enter the gap formed between the particles having a large particle size, whereby the insulating layer 30 can be filled with the filler more densely. For example, by mixing a group A having an average particle size of 0.7 μm and a group B having an average particle size of 3 μm (maximum particle size of 15 μm) at a composition ratio of 1: 4, the filling rate of the filler 40 is set to 70 Vol. %.

  The insulating layer 30 includes the voids 50 in a ratio of about 1 to 20 Vol%, more preferably about 2 Vol%, in terms of a filling rate (volume filling rate). Note that the gap 50 included in the insulating layer 30 must have a ratio (size and amount) that can maintain the mechanical strength of the insulating layer 30. When the ratio of the voids 50 is too large, it becomes impossible to withstand the stress load, the breaking strength of the insulating layer 30 is lowered, and the reliability of the circuit board is lowered. Moreover, it is preferable that a plurality of fillers 40 are provided in the gap 50 of the insulating layer 30 so as to be exposed. In this embodiment, voids having a diameter of about 2 μm are contained in the insulating layer 30 having a silica filler filling rate of 75 Vol% in the epoxy resin at a ratio of about 2%.

  As described above, when the insulating layer 30 including the particulate filler 40 contains the void 50, when a load is applied to the circuit board 10, the void 50 in the insulating layer 30 is deformed. Since absorption and relaxation can be performed, it is possible to prevent crushing of the filler 40 due to a load applied to the circuit board 10 and occurrence of cracks at the interface between the filler 40 and the insulating layer 30.

  Even when heat is applied to the circuit board 10, the expansion of the insulating layer 30 due to the temperature rise is absorbed and alleviated by the deformation and contraction of the voids 50 therein, so that the first wiring layer 20 or Peeling caused by the difference in coefficient of thermal expansion between the second wiring layer 70 and the insulating layer 30 can be prevented.

  Furthermore, when the plurality of fillers 40 are exposed in the gaps 50, when the load 50 is applied to the circuit board 10 or heat is applied and the gaps 50 are deformed, the fillers 40 are more than the insulating layer 30. Since the rigidity (Young's modulus) is high and hard, it is possible to prevent the filler 40 exposed in the gap 50 from contacting each other and the gap 50 from being crushed and disappearing, so that the buffering by the gap 50 in the insulating layer 30 is possible. It is possible to prevent the deterioration of the function. In the present embodiment, even when the temperature of the circuit board 10 is increased to about 100 ° C., no decrease in mechanical strength and no extreme deformation of the voids are observed.

As a result, a highly reliable circuit board can be provided.
(Production method)
2 and 3 show a method for manufacturing the circuit board 10 according to the present embodiment.

  First, as shown in FIG. 2A, a laminated body including the first wiring layer 20, the insulating layer 30, the filler 40, the gap 50, and the copper foil 70a is formed. The first wiring layer 20 can be formed in a predetermined wiring pattern by, for example, a processing method that combines a photolithography method and an etching method.

  Next, a laminated sheet with the insulating layer 30 and the copper foil 70a containing the filler 40 in a predetermined ratio in advance is prepared. Note that the laminated sheet is subjected to a hydrophilic treatment with a silane coupling agent on the surface of the filler 40 in order to prevent the fillers 40 from agglomerating and to easily become compatible with the insulating layer 30 which is an epoxy resin. These are kneaded at a predetermined ratio and applied onto the copper foil 70a. This laminated sheet is affixed on the first wiring layer 20 and cured by pressure bonding at 150 ° C. for 120 minutes. Due to the temperature rise at the time of bonding, a part of the chemical used for the hydrophilic treatment evaporates from the surface of the filler 40 to become a gas, and a void 50 is generated in the insulating layer 30. Since the void 50 is formed by vaporizing from the surface of the filler 40, the void 50 is easily formed in the state where the filler 40 is exposed.

  Here, the gas generated from the filler is not limited to the gas that has been vaporized by the chemical used in the hydrophilization treatment, but may be any gas that does not change the characteristics of the insulating layer 30 as long as it vaporizes at the crimping temperature. Under the processing conditions of this embodiment, the filler 40 may be preliminarily absorbed with an appropriate amount of moisture.

  Next, as shown in FIG. 2B, in combination with the photolithography method and the etching method, the copper foil 70a located on the formation region of the via hole 60 described later is removed. Thereby, the formation region of the via hole 60 in the insulating layer 30 is exposed.

  Next, as shown in FIG. 2C, a first position is irradiated from the exposed surface of the insulating layer 30 by irradiating a predetermined position with a UV laser (wavelength 355 nm, pulse width 15 nsec) from above the copper foil 70a. The region up to the surface of the wiring layer 20 is removed. As a result, a via hole 60 having a diameter of about 70 μm is opened in the insulating layer 30. It is preferable that the pulse energy and energy density of the laser in the UV laser irradiation are adjusted so that the resin constituting the insulating layer 30 is processed while the filler 40 is hardly processed.

  Next, as shown in FIG. 3, a copper thin film having a thickness of about 0.5 μm is deposited on the upper surface of the copper foil 70 a and the inner surface of the via hole 60 by electroless copper plating using palladium as a catalyst. Subsequently, a copper film with a thickness of about 15 μm is plated on the upper surface of the copper foil 70 a and the inside of the via hole 60 by an electrolytic plating process using a copper sulfate solution as a plating solution. As a result, the second wiring layer 70 made of copper is formed.

  Next, as shown in FIG. 1, the second wiring layer 70 is processed into a predetermined wiring pattern by a processing method combining a photolithography method and an etching method.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

  For example, in the above-described embodiment, the example in which the present invention is applied to the circuit board having the two-layer structure in which the insulating layer and the second wiring layer are sequentially formed on the first wiring layer has been described. Not limited to this, the present invention can also be applied to a circuit board having a three-layer structure in which an insulating layer and a third wiring layer are sequentially formed on the second wiring layer. Further, the present invention can be applied to a circuit board having a multilayer structure of four layers or more.

  Moreover, although the example applied to the insulating layer between wiring layers was demonstrated in the said embodiment, it is applicable also to the insulating layer between board | substrates, such as a metal substrate, and a wiring layer.

It is sectional drawing which shows the structure of the circuit board which concerns on embodiment. It is process sectional drawing which shows the manufacturing method of the circuit board which concerns on embodiment. It is process sectional drawing which shows the manufacturing method of the circuit board which concerns on embodiment. It is sectional drawing which showed the structure of the conventional circuit device roughly.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Circuit board 20 1st wiring layer 30 Insulating layer 40 Particulate filler 50 Void 60 Via hole 70 2nd wiring layer

Claims (4)

A first wiring layer or substrate ;
An insulating layer provided on the first wiring layer or substrate ;
A particulate filler having thermal conductivity filled in the insulating layer;
A second wiring layer provided on the insulating layer;
With
The filler is higher in rigidity than the insulating material constituting the insulating layer,
Has voids inside of the insulating layer Waso is exposed a plurality of the filler in the gap,
The circuit board , wherein the plurality of fillers exposed in the gap are arranged so that the fillers come into contact with each other when the gap is about to deform . A method for manufacturing a circuit board comprising a first wiring layer or substrate, an insulating layer, and a second wiring layer,
A first step of pressure-bonding a laminated sheet with an insulating layer and a copper foil filled with a particulate filler having thermal conductivity on the first wiring layer or the substrate;
A second step of patterning the copper foil to form a second wiring layer;
Have
The surface of the filler is subjected to a hydrophilic treatment,
In the first step, a void is formed in the insulating layer by pressure bonding at a temperature at which the chemical used in the hydrophilic treatment is vaporized. A method for manufacturing a circuit board comprising a first wiring layer or substrate, an insulating layer, and a second wiring layer,
A first step of pressure-bonding a laminated sheet with an insulating layer and a copper foil filled with a particulate filler having thermal conductivity on the first wiring layer or the substrate;
A second step of patterning the copper foil to form a second wiring layer;
Have
The filler is treated to absorb moisture,
In the first step, a void is formed in the insulating layer by pressure bonding at a temperature at which the water vaporizes. The method for manufacturing a circuit board according to claim 2, wherein the filler has higher rigidity than an insulating material constituting the insulating layer, and the filler is exposed in the gap.

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