JP4718784B2 - Semiconductor element peeling method and semiconductor device manufacturing method - Google Patents

Description

  The present invention relates to a method for peeling a semiconductor element formed over an insulating surface and a method for manufacturing a semiconductor device using the peeling method.

  In addition to flat panel displays for displaying images, portable electronic devices typified by mobile phones and electronic notebooks are required to have various functions such as sending and receiving mail, voice recognition, and video capture with a small camera. On the other hand, user needs for downsizing and weight reduction are still strong. Therefore, it is necessary to mount more ICs having a larger circuit scale and memory capacity in the limited volume of portable electronic devices. In order to secure a space for accommodating an IC and to reduce the size and weight of a portable electronic device, it is important to make a flat panel display to be mounted thin and light. In order to reduce the thickness and weight, it is considered most effective to reduce the thickness of the glass substrate used in the panel. However, considering the mechanical strength of the panel, the glass substrate should be made thinner and thinner. I can't. For example, when barium borosilicate glass, alumino borosilicate glass, or the like is used, the thickness of a 3-inch square panel is limited to about 1 to 2 mm at most and about 10 g in weight.

  Due to the above problems, research and development of flat panel displays using a plastic substrate instead of a glass substrate have been actively conducted. Since the plastic substrate is flexible, the plastic substrate is superior in mechanical strength against vibration and impact compared to the glass substrate, and the thickness can be easily suppressed. In addition, since the material itself is lightweight, it is considered to be a convenient substrate for making the flat panel display thinner and lighter. However, the plastic substrate is often not excellent in heat resistance to withstand heat treatment in the manufacturing process of the semiconductor element. Therefore, a manufacturing method has been proposed in which a semiconductor element is formed over a separately prepared heat-resistant substrate, and then the semiconductor element is peeled off from the substrate and bonded to a plastic substrate. The specific methods of peeling that are proposed vary from manufacturer to manufacturer, and each has its own technical ingenuity.

  In Patent Document 1 below, a porous GaN film having a large number of fine voids (voids) on the surface is formed on a substrate by photoetching, and then a GaN epifilm is formed on the porous GaN film by epitaxial growth. Next, the GaN layer having voids is removed by selective etching, ultra-high pressure water flow, GaAs jet, laser cleaving, etc., and the epi film is peeled off from the substrate and bonded to another substrate. A manufacturing method is disclosed.

JP 2001-223165 A

  In the case of a peeling method in which a void is formed between a substrate and a semiconductor film before the formation of the semiconductor film as in Patent Document 1, the semiconductor film itself is heated for the purpose of promoting the peeling after the formation of the semiconductor film. Since there is no need to separately perform processing, laser light irradiation, or the like, there is an advantage that the semiconductor film is not damaged. Further, the internal stress of the semiconductor film can be relieved by the presence of the void.

  However, in Patent Document 1 above, since voids are formed by photoetching, there is a limit to the size of voids that can be obtained. Therefore, for the purpose of suppressing the time taken for dissolution and fracture of the layer in which the void is formed, or for reducing the burden such as stress applied to the semiconductor film at the time of peeling, the void is fixed to some extent. It cannot be optimized beyond the size of. In addition, the above Patent Document 1 describes a method for peeling a single crystal semiconductor film, but a specific example of peeling a semiconductor element formed using a thin semiconductor film on an insulating surface using a void. No method is disclosed.

  In view of the above problems, an object of the present invention is to propose a peeling method for peeling a thin film semiconductor element over an insulating surface using a void and a method for manufacturing a semiconductor device for transferring the peeled semiconductor element.

  In the present invention, a first base film having unevenness is formed on a substrate, and a second base film is formed on the first base film. Then, the shape of the concave portion of the first base film is controlled so that a void is formed in the second base film at least on the concave portion. As the opening of the recess becomes narrower and deeper, voids are more easily formed, and the volume ratio of the void in the recess increases.

  In addition to the shape of the recess, the shape and volume of the void to be formed also depend on the method for forming the second base film. The better the step coverage (step coverage) of the insulating film to be deposited, the lower the ratio of voids to the concaves, and the lower the step coverage, the higher the percentage of voids to the concaves. . Specifically, for the second base film having voids, a sputtering method, a coating method, a CVD method, or the like can be used depending on conditions.

  A method for forming a second base film having voids will be described with reference to FIG. First, as shown in FIG. 1A, a first base film 100 having unevenness is formed. A method of forming the unevenness of the first base film will be described later in the embodiment. The portion indicated by 100a corresponds to a concave portion, and the portion indicated by 100b corresponds to a convex portion. Then, when the second base film 101 is formed by using, for example, a sputtering method, at the initial stage of film formation, as shown in FIG. 1A, on the convex portion 100b that is relatively horizontal and on the bottom portion of the concave portion 100a. In addition, the second base film 101 is preferentially formed.

  When the second base film 101 is further formed from the state shown in FIG. 1A, the state shown in FIG. 1B is obtained. As shown in FIG. 1B, the second base film 101 is formed thicker in the vicinity of the edge 102 of the convex portion 100b than the other portions. This is because when the molecules constituting the second base film 101 adhere to the surface to be formed, the molecules are likely to gather in the vicinity of the edge 102 of the convex portion 100b as a result of moving the surface in search of a stable site.

  Further, when the second base film is continuously formed, the film formation speed of the second base film 101 inside the recess 100a is slower than the film formation speed in the vicinity of the edge 102, so that FIG. As described above, the thickly deposited portion in the vicinity of the edge 102 further grows and eventually covers the recess 100a. A void 103 is formed in the second base film 101 on the recess 100a.

  The shape and volume of the void 103 depend on the shape of the recess 100a and the film forming method. For example, it is assumed that FIG. 1C corresponds to a cross-sectional view taken along line A-A ′ of the top view of the substrate illustrated in FIG. In FIG. 1D, the concave portion 100a extends in one direction in a stripe shape. In this case, the void 103 is formed so as to extend along the longitudinal direction of the stripe of the concave portion 100a.

  A thin semiconductor film is formed over the second base film 101 formed in this manner, and after forming a semiconductor element, the region including the void 103 of the second base film 101 is dissolved and pulverized. Thus, the semiconductor element is peeled off and transferred onto a separately prepared substrate. At this time, the separation may be performed by simply applying a physical force, or may be performed by performing a process such as selective etching, ultra-high pressure water flow or laser pulverization. In the present invention, peeling using a void may be performed by wet etching. In this case, a thin semiconductor film is formed over the second base film 101 formed as shown in FIG. 1, and after forming a semiconductor element, an opening reaching a part of the void 103 is formed. Then, the inner wall of the void is etched and spread by diffusing the etchant into the void 103 from the opening. Finally, the semiconductor element is peeled off by separating the second base film 101 from the surface intersecting with the plurality of voids 103, and the peeled semiconductor element is transferred onto a separately prepared substrate. At this time, peeling may be performed only by etching, or may be performed by applying a physical force after etching.

  Peeling does not require direct irradiation of the semiconductor element with a laser or heat treatment that affects the characteristics of the semiconductor element, so that damage to the semiconductor film can be suppressed. Further, the presence of voids can relieve internal stress of the second base film and the semiconductor film, and can suppress stress migration in the manufacturing process of the semiconductor element.

  In the present invention, by using an uneven insulating film, the size, shape, and layout of voids can be easily optimized, and the physical force required for peeling or the processing time for promoting peeling can be suppressed. As a result, it is possible to reduce the burden on the semiconductor element at the time of peeling. Further, in the present invention, by using an uneven insulating film, it is easy to optimize the size, shape, and layout of voids in a form suitable for etching, and the processing time for promoting peeling can be suppressed. Can reduce the physical force required. As a result, it is possible to reduce a burden on the semiconductor element at the time of peeling.

  As described above, in the present invention, by using an uneven insulating film, it is easy to optimize the size, shape, and layout of voids, and the physical force required for peeling, or the processing time for promoting peeling. As a result, it is possible to reduce the burden on the semiconductor element at the time of peeling. Further, in the present invention, the size, shape and layout of the voids can be easily optimized by using the uneven insulating film. Therefore, the etchant can be efficiently diffused into the void, and the area of the inner wall of the void in contact with the etchant can be increased, so that the etching processing time can be shortened. In the case where the semiconductor element is peeled off by a physical force after etching, the physical force necessary for the peeling can be suppressed. Therefore, as a result, the burden on the semiconductor element at the time of peeling can be reduced. In the present invention, peeling does not require direct irradiation of the semiconductor element with a laser or heat treatment that affects the characteristics of the semiconductor element, so that damage to the semiconductor film can be suppressed. Further, the presence of voids can relieve internal stress of the second base film and the semiconductor film, and can suppress stress migration in the manufacturing process of the semiconductor element.

(Embodiment 1)
Hereinafter, a method for manufacturing a semiconductor device using the peeling method of the present invention will be described.

  First, as shown in FIG. 2A, a first base film 201 having unevenness is formed over a first substrate 200. The first substrate 200 may be any material that can withstand the processing temperature of the subsequent process. For example, a quartz substrate, a silicon substrate, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a metal substrate, a stainless steel substrate, or the like may be used. Can be used.

  In this embodiment, a silicon oxide film is used as the first base film 201. Note that the material of the first base film 201 is not limited thereto, and may be an insulating film such as silicon nitride or silicon nitride oxide, or a metal film such as W or Mo. The method of forming the unevenness will be described in detail later. The first base film 201 is not limited to a single layer, and may have a stacked structure of two or more layers. In this case, all the layers may be an insulating film or a metal film. Alternatively, a stacked structure of an insulating film and a metal film may be used.

  The shape of the unevenness can be determined as appropriate by the designer in consideration of the film forming method and the peeling method. In the present embodiment, the recess 203 has a stripe shape, the width Wd in the direction perpendicular to the longitudinal direction is 1 μm or less, and the depth Wh is 2 μm or more.

  Next, as shown in FIG. 2B, a second base film 202 is formed so as to cover the first base film 201. The second base film 202 can be formed by a sputtering method, a coating method, a plasma CVD method, or the like. Note that the deposition method is not limited to these, and other known deposition methods can be used as long as voids can be formed in the second base film 202. The second base film 202 is preferably an insulating film, and specifically, silicon oxide, silicon nitride, silicon nitride oxide, and other known insulating films can be used. As the second base film 202, an insulating film including a Si—O bond and a Si—CHx bond formed using a siloxane-based material as a starting material may be used. In this embodiment, silicon oxide is formed as the second base film 202 by an RF sputtering method.

In this embodiment mode, film formation is performed in an Ar atmosphere with an RF power of 3 kW and a pressure of 0.4 Pa using a substrate temperature of 100 to 200 ° C., for example, 150 ° C., using a SiO ₂ target having a diameter of 305 mm. The total flow rate of Ar is 60 sccm, of which 10 sccm is heated to raise the temperature and sprayed to the back side of the substrate to suppress changes in the substrate temperature. The deposition rate is 68 to 72 nm / min.

  The second base film 202 is formed until the void 207 is formed by closing the opening in the recess 203. Therefore, it is desirable that the film thickness is appropriately determined depending on the shape of the recess 203 and the film forming method. In this embodiment mode, the film is formed so that the film thickness of the first base film 201 on the convex portion 204 is about 1 μm.

  Note that the surface of the second base film 202 immediately after the film formation may lack some flatness due to the unevenness of the first base film 201. Therefore, the surface of the second base film 202 may be polished in order to avoid affecting the characteristics of a semiconductor element to be formed later. In this embodiment mode, the surface of the second base film 202 is polished by using a CMP (Chemical-Mechanical Polishing) method, a so-called chemical / mechanical polishing method. The CMP method can be performed by a known method. In polishing an oxide film, a solid-liquid dispersion slurry in which an abrasive having a diameter of 100 to 1000 nm is generally dispersed in an aqueous solution containing a reagent such as a pH adjuster is used. In this embodiment, a silica slurry (pH = 10 to 11) in which 20 wt% of fumed silica particles obtained by thermally decomposing silicon chloride gas is used in an aqueous solution to which potassium hydroxide is added. Note that the polishing of the surface of the second base film 202 is not limited to the CMP method, and other polishing methods may be used as long as flatness can be ensured. By polishing the surface, the surface of the second base film 202 is planarized as shown in FIG.

  Next, a third base film 205 made of an insulating film is formed over the planarized second base film 202, and a semiconductor element 206, here, a TFT is formed over the third base film 205. (FIG. 2 (D)). The third base film 205 is a film having an etching rate relatively slower than that of the second base film 202. Thus, the semiconductor element 206 can be protected by the third base film 205 when peeling is performed on a portion of the second base film 202 including the void. Further, the semiconductor element 206 to be peeled is preferably covered and protected with an interlayer insulating film or the like.

  Next, the protective layer 212 is formed so as to cover the semiconductor element 206. The protective layer 212 has a function of protecting the semiconductor element 206 when the second substrate 209 is bonded or peeled later, and can be removed after the second substrate 209 is peeled off. Is used. For example, the protective layer 212 can be formed by applying an epoxy-based, acrylate-based, or silicon-based resin soluble in water or alcohol over the entire surface and baking it. In this embodiment, a water-soluble resin (manufactured by Toagosei Co., Ltd .: VL-WSHL10) is applied by spin coating so as to have a film thickness of 30 μm, and after exposure for 2 minutes for temporary curing, UV light is applied from the back surface Exposure is performed for 2.5 minutes and 10 minutes from the surface for a total of 12.5 minutes, followed by main curing to form the protective layer 212 (FIG. 3A).

In addition, when laminating | stacking several organic resin, there exists a possibility that it may melt | dissolve partially at the time of application | coating or baking with the solvent currently used between organic resins, or adhesiveness may become high too much. Therefore, in the case where an organic resin that is soluble in the same solvent is used for both the interlayer insulating film covering the semiconductor element 206 and the protective layer 212, the semiconductor element 206 is removed smoothly in the subsequent process. An inorganic insulating film (SiN _x film, SiN _x O _y film, AlN _x film, or AlN _x O _y film) is formed between the interlayer insulating film covering the film and the protective layer 212 formed later. It is preferable to keep it.

  Next, the second substrate 209 is attached to the protective layer 212 using the double-sided tape 208, and the third substrate 211 is attached to the first substrate 200 using the double-sided tape 210 (FIG. 3A). Note that it is not always necessary to use the double-sided tapes 208 and 210 for attachment. Any material having a function of attaching the second substrate 209 or the third substrate 211 may be used. For example, an adhesive may be used. By using an adhesive that is peeled off by ultraviolet rays, the burden on the semiconductor element can be reduced when the second substrate 209 is peeled off. By attaching the third substrate 211, the first substrate 200 can be prevented from being damaged in a later peeling step. As the second substrate 209 and the third substrate 211, it is preferable to use a substrate having a higher rigidity than the first substrate 200, such as a quartz substrate or a semiconductor substrate.

  Note that the thickness of the protective layer 212 may be increased so that the second substrate 209 is not attached. Further, the third substrate 211 is not necessarily provided as long as the first substrate 200 has rigidity enough to withstand peeling.

  Next, processing that triggers the start of peeling is performed so that the second base film 202 is partially separated into the first substrate 200 side and the second substrate 209 side in the void 207. Specifically, the void 207 is formed by damaging the exposed portion of the substrate end surface of the second base film 202 by locally applying pressure from the outside along the periphery of the region to be peeled. Speak. In the present embodiment, a hard needle such as a diamond pen is pressed perpendicularly to the vicinity of the end of the second base film 202 and moved along the second base film 202 with a load applied as it is. Preferably, a scriber device is used, the pushing amount is set to 0.1 mm to 2 mm, and the pressure is applied. In this way, by forming a portion with reduced adhesion that triggers the start of peeling before peeling, defects in the subsequent peeling step can be reduced, leading to improved yield. .

  Next, the second base film 202 is physically peeled so that the void 207 is peeled off from the first substrate 200 side and the second substrate 209 side (FIG. 3B). Peeling starts from the part that has been treated in the previous step and that triggers the start of peeling. By this peeling, the second base film 202 is peeled off from the first substrate 200 side and the second substrate 209 side at the surface intersecting with the void 207, and a part of the first base film 201 is also In some cases, the first substrate 200 side and the second substrate 209 side are separated. Then, the semiconductor element 206 is provided on the second substrate 209 side, the first substrate 200 is provided on the third substrate 211 side, a part of the second base film 202, and in some cases, a part of the first base film 201. The parts are separated from each other while being attached.

  The peeling can be performed by, for example, the wind pressure of a gas blown from a nozzle, ultrasonic waves, or the like. Alternatively, the void 207 may be peeled off by pulverizing the void 207 from the end face of the substrate by laser irradiation, water flow or other liquid jetting, or may be peeled off by expanding the void 207 by etching. Which method is used can be appropriately selected by the designer, but it is desirable to determine a peeling method according to the material so that the protective layer 212 is not dissolved.

  Note that after the peeling, a part of the second base film 202 peeled to the second substrate 209 side or a part of the first base film 201 in addition to that is removed to some extent or completely by etching. (FIG. 3C).

  Next, the semiconductor element 206 is bonded to a substrate (element substrate) 214 to which the semiconductor element is finally transferred with an adhesive 213. Specifically, the semiconductor element 206 is bonded to the element substrate 214 by adhering the surface that appears after peeling to the element substrate 214 (FIG. 4A). At the time of bonding, the adhesive force between the element substrate 214 and the semiconductor element 206 by the adhesive 213 is made higher than the adhesive force between the second substrate 209 and the protective layer 212 by the double-sided tape 208. It is important to select the material of the adhesive 213 so that it can.

  Examples of the adhesive 213 include various curable adhesives such as a reactive curable adhesive, a thermosetting adhesive, a photocurable adhesive such as an ultraviolet curable adhesive, and an anaerobic adhesive. More preferably, it is preferable that the adhesive 213 has high thermal conductivity by including powder or filler made of silver, nickel, aluminum, aluminum nitride.

  In this embodiment mode, a plastic substrate is used as the element substrate 214. Although it is effective to use a plastic substrate if emphasis is placed on making the semiconductor device thinner and lighter, the element substrate used in the present invention is not limited to this. As the element substrate, an interposer using glass epoxy or a substrate using other materials can be used.

  As the plastic substrate, ARTON: JSR made of norbornene resin with a polar group can be used. Polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), nylon, polyetheretherketone (PEEK), polysulfone (PSF), polyetherimide (PEI), poly A plastic substrate such as arylate (PAR), polybutylene terephthalate (PBT), or polyimide can be used.

  Next, as shown in FIG. 4A, the double-sided tape 208 and the second substrate 209 are peeled from the protective layer 212 in order or simultaneously. In addition, by using an ultraviolet curable adhesive as the adhesive 213 and using a tape or adhesive that is peeled off by ultraviolet rays as the double-sided tape 208, the double-sided tape 208 is peeled off and the adhesive 213 is simultaneously cured by a single UV irradiation. Can be done.

Then, as shown in FIG. 4B, the protective layer 212 is removed. Here, since a water-soluble resin is used for the protective layer 212, it is dissolved in water and removed. In the case where the protective layer 212 is left as a cause of failure, it is preferable to perform a cleaning process or an O ₂ plasma process on the surface after the removal to remove a part of the remaining protective layer 212.

  The semiconductor element can be transferred by the above steps. Note that in the case of stacking a second-layer semiconductor element for the purpose of making the integrated circuit three-dimensional, the transfer may be performed in the same manner as the first-layer semiconductor element. The distance between the layers can be controlled by adjusting the thickness of the adhesive used for bonding between the layers. The thickness of the adhesive depends on the pressure at the time of bonding, but it can be thin and bonded at about several μm.

  Note that in the case where a display device is formed by transfer, the display element is manufactured after transfer. Specifically, in the case of a liquid crystal display device, for example, a pixel electrode of a liquid crystal cell electrically connected to a TFT, which is one of semiconductor elements, and an alignment film covering the pixel electrode are manufactured, and then transferred. Then, a counter substrate prepared separately is bonded and liquid crystal is injected to complete. Examples of the display device included in the semiconductor device of the present invention include a liquid crystal display device, a light emitting device including a light emitting element typified by an organic light emitting element (electroluminescence element) in each pixel, and a DMD (Digital Micromirror Device). For example. The integrated circuit included in the semiconductor device of the present invention includes a microprocessor (CPU), a memory, a power supply circuit, and other digital circuits and analog circuits.

  Note that the transfer procedure of the semiconductor element peeled using the peeling method described above is not limited to the above-described configuration.

  Further, in the present invention, the semiconductor element may be peeled off at the void by using wet etching.

  In this case, a silicon oxide film is used as the first base film 201. Note that the material of the first base film 201 is not limited thereto, and an insulating film such as silicon nitride or silicon nitride oxide is desirable. Further, the first base film 201 is not limited to a single layer, and may have a stacked structure of two or more layers. The shape of the unevenness can be appropriately determined by the designer depending on the balance between the film forming method and the etching conditions at the time of peeling. In the present embodiment, the recess 203 has a stripe shape, the width Wd in the direction perpendicular to the longitudinal direction is 1 μm or less, and the depth Wh is 2 μm or more. Then, the protective layer 212 is applied so as not to cover a region where an opening is to be formed later.

  When wet etching is used, an opening 230 that reaches part of the void 207 is formed, and the protective layer 212 is formed to cover the semiconductor element 206. FIG. 5A shows a top view of the opening 230 at the time when the opening 230 is formed, and a cross-sectional view taken along A-A ′ of the top view. Note that FIG. 5A shows only the layout 231 of the active layer included in the semiconductor element 206. The opening 230 is formed to have a depth that reaches a part of the void 207. The opening 230 is formed avoiding the region where the semiconductor element 206 is formed. Note that the formation of the opening is not limited to the timing shown in this embodiment mode. The opening may be formed before the protective layer 212 is formed or before the second substrate 209 or the third substrate 211 is attached. Alternatively, the opening may be formed in the manufacturing process of the semiconductor element.

  Then, the inner wall of the void 207 is etched by diffusing the etchant from the opening 230 into the void 207. Finally, the second base film 202 is formed in the void 207 on the first substrate 200 side, Peeling is performed on the second substrate 209 side (FIG. 6A). By this peeling, the second base film 202 is peeled off on the first substrate 200 side and the second substrate 209 side at the surface intersecting with the void 207, and depending on the type of insulating film used, the first base film In some cases, 201 may be separated from the first substrate 200 side and the second substrate 209 side. 6B, after peeling, a part of the second base film 202 peeled to the second substrate 209 side or a part of the first base film 201 in addition thereto is etched. It may be removed to some extent or completely.

In this embodiment, as an etchant, a mixed solution containing 7.13% ammonium hydrogen fluoride (NH ₄ HF ₂ ) and 15.4% ammonium fluoride (NH ₄ F) (trade name, manufactured by Stella Chemifa Corporation) Wet etching is performed at 20 ° C. using LAL500). Note that the etching conditions are not limited to this, and the designer can appropriately select them.

  Note that although an example in which the peeling process is completely performed only by etching is described in this embodiment mode, peeling may be performed by applying a physical force after etching. The physical force can be performed by, for example, wind pressure of a gas blown from a nozzle, ultrasonic waves, or the like. Further, the void 207 may be peeled off by pulverizing the end face of the substrate by laser irradiation, water flow or other liquid jet.

  A specific transfer method of the light emitting device will be described with reference to FIG. It is desirable to transfer the light emitting device before forming the electroluminescent layer. In this embodiment mode, a case where transfer is performed after forming a pixel electrode and before forming an organic resin film used as a partition between pixels will be described as an example.

  FIG. 7A corresponds to a cross-sectional view of a pixel at the time when transfer is completed. Reference numeral 501 corresponds to a TFT used in a driving circuit, and 502 corresponds to a TFT for controlling supply of current to the light emitting element. A pixel electrode 503 of the light emitting element is electrically connected to the TFT 502. In the present embodiment, the pixel electrode 503 is formed of a transparent conductive film, for example, ITO. Note that although a transparent conductive film is used for the pixel electrode of the light-emitting element in this embodiment mode, the present invention is not limited to this. It is desirable to appropriately optimize the configuration of the light emitting element depending on whether the light from the light emitting element is directed toward the element substrate or in the opposite direction.

  Next, after the transfer is finished, as shown in FIG. 7B, a partition wall 504 having an opening so as to partially expose the pixel electrode 503 is formed. In this embodiment, the partition 504 is formed using an organic resin film. Then, an electroluminescent layer 505 and a cathode 506 are stacked so as to overlap with the pixel electrode 503 in the opening of the partition wall 504. A portion where the pixel electrode 503, the electroluminescent layer 505, and the cathode 506 overlap corresponds to the light emitting element 507.

  Note that the transparent conductive film used as the pixel electrode 503 may be a transparent conductive film in which indium oxide is mixed with 2 to 20% zinc oxide (ZnO) in addition to ITO. The pixel electrode 503 may be polished by wiping using a CMP method or a polyvinyl alcohol-based porous material so that the surface thereof is planarized. Further, after polishing using the CMP method, the surface of the pixel electrode 503 may be subjected to ultraviolet irradiation, oxygen plasma treatment, or the like. The electroluminescent layer 505 has a configuration in which a light emitting layer alone or a plurality of layers including a light emitting layer are stacked. For the cathode 506, other known materials can be used as long as the conductive film has a low work function. For example, Ca, Al, CaF, MgAg, AlLi, etc. are desirable.

Note that the partition 504 is preferably heated in a vacuum atmosphere before the electroluminescent layer 505 is formed in order to remove adsorbed moisture, oxygen, and the like. Specifically, heat treatment is performed in a vacuum atmosphere at 100 ° C. to 200 ° C. for about 0.5 to 1 hour. It is desirably 3 × 10 ⁻⁷ Torr or less, and if possible, 3 × 10 ⁻⁸ Torr or less is most desirable. In the case where the electroluminescent layer 505 is formed after the partition wall 504 is subjected to heat treatment in a vacuum atmosphere, reliability can be further improved by maintaining the vacuum emission atmosphere immediately before the film formation.

  In addition, the opening of the partition wall 504 from which the pixel electrode 503 is exposed is preferably rounded at the end. Since the end of the opening is rounded, it is possible to prevent the electroluminescent layer 505 from becoming extremely thin at the end and preventing a hole from being formed, and the pixel electrode 503 and the cathode 506 are short-circuited. Defects of the light emitting element 507 can be suppressed as much as possible. In addition, by relaxing the stress of the electroluminescent layer 505 at the end portion, defects called shrinkage in which a light emitting region is reduced can be reduced, and reliability can be improved. Specifically, it is desirable that the radius of curvature of the curve drawn by the cross section of the organic resin film in the opening is about 0.2 to 2 μm.

  In order to prevent a substance that causes deterioration of the light emitting element 507 such as moisture or oxygen from entering the light emitting element 507, the light emitting element 507 is covered with a protective film 508. Typically, for example, a DLC film, a carbon nitride film, a silicon nitride film formed by an RF sputtering method, or the like is preferably used as the protective film 508. The protective film 508 can be formed by stacking the above-described film that does not easily transmit a substance such as moisture or oxygen and a film that easily allows a substance such as moisture or oxygen to pass therethrough.

  After the protective film 508 is formed, the light emitting element 507 may be covered with a resin to which a desiccant is added in order to further ensure sealing of the light emitting element. Note that a semiconductor element to be transferred later may be bonded with a resin to which the desiccant is added.

  As described above, in the present invention, by using an uneven insulating film, it is easy to optimize the size, shape, and layout of voids, and the physical force required for peeling, or the processing time for promoting peeling. As a result, it is possible to reduce the burden on the semiconductor element at the time of peeling. Further, in the present invention, the size, shape and layout of the voids can be easily optimized by using the uneven insulating film. Therefore, the etchant can be efficiently diffused into the void, and the area of the inner wall of the void in contact with the etchant can be increased, so that the etching processing time can be shortened. In the case where the semiconductor element is peeled off by a physical force after etching, the physical force necessary for the peeling can be suppressed. Therefore, as a result, the burden on the semiconductor element at the time of peeling can be reduced. In the present invention, peeling does not require direct irradiation of the semiconductor element with a laser or heat treatment that affects the characteristics of the semiconductor element, so that damage to the semiconductor film can be suppressed. Further, the presence of voids can relieve internal stress of the second base film and the semiconductor film, and can suppress stress migration in the manufacturing process of the semiconductor element.

(Embodiment 2)
In this embodiment, a method for manufacturing a first base film having an unevenness using an insulating film is described. Note that the manufacturing method and its structure shown in this embodiment mode are merely examples, and the first base film used in the present invention is not limited to this.

First, as shown in FIG. 8A, a first insulating film 602 is formed over a first substrate 601. In this embodiment, silicon oxynitride is used for the first insulating film 602; however, the first insulating film 602 is not limited thereto, and may be an insulating film having a high etching selectivity with a second insulating film to be formed later. In this embodiment, the first insulating film 602 is formed using SiH ₄ and N ₂ O by a CVD method so as to have a thickness of 50 to 200 nm. Note that the first insulating film may be a single layer or a structure in which a plurality of insulating films are stacked.

  Next, as illustrated in FIG. 8B, a second insulating film 603 is formed so as to be in contact with the first insulating film 602. Since the second insulating film 603 forms a convex portion by patterning in a later step, it is necessary to set the film thickness in consideration of the depth of the convex portion. In this embodiment, silicon oxide is used for the second insulating film 603 and is formed by a plasma CVD method so as to have a film thickness of 0.5 μm to 3 μm.

Next, a mask 604 is formed as shown in FIG. 8C, and the second insulating film 603 is etched. In this example, a mixed solution (product name: LAL500, manufactured by Stella Chemifa) containing 7.13% ammonium hydrogen fluoride (NH ₄ HF ₂ ) and 15.4% ammonium fluoride (NH ₄ F) was used as an etchant. And wet etching at 20 ° C. By this etching, convex portions 605 are formed. The first insulating film 602 and the convex portion 605 are regarded as a first base film.

  Note that in the case where aluminum nitride, aluminum nitride oxide, or silicon nitride is used as the first insulating film 602 and a silicon oxide film is used as the second insulating film 603, the second insulating film 603 is patterned by an RF sputtering method. It is desirable. Since aluminum nitride, aluminum nitride oxide, or silicon nitride used as the first insulating film 602 has high thermal conductivity, generated heat can be quickly diffused, and deterioration of the TFT can be prevented.

Next, a method of forming a base film different from that in FIG. 8 will be described. First, an insulating film 702 is formed over the first substrate 701 as illustrated in FIG. The insulating film 702 is formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like. In the case of using a silicon oxide film, tetraethyl orthosilicate (TEOS) and O ₂ are mixed by plasma CVD to have a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 ° C., and high frequency (13.56 MHz) power. It can be formed by discharging at a density of 0.5 to 0.8 W / cm ² . In the case of using a silicon oxynitride film, SiH _4, N ₂ O, by forming silicon oxynitride film, or SiH _4, N silicon oxynitride film made from ₂ O, made from NH ₃ by the plasma CVD method It ’s fine. The production conditions in this case are a reaction pressure of 20 to 200 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (60 MHz) power density of 0.1 to 1.0 W / cm ² . Similarly, the silicon nitride film can be formed from SiH ₄ and NH ₃ by plasma CVD.

  Since the insulating film 702 forms a convex portion by patterning in a later step, it is necessary to set the film thickness in consideration of the depth of the convex portion. In the present embodiment, the film thickness is set to 0.5 μm to 3 μm.

Next, as shown in FIG. 9B, a mask 703 is formed by using a photolithography technique. Then, unnecessary portions are removed by etching, and a first base film 704 having a convex portion is formed. For the etching, a dry etching method using a fluorine-based gas may be used, or a wet etching method using a fluorine-based aqueous solution may be used. When the latter method is selected, for example, a mixed solution containing 7.13% ammonium hydrogen fluoride (NH ₄ HF ₂ ) and 15.4% ammonium fluoride (NH ₄ F) (manufactured by Stella Chemifa Corporation, Etching under the trade name LAL500) is preferable.

  Note that although the first base film 704 may be completed in the state illustrated in FIG. 9B, an insulating film may be formed so as to cover the first base film 704 and the first substrate 701. good. This insulating film is intended to cover the exposed portion of the first base film 704. Unlike the second base film to be formed later, the insulating film is thin enough not to form voids and has good step coverage. Form with. Therefore, it is desirable to determine the film thickness in consideration of the depth of the convex portion and the area of the opening. The insulating film can be formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like.

(Embodiment 3)
In this embodiment mode, a peeling method of the present invention in the case where a metal film is used as the first base film will be described.

  First, as illustrated in FIG. 10A, a first base film 801 having unevenness is formed over a first substrate 800. As in the case of using the insulating film described in Embodiment Mode 1, the first substrate 800 may be made of a material that can withstand the processing temperature in a later step. In this embodiment mode, W is used as the first base film 801. In this embodiment, a first base film 801 is obtained by forming a metal film over the first substrate 800 using a sputtering method and performing patterning. The first base film 801 is not limited to a single layer, and may be a stacked structure of two or more metal films.

  The shape of the unevenness can be determined as appropriate by the designer in consideration of the film forming method and the peeling method. In the present embodiment, the concave portion 802 is formed in a stripe shape, the width Wd in the direction perpendicular to the longitudinal direction is 1 μm or less, and the depth Wh is 2 μm or more.

After the first base film 801 is formed, the second base film 803 is formed without being exposed to the air. Here, a silicon oxide film is formed as the second base film 803 by a sputtering method. In this embodiment mode, when the second base film 803 is formed, pre-sputtering is performed in which plasma is generated by blocking the target and the substrate with a shutter as a pre-sputtering step. Pre-sputtering is performed with Ar at a flow rate of 10 sccm and O ₂ at a flow rate of 30 sccm, the temperature of the first substrate 800 being 270 ° C., and the deposition power being 3 kW in a parallel state. By pre-sputtering, a very thin metal oxide film 804 having a thickness of about several nm (here, 3 nm) is formed between the first base film 801 and the second base film 803. The metal oxide film 804 is formed by oxidizing the surface of the first base film 801. Therefore, in this embodiment, the metal oxide film 804 is formed using tungsten oxide.

  Note that although the metal oxide film 804 is formed by pre-sputtering in this embodiment mode, the present invention is not limited to this. For example, oxygen or an inert gas such as Ar may be added to oxygen, and the surface of the first base film 801 may be intentionally oxidized by plasma to form the metal oxide film 804. When the metal oxide film is formed by a method other than pre-sputtering, the film formation method of the second base film 803 is not limited to the sputtering method, and can be formed using a coating method, a plasma CVD method, or the like.

  The second base film 803 is preferably an insulating film, and specifically, silicon oxide, silicon nitride, silicon nitride oxide, and other known insulating films can be used. In this embodiment, silicon oxide is formed as the second base film 803 by a sputtering method. The second base film 803 is formed such that the void 805 is formed by closing the opening in the recess 802. Therefore, it is desirable that the film thickness be appropriately determined depending on the shape of the recess 802 and the film formation method. In this embodiment mode, the first base film 801 is formed so that the film thickness on the convex portion 806 is about 1 μm.

Note that in the case where a sputtering method is used, film formation is also performed on an end surface of the first substrate 800. Therefore, the second base film 803 formed on the end face is subjected to O ₂ ashing or the like in order to prevent the peeling of the second base film 803 from the void 805 at the boundary in the subsequent process. It is preferable that the first substrate 800 is selectively removed or the end portion of the first substrate 800 is cut by dicing or the like.

  Then, as in the case of using the insulating film described in Embodiment Mode 1, a third base film 813 is formed, and a semiconductor element 807, here, a TFT is formed over the third base film 813 (FIG. 10 (C)). However, in this embodiment mode, the metal oxide film 804 is crystallized in order to facilitate subsequent peeling during the manufacturing process of the semiconductor element. By crystallization, the metal oxide film 804 is easily broken at the grain boundaries, and brittleness can be increased. In this embodiment mode, heat treatment is performed at 420 ° C. to 550 ° C. for about 0.5 to 5 hours to perform crystallization. Note that the heat treatment for crystallizing the metal oxide film may be performed before the semiconductor element 807 is formed, or heat treatment performed in the process of forming the semiconductor element may be performed to crystallize the metal oxide film. It may also serve as the process.

  Then, similarly to the case where the insulating film described in Embodiment Mode 1 is used, the protective layer 808 is formed so as to cover the semiconductor element 807. Next, the second substrate 810 is attached to the protective layer 808 using the double-sided tape 809, and the third substrate 812 is attached to the first substrate 800 using the double-sided tape 811. Next, treatment for triggering peeling is performed so that the second base film 803 is partially separated into the first substrate 800 side and the second substrate 810 side in the void 805 or the metal oxide film 804. Then, the second base film 803 is physically peeled off so as to be peeled off from the first substrate 800 side and the second substrate 810 side in the void 805 or the metal oxide film 804 (FIG. 10D). . By this peeling, the semiconductor element 807 is separated while being attached to the second substrate 810 side.

  Thereafter, the semiconductor element can be transferred through the same steps as those in the case where the insulating film described in Embodiment Mode 1 is used.

  Like this embodiment, by making the metal oxide film brittle by crystallization, it is possible to further reduce the physical force required for peeling, or the processing time for promoting peeling, The burden on the semiconductor element can be reduced.

  Note that in this embodiment mode, tungsten is used as the metal film used for the first base film, but the metal film is not limited to this material in the present invention. Any metal-containing material may be used as long as a metal oxide film is formed on the surface and the substrate can be peeled off by crystallizing the metal oxide film. For example, TiN, WN, Mo, etc. can be used. Further, when these alloys are used as metal films, the optimum temperature for the heat treatment during crystallization differs depending on the composition ratio. Therefore, by adjusting the composition ratio, heat treatment can be performed at a temperature that does not interfere with the manufacturing process of the semiconductor element, and options for the process of the semiconductor element are not easily limited.

  In this embodiment, an example of a manufacturing method and a structure of a TFT which is peeled using the peeling method of the present invention will be described.

  First, an island-shaped semiconductor film 901 is formed over a third base film, and a gate insulating film 902, a first conductive film 903, and a second conductive film are sequentially formed so as to cover the island-shaped semiconductor film 901. . Then, by patterning the second conductive film, a first gate electrode 904 that functions as part of the gate electrode is formed. Then, an impurity element imparting one conductivity type is added to the island-shaped semiconductor film 901 using the first gate electrode 904 as a mask. In this embodiment, for example, an n-type impurity element is added. By the addition of the impurity element, a first impurity region 905 is formed in the island-shaped semiconductor film 901 (FIG. 11A).

  Next, an insulating film 906 for forming a sidewall is formed so as to cover the first gate electrode 904 and the first conductive film 903 (FIG. 11B). As the insulating film 906, silicon oxide, silicon nitride, silicon oxynitride, or another insulating film can be used.

  Then, the sidewall 907 made of an insulating film is formed by anisotropically etching the sidewall forming insulating film 906. FIG. 11C shows the shape of the sidewall 907 obtained by etching. In FIG. 11C, the sidewall 907 covers only the sidewall of the first gate electrode 904; however, the sidewall 907 may be formed so as to cover part or all of the upper surface of the first gate electrode 904. The sidewall 907 overlaps only part of the first impurity region 905 with the gate insulating film 902 and the first conductive film 903 interposed therebetween. That is, a part of the island-shaped semiconductor film 901 does not overlap with the sidewall 907. In order to form the source region and the drain region in this region, the first gate electrode 904 and the sidewalls 907 are doped again with the same conductivity type as that in the previous impurity addition step in the island-shaped semiconductor film 901. Is added as a mask. By this impurity addition step, a second impurity region 908 functioning as a source region and a drain region is formed. The concentration of impurities contained in the second impurity region 908 is made higher than the concentration of impurities contained in the first impurity region 905.

  Note that, among the first gate electrode 904 and the sidewall 907, a part 909 of the island-shaped semiconductor film 901 that overlaps only with the sidewall 907 is originally a part of the first impurity region 905; Impurities are added at a concentration lower than that of the impurity region 908. The region indicated by 909 (hereinafter referred to as a third impurity region to be distinguished from the first impurity region) functions as an LDD region.

  Next, the first conductive film 903 is etched using the first gate electrode 904 and the sidewalls 907 as masks, so that a second gate electrode 910 functioning as part of the gate electrode is formed. The second gate electrode 910 overlaps with the third impurity region 909 with the gate insulating film 902 interposed therebetween.

  Note that a semiconductor element to which the peeling method of the present invention can be applied is not limited to the TFT shown in this embodiment. The semiconductor element is not limited to a TFT, and can be applied to any circuit element such as a memory element (memory), a diode, a photoelectric conversion element, a resistance element, a coil, a capacitor element, and an inductor.

  FIG. 12 shows an external view of a display device formed using the peeling method of the present invention. The display device illustrated in FIG. 12 includes a pixel portion 1503 provided with a plurality of pixels, a scanning line driver circuit 1501 for selecting the pixels, and a signal line driver circuit 1502 for supplying a video signal to the selected pixels. . Various signals and power supply potential used for driving the pixel portion 1503, the signal line driver circuit 1502, or the scan line driver circuit 1501 are supplied through the FPC 1504. In this embodiment, a plastic substrate is used as the element substrate 1505 onto which the semiconductor element is transferred. By using a plastic substrate as an element substrate and forming a display device, the mechanical strength of the display device itself can be increased as compared with the case of using a glass substrate, and the thickness and weight can be reduced. it can.

  In this embodiment, an example of the shape of the first base film will be described.

  FIG. 13 is a top view of the first substrate 1100 at the time when the first base film is formed. As shown in FIG. 13, the first base film is divided into a portion 1100a arranged in a stripe shape and a portion 1100b provided so that a plurality of rectangular recesses are arranged. In the portion indicated by 1100a, voids are formed in the concave portions existing between the convex portions. In the portion indicated by 1100b, voids are formed in a plurality of rectangular recesses arranged in a row.

  The volume of the void can be controlled by the width between the convex portions arranged in stripes (in other words, the width of the concave portion) in the portion indicated by 1100a. In addition, the portion indicated by 1100b can be controlled by the width of a plurality of rectangular recesses arranged in a direction perpendicular to the longitudinal direction (in other words, the width of the recess).

  In this embodiment, when peeling is performed in a later step, the portion indicated by 1100a is subjected to a treatment that triggers peeling, and peeling is started from the portion. For this reason, the width of the concave portion of the portion shown in 1100a is made narrower and the volume of the void is made larger than the portion shown in 1100b so that the peeling can be performed relatively easily than the portion shown in 1100b.

  Note that the portion indicated by 1100b is different from the portion indicated by 1100a in that the recess is widely present in the region where the semiconductor element is formed. Therefore, the various solutions used in each process are likely to remain in the recesses in the portion indicated by 1100b rather than the portion indicated by 1100a. Therefore, in order to prevent the solution remaining in the recesses from adversely affecting the subsequent process, the layout is performed so that the recesses of the first base film are completely surrounded by the protrusions in the portion indicated by 1100b. Is desirable.

  The shape of the recess is not limited to the configuration shown in the present invention. The concave portion is not necessarily rectangular, and the effect of the present invention can be obtained even if the void is formed as long as a void is formed.

  Specific film forming conditions for the film formation method of the second base film 202 using the RF sputtering method of Embodiment 1 will be described.

In this embodiment, the substrate temperature is 100 to 200 ° C., for example, 150 ° C., and a film is formed in an Ar atmosphere with an RF power of 3 kW and a pressure of 0.4 Pa using a SiO ₂ target having a diameter of 305 mm. The total flow rate of Ar is 60 sccm, of which 10 sccm is heated to raise the temperature and sprayed to the back side of the substrate to suppress changes in the substrate temperature. The deposition rate is 68 to 72 nm / min.

When the second base film 202 formed under the above-described film formation conditions is peeled off by wet etching, 7.13% of ammonium hydrogen fluoride (NH ₄ HF ₂ ) and ammonium fluoride (NH ₄ ) are used as an etchant. A mixed solution containing 15.4% of F) (manufactured by Stella Chemifa, trade name LAL500) is used. Then, by performing wet etching at 20 ° C., etching can be performed at an etch rate of about 360 nm to 800 nm / min. Note that the etching conditions are not limited to this, and the designer can appropriately select them.

  Note that the film formation conditions described in this embodiment are merely examples, and the film formation conditions of the second base film are not limited thereto.

  In this example, an example of the layout of the first base film and the opening will be described.

  FIG. 14A shows a top view of the first base film 2100 at the time when the first base film is formed. As shown in FIG. 14A, the first base film 2100 is provided so that a plurality of rectangular recesses 2101 are arranged, and voids are formed so as to extend in the longitudinal direction of the recesses 2101. The volume of the voids can be controlled by the width (in other words, the width of the recesses) of the plurality of rectangular recesses 2101 arranged in the direction perpendicular to the longitudinal direction. Note that the number of voids formed in each recess 2101 may be one or more.

  Reference numeral 2102 corresponds to a region where an opening is formed in a later step. A region 2103 corresponds to a region where a semiconductor element is formed in a later step. The region 2102 serving as the opening is preferably laid out so as not to overlap with the region 2103 where the semiconductor element is formed.

  In FIG. 14A, there is only one region 2102 serving as an opening, and the region 2102 overlaps at least partly with the plurality of recesses 2101. Then, the inner wall of the void is exposed at the portion where the region 2102 to be the opening overlaps with the recess 2101 and is immersed in the etchant, so that the etchant is diffused into the void over the region that does not overlap with the region 2102 to be the opening. Can be made.

  Next, an embodiment in which the layout of the opening is different from that in FIG. 14A will be described with reference to FIG. FIG. 14B shows a top view of the first base film 2100 at the time when the first base film is formed. The layout of the first base film 2100 is the same as that in the case of FIG. Reference numerals 2105a and 2105b correspond to regions where openings are formed in a later step. A region indicated by 2104 corresponds to a region where a semiconductor element is formed in a later step. The regions 2105a and 2105b to be the openings are preferably laid out so as not to overlap with the region 2103 where the semiconductor element is formed.

  In FIG. 14B, regions 2105a and 2105b to be openings are laid out with the region 2104 interposed therebetween. In FIG. 14B, the regions 2105 a and 2105 b serving as openings overlap at least partly with the plurality of recesses 2101. Then, by exposing the inner wall of the void at the portion where the regions 2105a and 2105b serving as the opening and the recess 2101 overlap and immersing in the etchant, the inside of the void is spread over the region not overlapping the regions 2105a and 2105b serving as the opening. The etchant can be diffused. By providing two openings in one recess 2101, the etchant in the void can be diffused more efficiently, and the etching processing time can be shortened.

  Note that as can be said in both FIG. 14A and FIG. 14B, the concave portion 2101 of the first base film 2100 overlaps with regions 2103 and 2104 where semiconductor elements are formed. Therefore, various solutions used in each process may remain in the recess. Therefore, in order to prevent the solution remaining in the recesses from adversely affecting the subsequent process, it is desirable to lay out so that the four sides of the recesses of the first base film are completely surrounded by the protrusions.

  The shape of the recess is not limited to the configuration shown in the present invention. The concave portion is not necessarily rectangular, and the effect of the present invention can be obtained even if the void is formed as long as a void is formed.

The void formation method used with the peeling method of this invention. The figure which shows the peeling method of this invention. The figure which shows the peeling method of this invention. The figure which shows the peeling method of this invention. The figure which shows the peeling method of this invention. The figure which shows the peeling method of this invention. 4A and 4B illustrate a method for manufacturing a display device using the peeling method of the present invention. 4A and 4B illustrate a method for manufacturing unevenness using an insulating film. 4A and 4B illustrate a method for manufacturing unevenness using an insulating film. The figure which shows the peeling method of this invention at the time of using a metal film as a 1st base film. 10A and 10B show a manufacturing process of a TFT. 1 is an external view of a display device obtained by transferring a semiconductor element. The figure which shows an example of the layout of an unevenness | corrugation. The figure which shows an example of the layout of an unevenness | corrugation.

Explanation of symbols

100 First base film 100a Concave part 100b Convex part 101 Second base film 102 Near edge 103 Void 200 First substrate 201 First base film 202 Second base film 203 Concave part 204 Convex part 205 Third base film 206 Semiconductor element 207 Void 208 Double-sided tape 209 Second substrate 210 Double-sided tape 211 Third substrate 212 Protective layer 213 Adhesive 214 Element substrate 230 Opening 231 Active layer layout

Claims (21)

Forming a first base film having a plurality of protrusions on the substrate;
Forming a second base film having voids formed between the convex portions by forming an insulating film on the first base film;
Forming a third underlayer on the second underlayer;
After forming a semiconductor element on the third base film,
A method for peeling a semiconductor element, wherein the semiconductor element is peeled from the substrate at a surface intersecting with a plurality of the voids. Forming a first base film made of metal having a plurality of convex portions on a substrate;
A metal oxide film is formed on the surface by oxidizing the surface of the first base film,
Forming a second base film having voids formed between the convex portions by forming an insulating film on the first base film;
Forming a third underlayer on the second underlayer;
To form a semiconductor device on the third base film, after crystallizing the metal oxide film by heat treatment performed when forming the semiconductor element,
Peeling method of a semiconductor device characterized by peeling the semiconductor element bordering a surface intersecting the voids multiple from the substrate. In claim 1 or claim 2 ,
A method for peeling a semiconductor element, comprising polishing the surface of the second base film before forming the third base film. In any one of Claims 1 thru | or 3 ,
The peeling is performed by etching,
A method for peeling a semiconductor element, wherein an etching rate of the third base film is slower than an etching rate of the second base film. In any one of Claims 1 thru | or 4 ,
In the peeling, an opening reaching a part of each of the plurality of voids is formed in a region different from a region where the semiconductor element is formed, and the etchant is diffused into the plurality of voids from the opening. Thus, the semiconductor element peeling method is performed by expanding each of the plurality of voids. In any one of Claims 1 to 5 ,
The method for peeling a semiconductor element, wherein the substrate is a quartz substrate, a silicon substrate, a glass substrate, or a metal substrate. In any one of Claims 1 thru | or 6 ,
The method for peeling a semiconductor element, wherein the plurality of convex portions are arranged in a stripe shape. In any one of Claims 1 thru | or 7 ,
The width between said convex parts is 1 micrometer or less, and the height of the said convex part is 2 micrometers or more, The peeling method of the semiconductor element characterized by the above-mentioned. A method for manufacturing a semiconductor device having a semiconductor element,
Forming a first base film having a plurality of protrusions on the substrate;
Forming a second base film having voids formed between the convex portions by forming an insulating film on the first base film;
Forming a third underlayer on the second underlayer;
After forming the semiconductor element on the third base film,
A method for manufacturing a semiconductor device, wherein the semiconductor element is peeled from the substrate at a surface intersecting with a plurality of the voids. A method for manufacturing a semiconductor device having a semiconductor element,
Forming a first base film made of metal having a plurality of convex portions on a substrate;
A metal oxide film is formed on the surface by oxidizing the surface of the first base film,
Forming a second base film having voids formed between the convex portions by forming an insulating film on the first base film;
Forming a third underlayer on the second underlayer;
And forming said semiconductor device on said third base film, after crystallizing the metal oxide film by heat treatment performed when forming the semiconductor element,
A method for manufacturing a semiconductor device, wherein the semiconductor element is peeled from the substrate at a surface intersecting with a plurality of the voids. In claim 9 or claim 10 ,
A method for manufacturing a semiconductor device, comprising: polishing a surface of the second base film before forming the third base film. In any one of Claim 9 thru | or Claim 11 ,
The peeling is performed by etching,
A method for manufacturing a semiconductor device, wherein an etching rate of the third base film is slower than an etching rate of the second base film. In any one of claims 9 to 12,
In the peeling, an opening reaching a part of each of the plurality of voids is formed in a region different from a region where the semiconductor element is formed, and the etchant is diffused into the plurality of voids from the opening. Thus, a method for manufacturing a semiconductor device is performed by expanding each of the plurality of voids. In any one of claims 9 to 13 ,
The method for manufacturing a semiconductor device, wherein the substrate is a quartz substrate, a silicon substrate, a glass substrate, or a metal substrate. In any one of claims 9 to 14 ,
The method for manufacturing a semiconductor device, wherein the plurality of convex portions are arranged in a stripe shape. In any one of Claims 9 to 15 ,
A method for manufacturing a semiconductor device, wherein a width between the protrusions is 1 μm or less, and a height of the protrusions is 2 μm or more. It in any one of claims 9 to 16, wherein the semiconductor element, TFT, a memory element, a diode, a photoelectric conversion element, a resistor element, a coil, a capacitor, or a circuit element including any of the inductor A method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device, wherein the semiconductor device according to claim 9 is a display device. The method for manufacturing a semiconductor device, wherein the semiconductor device according to claim 9 is a liquid crystal display device, a light-emitting device, or a DMD. The method for manufacturing a semiconductor device, wherein the semiconductor device according to claim 9 is an integrated circuit. The method for manufacturing a semiconductor device, wherein the semiconductor device according to claim 9 is a microprocessor, a memory, or a power supply circuit.

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