JP4713560B2 - Differential amplifier circuit - Google Patents

Description

The present invention relates to a differential amplifier circuit.
In a semiconductor integrated circuit device, a comparator circuit and an operational amplifier circuit are widely used as basic operation circuits. With higher integration and lower power consumption of semiconductor integrated circuit devices, it is necessary to improve various characteristics of these basic operation circuits.

  FIG. 7 shows a first conventional example of a comparator circuit composed of MOS transistors. The sources of the P-channel MOS transistors Tr1 and Tr2 are connected to the power source Vcc (high potential side power source), the gates are connected to each other, and are connected to the drain of the transistor Tr1.

  The drain of the transistor Tr1 is connected to the current source 1. Accordingly, the transistors Tr1 and Tr2 constitute a current mirror circuit, and the transistor Tr2 operates as a constant current source, and a drain current equal to the current flowing through the current source 1 flows.

  The drain of the transistor Tr2 is connected to the sources of P-channel MOS transistors Tr3 and Tr4. The node N1, which is the drain of the transistor Tr3, is connected to the drain of the N-channel MOS transistor Tr5, and the source of the transistor Tr5 is connected to the ground GND (low potential side power supply).

  The drain of the transistor Tr4 is connected to the drain of the N-channel MOS transistor Tr6 and the gates of the transistors Tr5 and Tr6, and the source of the transistor Tr6 is connected to the ground GND.

  Input signals Vin1 and Vin2 are input to the gates of the transistors Tr3 and Tr4. Therefore, the transistors Tr3 to Tr6 constitute a differential input circuit that is activated based on the constant current supplied from the transistor Tr2.

  The node N1 is input to the gate of an N-channel MOS transistor Tr7, the drain of the transistor Tr7 is connected to the power supply Vcc through a resistor R, and the source is connected to the ground GND. The drain of the transistor Tr7 is connected to the output terminal To, and the output signal Vout is output from the output terminal To.

  In the comparator circuit configured as described above, when the input signal Vin1 becomes higher than the input signal Vin2, the node N1 is lowered to near the ground GND level, and the transistor Tr7 is turned off. Then, an H level output signal Vout is output from the output terminal To.

  When the input signal Vin1 becomes lower than the input signal Vin2, the potential at the node N1 rises and the transistor Tr7 is turned on. Then, the drain current of the transistor Tr7 flows through the resistor R, and the output signal Vout of the L level, that is, the ground GND level is output from the output terminal To.

  This comparator circuit can also be used as an operational amplifier circuit by inputting the output signal Vout as the input signal Vin2. At this time, a drain current that causes the output signal Vout to coincide with the input signal Vin1 flows through the transistor Tr7.

  FIG. 8 shows a second conventional example of the comparator circuit. In this comparator circuit, the resistor R of the first conventional example is replaced with a P-channel MOS transistor Tr8, and the gate of the transistor Tr8 is connected to the gates of the transistors Tr1 and Tr2.

  Therefore, the transistor Tr8 operates as a constant current source and supplies an idling current to the output terminal To. The idling current of the transistor Tr8 is set sufficiently smaller than the maximum drain current of the transistor Tr7.

  In the comparator circuit configured as above, when the potential of the node N1 rises and the drain current of the transistor Tr7 becomes larger than the idling current of the transistor Tr8, the output signal Vout becomes L level.

Further, when the potential of the node N1 decreases and the drain current of the transistor Tr7 falls below the idling current of the transistor Tr8, the output signal Vout becomes H level.
This comparator circuit can also be used as an operational amplifier circuit by inputting the output signal Vout as the input signal Vin2.

  FIG. 9 shows a third conventional example of the comparator circuit. In this comparator circuit, the resistor R of the first conventional example is replaced by a P-channel MOS transistor Tr9, and the gate potential of the transistor Tr9 is controlled by P-channel MOS transistors Tr10 and Tr11. The transistors Tr7 and Tr9 are set so that their load driving capabilities are substantially equal.

  The source of the transistor Tr10 is connected to the power source Vcc, and the gate is connected to the gates of the transistors Tr2 and Tr3. Therefore, the transistor Tr10 outputs a constant current from its drain.

  The drain of the transistor Tr10 is connected to the gate of the transistor Tr9 and the source of the transistor Tr11, and the gate of the transistor Tr11 is connected to the node N1. The drain of the transistor Tr11 is connected to the ground GND. The output current of the transistor Tr10 is set sufficiently smaller than the maximum drain current of the transistor Tr11.

  In the comparator circuit thus configured, when the potential of the node N1 rises and the transistor Tr7 is turned on, the source potential of the transistor Tr11 rises, the gate potential of the transistor Tr9 rises, and the transistor Tr9 is turned off. The Therefore, the output signal Vout becomes L level.

  When the potential of the node N1 is lowered and the transistor Tr7 is turned off, the source potential of the transistor Tr11 is lowered, the gate potential of the transistor Tr9 is lowered, the transistor Tr9 is turned on, and the output signal Vout is H level. It becomes.

  In this way, the transistors Tr7 and Tr9 perform a push-pull operation based on the change in the potential of the node N1.

In the comparator circuit of the first conventional example, when the transistor Tr7 is turned off, the source current Source that can be supplied from the output terminal To to the load is
Iso = (Vcc-Vout) / R
The current set by. Accordingly, the source current Iso changes based on the voltage change of the output signal Vout.

  Further, when the resistance value of the resistor R is set high, the source current Iso becomes small. Therefore, when the load connected to the output terminal To becomes excessive, the rise of the output signal Vout to the H level may be slow.

  If the resistance value of the resistor R is reduced, the source current Iso can be increased. However, when the transistor Tr7 is turned on and a sink current Ssi is drawn from the output terminal To to the transistor Tr7, the source current Iso is drawn. Since Iso becomes a load on the transistor Tr7, the output signal Vout falls slowly. Further, since the current flowing from the power source Vcc to the ground GND via the resistor R and the transistor Tr7 increases, the current consumption increases.

Further, the drain current of the MOS transistor increases as the potential difference between its gate potential Vg and source potential Vs increases. If the gate-source voltage of the transistor Tr3 is Vgs (Tr3) and the source-drain voltage is Vds (Tr3), the node N1, that is, the gate potential Vg (Tr7) of the transistor Tr7 is
Vg (Tr7) = Vin1 + Vgs (Tr3) -Vds (Tr3)
It becomes.

Then, when the input signal Vin1 falls and the potential of the node N1 rises, the rise of the node N1 is suppressed by the input signal Vin1 and does not rise to near the power supply Vcc level.
As a result, since the gate potential of the transistor Tr7 cannot be operated in full amplitude from the power supply Vcc to the ground GND level, the current drive capability of the transistor Tr7 cannot be utilized to the maximum when the output signal Vout is output at the L level. Therefore, the falling speed of the output signal Vout cannot be sufficiently increased.

  In the second conventional example, when the transistor Tr7 is turned off and the H level output signal Vout is output, the source current Iso supplied from the output terminal To to the load is set to a constant current by the drain current of the transistor Tr8. Is possible.

  However, if a sufficient source current Iso is secured, when the transistor Tr7 is turned on and the sink current Isi is sucked from the output terminal To, the source current Iso becomes a load of the transistor Tr7, and the output signal Vout falls slowly and is consumed. The current also increases. Further, as in the first conventional example, since the gate potential of the transistor Tr7 cannot be operated at full amplitude, the current driving capability of the transistor Tr7 cannot be fully utilized.

  In the third conventional example, the change in the potential of the node N1 is reflected in the gate potential of the transistor Tr9. When the potential of the node N1 rises and the sink current Isi of the transistor Tr7 increases, the gate potential of the transistor Tr9 can be raised to reduce the source current Iso, and the potential of the node N1 decreases. When the sink current Isi of the transistor Tr7 decreases, the gate potential of the transistor Tr9 can be lowered to increase the source current Iso. Therefore, the source current Iso of the transistor Tr9 can be controlled according to the load.

  However, like the first and second conventional examples, the potential of the node N1 cannot be operated at full amplitude. The potential difference between the gates of the transistors Tr7 and Tr9 is set by the gate-source voltage of the transistor Tr11. Therefore, when the potential of the node N1 becomes near Vcc / 2 based on the input signal Vin1, the transistors Tr7 and Tr9 When both are turned on, a large through current flows from the power source Vcc to the ground GND via the transistors Tr9 and Tr7, resulting in an increase in current consumption.

  Since the gate-source voltage of the transistor Tr11 fluctuates due to process variations or changes in ambient temperature, it is not easy to accurately manage this through current at the time of design.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a differential amplifier circuit that can reduce power consumption while ensuring sufficient load driving capability by maximizing the capability of an output element.

The differential amplifier circuit according to claim 1, a differential input circuit that amplifies a potential difference between a pair of input signals and outputs them as a first output signal and a second output signal , a high-potential-side power supply, and an output terminal wherein the first P-channel MOS transistor connected as an output transistor, and an N-channel MOS transistor connected as a second output transistor between the output terminal and a low potential side power supply between, the difference Based on the output signal of the dynamic input circuit, the pull-up operation in which the first output transistor operates to discharge the source current from the output terminal, and the second output transistor operates to sink current from the output terminal a differential amplifier circuit and an output circuit for performing a pull-down operation for sucking, a first output current of the first current control circuit that operates based on the first output signal The first MOS transistor is connected in series with the first MOS transistor between the high potential side power source and the low potential side power source, and the drain is connected to the first MOS transistor and is based on the second output signal. A second MOS transistor for flowing a first drain current, a third MOS transistor having a gate connected to a first connection point between the first MOS transistor and the second MOS transistor, and the first output in the first current control circuit. A fourth MOS transistor for supplying a second output current corresponding to the current and a high-potential-side power supply and a low-potential-side power supply connected in series to the fourth MOS transistor, corresponding to the drain current of the third MOS transistor A gate potential control circuit including a fifth MOS transistor for flowing a second drain current A gate of the first output transistor is connected to the first connection point; a gate of the second output transistor is connected to a second connection point of the fourth MOS transistor and the fifth MOS transistor; The potential control circuit applies a voltage based on a ratio of the first output current and the first drain current to the gate of the first output transistor, and applies the second output current to the gate of the second output transistor. When applying a voltage based on the ratio to the second drain current and performing the pull-up operation, the gate potential of the first output transistor is connected from the low potential side power source to the node of the differential input circuit. and the drain-source voltage of elevated levels of the first 2 MOS transistor, when performing the pull-down operation, the second output Trang The gate potential of the static you from the high potential side power supply and the fourth drain-source voltage of reduced levels of MOS transistors.

According to a second aspect of the present invention, in the differential amplifier circuit according to the first aspect, when the gate potential control circuit performs the pull-up operation, the gate potential of the second output transistor is changed from the low potential side power source to the fifth potential source . When the pull-down operation is performed with the level increased by the drain-source voltage of the MOS transistor, the gate potential of the first output transistor is decreased by the voltage between the drain-source of the first MOS transistor from the high potential side power supply. Level .

3. The differential amplifier circuit according to claim 1, wherein the first current control circuit is configured by a current mirror circuit, and an idling current of the first output transistor is supplied to the differential input circuit. to be set on the basis of the bias current of the circuit.

Claim 4 is, in the differential amplifier circuit according to claim 3, flow and said second 3M OS transistor and the first detection transistor which is current-mirror-connected, the first output current of the first current control circuit A second detection transistor connected in a current mirror connection with the first MOS transistor, and a difference for supplying a current equal to a current difference between the first detection transistor and the second detection transistor to the fifth MOS transistor; Ru includes a current compensation circuit comprising a current detection circuit.

Claim 5 is flowed in a differential amplifier circuit according to claim 3, said first 3M OS transistor and the first detection transistor which is current-mirror-connected, the first output current of the first current control circuit A current equal to the current difference between the second detection transistor connected to the first MOS transistor in a current mirror connection and the first detection transistor and the second detection transistor is sucked from the drain of the third MOS transistor. Ru comprises a current correction circuit comprising a differential current detection circuit.

The differential amplifier circuit according to claim 6, a differential input circuit that amplifies a potential difference between a pair of input signals and outputs them as a first output signal and a second output signal , a high-potential-side power supply, and an output terminal wherein the first P-channel MOS transistor connected as an output transistor, and an N-channel MOS transistor connected as a second output transistor between the output terminal and a low potential side power supply between, the difference Based on the output signal of the dynamic input circuit, the pull-up operation in which the first output transistor operates to discharge the source current from the output terminal, and the second output transistor operates to sink current from the output terminal a differential amplifier circuit and an output circuit for performing a pull-down operation for sucking, a first output current of the first current control circuit that operates based on the first output signal The first MOS transistor is connected in series with the first MOS transistor between the high potential side power source and the low potential side power source, and the drain is connected to the first MOS transistor and is based on the second output signal. A second MOS transistor for flowing a first drain current, a third MOS transistor having a gate connected to a first connection point between the first MOS transistor and the second MOS transistor, and the first output in the first current control circuit. A fourth MOS transistor for supplying a second output current corresponding to the current and a high-potential-side power supply and a low-potential-side power supply connected in series to the fourth MOS transistor, corresponding to the drain current of the third MOS transistor A gate potential control circuit including a fifth MOS transistor for flowing a second drain current And the gate of the first output transistor is connected to the first connecting point, the gate of the second output transistor is connected to the second connection point between the first 5MOS transistor and the second 4MOS transistor, the gate The potential control circuit applies a voltage based on a ratio of the first output current and the first drain current to the gate of the first output transistor, and applies the second output current to the gate of the second output transistor. When applying a voltage based on a ratio to the second drain current and performing the pull-up operation, a gate is connected to a node of the differential input circuit, and a low-potential-side power supply level is applied to the gate of the first output transistor. low potential side power supply of the gate potential of the first output transistor gate potential of the first 2 MOS transistor for supplying a high potential side power supply level And al the second drain-to-source voltage of elevated levels of the MOS transistor, when performing the pull-down operation, between the drain and source of the second of the first 1 MOS transistor gate potential from the high potential side power source of the output transistor It shall be the reduced level voltage.
Claim 7, in the differential amplifier circuit according to any one of claims 1 to 6, the source of the first 2 MOS transistor having a gate connected to the node connected to the low potential side power supply, the the drain of the 2 MOS transistor, a gate of the first 3 MOS transistor connected to a gate of said first output transistor Ru is connected.

(Function)
According to the first aspect of the present invention, the gate potential of the first and second output transistors operates substantially at full amplitude between the high potential side power supply level and the low potential side power supply level by the operation of the gate potential control circuit. That is, the current drive capability of the first output transistor is maximized during the pull-up operation, and the current drive capability of the second output transistor is maximized during the pull-down operation.

  In the second aspect, the second output transistor is turned off during the pull-up operation, the drain current of the first output transistor is discharged as the source current, and the first output transistor is turned off during the pull-down operation. The drain current of the output transistor is sucked as a sink current.

In the claims 3, by a current mirror circuit constituting a first current control circuit, the idling current of the first output transistor is set by the bias current of the differential input circuit.
In the claims 4, to the 5MOS transistor, the drain current is insufficient is supplied from the current correction circuit, the second output transistor is reliably turned off during the pull-up operation.

In the claims 5, drain current becomes excessive drain of the 3MOS transistor is sucked into the current correction circuit, the second output transistor is reliably turned off during the pull-up operation.

In the claims 6, when performing a pull-up operation based on the first and second output signals of the differential input circuit, the gate potential for turning on the first output transistor is a low-potential side power source level, the pull-down operation When performing, the gate potential for turning on the second output transistor is set to the high potential side power supply level. Further, when the pull-up operation is performed, the gate potential of the second MOS transistor that supplies the low-potential-side power supply level to the gate of the first output transistor is set to the high-potential-side power supply level, and the gate potential of the first output transistor is set. Is set to a level increased by the voltage between the drain and source of the second MOS transistor from the low potential side power supply, and when performing a pull-down operation, the gate potential of the second output transistor is changed from the high potential side power supply to the drain of the first MOS transistor. The level is reduced by the source-to-source voltage. The current drive capability of the first output transistor is maximized during the pull-up operation, and the current drive capability of the second output transistor is maximized during the pull-down operation.

  ADVANTAGE OF THE INVENTION According to this invention, the differential amplifier circuit which can aim at reduction of power consumption can be provided, fully demonstrating the capability of an output element and ensuring load drive capability fully.

(First embodiment)
FIG. 2 shows an operational amplifier circuit according to a first embodiment embodying the present invention. The current mirror circuit composed of the transistors Tr1 and Tr2 and the differential circuit composed of the transistors Tr3 to Tr6 have the same configuration as the conventional example.

  The node N2, which is the drain of the transistors Tr3 and Tr5, is connected to the gate of the N-channel MOS transistor Tr21. The node N3, which is the drain of the transistors Tr4 and Tr6, is connected to the gate of the N-channel MOS transistor Tr22.

  The source of the transistor Tr21 is connected to the ground GND, and the drain thereof is connected to the power source Vcc via the P-channel MOS transistor Tr23. The transistor Tr21 operates as a current mirror with respect to the transistor Tr5.

  The gate of the transistor Tr23 is connected to the drain of the transistor Tr23 and the gate of the P-channel MOS transistor Tr24, the source of the transistor Tr24 is connected to the power source Vcc, and the drain is connected to the drain of the transistor Tr22. The source of the transistor Tr22 is connected to the ground GND. The transistors Tr23 and Tr24 perform a current mirror operation.

  The node N5 which is the drain of the transistors Tr23 and Tr21 is connected to the gate of the P-channel MOS transistor Tr25, and the source of the transistor Tr25 is connected to the power supply Vcc. The transistor Tr25 performs a current mirror operation with respect to the transistor Tr23.

  The node N6 which is the drain of the transistors Tr24 and Tr22 is connected to the gate of a P-channel MOS transistor Tr26, and the source of the transistor Tr26 is connected to the power supply Vcc.

  The node N7 which is the drain of the transistor Tr25 is connected to the drain of the N-channel MOS transistor Tr27. The drain of the transistor Tr26 is connected to the drain of the transistor Tr28 and the gates of the transistors Tr28 and Tr27. The sources of the transistors Tr27 and Tr28 are connected to the ground GND. The transistors Tr27 and Tr28 perform a current mirror operation.

  The node N6 is connected to the gate of a P-channel MOS transistor Tr29 which is an output transistor, and the node N7 is connected to the gate of an N-channel MOS transistor Tr30 which is an output transistor. The transistors Tr26 and Tr29 perform a current mirror operation.

  The source of the transistor Tr29 is connected to the power supply Vcc, the drains of the transistors Tr29 and Tr30 are connected to the output terminal To, and the source of the transistor Tr30 is connected to the ground GND. The output signal Vout output from the output terminal To is input as the input signal Vin2 to the gate of the transistor Tr4.

  The transistors Tr21 to Tr28 constitute a gate potential control circuit for the output transistors Tr29 and Tr30, the transistors Tr21 and Tr23 to Tr25 constitute a first current control circuit, and the transistors Tr27 and Tr28 constitute a second current control circuit. Is done.

Next, the operation of the operational amplifier circuit configured as described above will be described.
(1) When a capacitive load is connected between the output terminal To and the ground GND, and the input signal Vin1 is raised.

  Based on the rise of the input voltage Vin1, the drain current of the transistor Tr3 decreases and the drain current of the transistor Tr4 relatively increases. As a result, the potential of the node N2 decreases and the potential of the node N3 increases, turning off the transistor Tr21 and turning on the transistor Tr22.

  Based on the turning-off operation of the transistor Tr21, the transistors Tr23 and Tr24 are also turned off. Then, the node N6 becomes higher than the ground GND by the voltage between the drain and source of the transistor Tr22, and is almost at the ground GND level.

  At the same time, the transistor Tr25 is turned off, the transistor Tr26 is turned on, and the transistors Tr27 and Tr28 are turned on. Then, the node N7 has a level higher than the ground GND by the voltage between the drain and source of the transistor Tr27, and is almost at the ground GND level.

  Accordingly, the transistor Tr29 is turned on, the transistor Tr30 is turned off, the source current Iso is output to the capacitive load connected to the output terminal To, and the output signal Vout rises until it matches the voltage level of the input signal Vin1. .

(2) When a capacitive load is connected between the output terminal To and the ground GND, and the input signal Vin1 is lowered.
Based on the decrease of the input signal Vin1, the drain current of the transistor Tr3 increases and the drain current of the transistor Tr4 relatively decreases. Then, the potential of the node N2 increases and the potential of the node N3 decreases, turning on the transistor Tr21 and turning off the transistor Tr22.

  The transistors Tr23 and Tr24 are also turned on based on the on operation of the transistor Tr21. Then, the node N6 becomes lower than the power source Vcc by the voltage between the drain and source of the transistor Tr24, and is almost at the power source Vcc level.

  At the same time, the transistor Tr25 is turned on, the transistor Tr26 is turned off, and the transistors Tr27 and Tr28 are turned off. Then, the node N7 is at a level lower than the power supply Vcc by the voltage between the drain and source of the transistor Tr25, and is almost at the power supply Vcc level.

  Accordingly, the transistor Tr29 is turned off and the transistor Tr30 is turned on, so that the sink current Isi is absorbed from the capacitive load connected to the output terminal To, and the output signal Vout decreases until it matches the voltage level of the input signal Vin1. .

(3) When the input signals Vin1 and Vin2 match.
When the input signals Vin1 and Vin2 match, that is, when the output signal Vout matches the input signal Vin1, the drain currents of the transistors Tr3 and Tr4 become equal, and the nodes N2 and N3 have the same potential.

  Then, the drain currents of the transistors Tr21 and Tr22 are equalized, and the drain currents of the transistors Tr23, Tr24 and Tr25 are equalized. Further, the drain currents of the transistors Tr24 and Tr22 become equal, and the node N6 is in the vicinity of an intermediate level between the power supply Vcc and the ground GND.

  Further, the drain currents of the transistors Tr25 and Tr27 are equal, and the drain currents of the transistors Tr25 and Tr26 are equal. Therefore, the node N7 is in the vicinity of an intermediate level between the power supply Vcc and the ground GND.

Since the transistors Tr26 and Tr29 perform a current mirror operation, the drain currents of the transistors Tr26 and Tr29 are equal.
By such an operation, the drain currents of the transistors Tr21, Tr29, and Tr30 become equal, and the idling current of the transistor Tr29 can be set by the drain current of the transistor Tr21.

  The drain current of the transistor Tr21 is equal to the drain current of the transistor Tr5. When the input signals Vin1 and Vin2 match, the drain currents of the transistors Tr5 and Tr6 are equal. Therefore, the drain current of the transistor Tr5 is the drain current of the transistor Tr2. That is, it becomes 1/2 of the bias current supplied to the input differential pair.

Therefore, the idling current of the transistor Tr29 can be set by the bias current of the input differential circuit.
(4) When sink current load and source current load are connected.

  When the sink current load is connected, the sink current Isi is absorbed from the load toward the transistor Tr30, and the input signals Vin1 and Vin2 operate so as to be equal. Therefore, the voltage level of the input signal Vin1 is lowered. Works as well.

  The gate potential of the transistor Tr30 becomes a level that is lowered from the power supply Vcc by the voltage between the source and drain of the transistor Tr25, and the maximum value can rise to the vicinity of the power supply Vcc level.

  At this time, in the state where the drain current of the transistor Tr24 flows to the transistor Tr22, the voltage between the drain and the source of the transistor Tr22 increases due to the decrease of the potential of the node N3, and the potential of the node N6 increases. Then, the drain current of the transistor Tr26 decreases, and the drain potential of the transistor Tr28 and the gate potentials of the transistors Tr28 and Tr27 decrease.

  Since a constant drain current is supplied from the transistor Tr25 to the transistor Tr27, the transistor Tr27 responds by increasing the drain-source voltage based on the decrease in the gate potential. When the voltage between the source and drain of the transistor Tr25 drops to the operating limit, the gate potential of the transistor Tr30 becomes the maximum value, and the drain current of the transistor Tr30 based on the gate potential is drawn into the transistor Tr30 from the load. Sink current.

  When the source current load is connected, the source signal Iso is discharged from the transistor Tr29 toward the load, and the input signals Vin1 and Vin2 operate so as to be equal. Therefore, when the voltage level of the input signal Vin1 is raised. Works as well.

  The gate potential of the transistor Tr29 becomes a level increased by the voltage between the source and drain of the transistor Tr22 from the ground GND, and the minimum value thereof can be lowered to the vicinity of the ground GND level.

  At this time, as the drain current of the transistor Tr29 increases, the drain current of the transistor Tr26 increases, and the drain voltage and gate voltage of the transistor Tr28 increase based on the increase of the drain current.

  The transistor Tr27 that performs current mirror operation with the transistor Tr28 reduces the drain-source voltage to the operating limit of the MOS transistor based on the constant drain current supplied from the transistor Tr25.

  Therefore, the drain currents of the transistors Tr28 and Tr26 when the drain-source voltage of the transistor Tr27 drops to the operating limit is the maximum source current discharged from the transistor Tr29 to the load.

In the operational amplifier circuit configured as described above, the following operational effects can be obtained.
(A) Regardless of the voltage levels of the input signals Vin1 and Vin2, the gate potentials of the output transistors Tr29 and Tr30 can be operated at full amplitude.

  (B) When sink current is sucked from the load connected to the output terminal To, the gate potential of the output transistor Tr30 can be raised to near the power supply Vcc level regardless of the voltage levels of the input signals Vin1 and Vin2. Therefore, the current driving capability of the output transistor Tr30 can be utilized to the maximum.

  (C) When discharging the source current to the load connected to the output terminal To, the gate potential of the output transistor Tr29 can be lowered to near the ground GND level regardless of the voltage levels of the input signals Vin1 and Vin2. Therefore, the current driving capability of the output transistor Tr29 can be utilized to the maximum.

  (D) When a capacitive load is connected to the output terminal To and the gate potential of the output transistor Tr30 rises to near the power supply Vcc level, the gate potential of the output transistor Tr29 also rises to near the power supply Vcc level. Then, when the output transistor Tr30 exhibits its current driving capability to the maximum, the output transistor Tr29 is turned off, so that the through current flowing through the transistors Tr29 and Tr30 is cut off, and the current consumption can be reduced.

  (E) When a capacitive load is connected to the output terminal To and the gate potential of the output transistor Tr29 decreases to near the ground GND level, the gate potential of the output transistor Tr30 also decreases to near the ground GND level. Then, when the output transistor Tr29 exhibits its current driving capability to the maximum, the output transistor Tr30 is turned off, so that the through current flowing through the transistors Tr29 and Tr30 is cut off, and the current consumption can be reduced.

  (F) Since the current drive capability of the output transistors Tr29 and Tr30 can be maximized, the equivalent load drive capability can be ensured even if a smaller output transistor is used than the conventional example. it can.

  (G) Since the idling current flowing through the output transistor Tr29 can be set by the bias current of the differential input section, the load drive capability and the power consumption can be set appropriately by appropriately setting the bias current. it can.

(Second embodiment)
FIG. 3 shows a second embodiment in which the present invention is embodied. This embodiment is different from the first embodiment only in that the drains of the transistors Tr5 and Tr6 of the differential input circuit are connected to the gate and are respectively diode-connected.

  Although the transistors Tr5 and Tr6 do not perform a current mirror operation, the transistors Tr5 and Tr5 are arranged so that a necessary potential difference is generated between the nodes N2 and N3 based on the change in drain current of the transistors Tr3 and Tr4 based on the input signals Vin1 and Vin2. What is necessary is just to set the size of Tr6.

The operational amplifier circuit configured as described above operates in the same manner as in the first embodiment, and can obtain the same effects.
(Third embodiment)
FIG. 4 shows a third embodiment that embodies the present invention. In this embodiment, the transistors Tr5 and Tr6 of the differential input circuit of the first embodiment are replaced with N-channel MOS transistors Tr31 to Tr34, and the other configuration is the same as that of the first embodiment. is there.

  That is, the drain of the transistor Tr3 is connected to the drain of the transistor Tr31 and the gates of the transistors Tr31 and Tr32, and the drain of the transistor Tr32 is connected to the drain of the transistor Tr4.

  The drain of the transistor Tr4 is connected to the drain of the transistor Tr34 and the gates of the transistors Tr33 and Tr34, and the drain of the transistor Tr33 is connected to the drain of the transistor Tr3. The sources of the transistors Tr31 to Tr34 are connected to the ground GND.

Therefore, the transistors Tr31 and Tr32 and the transistors Tr33 and Tr34 each perform a current mirror operation.
With such a configuration, the potential of the node N3 is determined based on the potential of the node N2 due to the drain current of the transistor Tr3, and the potential of the node N2 is determined based on the potential of the node N3 due to the drain current of the transistor Tr4.

  By such an operation, the accuracy of the potentials of the nodes N2 and N3 based on the input signals Vin1 and Vin2 can be improved as compared with the first embodiment. Other functions and effects are the same as those of the first embodiment.

(Fourth embodiment)
FIG. 5 shows a fourth embodiment that embodies the present invention. In this embodiment, in order to further increase the maximum source current of the first embodiment, a current correction circuit comprising P-channel MOS transistors Tr35 and Tr36 and a difference current detection circuit 2 is added to the first embodiment. Is added.

  The transistor Tr35 has a source connected to the power supply Vcc, a drain connected to the differential current detection circuit 2, and a gate connected to the gates of the transistors Tr23 to Tr25. Therefore, the transistor Tr35 performs a current mirror operation on the transistors Tr23 to Tr25.

  The transistor Tr36 has a source connected to the power source Vcc, a drain connected to the differential current detection circuit 2, and a gate connected to the gates of the transistors Tr26 and Tr29. Therefore, the transistor Tr36 performs a current mirror operation on the transistors Tr26 and Tr29.

The difference current detection circuit 2 detects the difference between the drain currents of the transistors Tr35 and Tr36 and supplies a current Id1 equal to the current difference to the drain of the transistor Tr27.
With such a configuration, when the drain current of the transistor Tr26 increases as the source current output from the transistor Tr29 to the load increases, the difference between the drain currents of the transistors Tr25 and Tr26 is the difference between the drain currents of the transistors Tr35 and Tr36. The difference is detected by the difference current detection circuit 2, and the difference current Id1 is supplied to the drain of the transistor Tr27.

  Therefore, even if the source current output from the transistor Tr29 to the load increases and a difference occurs in the drain currents of the transistors Tr25 and Tr26, the difference current Id1 is supplied to the drain of the transistor Tr27, so that the transistors Tr27 and Tr28 Then, stable current mirror operation is performed.

  Since sufficient drain current is supplied to the transistor Tr27 and the node N7 is sufficiently lowered, the drain current of the output transistor Tr30 is substantially cut off, and the drain current of the output transistor Tr29 is not absorbed by the output transistor Tr30. Supplied as a source current to the load.

Therefore, the maximum source current can be increased as compared with the first embodiment.
(Fifth embodiment)
FIG. 6 shows a fifth embodiment of the present invention. This embodiment has the same configuration as that of the fourth embodiment except for the difference current detection circuit 3.

  The output terminal of the differential current detection circuit 3 is connected to the drain of the transistor Tr28. Then, the differential current detection circuit 3 operates so as to draw the differential current Id2 equal to the current difference between the drain currents of the transistors Tr35 and Tr36 from the drain of the transistor Tr28.

  With such a configuration, when the source current output from the output transistor Tr29 to the load increases and a difference occurs between the drain currents of the transistors Tr25 and Tr26, the difference current Id2 is absorbed by the difference current detection circuit 3. The substantially same effect as that of the fourth embodiment can be obtained.

It is a principle explanatory view of the present invention. It is a circuit diagram showing a first embodiment. It is a circuit diagram which shows 2nd embodiment. It is a circuit diagram which shows 3rd embodiment. It is a circuit diagram which shows 4th Embodiment. It is a circuit diagram which shows 5th embodiment. It is a circuit diagram which shows a 1st prior art example. It is a circuit diagram which shows a 2nd prior art example. It is a circuit diagram which shows a 2nd prior art example.

Explanation of symbols

11 Differential Input Circuit 12 Gate Potential Control Circuit Vin1 and Vin2 Input Signal V1 High Potential Power Supply V2 Low Potential Power Supply Tr29 First Output Transistor Tr30 Second Output Transistor

Claims (7)

A differential input circuit that amplifies the potential difference between the pair of input signals and outputs the first output signal and the second output signal ;
And P-channel MOS transistor connected as a first output transistor between the high potential power supply and the output terminal, N-channel MOS connected as a second output transistor between the output terminal and a low potential side power supply and a transistor, on the basis of the output signal of the differential input circuit, a pull-up operation of ejecting source current from the output terminal to operate the first output transistor, the second output transistor operates a differential amplifier circuit and an output circuit for performing a pull-down operation for sucking sink current from the output terminal Te,
A first MOS transistor for flowing a first output current of a first current control circuit operating based on the first output signal;
The high potential side power source and the low potential side power source are connected in series to the first MOS transistor, the drain is connected to the first MOS transistor, and the first drain current is generated based on the second output signal. A second MOS transistor for flowing;
A third MOS transistor having a gate connected to a first connection point between the first MOS transistor and the second MOS transistor;
A fourth MOS transistor for passing a second output current corresponding to the first output current in the first current control circuit;
A fifth MOS transistor connected in series to the fourth MOS transistor between the high-potential-side power supply and the low-potential-side power supply, and passing a second drain current corresponding to the drain current of the third MOS transistor;
A gate potential control circuit including
A gate of the first output transistor is connected to the first connection point; a gate of the second output transistor is connected to a second connection point of the fourth MOS transistor and the fifth MOS transistor;
The gate potential control circuit applies a voltage based on a ratio of the first output current and the first drain current to the gate of the first output transistor, and applies the second output to the gate of the second output transistor. When a voltage based on the ratio of the current and the second drain current is applied and the pull-up operation is performed, the gate potential of the first output transistor is changed from the low potential side power source to the node of the differential input circuit. When the pull-down operation is performed with the level increased by the drain-source voltage of the connected second MOS transistor, the gate potential of the second output transistor is changed from the high potential side power supply to the drain / source of the fourth MOS transistor. the level and to Turkey with reduced voltage of between source,
A differential amplifier circuit. When performing the pull-up operation, the gate potential control circuit sets the gate potential of the second output transistor to a level increased by a voltage between the drain and source of the fifth MOS transistor from a low-potential side power supply, and performs the pull-down operation. 2. The differential amplification according to claim 1, wherein when performing the step, the gate potential of the first output transistor is set to a level lower than the drain-source voltage of the first MOS transistor from the high-potential side power supply. circuit. It said first current control circuit, according to claim 1 which constitutes a current mirror circuit, characterized in that the idling current of the first output transistor and can be set based on the bias current of said differential input circuit Or the differential amplifier circuit of 2. Wherein the 3M OS transistor and the first detection transistor which is a current mirror connection, the first second detection transistor that first is the first MOS transistor and a current mirror an output current connection of the current control circuit And a current correction circuit comprising a difference current detection circuit for supplying a current equal to the current difference between the first detection transistor and the second detection transistor to the fifth MOS transistor. The differential amplifier circuit according to claim 3 . Wherein the 3M OS transistor and the first detection transistor which is a current mirror connection, the first second detection transistor that first is the first MOS transistor and a current mirror an output current connection of the current control circuit And a current correction circuit comprising a difference current detection circuit that draws a current equal to the current difference between the first detection transistor and the second detection transistor from the drain of the third MOS transistor. The differential amplifier circuit according to claim 3 . A differential input circuit that amplifies the potential difference between the pair of input signals and outputs the first output signal and the second output signal ;
And P-channel MOS transistor connected as a first output transistor between the high potential power supply and the output terminal, N-channel MOS connected as a second output transistor between the output terminal and a low potential side power supply and a transistor, on the basis of the output signal of the differential input circuit, a pull-up operation of ejecting source current from the output terminal to operate the first output transistor, the second output transistor operates a differential amplifier circuit and an output circuit for performing a pull-down operation for sucking sink current from the output terminal Te,
A first MOS transistor for flowing a first output current of a first current control circuit operating based on the first output signal;
The high potential side power source and the low potential side power source are connected in series to the first MOS transistor, the drain is connected to the first MOS transistor, and the first drain current is generated based on the second output signal. A second MOS transistor for flowing;
A third MOS transistor having a gate connected to a first connection point between the first MOS transistor and the second MOS transistor;
A fourth MOS transistor for passing a second output current corresponding to the first output current in the first current control circuit;
A fifth MOS transistor connected in series to the fourth MOS transistor between the high-potential-side power supply and the low-potential-side power supply, and passing a second drain current corresponding to the drain current of the third MOS transistor;
A gate potential control circuit including
A gate of the first output transistor is connected to the first connection point; a gate of the second output transistor is connected to a second connection point of the fourth MOS transistor and the fifth MOS transistor;
The gate potential control circuit applies a voltage based on a ratio of the first output current and the first drain current to the gate of the first output transistor, and applies the second output to the gate of the second output transistor. When a voltage based on the ratio of the current and the second drain current is applied and the pull-up operation is performed, a gate is connected to a node of the differential input circuit, and a low-potential-side power source is connected to the gate of the first output transistor the gate potential of the first 2 MOS transistor for supplying a level of the gate potential of the first output transistor and the low potential side power supply and the drain-source voltage of elevated levels of the first 2 MOS transistor as the high-potential power supply level when performing the pull-down operation, the second of the first 1 MOS Trang the gate potential from the high potential side power source of the output transistor Differential amplifier circuit, characterized in that the static drain-source voltage of a reduced level. The source of the second MOS transistor whose gate is connected to the node is connected to the low-potential-side power supply, the drain of the second MOS transistor is connected to the gate of the first output transistor, and the third MOS transistor is connected to the gate of the first output transistor. the differential amplifier circuit according to any one of claims 1 to 6, characterized in that the gate of the transistors are connected.

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