JPH03274911A - Operational amplifier - Google Patents

Abstract

PURPOSE:To drive the load of a small impedance by a small FET by composing a level shift step of a differential amplifier equipped with a pair of PchFET and connecting a resistor between the drain terminals of paired current mirror type load FET connected paired input FET. CONSTITUTION:In an input step 1, outputs are generated at the drains of FET Q6 and Q7 by receiving the drain voltages of Q1 and Q2 at the sources, amplifying the voltages to apply the voltages to prebuffers 2a and 2b. A Q41 is connected between the drains of loads Q23 and Q24 in the buffer 2a of a PMOS and on the other hand, a Q42 is connected between loads Q28 and Q29 in the buffer 2b of an NMOS input. Then, a ground potential and a VDD are applied to the gates of the Q41 and Q42 and they are turned on at all times so as to be operated as resistors. Thus, when the gains of the prebuffers 2a and 2b are suppressed by the ON resistors of the MOS, an influence to be exerted upon the characteristic dispersion of the output step by input offset is made small. Therefore, when properly controlling the gains of the prebuffers 2a and 2b, the control of the characteristic dispersion can be balanced with driving ability.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuit technology and to a technology that is particularly effective when applied to class AB operational amplifier circuits consisting of MOSFETs. The present invention relates to a technique that is effective for use in a transmission buffer amplifier for driving a low impedance load.

[Prior Art] In recent years, transmission buffer amplifiers for driving low impedance loads such as subscriber lines have been built into communication LSIs such as GODECs. Since such communication LSIs are required to have low power consumption, class AB amplifiers with push-pull output stages are often used. However, although it is desired to suppress the steady state current as much as possible in class AB amplifiers, the steady state current tends to fluctuate due to process variations, so stabilizing the steady state current has become an important issue.

Therefore, as shown in FIG. 3, a level shift stage 2 is provided between the loaded cascode differential amplifier stage 1 and the complementary push-pull output stage 3 to level shift the output of the differential amplifier stage. The transfer voltage to stage 3 is increased to suppress the steady current and AB with high driving ability.
Invention related to amplifiers with class operation (Japanese Patent Laid-Open No. 62-683
No. 08) has been proposed.

In order to realize a class AB amplifier with low power consumption and high drive capability, the key point is that the variable range of the output of the differential amplifier stage 1 is wide. Therefore, in the above-mentioned prior invention, the differential MOS FETMI3 is used.

The potential of the well region where MI4 is formed is set to a negative voltage, and the MO3FET MI5. MI6
As such, a MOSFET is used in which the threshold voltage is increased by the band gap of silicon by introducing impurities of a conductivity type opposite to that of the source/drain regions into the gate electrode. This increases the variable range of the output of the differential amplifier stage and level-shifts the output MOSFET.
By driving MOl and MO2, small MO
The SFET realizes an amplifier with high drive capability that can drive a low impedance load.

[Problems to be Solved by the Invention] In the amplifier shown in FIG. 3, four MOSFETs MB are used to eliminate systematic offsets.
A four-stage bias circuit 4 formed by connecting I-MBs 4 in series is provided, and optimum constant settings are performed so that the power consumption of the amplifier is proportional to the power consumption of the bias circuit 4. Further, the power consumption of the bias circuit greatly depends on the difference between the sum of the threshold voltages of the four vertically stacked MOSFETs MBI to MB4 and the power supply voltage.

However, the power supply voltages of the amplifier in FIG. 3 are +V and -V (usually ±5V), and the amplifier is designed with a power supply voltage difference of 10V. Therefore, if a circuit with the above configuration is built into an LSI with a single +5V power supply, for example, there is a problem in that the power consumption is greatly affected by fluctuations in process parameters such as threshold voltage.

In recent years, with the miniaturization of processes, communication LSIs have tended to use a 5V single power supply, so there is a demand for buffer amplifiers that consume less power and have less fluctuation in characteristics even when the power supply voltage decreases.

The purpose of this invention is to have stable power consumption and characteristics,
Moreover, it is an object of the present invention to provide a class AB amplifier having low power consumption and large driving capability.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a loaded cascode differential amplifier is used in the input stage, and a differential amplifier stage with 5 PMO inputs and NM are used in the subsequent stage.
A pre-buffer consisting of a differential amplification stage with O8 input is provided as a level shifter, and a resistor is inserted between the drain terminals of the current mirror-connected load MOSFETs in these pre-buffers to suppress the gain of the pre-buffer to about 10 dB or less. , each output MO5FET of the push-pull output stage is driven by this low gain pre-buffer.

Further, as a bias circuit for driving the constant current source in the differential input stage and pre-buffer, a circuit with low dependence on power supply voltage and process parameters is used.

[Since the gain of the output stage decreases with low impedance drive,
Conventional operational amplifiers had the disadvantage of low DC gain and poor linearity even with voltage followers, but with the above-mentioned method, the input stage alone uses a forced cascode differential amplifier, so the input stage alone has a gain of about 40 dB. A high DC gain can be obtained, and even if the gain of the output stage is low, a high gain and good linearity can be obtained as a whole circuit.

In addition, PMO5 input receives the output of the differential input stage, and NMO5 input receives the output of the differential input stage.
By installing a resistor in the 8-input pre-buffer and suppressing the pre-buffer gain to 10 dB or less, fluctuations in the bias point of the output stage due to variations in the input offset of the pre-buffer can be suppressed within a practical allowable range. This makes it possible to provide a circuit with high resistance to dependence on various parameters during mass production.

Furthermore, even in bias circuits, circuit configurations that reduce parameter dependence other than temperature dependence have become practical, and by applying such circuits to the amplifier of the present invention, low power consumption with small characteristic variations can be achieved. It is possible to realize a low impedance drive amplifier, and it is also highly resistant to fluctuation factors, so malfunctions can be prevented.

[Embodiment] FIG. 1 shows a circuit diagram of an embodiment of the present invention. Each circuit element in the figure is a well-known CM○S (complementary MO
8) Formed on a single semiconductor substrate, such as single crystal silicon, by integrated circuit manufacturing techniques. In the same figure, the MOSFET with an arrow added to the channel part
is of P-channel type.

In this embodiment, the input stage 1 is composed of a loaded cascode type differential amplifier circuit. That is, a pair of N-channel type input differential M whose source terminals are commonly connected to each other.
OSFET Ql, Q2 (7) A P-channel type load MO5FET Q4.current mirror connected between the drain terminal and the power supply voltage vDD. Q5 is connected. A P-channel type MO5FET Q is connected between the drain terminal of this MOSFET Q4 and the ground point.
6 and N-channel MOSFET Q8. QIO is
A P-channel type MOSFET Q7 and N-channel type MOSFETs Q9 and Qll are connected in series between the drain terminal of the master MO5FET Q5 and the ground point, respectively.

Among the MOSFETs Q6 to Qll above, Q6 and Q7
And Q8 and Q9 are each connected in a current mirror. Furthermore, MOSFETs QIO and Qll operate as constant current sources by supplying a constant voltage from the bias circuit 4 to their gates. Shikamo, MOSFE
T QIO, Qll have input differential MO5FET Q
l, Q2 (7) Constant current M connected to common source terminal
Current flowing through O5FETQ3■. The constant of each MOSFET is set so that half of the current flows through the MOSFET.

In the input stage 1 consisting of this loaded cascode type differential amplifier circuit, MOSFET Q6゜Q7 has its source terminal connected to the output of the input stage, that is, the MOSFET
By receiving the drain voltages of Ql and Q2 and generating an output voltage from the drain terminal, it performs a voltage amplification operation similar to that of a common gate type amplification element. As a result, the differential input stage 1 has a DC gain of about 60 dB by itself. In this embodiment, the MOSFET Q6. Q
A pre-buffer 2a with a PMO5 input and a pre-buffer 2b with an NMOS input, which operate in response to a drain voltage of 7, are provided.

The pre-buffer 2a is a pair of P-channel type differential MO3Fs.
ET Q21. Q22 and a current mirror type load MO connected between its drain terminal and the power supply voltage vDD.
5FET Q23. This is a differential amplifier circuit consisting of a constant current MOSFET Q24 and a constant current MOSFET Q25 connected to a common source terminal. Further, the pre-buffer 2b has a pair of N
Channel type differential MOSFET Q26. Q27 and
A current mirror type load MO3FET connected between its drain terminal and ground point Q28. Q29 and
Constant current MOSFETQ2 connected to common source terminal
This is a differential amplifier circuit consisting of 0 and 0.

In this embodiment, the load MO5FET of the pre-buffer 2a
MOSFET between the drain terminals of Q23 and Q24
Q41 is also the load MOSFET of the pre-buffer 2b.
MOSFET in Q28, Q29 and (7) rffl
Q42 are connected to each other.

The gate terminals of the MOSFETs Q41 and Q42 are kept on at all times by applying a ground potential and a power supply voltage vDD, respectively, and function as resistance elements.

In this embodiment, the gains of pre-buffers 2a and 2b are set to 1 odB or less by adjusting the on-resistances of MOSFETs Q41 and Q42.

The single-end outputs of these pre-buffers 2a and 2b are output to the output MOSFET Q of the push-pull output stage 3.
31. They are respectively supplied to the gate terminals of Q32.

As a result, the pre-buffers 2a and 2b operate as a level shifter with a low gain and provide an appropriate bias point to the MOSFET in the output stage.

In the above pre-buffers 2a and 2b, MOSFET
Q41. If Q42 is provided and the gain is not suppressed by its on-resistance, assuming an input offset of 5 mV to both pre-buffers, a variation of about 500 mV, which is 100 times that amount, will occur on the output side of the pre-buffers. Therefore, the MOS
The bias points of FETs Q31 and Q32 fluctuated greatly, and in the direction of approaching each other, they swung by nearly 1V, and at this time, the bias points of MOSFET Q31. A large current flows through Q32. On the other hand, if it swings away from you.

Almost no current flows through the output stage 3, and desired characteristics cannot be obtained. However, in the above embodiment, since the gains of the pre-buffers 2a and 2b are suppressed by the on-resistance of the MOS, even if the input offset is assumed to be 5 mV, the variation on the output side of the pre-buffers can be suppressed to about 30 mV. Therefore, the influence this has on the characteristic variations of the output stage is relatively small. By appropriately controlling the gain of the pre-buffer in this way, characteristic variations can be suppressed and
The characteristic of the amplifier of this embodiment is that it achieves a balance with the drive capacity.

FIG. 2 shows a configuration example of a bias circuit with small process variations suitable for the buffer amplifier of the above embodiment.

That is, this bias circuit applies a voltage generated by a reference voltage generation circuit 5 that generates a reference voltage V r e f such as 1.2V to a non-inverting amplifier 7 having a variable resistor 6 that can be trimmed by a fuse or the like. It generates a constant voltage Vs such as 2.2V.

Then, this constant voltage Va is applied to a diode-connected MOSFE
TQ52 is connected to the gate of N-channel MOSFET Q51, whose drain is connected as a load. Along with this, a MOSFET Q53 connected with the above MOSFET Q52 in a current mirror is provided, and this MOSFET
MOSF with diode connected to the drain of ET Q53
ET Q54 and Q55 are connected in series and designed so that the currents flowing through Q52 and Q53 are the same (Is□).

Furthermore, the drain voltage of MOSFET Q53 is transferred to an N-channel MOSFET whose drain is connected as a load to the diode-connected MOSFET Q57.
In addition to entering the gate of Q56, the above MO3FET
MOSFET connected with Q57 by current mirror
058 is provided, and a diode-connected MOSFET Q59 is connected in series to the drain of this MOSFET Q58, so that the currents flowing through Q57 and 058 are the same (IB2
).

Then, the drain voltages of the MO5FETs Q56 and Q59 are changed to the bias voltage In1. As In2, a constant current MOSFET Q3. QIO, Qll and Q25. Q2
0 gate terminal to flow a bias current determined by the size of the MOS.

In the bias circuit of Fig. 2, MOSFET Q
51. Q54. Q55. The W/L ratio (ratio of gate width to gate length) of Q56 is β0. β2. β3゜β, Toki, β
When designed so that 2=β□=4β1, the MOSFET
The current In flowing through Q5 is determined by the following equation. As a result, the generated bias voltage V B1
1 V B2 is MOSFET due to process variation
A highly stable bias circuit that does not depend on variations in the threshold voltage Vth but only on the temperature coefficient can be obtained.

In the above embodiment, the load MOSFETs Q23, Q24 and Q28 . MOSFET between the drain terminals of Q29
Q41. Although the on-resistance of Q42 is included, the gain may be controlled by other circuit systems. For example, if the gain of pre-buffers 2a and 2b is only 1, MOSFET Q41. Q42 and MO3
By omitting the current mirror connections of FETQ23 and Q24 and Q28 and Q29, Q23. Q24 and Q28. Q29 may be simply a diode-connected load MO5FET.

Furthermore, in the above embodiment, the input stage 1 is an N-channel MOSFET.
The one shown here consists of an NMO3 input differential amplifier circuit with ET as the input transistor, but the P-channel M
Needless to say, the present invention can also be applied to a buffer amplifier using a PMO 8-input differential amplifier circuit in the input stage with an OSFET as the input transistor.

As explained above, the above embodiment uses a loaded cascode differential amplifier in the input stage, and a PMO5 in the subsequent stage.
A pre-buffer consisting of an input differential amplification stage and an NMO5 input differential amplification stage is provided as a level shifter, and a current mirror-connected load MOS in these pre-buffers is provided.
A resistor is inserted between the drain terminals of each FET to suppress the gain of the pre-buffer to about 10 dB or less, and this low-gain pre-buffer is used to control each output MO5F of the push-pull output stage.
I decided to drive each ET.

Variations in the bias point of the output stage due to pre-buffer input offset variations can be suppressed within a practical tolerance range, and a circuit with high resistance to dependence on various parameters during mass production can be provided. This has the effect of realizing a class AB amplifier with stable power and characteristics, low power consumption, and large drive capability.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, although phase compensation is not mentioned in the above embodiment, the output terminal OUT and the output MO3FETQ31. Between the gate terminal of Q32 or the output terminal OUT and the output node n of input stage 1. A capacitor or resistor for phase compensation may be inserted between the two.

In the above explanation, the invention made by the present inventor was mainly explained using an example in which the invention was applied to a transmitting buffer amplifier for driving a subscriber line, which is the field of application in which the invention was made, but this invention is not limited to that. Instead, buffer amplifiers that drive low impedance loads can generally be used.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, it is possible to realize a buffer amplifier with AB class operation that can stably drive a low impedance load with low power consumption using the minimum size output MO3FET.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a buffer amplifier according to the present invention. FIG. 2 is a circuit diagram showing a configuration example of a bias circuit suitable for this purpose. FIG. 3 is a circuit diagram showing an example of a conventional buffer amplifier. 1...Input stage, 2a, 2b...Pre-buffer (
level shift stage), 3...output stage, 4...bias circuit. λ

Claims (1)

[Claims] 1. A differential input stage, a push-pull type output stage, and level-shifting the output of the differential input stage and transmitting the level-shifted output to the output stage,
In an operational amplifier comprising a level shift stage that performs push-pull operation, the level shift stage is a differential amplifier having a pair of P-channel MOSFETs as input transistors and a differential amplifier having a pair of N-channel MOSFETs as input transistors. a current mirror type load MO configured and connected to each input transistor pair;
An operational amplifier characterized in that a resistor is connected between the drain terminals of each pair of SFETs to suppress the gain thereof. 2. The operational amplifier according to claim 1, wherein the resistor is formed using an on-resistance of a MOSFET. 3. The differential input stage includes a differential amplifier, a gate-grounded MOSFET whose source terminal receives the output of the differential amplifier circuit, and outputs it from its drain terminal, and this MOS
3. The operational amplifier according to claim 1, wherein the operational amplifier is a loaded cascode differential amplifier circuit comprising an amplification stage having a current source that supplies a bias current to the FET.