JP4029958B2 - Semiconductor circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor circuit constituting a differential amplifier circuit and a current mirror circuit.
[0002]
[Prior art]
FIG. 12 is a diagram showing a configuration of a general differential amplifier circuit. The commonly connected source terminals of the NMOS transistors 11 and 12 are connected to the current source 13. Load resistors 16 and 17 are connected to the drain terminals of the transistors 11 and 12, respectively. The current amount of the current source 13 is equal to the sum of the current amounts flowing in the transistors 11 and 12. A bias voltage Vb higher than the threshold voltage of the transistors 11 and 12 is applied to the gate terminals of the transistors 11 and 12.
[0003]
Here, ΔV is input to the transistors 11 and 12 as a differential signal, the input voltage to the gate terminal of the transistor 11 is increased by ΔV / 2, and the input voltage to the gate terminal of the transistor 12 is ΔV / 2. Suppose that it only decreased. At this time, the drain currents of the transistors 11 and 12 are determined by the change in the gate voltage and the mutual conductance. That is, the drain current of the transistor 11 increases by “mutual conductance × ΔV”, and the drain voltage of the transistor 12 decreases by “mutual conductance × ΔV”. As a result, the drain voltage changes depending on the current flowing through the load resistors 16 and 17.
[0004]
That is, the voltage difference ΔV input to the two gate terminals is amplified and appears as a drain voltage difference. At this time, the relationship between the gate voltage difference and the drain voltage difference is:
Drain voltage difference = Gate voltage difference x Mutual conductance x Output resistance (1)
Represented by Here, the mutual conductance is obtained by differentiating the drain current with respect to the gate voltage, and represents the increasing rate of the drain current with respect to the change of the gate voltage. The output resistance is equivalent to that in which the drain resistance and the load resistance of the transistor are connected in parallel.
[0005]
On the other hand, FIG. 13 is a diagram showing a configuration of a general current mirror circuit. The drain terminal and gate terminal of the NMOS transistor 21 and the gate terminal of the NMOS transistor 22 are connected to the current source 23. The source terminals of both transistors 21 and 22 are commonly connected to ground.
[0006]
In the current mirror circuit, a current having the same magnitude as the current I21 flowing through the transistor 21 is passed through the transistor 22 as I22. If the drain resistance of the transistors 21 and 22 is large, the drain voltage dependency of the drain current is small. Therefore, even if the drain voltages of both the transistors 21 and 22 are different, the same gate voltage is applied, so that the transistor 22 flows. The current I22 is almost equal to the current I21 flowing through the transistor 21.
[0007]
[Problems to be solved by the invention]
Both the differential amplifier circuit and the current mirror circuit use a large drain resistance of a transistor, but the drain resistance is small in a fine process. That is, a MOS transistor with a short channel length produced by a current fine process has a low drain resistance due to the short channel effect. For this reason, when a fine process is used, a high gain cannot be obtained with the differential amplifier circuit as shown in FIG. 12, and an error in the current flowing through two transistors in the current mirror circuit as shown in FIG. Which are particularly noticeable at low power supply voltages.
[0008]
The present invention has been made in view of the above points, and an object of the present invention is to increase the drain resistance equivalently by reducing the drain voltage dependency of the drain current, and to achieve a high gain differential even at a low power supply voltage. This is to realize a current mirror circuit close to the ideal characteristic with the amplifier circuit.
[0009]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the invention of claim 1 is characterized in that the source terminals of the first and second MOS transistors are connected in common , the body terminal of the first MOS transistor, the drain terminal of the second MOS transistor, And a drain terminal of the first MOS transistor and a body terminal of the second MOS transistor are connected to form a semiconductor circuit.
A second aspect of the present invention, in claim 1, and a semiconductor circuit, characterized by comprising connecting a current source between before Symbol source terminal and the power supply terminal of the common connection of the first and second MOS transistors.
A third aspect of the present invention, in claim 1, the gate terminal of the pre-Symbol first and second MOS transistors are commonly connected, and connecting the drain terminal of the gate terminal connected said common first MOS transistor Thus, the semiconductor circuit is characterized.
According to a fourth aspect of the present invention, the source terminals of the first and second MOS transistors are connected in common , the body terminal of the first MOS transistor is connected to the drain terminal of the second MOS transistor, and the first terminal is connected to the first MOS transistor. the opening between the drain terminal of the MOS transistor and the body terminal of said second MOS transistor, the gate terminal of the pre-Symbol first and second MOS transistors connected in common, said the and gate terminal connected said common first The semiconductor circuit is characterized in that it is connected to the drain terminal of one MOS transistor.
According to a fifth aspect of the present invention, in the second aspect, the drain terminals of the third and fourth MOS transistors are connected to the drain terminals of the first and second MOS transistors, respectively, and the body terminal of the third MOS transistor wherein a drain terminal of the fourth MOS transistor is connected, to connect the body terminal of the third drain terminal and the fourth MOS transistor of the MOS transistor, the third MOS transistor and a fourth MOS and The semiconductor circuit is characterized in that the gate terminals of the transistors are connected in common, and the commonly connected gate terminal and the drain terminal of the third MOS transistor are connected.
According to a sixth aspect of the present invention, in the second aspect, the drain terminals of the third and fourth MOS transistors are connected to the drain terminals of the first and second MOS transistors, respectively, and the body terminal of the third MOS transistor Are connected to the drain terminal of the fourth MOS transistor, the drain terminal of the third MOS transistor and the body terminal of the fourth MOS transistor are opened, and the third MOS transistor and the fourth MOS transistor are connected to each other . The gate terminals of the MOS transistors are commonly connected, and the commonly connected gate terminal is connected to the drain terminal of the third MOS transistor.
A seventh aspect of the present invention is directed to the fifth MOS transistor according to the second, fifth, or sixth aspect, wherein the current source includes a fifth MOS transistor having a drain terminal connected to a commonly connected source terminal of the first and second MOS transistors. The fifth MOS transistor and a sixth MOS transistor having a gate terminal connected in common, and connecting the body terminal of the fifth MOS transistor and the drain terminal of the sixth MOS transistor, A drain terminal of the fifth MOS transistor and a body terminal of the sixth MOS transistor , a gate terminal commonly connected to the fifth MOS transistor and the sixth MOS transistor, and a drain terminal of the sixth MOS transistor; connect the door, wherein a sixth source terminal of the MOS transistor of the sixth MOS transistor To become commonly connecting the source terminal and the semiconductor circuit according to claim.
The invention of claim 8 is the seventh MOS transistor according to claim 2, 5 or 6, wherein the current source is a seventh MOS transistor having a drain terminal connected to a source terminal commonly connected to the first and second MOS transistors. The seventh MOS transistor and an eighth MOS transistor having a gate terminal connected in common, and opening between the body terminal of the seventh MOS transistor and the drain terminal of the eighth MOS transistor, The drain terminal of the seventh MOS transistor is connected to the body terminal of the eighth MOS transistor , and the gate terminal commonly connected to the seventh MOS transistor and the eighth MOS transistor is connected to the eighth MOS transistor. and connecting the drain terminal, said source terminal of the seventh MOS transistor eighth MOS transient It was a semiconductor circuit, characterized in comprising commonly connecting the source terminals of the motor.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
FIG. 1 is a diagram showing a configuration of a differential circuit according to the first aspect of the present invention. The source terminals of the NMOS transistors 11 and 12 are connected in common, the drain terminal of the transistor 11 is connected to the body terminal of the transistor 12, and the drain terminal of the transistor 12 is connected to the body terminal of the transistor 11.
[0016]
FIG. 2 is a diagram showing a circuit configuration of the invention of claim 2 in which a current source 13 is connected between a common source terminal of the transistors 11 and 12 of the circuit configuration of FIG. 1 and ground (one power supply terminal). In the configuration of FIG. 2, since the sum of the drain currents of both transistors 11 and 12 is constant, a gate voltage difference or a drain current difference appears as a drain voltage difference.
[0017]
When used as a differential amplifier circuit, as shown in FIG. 3, current sources 14 and 15 are connected to the drain terminals of the transistors 11 and 12, and differential signals are input to the two gate terminals. At this time, if the currents of the current sources 14 and 15 are I, the current of the current source 13 is 2I.
[0018]
When the drain voltage of one of the transistors 11 and 12 decreases in accordance with the differential signal at the gate terminals, the other drain voltage increases. When the drain voltage decreases, the drain current decreases due to the influence of the drain resistance. However, the potential of the other drain terminal to which the body terminal is connected is rising. When the potential of the body terminal increases, the threshold voltage of the transistor decreases due to the substrate bias effect, and the drain current increases. Accordingly, the change in the drain current is reduced by the decrease in the drain current due to the decrease in the drain voltage and the increase in the drain current due to the decrease in the threshold voltage. Conversely, when the drain voltage increases, the drain current increases. However, since the other drain voltage decreases, the potential of the body terminal decreases and the drain current decreases.
[0019]
As described above, since the change in the drain current due to the change in the drain voltage can be kept small, the drain resistance is equivalently increased. Since the DC gain of the differential amplifier is “mutual conductance × output resistance” as shown in the above equation (1), according to this configuration, the drain resistance is equivalently increased, so that the output resistance is increased. A large DC gain can be obtained.
[0020]
In FIG. 3, the current sources 14 and 15 connected to the drain sides of the two transistors 11 and 12 may be replaced with resistors 16 and 17 as shown in FIG. Further, as shown in FIG. 5, an active load constituted by a current mirror circuit composed of PMOS transistors 18 and 19 may be substituted. Furthermore, in the differential circuit shown in the first embodiment, the differential pair is configured by an NMOS transistor, but this may be replaced by a PMOS transistor. The active load at this time is configured as a current mirror circuit of an NMOS transistor.
[0021]
[Second Embodiment]
FIG. 6 is a diagram showing the configuration of the current mirror circuit according to the third aspect of the present invention. Here, the gate terminals of the NMOS transistors 21 and 22 having the source terminals connected in common are connected in common, the gate terminals are connected to the drain terminal of the transistor 21 and the common connection point of the current source 23, and the body terminal of the transistor 21 and The drain terminal of the transistor 22 is connected, and the body terminal of the transistor 22 and the drain terminal of the transistor 21 are connected.
[0022]
As described above, by connecting the body terminal of one transistor with a common gate connected to the drain terminal of the other transistor and connecting the body terminal of the other transistor to the drain terminal of the one transistor, Drain resistance increases. Therefore, the drain current is constant without depending on the change of the drain voltage, and a current mirror circuit close to ideal characteristics can be realized.
[0023]
Although the current mirror circuit is composed of NMOS transistors 21 and 22, it may be replaced with a PMOS transistor. Further, by setting the size of the transistor 22 on the output side to n times the size of the transistor 21, the current I22 can be made n times I21.
[0024]
[Third Embodiment]
FIG. 7 is a diagram showing a configuration of a constant current source circuit according to the fourth aspect of the present invention. Here, a constant current source circuit using a current mirror circuit is cited. For the NMOS transistor 21 in which the current source 23 is connected to the drain terminal and the gate terminal, the gate terminal of the NMOS transistor 22 is connected to the gate terminal of the transistor 21 and the drain terminal is connected to the body terminal of the transistor 21.
[0025]
By supplying a constant current I21 from the current source 23, a current can be supplied to the circuit block by the transistor 22 by the current mirror action. At this time, since the drain voltage of the transistor 21 having the drain terminal and the gate terminal connected in common is constant, the drain terminal of the transistor 21 does not need to be connected to the body terminal of the transistor 22 serving as a current source to the circuit block. .
[0026]
Note that by making the size of the transistor 22 n times larger than the size of the transistor 21, I22 can be made n times larger than I21.
[0027]
[Fourth Embodiment]
FIG. 8 shows a differential amplifier circuit (first embodiment) connected to the active load shown in FIG. 5 in which the active load is replaced with a current mirror circuit (second embodiment) composed of PMOS transistors 24 and 25. It is a differential amplifier circuit. This active load may be replaced with the current mirror circuit (third embodiment) of FIG. FIG. 9 shows a differential amplifier circuit in which the load resistors 16 and 17 are replaced with current mirror circuits (second embodiment) composed of PMOS transistors 24 and 25 in the conventional differential amplifier circuit shown in FIG. It is. With this configuration, a high gain differential amplifier circuit can be realized.
[0028]
[Fifth Embodiment]
FIG. 10 shows a differential amplifier circuit in which the current source 13 of the differential amplifier circuit (first embodiment) in FIG. 3 is replaced with the current mirror circuit (second embodiment) in FIG. The current source 13 may be replaced with the current mirror circuit (third embodiment) shown in FIG. With this configuration, a high gain differential amplifier circuit can be realized.
[0029]
[Sixth Embodiment]
FIG. 11 shows the differential amplifier circuit shown in FIG. 10 (fifth embodiment), in which the current sources 14 and 15 are replaced with active loads of a current mirror circuit (second embodiment) composed of PMOS transistors 24 and 25. Is. As the active load, a circuit in which the transistor polarity of the current mirror circuit (third embodiment) in FIG. 7 is P-type can be used. With this configuration, a high gain differential amplifier circuit can be realized.
[0030]
【The invention's effect】
As described above, according to the present invention, the drain resistance can be increased equivalently, so that even if the power supply voltage is low, a large DC gain can be obtained if used in a differential amplifier circuit. If used, there is an advantage that characteristics close to ideal characteristics can be obtained.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a differential circuit according to a first embodiment.
2 is a circuit diagram of a differential circuit in which a current source is attached to a common source terminal of the differential circuit of FIG. 1;
3 is a circuit diagram of a differential amplifier circuit in which a current source is attached to each drain terminal of the differential circuit of FIG. 2;
4 is a circuit diagram of a differential amplifier circuit in which the current source at the drain terminal of the differential amplifier circuit of FIG. 3 is replaced with a load resistor.
5 is a circuit diagram of a differential amplifier circuit in which a current source at a drain terminal of the differential amplifier circuit of FIG. 3 is replaced with an active load including a current mirror circuit.
FIG. 6 is a circuit diagram of a current mirror circuit of a second embodiment.
FIG. 7 is a circuit diagram of a constant current source circuit according to a third embodiment.
FIG. 8 is a circuit diagram of a differential amplifier circuit according to a fourth embodiment.
FIG. 9 is a circuit diagram of a modification of the differential amplifier circuit of the fourth embodiment.
FIG. 10 is a circuit diagram of a differential amplifier circuit according to a fifth embodiment.
FIG. 11 is a circuit diagram of a differential amplifier circuit according to a sixth embodiment.
FIG. 12 is a circuit diagram of a conventional differential amplifier circuit.
FIG. 13 is a circuit diagram of a conventional current mirror circuit.
[Explanation of symbols]
11, 12: NMOS transistor, 13, 14, 15: current source, 16, 17: load resistance, 18, 19: PMOS transistor 21, 22: NMOS transistor, 23: current source

Claims (8)

The source terminals of the first and second MOS transistors are connected in common , the body terminal of the first MOS transistor and the drain terminal of the second MOS transistor are connected, and the drain terminal of the first MOS transistor A semiconductor circuit comprising a body terminal of the second MOS transistor connected thereto. In claim 1,
Semiconductor circuit, characterized in that formed by connecting the current source between the source terminal and the power supply terminal of the pre-Symbol common connection of the first and second MOS transistors. In claim 1,
Before SL commonly connecting the gate terminals of the first and second MOS transistors, and semiconductor circuit, characterized in that formed by connecting the drain terminal of the gate terminal connected said common first MOS transistor. The source terminals of the first and second MOS transistors are connected in common , the body terminal of the first MOS transistor and the drain terminal of the second MOS transistor are connected, and the drain terminal of the first MOS transistor said second opening between the body terminals of MOS transistors, before Symbol gate terminals of the first and second MOS transistors are commonly connected, and a drain terminal of the gate terminal connected said common first MOS transistor A semiconductor circuit characterized by being connected to each other. In claim 2,
The drain terminals of the third and fourth MOS transistors are connected to the drain terminals of the first and second MOS transistors, respectively, and the body terminal of the third MOS transistor and the drain terminal of the fourth MOS transistor are connected to each other. Connecting the drain terminal of the third MOS transistor and the body terminal of the fourth MOS transistor , connecting the gate terminals of the third MOS transistor and the fourth MOS transistor in common, and connecting the common connection A semiconductor circuit comprising a gate terminal connected to a drain terminal of the third MOS transistor. The drain terminal of each of the first and second MOS transistors is connected to the drain terminals of the third and fourth MOS transistors, respectively, and the body terminal of the third MOS transistor and the fourth MOS transistor are connected. A drain terminal of the third MOS transistor, and a body terminal of the fourth MOS transistor is opened between the drain terminal of the third MOS transistor and the gate terminals of the third MOS transistor and the fourth MOS transistor. A semiconductor circuit comprising a common connection and a gate terminal connected in common and a drain terminal of the third MOS transistor. The current source according to claim 2, 5 or 6,
A fifth MOS transistor having a drain terminal connected to a commonly connected source terminal of the first and second MOS transistors; a sixth MOS transistor having a gate terminal commonly connected to the fifth MOS transistor; And connecting the body terminal of the fifth MOS transistor and the drain terminal of the sixth MOS transistor, and connecting the drain terminal of the fifth MOS transistor and the body terminal of the sixth MOS transistor. A gate terminal commonly connected to the fifth MOS transistor and the sixth MOS transistor is connected to a drain terminal of the sixth MOS transistor, and a source terminal of the sixth MOS transistor is connected to the sixth MOS transistor. A semiconductor circuit characterized by being commonly connected to the source terminal of the circuit. The current source according to claim 2, 5 or 6,
A seventh MOS transistor having a drain terminal connected to a commonly connected source terminal of the first and second MOS transistors; an eighth MOS transistor having a gate terminal commonly connected to the seventh MOS transistor; The body terminal of the seventh MOS transistor and the drain terminal of the eighth MOS transistor are opened, and the drain terminal of the seventh MOS transistor and the body terminal of the eighth MOS transistor are connected to each other. connected, the seventh MOS transistor is connected to the and the drain terminal of the eighth MOS transistor connected in common to the gate terminal of the eighth MOS transistor of the seventh MOS transistor of the source terminal and the eighth semiconductor times, characterized in that the source terminal of the MOS transistor formed by common connection .

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