JP4662704B2 - Cvd法によって誘電体材料上に均一でかつ制御されたサイズの半導体材料のナノ構造を形成する方法 - Google Patents
Cvd法によって誘電体材料上に均一でかつ制御されたサイズの半導体材料のナノ構造を形成する方法 Download PDFInfo
- Publication number
- JP4662704B2 JP4662704B2 JP2003392551A JP2003392551A JP4662704B2 JP 4662704 B2 JP4662704 B2 JP 4662704B2 JP 2003392551 A JP2003392551 A JP 2003392551A JP 2003392551 A JP2003392551 A JP 2003392551A JP 4662704 B2 JP4662704 B2 JP 4662704B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor material
- precursor
- nanostructure
- cvd
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000002086 nanomaterial Substances 0.000 title claims description 94
- 239000000463 material Substances 0.000 title claims description 59
- 239000004065 semiconductor Substances 0.000 title claims description 59
- 238000005229 chemical vapour deposition Methods 0.000 title claims description 50
- 238000000034 method Methods 0.000 title claims description 47
- 239000003989 dielectric material Substances 0.000 title claims description 17
- 239000002243 precursor Substances 0.000 claims description 52
- 229910052710 silicon Inorganic materials 0.000 claims description 52
- 239000010703 silicon Substances 0.000 claims description 52
- 239000000758 substrate Substances 0.000 claims description 43
- 229910052732 germanium Inorganic materials 0.000 claims description 36
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 36
- 238000000151 deposition Methods 0.000 claims description 30
- 230000008021 deposition Effects 0.000 claims description 23
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 14
- 229910000077 silane Inorganic materials 0.000 claims description 14
- 229910000078 germane Inorganic materials 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 claims description 6
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 5
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052691 Erbium Inorganic materials 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910008051 Si-OH Inorganic materials 0.000 claims description 3
- 229910006358 Si—OH Inorganic materials 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 50
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 238000009826 distribution Methods 0.000 description 10
- 230000012010 growth Effects 0.000 description 9
- 230000006911 nucleation Effects 0.000 description 9
- 238000010899 nucleation Methods 0.000 description 9
- 239000000377 silicon dioxide Substances 0.000 description 9
- 239000012686 silicon precursor Substances 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- 239000002159 nanocrystal Substances 0.000 description 5
- 230000003698 anagen phase Effects 0.000 description 3
- 230000014759 maintenance of location Effects 0.000 description 3
- 210000000352 storage cell Anatomy 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 101000635799 Homo sapiens Run domain Beclin-1-interacting and cysteine-rich domain-containing protein Proteins 0.000 description 2
- 102100030852 Run domain Beclin-1-interacting and cysteine-rich domain-containing protein Human genes 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010494 dissociation reaction Methods 0.000 description 2
- 230000005593 dissociations Effects 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 241000396922 Pontia daplidice Species 0.000 description 1
- -1 Si 3 N 4 Inorganic materials 0.000 description 1
- 238000004581 coalescence Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 239000002096 quantum dot Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/04—Coating on selected surface areas, e.g. using masks
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/60—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape characterised by shape
- C30B29/605—Products containing multiple oriented crystallites, e.g. columnar crystallites
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/0242—Crystalline insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02513—Microstructure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
- H01L21/02645—Seed materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/967—Semiconductor on specified insulator
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Nanotechnology (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Ceramic Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Mechanical Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Chemical Vapour Deposition (AREA)
- Electrodes Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
Description
本発明はさらに、本発明による方法で得られたナノ構造を有する装置に関するものである。
このように形成されたナノ構造は、電子、光学又は電子光学装置、特に量子ドットを利用するクーロンブロッケイド装置を作製することを意図したものである。
本発明が特にターゲットにしている用途は粒状ゲート記憶(ストレージ)セルや、ナノ構造を利用する電界効果トランジスタであるDOTFETである。
−CVDによって第1の半導体材料の前駆体からアイランド状の第1の半導体材料の安定な核を基板上に形成する段階であって、第1の半導体材料の前駆体は前記核の形成を可能とするように選択されているところの段階と、
−CVDによって前記核の上にだけ第2の半導体材料が選択的に堆積されるように選択された前駆体を用いて、第1の半導体材料の安定核から第2の半導体材料のナノ構造を形成する段階と、を備えている。
用いた共堆積又は注入によってドーピングしてもよい。
−安定なシリコン核が誘電体基板上に堆積される第1の段階(図2A)、
−誘電体基板上に代わって、第1の段階で形成された核の上にゲルマニウムのナノ構造を選択的に成長させる第2の段階(図2B)。
[1]T. BARON, F. MARTIN., P. MUR, C. WYON, Journal of Crystal Gwoeth, 209, 1004-1008 (2000)
[2]H. ISHI, Y. TAKAHASHI, J. MUROTA, Applied Physics Letters, 47, 863-865 (1985)
[3]OZTURK, MEHMET, WORTMAN, JUMMIE, 米国特許第5 250 452号明細書
[4]M.N. SEMERITA, P. MUR, F. MARTIN, F. FOURNEL, H. MORICEAU, J. EYMERY, N. MAGNEA, T. BARON, 仏国特許出願第2 815 026号明細書
[5]S. MADHUKAR, K. SMITH, R. MURALIDHAR, D. O'MERAR, M. SADO, B-Y NGUYEN, B. WHITE, B. JONES, Material Research Society Symposium proceeding 638, F 5. 2. 1 (2001)
12 基板
14 核
16A,16B ナノ構造
21 前駆体
Claims (14)
- 化学的気相堆積法(CVD)によって、誘電体材料上に半導体材料のナノ構造を形成する方法であって:
−基板(12)上に、CVDによって第1の半導体材料の前駆体(11)から第1の半導体材料の安定核(14)を形成する段階であって、前記第1の半導体材料の前駆体は誘電体材料(12)が前記核(14)の形成を可能とするように選択されているところの段階と、
−CVDによって前記核(14)の上にだけ第2の半導体材料が選択的に堆積されるように選択された前駆体(21)を用いて、第1の半導体材料の安定核(14)から第2の半導体材料のナノ構造(16A,16B)を形成する段階と、を備えており、
前記第1及び第2の半導体材料はシリコンであり、及び前記第2の半導体材料の前駆体(21)はジクロロシランであることを特徴とする方法。 - 化学的気相堆積法(CVD)によって、誘電体材料上に半導体材料のナノ構造を形成する方法であって:
−基板(12)上に、CVDによって第1の半導体材料の前駆体(11)から第1の半導体材料の安定核(14)を形成する段階であって、前記第1の半導体材料の前駆体は誘電体材料(12)が前記核(14)の形成を可能とするように選択されているところの段階と、
−CVDによって前記核(14)の上にだけ第2の半導体材料が選択的に堆積されるように選択された前駆体(21)を用いて、第1の半導体材料の安定核(14)から第2の半導体材料のナノ構造(16A,16B)を形成する段階と、を備えており、
前記第1の半導体材料はシリコンであり、第2の半導体材料はゲルマニウムであり、及び前記第2の半導体材料の前駆体(21)はゲルマンであることを特徴とする方法。 - 誘電体材料基板(12)は、第1の半導体材料の前駆体(11)に対してできるだけ反応性が高くなるように選択された請求項1または2に記載の方法。
- 前記誘電体材料基板(12)は、SiO2、表面に高密度のSi−OH基を有するSiO2、Si3N4、Al2O3、及びHfO2から成る群から選択された請求項1または2に記載の方法。
- 第1の半導体材料の安定核(14)を形成する段階は、所望の核密度の関数として選択された曝露時間の間実施する請求項1または2に記載の方法。
- 第2の半導体材料のナノ構造(16A)を形成する段階は、所望サイズのナノ構造(16B)の関数として選択された曝露時間の間実施する請求項1または2に記載の方法。
- 前記段階は、前駆体(11,21)の低い分圧で実施する請求項1または2に記載の方法。
- 第1の半導体材料の前駆体(11)はシランである請求項1または2に記載の方法。
- 第1の半導体材料の核(14)の形成は、温度550℃から700℃の間の温度でかつシランの133 Pa(1 Torr)以下の低い分圧で実施する請求項8に記載の方法。
- 第1の半導体材料の安定核(14)を形成する段階を1.33 Pa(10 mTorr)以下の分圧で実施し、第1の半導体材料の前駆体(11)を基板に曝露する時間は15分以下である請求項8に記載の方法。
- 第1の半導体材料の安定核(14)を形成する段階を133 Pa(1 Torr)以下の分圧で実施し、第1の半導体材料の前駆体(11)を基板に曝露する時間は1分以下である請求項8に記載の方法。
- ナノ構造(16A)を形成する段階は、300℃から1000℃の間の温度でかつ133 Pa(1 Torr)以下の前駆体(21)の分圧で実施する請求項1または2に記載の方法。
- ホウ素、リン、砒素及びエルビウムの中から選択される元素を共堆積又は注入によって前記ナノ構造にドーピングする段階をさらに備えている請求項1または2に記載の方法。
- 誘電体の堆積によって前記ナノ構造を被覆する段階をさらに備えている請求項1または2に記載の方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0214658A FR2847567B1 (fr) | 2002-11-22 | 2002-11-22 | Procede de realisation par cvd de nano-structures de materiau semi-conducteur sur dielectrique, de tailles homogenes et controlees |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004179658A JP2004179658A (ja) | 2004-06-24 |
JP4662704B2 true JP4662704B2 (ja) | 2011-03-30 |
Family
ID=32241521
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003392551A Expired - Fee Related JP4662704B2 (ja) | 2002-11-22 | 2003-11-21 | Cvd法によって誘電体材料上に均一でかつ制御されたサイズの半導体材料のナノ構造を形成する方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6946369B2 (ja) |
EP (1) | EP1426328B1 (ja) |
JP (1) | JP4662704B2 (ja) |
KR (1) | KR101060304B1 (ja) |
FR (1) | FR2847567B1 (ja) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100236705A1 (en) * | 2000-07-18 | 2010-09-23 | Chou Stephen Y | Fluidic and Microdevice Apparatus and Methods For Bonding Components Thereof |
WO2005093798A1 (ja) | 2004-03-26 | 2005-10-06 | Nissin Electric Co., Ltd. | シリコンドット形成方法及びシリコンドット形成装置 |
US7785922B2 (en) * | 2004-04-30 | 2010-08-31 | Nanosys, Inc. | Methods for oriented growth of nanowires on patterned substrates |
KR100644219B1 (ko) * | 2004-09-16 | 2006-11-10 | 주식회사 피앤아이 | 나노 입자의 형성방법, 그의 장치 및 그의 응용제품 |
US20060189079A1 (en) * | 2005-02-24 | 2006-08-24 | Merchant Tushar P | Method of forming nanoclusters |
US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
FR2888833B1 (fr) * | 2005-07-22 | 2007-08-24 | Commissariat Energie Atomique | Procede de realisation d'etalons de bruit de fond diffus comportant des nano-structures sur une couche mince isolante |
US7575978B2 (en) | 2005-08-04 | 2009-08-18 | Micron Technology, Inc. | Method for making conductive nanoparticle charge storage element |
US7989290B2 (en) | 2005-08-04 | 2011-08-02 | Micron Technology, Inc. | Methods for forming rhodium-based charge traps and apparatus including rhodium-based charge traps |
JP4730034B2 (ja) * | 2005-09-20 | 2011-07-20 | 日新電機株式会社 | シリコンドット付き基板の形成方法 |
JP4529855B2 (ja) | 2005-09-26 | 2010-08-25 | 日新電機株式会社 | シリコン物体形成方法及び装置 |
KR100690925B1 (ko) * | 2005-12-01 | 2007-03-09 | 삼성전자주식회사 | 나노 크리스탈 비휘발성 반도체 집적 회로 장치 및 그 제조방법 |
KR101287350B1 (ko) | 2005-12-29 | 2013-07-23 | 나노시스, 인크. | 패터닝된 기판 상의 나노와이어의 배향된 성장을 위한 방법 |
KR100745167B1 (ko) * | 2006-02-13 | 2007-08-01 | 한국표준과학연구원 | 나노 패턴을 이용한 기판 제조방법 |
KR100735534B1 (ko) * | 2006-04-04 | 2007-07-04 | 삼성전자주식회사 | 나노 크리스탈 비휘발성 반도체 집적 회로 장치 및 그 제조방법 |
FR2910176B1 (fr) * | 2006-12-15 | 2009-10-23 | Commissariat Energie Atomique | Procede de realisation d'un dispositif a base de nanocristaux recouverts d'une couche de nitrure deposee par cvd |
US7880241B2 (en) * | 2007-02-23 | 2011-02-01 | International Business Machines Corporation | Low-temperature electrically activated gate electrode and method of fabricating same |
US8367506B2 (en) | 2007-06-04 | 2013-02-05 | Micron Technology, Inc. | High-k dielectrics with gold nano-particles |
WO2009139936A2 (en) * | 2008-02-14 | 2009-11-19 | California Institute Of Technology | Single photon detection with self-quenching multiplication |
US8623288B1 (en) | 2009-06-29 | 2014-01-07 | Nanosys, Inc. | Apparatus and methods for high density nanowire growth |
US9950926B2 (en) * | 2009-11-09 | 2018-04-24 | The University Of Kentucky Research Foundation | Method for production of germanium nanowires encapsulated within multi-walled carbon nanotubes |
FR3103806B1 (fr) | 2019-11-28 | 2021-12-03 | Commissariat Energie Atomique | procédé de réalisation de nanostructure par MOCVD |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5250452A (en) * | 1990-04-27 | 1993-10-05 | North Carolina State University | Deposition of germanium thin films on silicon dioxide employing interposed polysilicon layer |
JPH0620958A (ja) * | 1992-04-10 | 1994-01-28 | Internatl Business Mach Corp <Ibm> | 粗いシリコン表面の形成およびその応用 |
JP2005537660A (ja) * | 2002-08-30 | 2005-12-08 | フリースケール セミコンダクター インコーポレイテッド | ナノ結晶を形成する方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2815026B1 (fr) * | 2000-10-06 | 2004-04-09 | Commissariat Energie Atomique | Procede d'auto-organisation de microstructures ou de nanostructures et dispositif a microstructures ou a nanostructures |
US6872645B2 (en) * | 2002-04-02 | 2005-03-29 | Nanosys, Inc. | Methods of positioning and/or orienting nanostructures |
-
2002
- 2002-11-22 FR FR0214658A patent/FR2847567B1/fr not_active Expired - Fee Related
-
2003
- 2003-11-18 KR KR1020030081411A patent/KR101060304B1/ko not_active IP Right Cessation
- 2003-11-19 US US10/718,109 patent/US6946369B2/en not_active Expired - Lifetime
- 2003-11-21 JP JP2003392551A patent/JP4662704B2/ja not_active Expired - Fee Related
- 2003-11-21 EP EP03104318.5A patent/EP1426328B1/fr not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5250452A (en) * | 1990-04-27 | 1993-10-05 | North Carolina State University | Deposition of germanium thin films on silicon dioxide employing interposed polysilicon layer |
JPH0620958A (ja) * | 1992-04-10 | 1994-01-28 | Internatl Business Mach Corp <Ibm> | 粗いシリコン表面の形成およびその応用 |
JP2005537660A (ja) * | 2002-08-30 | 2005-12-08 | フリースケール セミコンダクター インコーポレイテッド | ナノ結晶を形成する方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20040045308A (ko) | 2004-06-01 |
US20040147098A1 (en) | 2004-07-29 |
EP1426328A2 (fr) | 2004-06-09 |
KR101060304B1 (ko) | 2011-08-29 |
EP1426328A3 (fr) | 2004-06-23 |
EP1426328B1 (fr) | 2018-05-23 |
US6946369B2 (en) | 2005-09-20 |
FR2847567A1 (fr) | 2004-05-28 |
FR2847567B1 (fr) | 2005-07-01 |
JP2004179658A (ja) | 2004-06-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4662704B2 (ja) | Cvd法によって誘電体材料上に均一でかつ制御されたサイズの半導体材料のナノ構造を形成する方法 | |
US7811883B2 (en) | Method of forming a nanowire based non-volatile floating-gate memory | |
US7985454B2 (en) | Systems and methods for nanowire growth and manufacturing | |
US7776760B2 (en) | Systems and methods for nanowire growth | |
TW452856B (en) | Microstructure producing method capable of controlling growth position of minute particle or thin line and semiconductor device employing the microstructure | |
US7560394B2 (en) | Nanodots formed on silicon oxide and method of manufacturing the same | |
KR100723882B1 (ko) | 실리콘 나노점 박막을 이용한 실리콘 나노와이어 제조 방법 | |
US8513641B2 (en) | Core-shell nanowire comprising silicon rich oxide core and silica shell | |
JPH1197667A (ja) | 超微粒子あるいは超細線の形成方法およびこの形成方法による超微粒子あるいは超細線を用いた半導体素子 | |
JP2007235141A (ja) | ナノ結晶を有するメモリ素子及びその製造方法 | |
JP4116790B2 (ja) | シリコン−ゲルマニウム膜の形成方法 | |
US8088674B2 (en) | Method of growing, on a dielectric material, nanowires made of semi-conductor materials connecting two electrodes | |
Gogna et al. | Nonvolatile silicon memory using GeO x-Cladded Ge quantum dots self-assembled on SiO 2 and lattice-matched II–VI tunnel insulator | |
KR20050006632A (ko) | 나노선과 나노튜브 표면에 원자층 증착방법을 사용하여알루미나 박막을 코팅하는 방법 | |
JP2004087888A (ja) | 半球状シリコン微結晶の形成方法 | |
KR101122129B1 (ko) | Si 과잉 산화막을 이용한 Si/SiOx 코어/쉘 이중구조 나노선 제조 방법 | |
Madhukar et al. | CVD growth of Si nanocrystals on dielectric surfaces for nanocrystal floating gate memory application | |
JP2007517136A (ja) | ナノストラクチャーの組織化された成長 | |
JP3525137B2 (ja) | 半導体微粒子集合体の製造方法 | |
Guliants et al. | Self-assembly of spatially separated silicon structures by Si heteroepitaxy on Ni disilicide | |
Kamiya et al. | Modification of the tunneling barrier in a nanocrystalline silicon single-electron transistor | |
JPH02191321A (ja) | 結晶の形成方法 | |
JPS6344720A (ja) | 結晶性堆積膜の形成方法 | |
Kim et al. | Growth of silicon nanocrystals by low-temperature photo chemical vapor deposition | |
Wu | Synthesis, properties, and assembly of semiconductor nanowires and nanowire heterostructures |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060926 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100423 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100511 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20100811 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20100816 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101111 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20101130 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110104 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140114 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |