JP4659571B2 - Ferroelectric memory - Google Patents

Description

  The present invention relates to a ferroelectric memory that stores binary data according to the polarity of polarization of a ferroelectric capacitor, and more particularly to a 1T / 1C (1 transistor / 1 capacitor) type ferroelectric memory.

  A ferroelectric memory stores binary data by saturation polarization of a ferroelectric capacitor provided in a data memory cell, positively or negatively. As such a ferroelectric memory, a 1T / 1C type and a 2T / 2C type are known.

  In the 1T / 1C type ferroelectric memory, one data memory cell is provided with one transistor and one ferroelectric capacitor. Further, in this type of ferroelectric memory, one 1T / 1C type reference memory cell is provided for each bit line. Then, the stored value of the data memory cell is determined by comparing the potential read from the data memory cell (read potential) with the potential read from the reference memory cell (reference potential).

  On the other hand, in the 2T / 2C type ferroelectric memory, two transistors and two ferroelectric capacitors are provided in one data memory cell. In this type of ferroelectric memory, complementary data is written into a ferroelectric capacitor pair. The stored value is determined by comparing the potentials read from the ferroelectric capacitor pair.

  The 1T / 1C type ferroelectric memory has an advantage that the circuit scale is small and high integration is easy. On the other hand, the 1T / 1C type ferroelectric memory has a drawback that the ferroelectric capacitor in the reference memory cell is easily deteriorated. This is because the access frequency to the reference memory cell is much higher than the access frequency to the data memory cell. For example, when 256 data memory cells are connected to one bit line, if the stored data of these data memory cells is read one by one, access to the reference memory cell is 256. Times. This deterioration causes a decrease in the reference potential read from the reference memory cell, which causes a decrease in read data reliability and element lifetime.

  As a technique for suppressing the deterioration of the ferroelectric capacitor, for example, those disclosed in the following Patent Documents 1 to 4 are known.

  In the technique of Patent Document 1, deterioration of the ferroelectric capacitor is suppressed by alternately switching the polarization states of the two ferroelectric capacitors (see paragraphs 0011 and 0059 of Patent Document 1).

  In the technique of Patent Document 2, deterioration of the ferroelectric capacitor is suppressed by providing a paraelectric capacitor in parallel with the ferroelectric capacitor (see Paragraph 0040 of FIG. 1, FIG. 1, etc.).

  In the technique of Patent Document 3, by providing a reference memory cell for each small block, the access frequency to the reference memory cell is reduced, thereby reducing the deterioration of the ferroelectric capacitor provided in the reference memory cell. (Refer to paragraphs 0022 to 0024 of Patent Document 3).

In the technique of Patent Document 4, the frequency of access to the reference memory cell is reduced by switching the reference memory cell every read cycle, thereby reducing the deterioration of the ferroelectric capacitor provided in the reference memory cell. (Refer to paragraph 0061 of Patent Document 4).
JP-A-9-265785 Japanese Patent Laid-Open No. 2000-18789 JP 2002-15562 A JP 2004-87047 A

  However, although the techniques of Patent Documents 1 to 4 described above can suppress the deterioration of the ferroelectric capacitor to some extent, it is not possible to obtain the same life as the data memory cell. For this reason, with these techniques, the reliability of read data cannot be sufficiently improved.

  In the techniques of Patent Documents 3 and 4, the deterioration of the ferroelectric capacitor provided in the reference memory cell can be further reduced by increasing the number of reference memory cells. However, as the number of reference memory cells is increased, the circuit scale increases, and the advantage of the 1T / 1C type ferroelectric memory that high integration is possible is impaired.

  An object of the present invention is to provide a 1T / 1C type ferroelectric memory having high read data reliability and a long element life without increasing the number of reference memory cells.

  (1) The ferroelectric memory according to the first aspect of the present invention is the first when a bit line pair having a first bit line for reading data and a second bit line for reading reference potential is activated and when an equalize signal is activated. An equalizing circuit for conducting the 1 bit line and the second bit line; and when the potential of the first bit line is higher than the potential of the second bit line, a predetermined first potential is applied to the first bit line and When a predetermined second potential lower than the potential is applied to the second bit line and the potential of the first bit line is lower than the potential of the second bit line, the second potential is applied to the first bit line and the first A sense amplifier for applying a potential to the second bit line; a transistor having one main electrode connected to the first bit line and a control electrode connected to the corresponding word line; and one electrode to the other main electrode of the transistor Is connected and A plurality of data memory cells having a ferroelectric capacitor for inputting a plate voltage from the other electrode, and a first SRAM for applying a first potential to the second bit line when the first reference word line is activated The second bit line is set to an intermediate potential between the first and second potentials using the second SRAM cell that applies the second potential to the second bit line when the cell and the second reference word line are activated. And a reference memory cell.

  (2) The ferroelectric memory according to the second aspect of the present invention is the first when a bit line pair having a first bit line for reading data and a second bit line for reading reference potential is activated and an equalize signal is activated. An equalizing circuit for conducting the 1 bit line and the second bit line; and when the potential of the first bit line is higher than the potential of the second bit line, a predetermined first potential is applied to the first bit line and When a predetermined second potential lower than the potential is applied to the second bit line and the potential of the first bit line is lower than the potential of the second bit line, the second potential is applied to the first bit line and the first A sense amplifier for applying a potential to the second bit line; a transistor having one main electrode connected to the first bit line and a control electrode connected to the corresponding word line; and one electrode to the other main electrode of the transistor Is connected and A plurality of data memory cells having a ferroelectric capacitor for inputting a plate voltage from the other electrode; a first EPROM cell for applying a first potential to the second bit line when the reference word line is activated; A reference memory cell that sets the second bit line to an intermediate potential between the first and second potentials using a second EPROM cell that applies a second potential to the second bit line when the reference word line is activated. And have.

(3) A ferroelectric memory according to a third aspect of the present invention includes a bit line pair having a first bit line for reading data and a second bit line for reading reference potential, and when the equalize signal is activated. An equalizing circuit for conducting the 1 bit line and the second bit line; and when the potential of the first bit line is higher than the potential of the second bit line, a predetermined first potential is applied to the first bit line and When a predetermined second potential lower than the potential is applied to the second bit line and the potential of the first bit line is lower than the potential of the second bit line, the second potential is applied to the first bit line and the first A sense amplifier for applying a potential to the second bit line; a transistor having one main electrode connected to the first bit line and a control electrode connected to the corresponding word line; and one electrode to the other main electrode of the transistor Is connected and A plurality of data memory cells having a ferroelectric capacitor for inputting a plate voltage from the other electrode; a first DRAM cell for applying a first potential to the second bit line when the reference word line is activated; A reference memory cell for setting the second bit line to an intermediate potential between the first and second potentials using a second DRAM cell that applies a second potential to the second bit line when the reference word line is activated. It possesses the door, further comprising a first, first, DRAM control circuit for performing a refresh operation after the writing and the writing of the second potential to the first 2DRAM cell.

  According to the first to third aspects of the present invention, two memory cells not using a non-ferroelectric capacitor are connected to one second bit line, thereby connecting the second bit line to the first potential and the second potential. The intermediate potential was set to the potential. Thereby, the reliability of read data and the element life of the ferroelectric memory can be improved.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the size, shape, and arrangement relationship of each component are shown only schematically to the extent that the present invention can be understood, and the numerical conditions described below are merely examples. .

First Embodiment A ferroelectric memory according to a first embodiment of the present invention will be described with reference to the circuit diagram of FIG.

  As shown in FIG. 1, the ferroelectric memory 100 according to this embodiment includes a bit line pair BP1 to BPm, an equalization control line EQL, equalization transistors EQ1 to EQm, a sense amplifier 101, and a data amplifier. Memory cells 102-11 to 102-mn, reference memory cells 103-11 to 103-m2, data word lines WL1 to WLn, and reference word lines WLref1 and WLref2 are provided.

  The bit line pairs BP1 to BPm have first bit lines BL1 to BLm for reading data and second bit lines / BL1 to / BLm for reading reference potential. These bit line pairs BP1 to BPm are arranged corresponding to the respective rows of data memory cells 102-11 to 102-mn.

  The equalizing transistors EQ1 to EQm are turned on when the equalizing control line EQL is set to a high level (here, VCC), and the first and second bit lines BL1 to BLm in the bit line pairs BP1 to BPm are set. , / BL1 to / BLm are mutually conducted. As a result, the potential of each bit line pair becomes the same. On the other hand, when the equalizing control line EQL is set to a low level (here, zero volts), the equalizing transistors EQ1 to EQm are turned off, and the first and second bit lines in the bit line pairs BP1 to BPm are turned off. BL1 to BLm, / BL1 to / BLm are electrically insulated.

  The sense amplifier 101 compares the potentials of the first bit lines BL1 to BLn with the potentials of the second bit lines / BL1 to / BLm for each of the bit line pairs BP1 to BPm. When the potential of the first bit line is higher than the potential of the second bit line, the sense amplifier 101 applies a high level potential (VCC) to the first bit line and applies a low level potential (zero volts) to the second bit line. When the potential of the first bit line is lower than the potential of the second bit line, the low level potential is applied to the first bit line and the high level potential is applied to the second bit line. In addition, the sense amplifier 101 writes / reads data and reference values to / from the data memory cells 102-11 to 102-mn and the reference memory cells 103-11 to 103-m2, as will be described later. .

  Data memory cells 102-11 to 102-mn are arranged in a matrix. Each of the data memory cells 102-11 to 102-mn includes one transistor Td and one capacitor Cd. That is, the ferroelectric memory according to this embodiment is a 1T / 1C type ferroelectric memory. The transistor Td has a source connected to the corresponding first bit line and a gate connected to the corresponding word line. The capacitor Cd has one electrode connected to the drain of the corresponding transistor Td and receives the plate voltage Vp from the other electrode.

  Two reference memory cells 103-11 to 103-m2 are provided for each of the bit line pairs BP1 to BPm. In this embodiment, these reference memory cells 103-11 to 103-m2 are constituted by SRAM (Static Random Access Memory) cells. That is, each of the reference memory cells 103-11 to 103-m2 includes an inversion circuit (hereinafter, inversion circuits T1 and T2) formed by the pMOS transistor T1 and the nMOS transistor T2, and an inversion formed by the pMOS transistor T3 and the nMOS transistor T4. A circuit (hereinafter referred to as inverting circuits T3 and T4) and gate nMOS transistors T5 and T6 provided between the inverting circuit and the first and second bit lines. The output potentials of the inverting circuits T1 and T2 and the inverting circuits T3 and T4 become the input potential of the other inverting circuit. The gates of the transistors T5 and T6 are connected to corresponding ones of the reference word lines WLref1 and WLref2. Of the reference memory cell pairs provided in each of the bit line pairs BP1 to BPm, one reference memory cell (in this embodiment, the reference memory cells 103-11, 103-21,. −m1) applies a low level potential to the first bit lines BL1 to BLm and sets the second bit lines / BL1 to / BLm to a high level when the first reference word line WLref1 becomes a high level. Apply potential. The other reference memory cell (in this embodiment, reference memory cells 103-12, 103-22,..., 103-m2 in the right column) has the second reference word line WLref2 at the high level. Then, a high level potential is applied to the first bit lines BL1 to BLm and a low level potential is applied to the second bit lines / BL1 to / BLm. As described above, in this embodiment, the potentials of the bit lines BL1 to BLm, / BL1 to / BLm are set to the intermediate potential between the low level and the high level (that is, by causing the reference memory cell pair to output opposite potentials to each other). VCC / 2) (described later).

  The operation of the ferroelectric memory 100 shown in FIG. 1 will be described below.

  First, an operation of writing a reference value to the reference memory cells 103-11 to 103-m1 will be described.

  First, the reference word line WLref1 is set to a high level. As a result, the gate MOS transistors T5 and T6 in the reference memory cells 103-11 to 103-m2 are turned on.

  Next, the sense amplifier 101 applies a low level to the first bit lines BL1 to BLm, and applies a high level to the second bit lines / BL1 to / BLm. As a result, a high level is input to the inverting circuits T1 and T2, and a low level is input to the inverting circuits T3 and T4. When a high level is input to the inverting circuits T1 and T2, the pMOS transistor T1 is turned off and the nMOS transistor T2 is turned on. On the other hand, when a low level is input to the inverting circuits T3 and T4, the pMOS transistor T3 is turned on and the nMOS transistor T4 is turned off. As a result, the outputs of the inverting circuits T1 and T2 are fixed at a low level, and the outputs of the inverting circuits T3 and T4 are fixed at a high level.

  Subsequently, the reference word line WLref1 is set to a low level. As a result, the gate MOS transistors T5 and T6 are turned off, and the reference memory cells 103-11 to 103-mn and the bit lines BL1 to BLm, / BL1 to / BLm are electrically insulated. Here, as described above, the output potentials of the inverting circuits T1 and T2 and the inverting circuits T3 and T4 are the input potential of the other inverting circuit. Therefore, even after the reference memory cells 103-11 to 103-mn and the bit lines BL1 to BLm, / BL1 to / BLm are electrically insulated, the outputs of the inverting circuits T1 and T2 are maintained at a low level. The outputs of the inverting circuits T3 and T4 are maintained at a high level.

  Thereafter, the sense amplifier 101 sets the outputs to the bit lines BL1 to BLm, / BL1 to / BLm to high impedance.

  The operation of writing the reference value to the reference memory cells 103-12 to 103-m2 is the same as that of the reference memory cells 103-11 to 103-m1. However, in this embodiment, in the reference memory cells 103-12 to 103-m2, the outputs of the inverting circuits T1 and T2 are fixed at a high level and the outputs of the inverting circuits T3 and T4 are fixed at a low level.

  Next, a data read operation of the ferroelectric memory 100 will be described by taking as an example a case where data is read simultaneously from a column including the data memory cells 102-11 to 102-m1.

  First, the equalization control line EQL is set to a high level. As a result, the equalizing transistors EQ1 to EQm are turned on to connect the first bit lines BL1 to BLm and the second bit lines / BL1 to / BLm in each of the bit line pairs BP1 to BPm. Are the same. Thereafter, the equalizing control line EQL is set to a low level to electrically insulate the bit line pairs BP1 to BPm.

  Next, the reference word lines WLref1 and WLref2 are set to a high level. By setting the reference word line WLref1 to the high level, the MOS transistors T5 and T6 in the reference memory cells 103-11 to 103-m1 are turned on, respectively, and the inverting circuits T1 and T2 and the first bit line BL1 are turned on. To BLm, and the inverting circuits T3 and T4 and the second bit lines / BL1 to / BLm are conducted. As described above, in the reference memory cell 103-11, the outputs of the inverting circuits T1 and T2 are fixed at a low level and the outputs of the inverting circuits T3 and T4 are fixed at a high level. A low level is outputted to .about.BLm and a high level is outputted to the second bit lines / BL1 to / BLm. On the other hand, in the reference memory cell 103-12, since the outputs of the inverting circuits T1 and T2 are fixed at a high level and the outputs of the inverting circuits T3 and T4 are fixed at a low level, the first bit lines BL1 to BLm Is output at a high level, and a low level is output to the second bit lines / BL1 to / BLm. Therefore, the potentials of the bit lines BL1 to BLm, / BL1 to / BLm are respectively an intermediate potential (VCC / 2) between the low level and the high level. Thereafter, the reference word lines WLref1 and WLref2 are set to a low level, and the reference memory cells 103-11 to 103-m2 and the bit line pairs BP1 to BPm are electrically insulated.

  Subsequently, the data word line WL1 is set to a high level. As a result, the transistors Td of the data memory cells 102-11 to 102-m1 are turned on, and the potential (high level or low level) corresponding to the polarization state of the ferroelectric capacitor Cd is applied to the first bit lines BL1 to BLm. Is output. For example, in the data memory cell 102-11, when the high level is output, the potential of the first bit line BL1 rises from the above-described intermediate potential (VCC / 2). That is, since the potential of the first bit line BL1 becomes higher than the potential of the second bit line / BL1, the sense amplifier 101 sets the first bit line BL1 to the high level (VCC) and the second bit line / BL1. Set to low level (zero volts). On the other hand, when the data memory cell 102-11 outputs a low level, the potential of the first bit line BL1 falls from the intermediate potential. That is, since the potential of the first bit line BL1 is lower than the potential of the second bit line / BL1, the sense amplifier 101 sets the first bit line BL1 to the low level and sets the second bit line / BL1 to the high level. Set to. The operations of the other data memory cells 102-21 to 102-m1 are the same as this. The potentials of the first and second bit lines BL1 to BLm, / BL1 to / BLm are output from the ferroelectric memory 100 as read potentials. Further, the ferroelectric capacitor Cd in the data memory cell 102-11 is overwritten with the potential of the first bit line BL1.

  Thereafter, the potential of the data word line WL1 is set to a low level, and the reading process is completed.

  As described above, the ferroelectric memory 100 according to this embodiment uses SRAM cells as the reference memory cells 103-11 to 103-m2. For this reason, in the reference memory cell of this embodiment, fatigue due to reading of the reference potential does not substantially occur. Therefore, only the data memory cells 102-11 to 102-mn cause the element fatigue. Therefore, the reliability at the time of reading and the life of the ferroelectric memory element are reduced with that of the 2T / 2C type ferroelectric memory. It can be improved to the same level.

  Further, in this embodiment, since the SRAM cells are used as the reference memory cells 103-11 to 103-m2, the operation when reading the reference potentials to the bit line pairs BP1 to BPm can be speeded up.

  In addition, in this embodiment, since the initial potential of the bit line pairs BP1 to BPm is set to the intermediate potential (VCC / 2), data read from the data memory cells 102-11 to 102-mn is started. The time required until the sense amplifier 101 starts voltage application can be shortened, and therefore the data read operation can be speeded up.

  Further, in this embodiment, since only two SRAM cells need be provided for each of the bit line pairs BP1 to BPm, the ferroelectric memory can be easily highly integrated.

  In this embodiment, the reference potential is also applied to the first bit lines BL1 to BLm in the reference memory cells 103-12 to 103-m2, but only the second bit lines / BL1 to / BLm are referred to. An electric potential may be applied.

Second Embodiment Next, a ferroelectric memory according to a second embodiment of the present invention will be described with reference to the circuit diagram of FIG. 2, the same reference numerals as those in FIG. 1 denote the same components as those in FIG.

  As shown in FIG. 2, the ferroelectric memory 200 according to this embodiment includes reference memory cells 201-11 to 201-m2.

  Two reference memory cells 201-11 to 201-m2 are provided for each of the second bit lines / BL1 to / BLm. In this embodiment, each of these reference memory cells 201-11 to 201-m2 is composed of an EPROM (Erasable Programmable Read Only Memory) cell.

  Each of these EPROM cells 201-11 to 201-m2 has a source connected to the corresponding second bit line / BL1 to / BLm, a drain connected to a power source (for example, VCC), and a gate connected to a data word line WLn. It is connected to the. That is, in this embodiment, the reference word line is shared with the data word line WLn. However, a reference word line may be provided independently of the data word lines WL1 to WLn. In addition, separate reference word lines may be provided for the EPROM cells 201-11 to 201-m1 in the left column and the EPROM cells 201-12 to 201-m2 in the right column.

  Among the EPROM cells 201-11 to 201-m2, one of the EPROM cells (in this embodiment, the left column EPROM cells 201-11 to 201-m1) is set when the word line WLn becomes high level. A high level potential is applied to the second bit lines / BL1 to / BLm. The other EPROM cell (in this embodiment, the right column EPROM cells 201-12 to 201-m2) is connected to the second bit lines / BL1 to / BLm when the word line WLn becomes high level. Apply a low level potential. As described above, in this embodiment as well, the potentials of the bit lines BL1 to BLm, / BL1 to / BLm are lowered by causing the reference memory cell pairs to output opposite potentials as in the first embodiment. An intermediate potential between the level and the high level (that is, VCC / 2) is set.

  As is well known, an EPROM cell is a non-volatile memory. Therefore, it is not necessary to write the reference value to the EPROM cells 201-11 to 201-m2 every time the power is turned on. Therefore, for example, a reference value may be written into the EPROM cells 201-11 to 201-m2 by a known method at the time of shipment of the ferroelectric memory 200, so that writing to the reference memory cell pair can be performed. There is no need to configure the sense amplifier 101.

  Hereinafter, the read operation of the ferroelectric memory 200 shown in FIG. 2 will be described by taking as an example a case where data is simultaneously read from a column including the data memory cells 102-1n to 102-mn.

  First, the equalization control line EQL is set to a high level. As a result, the equalizing transistors EQ1 to EQm are turned on, and the first bit lines BL1 to BLm and the second bit lines / BL1 to / BLm in each of the bit line pairs BP1 to BPm become conductive, and the potentials of these bit lines Are the same. Thereafter, the equalizing control line EQL is set to a low level to electrically insulate the bit line pairs BP1 to BPm.

  Next, the word line WLn is set to a high level. When the word line WLn is set to the high level, the reference memory cells 201-11 to 201-m2 are turned on. As described above, in this embodiment, a high level potential is output from the left column EPROM cells 201-11 to 201-m1, and a low level potential is output from the right column EPROM cells 201-12 to 201-m2. Is done. For this reason, the potentials of the second bit lines / BL1 to / BLm are respectively an intermediate potential (VCC / 2) between the low level and the high level. When the word line WLn is set to the high level, the MOS transistors Td in the data memory cells 102-1n to 102-mn are turned on, and the potential (high) corresponding to the polarization state of the ferroelectric capacitor Cd is set. Level or low level) is output to the first bit lines BL1 to BLm. For example, when a high level is output in the data memory cell 102-1n, the potential of the first bit line BL1 rises. As a result, the potential of the first bit line BL1 becomes higher than the potential of the second bit line / BL1, so that the sense amplifier 101 sets the first bit line BL1 to the high level (VCC) and the second bit Set the line / BL1 to low level. At this time, the potential of the second bit line / BL1 is maintained at VCC / 2. On the other hand, when the data memory cell 102-1n outputs a low level, the potential of the first bit line BL1 drops. That is, since the potential of the first bit line BL1 becomes lower than the potential of the second bit line / BL1, the sense amplifier 101 sets the first bit line BL1 to the low level and sets the second bit line / BL1 to the low level. Set to high level. The operation of other data memory cells is the same as this. The potentials of the first and second bit lines BL1 to BLm, / BL1 to / BLm are output from the ferroelectric memory 200 as read potentials. Further, the ferroelectric capacitor Cd in the data memory cell 102-11 is overwritten with the potential of the first bit line BL1.

  Subsequently, the potential of the data word line WLn is set to a low level, and the reading process is completed.

  Thereafter, by setting the potentials of the word lines WLn−1, WLn−2,..., WL1 to a high level, the stored values of the data memory cells in other columns are sequentially read out. At this time, since the potentials of the second bit lines / BL1 to / BLm are maintained at VCC / 2, the potential corresponding to the polarization of each data memory cell is simply output to the first bit lines BL1 to BLm. Data reading is performed.

  As described above, the ferroelectric memory 200 according to this embodiment uses two EPROM cells as the reference memory cells 201-11 to 201-m2. For this reason, in the reference memory cell of this embodiment, fatigue due to reading of the reference potential does not substantially occur. Therefore, only the data memory cells 102-11 to 102-mn cause the element fatigue. Therefore, the reliability at the time of reading and the life of the ferroelectric memory element are reduced with that of the 2T / 2C type ferroelectric memory. It can be improved to the same level.

  Furthermore, in this embodiment, since EPROM cells are used as the reference memory cells 201-11 to 201-m2, the operation when reading the reference potential to the bit line pairs BP1 to BPm can be speeded up.

  Further, in this embodiment, since only two EPROM cells need be provided for each of the bit line pairs BP1 to BPm, high integration of the ferroelectric memory is easy.

Third Embodiment Next, a ferroelectric memory according to a third embodiment of the present invention will be described with reference to the circuit diagram of FIG. In FIG. 3, the components denoted by the same reference numerals as those in FIG. 1 are the same as those in FIG. 1.

  As shown in FIG. 3, the ferroelectric memory 300 according to this embodiment includes reference memory cells 301-11 to 301-m2.

  Two reference memory cells 301-11 to 301-m2 are provided for each of the second bit lines / BL1 to / BLm. In this embodiment, each of these reference memory cells 301-11 to 301-m2 is constituted by a DRAM (Dynamic Random Access Memory) cell.

  The DRAM cells 301-11 to 301-m2 include a transistor Tr whose source is connected to the corresponding second bit line / BL1 to / BLm and whose gate is connected to the data word line WLn, and one end of which is the drain of the transistor Tr. And a capacitor Cr for inputting a plate potential from the other end. Thus, in this embodiment, the reference word line is shared with the data word line WLn. However, a reference word line may be provided independently of the data word lines WL1 to WLn. In addition, separate reference word lines may be provided in the DRAMs 301-11 to 301-m1 in the left column and the DRAMs 301-12 to 301-m2 in the right column.

  Of the DRAM cells 301-11 to 301-m 2, the DRAM cells 301-11 to 301-m 1 in the left column are high level to the second bit lines / BL 1 to / BLm when the word line WLn is high level. Apply potential. The DRAM cells 301-12 to 301-m2 in the right column apply a low level potential to the second bit lines / BL1 to / BLm when the word line WLn becomes a high level. Thus, in this embodiment as well, as in the first and second embodiments described above, by causing the reference memory cell pairs to output opposite potentials, the bit lines BL1 to BLm, / BL1 to / BLm The potential is set to an intermediate potential between the low level and the high level (that is, VCC / 2).

  Reference values are written into the DRAM cells 301-11 to 301-m2 using a DRAM control circuit (not shown). The DRAM control circuit writes a high level to the DRAM cells 301-11 to 301-m1 in the left column among the DRAM cells 301-11 to 301-m2, and the DRAM cells 301-12 to 301-m2 in the right column. Write a low level to. In addition, the DRAM control circuit refreshes the DRAM cells 301-11 to 301-m2. In this embodiment, the values written in the DRAM cells 301-11 to 301-m2 are reference values, and the left side of the DRAM cell pair is fixed at the high level and the right side is fixed at the low level. Therefore, the DRAM cells 301-11 to 301-m2 can be refreshed simply by periodically writing the same value. However, as in a normal DRAM, the potential read from each DRAM cell 301-11 to 301-m2 may be amplified by a sense amplifier in the DRAM control circuit and rewritten.

  Hereinafter, the operation of the ferroelectric memory 300 shown in FIG. 3 will be described by taking as an example a case where data is simultaneously read from a column including the data memory cells 102-1n to 102-mn.

  First, the equalization control line EQL is set to a high level. As a result, the equalizing transistors EQ1 to EQm are turned on, and the first bit lines BL1 to BLm and the second bit lines / BL1 to / BLm in each of the bit line pairs BP1 to BPm become conductive, and the potentials of these bit lines Are the same. Thereafter, the equalizing control line EQL is set to a low level to electrically insulate the bit line pairs BP1 to BPm.

  Next, the word line WLn is set to a high level. When the word line WLn is set to the high level, the reference memory cells 301-11 to 301-m2 are turned on. As described above, in this embodiment, a high level potential is output from the DRAM cells 301-11 to 301-m1 in the left column and a low level potential is output from the DRAM cells 301-12 to 301-m2 in the right column. Is done. For this reason, the potentials of the second bit lines / BL1 to / BLm are respectively an intermediate potential (VCC / 2) between the low level and the high level. When the word line WLn is set to the high level, the MOS transistors Td in the data memory cells 102-1n to 102-mn are turned on, and the potential (high) corresponding to the polarization state of the ferroelectric capacitor Cd is set. Level or low level) is output to the first bit lines BL1 to BLm. For example, when a high level is output in the data memory cell 102-1n, the potential of the first bit line BL1 rises. As a result, the potential of the first bit line BL1 becomes higher than the potential of the second bit line / BL1, so that the sense amplifier 101 sets the first bit line BL1 to the high level (VCC) and the second bit Set the line / BL1 to low level. On the other hand, when the data memory cell 102-1n outputs a low level, the potential of the first bit line BL1 drops. That is, since the potential of the first bit line BL1 becomes lower than the potential of the second bit line / BL1, the sense amplifier 101 sets the first bit line BL1 to the low level and sets the second bit line / BL1 to the low level. Set to high level. The operation of other data memory cells is the same as this. The potentials of the first and second bit lines BL1 to BLm, / BL1 to / BLm are output from the ferroelectric memory 300 as read potentials. In addition, the ferroelectric capacitor Cd in the data memory cell 102-1n is overwritten with the potential of the first bit line BL1.

  Subsequently, the potential of the data word line WLn is set to a low level, and the reading process is completed.

  Thereafter, by setting the potentials of the word lines WLn−1, WLn−2,..., WL1 to a high level, the stored values of the data memory cells in other columns are sequentially read out. At this time, since the potentials of the second bit lines / BL1 to / BLm are maintained at VCC / 2, the potential corresponding to the polarization of each data memory cell is simply output to the first bit lines BL1 to BLm. Data reading is performed.

  As described above, the ferroelectric memory 300 according to this embodiment uses DRAM cells as the reference memory cells 301-11 to 301-m2. For this reason, in the reference memory cell of this embodiment, fatigue due to reading of the reference potential does not substantially occur. Therefore, only the data memory cells 102-11 to 102-mn cause the element fatigue. Therefore, the reliability at the time of reading and the life of the ferroelectric memory element are reduced with that of the 2T / 2C type ferroelectric memory. It can be improved to the same level.

  Furthermore, in this embodiment, since DRAM cell cells are used as the reference memory cells 301-11 to 301-m2, the operation when reading the reference potential to the bit line pairs BP1 to BPm can be speeded up.

  In this embodiment, since only two DRAM cells need be provided for each of the bit line pairs BP1 to BPm, high integration of the ferroelectric memory is easy.

1 is a circuit diagram showing a ferroelectric memory according to a first embodiment. FIG. FIG. 5 is a circuit diagram showing a ferroelectric memory according to a second embodiment. FIG. 6 is a circuit diagram showing a ferroelectric memory according to a third embodiment.

Explanation of symbols

101 sense amplifiers 102-11 to 102-mn data memory cells 103-11 to 103-m2 reference memory cells BP1 to BPm bit line pairs BL1 to BLm first bit lines / BL1 to / BLm second bit lines EQL for equalization Control lines EQ1 to EQm Equalizing transistors WL1 to WLn Data word lines WLref1 and WLref2 Reference word lines T1 to T6 MOS transistors

Claims (5)

A bit line pair having a first bit line for reading data and a second bit line for reading reference potential;
An equalize circuit for conducting the first bit line and the second bit line when an equalize signal is activated;
When the potential of the first bit line is higher than the potential of the second bit line, a predetermined first potential is applied to the first bit line and a predetermined second potential lower than the first potential is applied to the first bit line. And when the potential of the first bit line is lower than the potential of the second bit line, the second potential is applied to the first bit line and the first potential is applied to the first bit line. A sense amplifier applied to a 2-bit line;
A transistor having one main electrode connected to the first bit line and a control electrode connected to the corresponding word line, and one electrode connected to the other main electrode of the transistor and receiving a plate voltage from the other electrode A plurality of data memory cells having a ferroelectric capacitor for input; and
A first SRAM cell that applies the first potential to the second bit line when the first reference word line is activated; and a second SRAM that is activated when the second reference word line is activated. A reference memory cell for setting the second bit line to an intermediate potential between the first and second potentials using a second SRAM cell to which the second potential is applied;
A ferroelectric memory characterized by comprising:   The first SRAM cell applies the second potential to the first bit line when the first reference word line is activated, and the second reference word line is activated. The second SRAM cell sets the first bit line to an intermediate potential between the first and second potentials by applying the first potential to the first bit line. Ferroelectric memory. The first SRAM cell is activated by activating the first reference word line with the sense amplifier applying the second potential to the first bit line and applying the first potential to the second bit line. A reference value is written to
The second SRAM cell is activated by activating the second reference word line with the sense amplifier applying the first potential to the first bit line and applying the second potential to the second bit line. A reference value is written to
The ferroelectric memory according to claim 2, wherein: A bit line pair having a first bit line for reading data and a second bit line for reading reference potential;
An equalize circuit for conducting the first bit line and the second bit line when an equalize signal is activated;
When the potential of the first bit line is higher than the potential of the second bit line, a predetermined first potential is applied to the first bit line and a predetermined second potential lower than the first potential is applied to the first bit line. And when the potential of the first bit line is lower than the potential of the second bit line, the second potential is applied to the first bit line and the first potential is applied to the first bit line. A sense amplifier applied to a 2-bit line;
A transistor having one main electrode connected to the first bit line and a control electrode connected to the corresponding word line, and one electrode connected to the other main electrode of the transistor and receiving a plate voltage from the other electrode A plurality of data memory cells having a ferroelectric capacitor for input; and
A first EPROM cell that applies the first potential to the second bit line when a reference word line is activated; and a second EPROM cell that applies the second potential to the second bit line when the reference word line is activated. A reference memory cell for setting the second bit line to an intermediate potential between the first and second potentials using a second EPROM cell to which a potential is applied;
A ferroelectric memory characterized by comprising: A bit line pair having a first bit line for reading data and a second bit line for reading reference potential;
An equalize circuit for conducting the first bit line and the second bit line when an equalize signal is activated;
When the potential of the first bit line is higher than the potential of the second bit line, a predetermined first potential is applied to the first bit line and a predetermined second potential lower than the first potential is applied to the first bit line. And when the potential of the first bit line is lower than the potential of the second bit line, the second potential is applied to the first bit line and the first potential is applied to the first bit line. A sense amplifier applied to a 2-bit line;
A transistor having one main electrode connected to the first bit line and a control electrode connected to the corresponding word line, and one electrode connected to the other main electrode of the transistor and receiving a plate voltage from the other electrode A plurality of data memory cells having a ferroelectric capacitor for input; and
A first DRAM cell that applies the first potential to the second bit line when a reference word line is activated; and a second DRAM cell that applies the second potential to the second bit line when the reference word line is activated. A reference memory cell for setting the second bit line to an intermediate potential between the first and second potentials using a second DRAM cell to which a potential is applied;
I have a,
A ferroelectric memory , further comprising: a DRAM control circuit for performing writing of the first and second potentials to the first and second DRAM cells and a refresh operation after the writing .

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