JP4470109B2 - Ferroelectric memory device, electronic equipment - Google Patents

Description

  The present invention relates to a data read technique in a ferroelectric memory device (ferroelectric memory) using a ferroelectric capacitor.

  Ferroelectric memory devices (FeRAM) have attracted attention in recent years because they are non-volatile and can operate in the same manner as conventional DRAMs and the like. In the 1T1C type ferroelectric memory device, when reading data (“0” or “1”) stored in a memory cell, a reference potential as a reference is required. As a method for generating the reference potential, there is a method using a reference memory cell (dummy cell). In such a 1T1C type ferroelectric memory device, an arrangement method in which a memory cell and a dummy cell share a word line (WL) and a plate line (PL) is known. For example, Japanese Patent Laid-Open No. 2002-15562 (patent) Reference 1) and the like.

  However, the ferroelectric memory device described in Patent Document 1 does not disclose a specific configuration of the sense amplifier. Therefore, considering a sense amplifier that can be applied in consideration of known techniques, it is considered difficult to apply a column type (latch type) sense amplifier that is generally widely used in ferroelectric memory devices. Even when a sense amplifier other than the column type is applied, it is not easy to set an appropriate reference potential (Vref) because the parasitic capacitances of the bit line and the reference bit line (dummy bit line) are different. Specifically, a method such as making the area of the ferroelectric capacitor constituting the dummy cell larger than that of other memory cells can be considered, but in this case, the ferroelectric material expected due to variations in the manufacturing process, etc. In many cases, characteristics cannot be obtained. In addition, the size of the ferroelectric capacitor must be determined in consideration of the difference in parasitic capacitance between the bit line and the reference bit line. Further, when such a method is adopted, there is a disadvantage that the device area is increased. Therefore, a technique that can easily generate a stable (accurate) reference potential is desired.

JP 2002-15562 A

  Accordingly, an object of the present invention is to provide a technique capable of easily generating a stable reference potential in a ferroelectric memory device that generates a reference potential using a dummy cell.

  According to the first aspect of the present invention, a pair of word lines and plate lines, a plurality of bit lines intersecting the word lines and the plate lines, and intersections of the word lines and the plate lines and the bit lines are provided. A plurality of memory cells connected to a position; a reference bit line commonly provided for the plurality of bit lines crossing the word line and the plate line; and a configuration substantially the same as the memory cell. A reference memory cell provided at each crossing position of the word line and the plate line and the reference bit line, provided corresponding to each of the plurality of bit lines, connected to each of the bit lines, and Each is connected to the common reference bit line, and a plurality of sense amplifiers for comparing and detecting a reference potential generated on the reference bit line and a potential generated on the bit line. Each of the plurality of sense amplifiers includes at least two MOS transistors, the bit line is connected to the gate of one of the MOS transistors, and the reference is made to the gate of the other MOS transistor. A bit line is connected, and the reference bit line corresponds to “1” data of the reference memory cell, and the reference potential read to the reference bit line corresponds to the “1” data of the memory cell. The number of the sense amplifiers connected to the reference bit line is lower than the potential read to the bit line and higher than the potential read to the bit line corresponding to the “0” data of the memory cell. Each of the plurality of sense amplifiers is set to a first P-channel MOS whose gate is connected to the bit line. A transistor, a second P-channel MOS transistor having a gate connected to the reference bit line, a gate connected to the drain of the second P-channel MOS transistor, and a source connected to the drain of the first P-channel MOS transistor; Is connected to the drain of the first P-channel MOS transistor, and the source is connected to the drain of the second P-channel MOS transistor. An on / off N-channel MOS transistor which is connected between the drain of each of the first and second N-channel MOS transistors and the ground terminal and which switches on / off of the sense amplifier; Each drain of the first and second P-channel MOS transistors Is a ferroelectric memory device including an equalizing P-channel MOS transistor, one of which is connected to the source and the other is connected to the drain.

  In this configuration, each bit line is connected to the gate of one sense amplifier, while the reference bit line (dummy bit line) is commonly connected to the gates of a plurality of sense amplifiers. As a result, one bit gate capacitance is added to each bit line, and a plurality of MOS transistor gate capacitances are added to the reference bit line. The capacity is set large. Therefore, it is possible to easily generate a stable reference potential. In particular, since the gate capacitance added to the reference bit line can be optimized by increasing or decreasing the number of sense amplifiers connected to the reference bit line, there is an advantage that an optimum potential can be easily set as the reference potential. The reference bit line has a reference potential read to the reference bit line corresponding to the “1” data of the reference memory cell lower than the potential read to the bit line corresponding to the “1” data of the memory cell, The number of sense amplifiers connected to the reference bit line is set so as to be higher than the potential read to the bit line corresponding to the “0” data of the memory cell. Thereby, the wiring capacitance generated in the reference bit line can be increased, and the difference between the bit line capacitance and the reference bit line capacitance can be set larger. Further, by adopting the sense amplifier having such a configuration, it becomes easy to estimate the gate capacitance of the P-channel MOS transistor receiving the bit line potential.

  The second aspect of the present invention is an electronic apparatus including the ferroelectric memory device described above. Here, “electronic device” refers to a general device having a certain function, and its configuration is not particularly limited. For example, a general computer device including the above storage device, a mobile phone, a PHS, a PDA (portable information) Any device in which a storage device (memory) is incorporated, such as a terminal), an electronic notebook, an IC card, or the like may be applicable.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram illustrating a basic configuration of a ferroelectric memory device according to an embodiment. The ferroelectric memory device according to this embodiment shown in FIG. 1 includes a memory cell array MCAR, a dummy cell array DMAR, and a plurality of sense amplifiers SA. Note that illustration of other peripheral circuits (for example, a word line driver) is omitted.

  The memory cell array MCAR includes a plurality of memory cells arranged in a matrix. As each memory cell, a 1T1C type that is formed by combining one transistor and one ferroelectric capacitor is used. A plurality of pairs of word lines WL and plate lines PL are arranged in the row direction of the memory cell array MCAR. In the column direction of the memory cell array MCAR, a plurality of bit lines BL intersecting with the word lines WL and the plate lines PL are arranged. Each memory cell is connected to each intersection position of the word line WL, the plate line PL, and the bit line BL, and its operation is controlled via the bit line BL, the word line WL, and the plate line PL.

  The dummy cell array DMAR includes a plurality of dummy cells (reference memory cells) arranged in a line along the column direction of the memory cell array MCAR. As each dummy cell, a 1T1C type cell having substantially the same configuration as the memory cell described above is used. The dummy cell array DMAR is configured to share the word line WL and the plate line PL with the memory cell array MCAR. A dummy bit line (reference bit line) DBL that intersects the word line WL and the plate line PL is arranged in the column direction of the dummy cell array DMAR. Each dummy cell is connected to each intersection position of the word line WL and the plate line PL and the dummy bit line DBL, and its operation is controlled via the dummy bit line DBL, the word line WL and the plate line PL.

  Each sense amplifier SA is provided for each bit line BL and is connected to each bit line BL, and as shown in the drawing, each dummy bit line DBL is shared by each sense amplifier SA and the corresponding dummy bit line DBL. The reference potential generated on the dummy bit line DBL and the potential generated on the bit line BL are compared and detected. More specifically, each sense amplifier SA includes at least two MOS transistors, each bit line BL is connected to the gate of one MOS transistor, and a dummy bit line DBL is connected to the gate of the other MOS transistor. It is connected. The dummy bit line DBL is set so that the line width and line thickness are substantially the same as each bit line BL and the line length is long.

  FIG. 2 is a diagram illustrating a specific circuit example of the sense amplifier SA. In the present embodiment, a cross-coupled sense amplifier that receives the potential of the bit line BL at the gate of the MOS transistor is employed. Specifically, as shown in FIG. 2, the sense amplifier SA of this embodiment includes P-channel MOS transistors 11, 12, and 17, N-channel MOS transistors 13, 14, and 16, and a clocked gate inverter 15. Has been.

  P channel MOS transistor 11 has a gate connected to bit line BL and a source connected to the power supply potential. P channel MOS transistor 12 has a gate connected to dummy bit line DBL and a source connected to the power supply potential. The N channel MOS transistor 13 has a gate connected to the drain of the P channel MOS transistor 12 and a source connected to the drain of the P channel MOS transistor 11. N channel MOS transistor 14 has a gate connected to the drain of P channel MOS transistor 11 and a source connected to the drain of P channel MOS transistor 12. Note that the drains of the P-channel MOS transistors 11 and 12 become the output terminals OUT and OUTb of the sense amplifier SA.

  The N channel MOS transistor 16 is connected between the drains of the N channel MOS transistors 13 and 14 and the ground terminal. The N-channel MOS transistor 16 is turned on / off by a signal supplied to the gate via the signal line SAON, and functions as an on / off N-channel MOS transistor for switching on / off of the sense amplifier SA.

  The clocked gate inverter 15 has an input terminal connected to the drain of the P-channel MOS transistor 11 and an output terminal connected to the bit line BL, and generates an inverted signal obtained by inverting the output signal of the sense amplifier SA. At the same time, whether or not to output the inverted signal can be selected based on a control signal given from the outside via the signal lines RW and RWb. Here, a rewrite signal (rewrite signal) is used as the control signal. In the ferroelectric memory device of this embodiment, data is rewritten to the memory cell by the inverted signal generated using the clocked gate inverter 15.

  The P-channel MOS transistor 17 is an equalizing transistor that uniformly adjusts the output terminal potential of the sense amplifier SA. One of the drains of the P-channel MOS transistors 11 and 12 is connected to the source and the other is connected to the drain. By applying a control signal from the outside to the P channel MOS transistor 17 via the signal line SAEQb, the output terminals OUT and OUTb are precharged to the power supply potential (VCC).

  FIG. 3 is a diagram (graph) for explaining the principle of the data read operation. In the figure, the horizontal axis corresponds to the voltage V applied to the ferroelectric capacitor, and the vertical axis corresponds to the charge Q accumulated in the ferroelectric capacitor.

As described above, each bit line BL is connected to the gate of one sense amplifier SA, while the dummy bit line DBL is connected in common to the gates of a plurality of sense amplifiers SA. Therefore, only the gate capacitance for one MOS transistor is connected to each bit line, whereas the gate capacitance for a plurality of MOS transistors is connected to the dummy bit line DBL. Furthermore, in the present embodiment, as described above, the dummy bit lines have a longer line length than the respective bit lines, and thus an extra wiring capacity is generated. Therefore, as shown in the following equation (1), the dummy bit line capacitance CDBL generated in the dummy bit line DBL is larger than the bit line capacitance CBL generated in each bit line.
CBL <CDBL (1)

  Since the relationship between the bit line capacitance and the dummy bit line capacitance is as described above, “1” data is stored in the dummy cell, and the memory cell and the shared word line and plate line are driven, so that the memory cell A potential Vref lower than the potential VBL1 read to the bit line corresponding to “1” data is read to the dummy bit line DBL. Further, the potential Vref is applied to the bit line corresponding to the “0” data of the memory cell by optimizing the number of sense amplifiers SA sharing one dummy bit line DBL and the line length of the dummy bit line DBL. It becomes higher than the read potential VBL0. That is, the potential Vref generated in the dummy bit line DBL is an intermediate potential between the potential VBL1 and the potential VBL0, and is suitable as a reference potential.

  FIG. 4 is a circuit diagram illustrating a more detailed configuration example of the ferroelectric memory device. As illustrated, the memory cell array MCAR and the dummy cell array DMAR share a plurality of word lines WL0 to WLm and plate lines PL0 to PLm extending in the column direction. A plurality of bit lines BL0 to BLn extend in the row direction of the memory cell array MCAR. Similarly, one dummy bit line DBL extends in the row direction of the dummy cell array DMAR. A 1T1C type memory cell MC is connected to each word line, the crossing position of the plate line and the bit line. Further, 1T1C type dummy cells DMC that are substantially the same as the memory cells MC are connected to the intersections of the word lines and the plate lines and the dummy bit lines.

  The dummy bit line DBL is shared across the plurality of sense amplifiers SA0 to SAn, and is commonly connected to the gates of P-channel MOS transistors included in each sense amplifier. The configuration of each sense amplifier SA0 and the like is basically as described above (see FIG. 2), but in the example shown in FIG. 4, an inverter 18 is further added. Here, the input terminal of the inverter 18 is connected to the drain of the P-channel MOS transistor 12 (see FIG. 2), and the output terminal is in a floating state. As described above, since the clocked inverter 15 for rewriting the memory cell MC is connected to the drain of one P-channel MOS transistor 11 (that is, one output terminal of the sense amplifier SA), as in this example. By connecting the inverter 18 also to the drain of the other P-channel MOS transistor 12 (that is, the other output terminal of the sense amplifier SA), the capacitance balance of both output terminals is adjusted, and a better sensing operation is performed. Is possible.

  In the configuration shown in FIG. 4, a precharge switch PCSW for rewriting data in the dummy cell DMC is connected to the dummy bit line DBL. In this example, a P-channel MOS transistor is used as the precharge switch PCSW, and is configured to receive an external control signal (rewrite signal) DWRb at the gate.

  Further, equalizing N-channel MOS transistors EQTr0 to EQTrn are connected to the bit lines BL0 to BLn, and the potential of each bit line is discharged to the ground potential by applying a control signal via the control line BLEQ. Can be done. Similarly, an N-channel MOS transistor DEQTr for equalization is connected to the dummy bit line DBL, and the potential of the dummy bit line can be discharged to the ground potential by applying a control signal via the control line BLEQ. It can be done.

  In such a configuration, the bit line BL and the dummy bit line DBL are discharged to the ground potential before data reading, and thereby the output of the sense amplifier SA is precharged to the power supply voltage VCC. Therefore, it becomes easy to estimate the gate capacitance of the P channel MOS transistor receiving the bit line potential.

  The ferroelectric memory device of the present embodiment has such a configuration. Next, the operation content will be described with reference to waveform diagrams.

  FIG. 5 is a waveform diagram for explaining the operation contents of the ferroelectric memory device.

(Memory cell readout period)
When an H level potential (for example, power supply voltage Vcc) is applied to the word line WL at time t1 (FIG. 5A) and then an H level potential is applied to the plate line PL (FIG. 5C), the memory cell MC A potential corresponding to the data (charge amount) written in the ferroelectric capacitor is generated on the bit line BL (FIG. 5H). In parallel with this operation, a potential corresponding to the data written in the ferroelectric capacitor of the dummy cell DMC (in this example, “1” data) is generated on the dummy bit line DBL (FIG. 5I). Further, the control line BLEQ is set to the L level (for example, the ground potential) after the potential of the word line WL becomes the H level (FIG. 5B), and the bit line BL and the dummy bit line are disconnected from the ground potential. It is.

(Sense period)
Next, at time t2, the control line SAEQb, which has been at the L level, is switched to the H level (FIG. 5E), and the equalizing P that has made the output terminal potential of the sense amplifier uniform so that stable sensing can be performed. The channel MOS transistor 17 is turned off and both outputs are disconnected, enabling output operation. In parallel with this, when an H level potential is applied to the signal line SAON (FIG. 5D), the sense amplifier SA operates, and each output terminal corresponds to the respective potentials of the bit line BL and the dummy bit line. A potential representing “0” data (indicated by a dotted line in the figure) or a potential representing “1” data (indicated by a solid line in the figure) appears in OUT and OUTb, respectively (FIG. 5J).

(Memory cell rewrite period)
When the H level potential is applied to the signal line RW at time t3 after the above-described detection operation by the sense amplifier circuit is almost completed (FIG. 5F), the clocked gate inverter 15 operates and the output terminal OUTb is connected. An inverted signal obtained by inverting the appearing potential is output from the clocked gate inverter 15, and the bit line BL becomes a predetermined potential corresponding to the read data (FIG. 5 (H)). After that, by setting the potential of the plate line PL to L level (for example, ground potential) (FIG. 5C), the memory cell is based on the relative relationship between the potential of the plate line PL and the potential of the bit line BL. Data is rewritten to

(Dummy cell rewrite period)
At time t4, the potentials of the control lines SAON and SAEQb are set to the L level (FIGS. 5D and 5E), the operation of the sense amplifier SA is completed, and each equalizing P channel MOS transistor 17 is turned on. It operates again, and the output terminals of the sense amplifier are set to substantially the same potential. Further, the potential of the control line RW is also set to the L level (FIG. 5F), and the rewriting operation to the memory cell is also finished. In this state, when the potential of the control line DRWb is changed from the H level to the L level, the precharge switch PCSW operates to raise the potential of the dummy bit line DBL to a predetermined level. Since the potential of the plate line PL is at L level (FIG. 5C), “1” data is rewritten in the dummy cell DMC.

(Recovery period)
At time t5, when the potential of the control line BLEQ is set to the H level (FIG. 5B) and the potential of the control line DRWb is set to the L level (FIG. 5G), the bit line BL and the dummy bit line are grounded. It is discharged to a potential (FIGS. 5H and 5I). After the elapse of a predetermined period, the potential of the word line WL is also set to the L level (FIG. 5A), and one cycle of data reading / rewriting is completed.

  FIG. 6 is a perspective view showing a configuration of a personal computer 100 which is an example of an electronic apparatus provided with the ferroelectric memory device according to the present embodiment. In FIG. 6, the personal computer 100 includes a main body 102 having a keyboard 101 and a display panel 103. The ferroelectric memory device according to this embodiment is used as a storage medium of the main body 102 of the personal computer 100, particularly as a nonvolatile memory.

  Thus, in this embodiment, each bit line is connected to the gate of one sense amplifier, while the dummy bit line (reference bit line) is commonly connected to the gates of a plurality of sense amplifiers. . As a result, one bit gate capacitance is added to each bit line, and a plurality of MOS transistor gate capacitances are added to the reference bit line. The capacity is set large. Therefore, it is possible to easily generate a stable reference potential.

  In particular, since the gate capacitance added to the reference bit line can be optimized by increasing or decreasing the number of sense amplifiers connected to the reference bit line, there is an advantage that an optimum potential can be easily set as the reference potential.

  In addition, since the memory cell and the dummy cell can be configured substantially the same, fluctuations in the characteristics of the memory cell and the dummy cell can be suppressed as much as possible.

  In addition, this invention is not limited to the content of embodiment mentioned above, A various deformation | transformation implementation is possible within the range of the summary of this invention.

  FIG. 7 is a block diagram illustrating another configuration example of the ferroelectric memory device. Components common to those in the ferroelectric memory device shown in FIG. 1 are given the same reference numerals. As shown in the configuration example shown in FIG. 7, the ferroelectric memory is configured such that the sense amplifiers SA are provided on both sides of the memory cell array MCAR, and the bit lines BL are alternately connected to the sense amplifiers SA on both sides. The present invention can also be applied to an apparatus. Such a configuration has an advantage that the sense amplifier can be arranged efficiently even when each memory cell becomes small.

  In the above-described embodiment, the cross-couple type is described as a specific example of the sense amplifier SA. However, any other type (for example, a sense amplifier that receives the bit line potential at the gate of the MOS transistor) may be used. , Current mirror type, etc.). Furthermore, in the above-described example, the N-channel MOS transistor is cross-coupled, but a P-channel MOS transistor may be cross-coupled.

  Further, a capacitor for adjusting the capacitance CDBL of the dummy bit line is prepared for the above-described ferroelectric memory device so that the capacitor can be connected / disconnected via a fuse. It may be configured. As a result, the reference potential can be adjusted more accurately.

It is a block diagram explaining the structure of the ferroelectric memory device of one Embodiment. It is a figure explaining the example of a specific circuit of a sense amplifier. It is a figure (graph) for demonstrating the principle of data read-out operation | movement. It is a circuit diagram explaining the more detailed structural example of a ferroelectric memory device. It is a wave form diagram for demonstrating the operation | movement content of a ferroelectric memory device. It is a perspective view which shows the structural example of the electronic device provided with the ferroelectric memory device. It is a block diagram explaining the other structural example of a ferroelectric memory device.

Explanation of symbols

  MCAR ... memory cell array, DMAR ... dummy memory cell array (reference memory cell array), WL ... word line, PL ... plate line, BL ... bit line, DBL ... dummy bit line (reference bit line), SA ... sense amplifier,

Claims (2)

A pair of word lines and plate lines;
A plurality of bit lines intersecting the word lines and the plate lines;
A plurality of memory cells connected to each intersection position of the word line and the plate line and the bit line;
A reference bit line provided in common for the plurality of bit lines crossing the word line and the plate line;
A reference memory cell having substantially the same configuration as the memory cell and provided at each intersection position of the word line and the plate line and the reference bit line;
Provided corresponding to each of the plurality of bit lines, connected to each of the bit lines, and each connected to the commonly provided reference bit line, and a reference potential generated in the reference bit line and the A plurality of sense amplifiers for comparing and detecting the potential generated in the bit line,
Each of the plurality of sense amplifiers includes at least two MOS transistors, the bit line is connected to the gate of one of the MOS transistors, and the reference bit line is connected to the gate of the other MOS transistor. And
In the reference bit line, a reference potential read to the reference bit line corresponding to “1” data of the reference memory cell is greater than a potential read to the bit line corresponding to “1” data of the memory cell. The number of the sense amplifiers connected to the reference bit line is set so as to be higher than the potential read to the bit line corresponding to the “0” data of the memory cell,
Each of the plurality of sense amplifiers is
A first P-channel MOS transistor having the gate connected to the bit line;
A second P-channel MOS transistor having a gate connected to the reference bit line;
A first N-channel MOS transistor having a gate connected to the drain of the second P-channel MOS transistor and a source connected to the drain of the first P-channel MOS transistor;
A second N-channel MOS transistor having a gate connected to the drain of the first P-channel MOS transistor and a source connected to the drain of the second P-channel MOS transistor;
An on / off N-channel MOS transistor that is connected between each drain of the first and second N-channel MOS transistors and a ground terminal and switches on / off of the sense amplifier;
An equalizing P-channel MOS transistor in which one of the drains of the first and second P-channel MOS transistors is connected to the source and the other is connected to the drain, respectively.
Ferroelectric memory device. An electronic apparatus comprising the ferroelectric memory device according to claim 1 .

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