JP2007213659A - Semiconductor memory device and its testing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten fatigue testing time while suppressing the increase in a chip area. <P>SOLUTION: In the fatigue test, data are rewritten to "0"→"1"→"0" with respect to a ferroelectric capacitor Cxx0 and rewritten to "1"→"0"→"1" with respect to a ferroelectric capacitor Cxx1. Transfer gates CT00, CT01, ..., are used for supplying a reference potential Vref by utilizing a path to be used in a Vref applying test and further the reference potential Vref is supplied from the outside of ferroelectric memory chip via a pad. Consequently, there is no need of considering driving ability of a transistor of which the supply of potential for the fatigue test is formed inside the ferroelectric memory chip such as a write buffer, the fatigue testing time can be shortened while suppressing the increase in the area of ferroelectric memory chip. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a fatigue test method that is a fatigue test and its circuit configuration in a nonvolatile semiconductor memory device that is a ferroelectric memory (Ferroelectric Random Access Memory; FeRAM) using the polarization of a ferroelectric. .

  FIG. 11 is a diagram showing hysteresis characteristics of a ferroelectric memory for explaining the prior art, in which the horizontal axis represents the potential V and the vertical axis represents the amount of polarization.

  Conventionally, a ferroelectric memory characterized in that information (data) is stored by utilizing a polarization state having hysteresis characteristics as shown in FIG. 11 has been proposed in the following documents, for example.

Japanese Patent Laying-Open No. 2005-25878

  This Patent Document 1 describes a technique for shortening the fatigue test time by executing data writing during a fatigue test of a ferroelectric memory through a path other than the normal data write path.

  Typical ones in ferroelectric memory are one that forms a 1-bit memory cell with two selection transistors and two ferroelectric capacitors (2T2C type), one selection transistor and one ferroelectric. There is a capacitor (1T1C type) that forms a 1-bit memory cell with a capacitor.

(Configuration of 2T2C type ferroelectric memory)
FIG. 12 is a block diagram showing a main part of a conventional 2T2C type ferroelectric memory.

  This ferroelectric memory has a plurality of 2T2C type memory cells MC00 that are cell units for storing data, and a plurality of sense amplifiers SA0 that detect and amplify data read from these memory cells MC00. ing. The memory cell MC00 has a bit line bl and a complementary bit line blb having a phase opposite to that of the bit line bl (the last word “b” of this symbol means a phase opposite. The same applies hereinafter) blb and the word line wl , And the plate line pl, for example, two select transistors T0, T1 made of N-channel MOS transistors (hereinafter referred to as “NMOS”) and two ferroelectric capacitors C0, C1. It is comprised by.

  The gates of the selection transistors T0 and T1 are connected to the word line wl, the bit line bl is connected to the plate line pl via the selection transistor T0 and the ferroelectric capacitor C0, and the complementary bit line blb is connected to the bit line bl. It is connected to the plate line pl through the selection transistor T1 and the ferroelectric capacitor C1.

  The sense amplifier SA0 includes equalizing transistors TN1 and TN2 made of NMOS for equalizing the bit line bl and the complementary bit line blb to the ground potential VSS by the equalizing signal bleq of logic “H”, and “H” A differential amplifying circuit 10 that is activated by the equalize signal sae and differentially amplifies the potential difference between the bit line bl and the complementary bit line blb is connected between the bit line bl and the digit line db by the column selection signal ysel of “H”. And a transfer gate TG1 made of NMOS for connecting the complementary bit line blb and the complementary digit line dbb by the column selection signal ysel of “H”, and the digit line db The complementary digit line dbb is connected to an input / output circuit (not shown) or the like.

  The differential amplifier circuit 10 includes a complementary MOS (hereinafter referred to as “CMOS”) inverter 11 composed of a PMOS 11a and an NMOS 11b, and a CMOS inverter 12 composed of a PMOS 12a and an NMOS 12b. The inverter 11 has an input terminal connected to the complementary bit line blb, an output terminal connected to the bit line bl, and the inverter 12 has an input terminal connected to the bit line bl and an output terminal connected to the complementary bit line blb. Connected to line blb. The inverters 11 and 12 have their positive power supply terminals connected to the power supply potential VDD via a power supply transistor TP0 made of a P-channel MOS transistor (hereinafter referred to as “PMOS”) PMOS, and their negative power supply terminals connected to the NMOS. The power supply transistor TN0 is connected to the ground potential VSS. When the sense amplifier enable signal sae becomes “H”, it is inverted by the inverter IN0, the transistor TP0 is turned on, the transistor TN0 is turned on, and the inverters 11 and 12 are connected to the power supply potential VDD and the ground potential VSS. Then, an amplification operation is performed.

(Rewrite operation of 2T2C type ferroelectric memory)
FIG. 13 is an operation waveform diagram for explaining the data rewrite operation of the memory cell MC00 of FIG. 12, where the horizontal axis represents time and the vertical axis represents potential.

  For example, it is assumed that data “0” (that is, data “0” is stored in the ferroelectric capacitor C0 and “1” is stored in C1) is written in the memory cell MC00.

  At time t1, when the equalize signal bleq is “L”, the word line wl and the plate line pl are “H”, the transistors TN1 and TN2 are turned off, the selection transistors T0 and T1 are turned on, and the selection transistors T0 and T1 The charge of the dielectric capacitor C0 is distributed to the bit line bl via the potential V0, the charge of the dielectric capacitor C1 is distributed to the complementary bit line blb to the potential V1, and a small potential difference between the bit lines bl / blb ΔV (= V1−V0) is generated.

  At time t2, the sense amplifier enable signal sae becomes “H”, the differential amplifier circuit 10 in the sense amplifier SA0 is activated, and charges (stores) the bit lines bl / blb. At time t3, in order to write data “1” to the memory cell MC00, the digit line db becomes “H”, the complementary digit line dbb becomes “L”, the column selection signal ysel becomes “H”, and the transfer gate TG1 TG2 is turned on, the bit line bl / blb is inverted, and the reverse data “1” is written to the memory cell MC00.

(Configuration of 1T1C type ferroelectric memory)
FIG. 14 is a block diagram showing a main part of a conventional 1T1C type ferroelectric memory. Elements common to those in FIG. 12 are denoted by common reference numerals.

  The 1T1C type memory cell MC00 is connected to the intersection of the bit line bl and the word line wl0 and the plate line pl0, and the 1T1C type memory cell MC01 is connected to the intersection of the complementary bit line blb, the word line wl1 and the plate line pl1. It is connected. The memory cell MC00 has a selection transistor T0 made of NMOS that is turned on / off by the potential of the word line wl0, and a ferroelectric capacitor C0, which are connected in series between the bit line bl and the plate line pl0. Has been. Similarly, the memory cell MC01 has a selection transistor T1 made of NMOS that is turned on / off by the potential of the word line wl1, and a ferroelectric capacitor C1, which are arranged between the complementary bit line blb and the plate line pl1. Connected in series. A reference potential generation circuit (hereinafter referred to as “Vref generation circuit”) 20 for applying a reference potential Vref is connected to one end of the bit line bl and the complementary bit line blb. The other ends of the bit line bl and the complementary bit line blb are connected to the digit line db and the complementary digit line dbb via the sense amplifier SA0.

(Rewrite operation of 1T1C type ferroelectric memory)
FIG. 15 is an operation waveform diagram for explaining the data rewrite operation of the memory cell MC00 of FIG. 14, where the horizontal axis represents time and the vertical axis represents potential.

  For example, it is assumed that data “0” (that is, data “0” is written in the ferroelectric capacitor C0) is written in the memory cell MC00.

  When the equalize signal bleq is “L” and the word line wl0 and the plate line pl0 are “H” at time t1, the bit line bl and the complementary bit line blb are disconnected from the ground potential VSS, and the selection transistor T0 is turned on. Thus, the charge of the ferroelectric capacitor C0 is distributed to the bit line bl. On the other hand, the reference potential Vref is generated by the Vref generation circuit 20 on the complementary bit line blb. Various methods for generating the reference potential Vref have been proposed, but it is generally generated by two ferroelectric capacitors.

  After time t2, the operation is the same as that of the 2T2C type memory cell MC00. When the bit line bl becomes “H” level at time t3, data “1” is written in the memory cell MC00, that is, the ferroelectric capacitor C0.

(Configuration of Vref application test for ferroelectric memory)
FIG. 16 is a distribution diagram of potentials V0 and V1 due to process variations of a conventional ferroelectric capacitor, where the horizontal axis represents potential [V] and the vertical axis represents several [pieces]. FIG. 17 is a configuration diagram of a circuit mounted for performing a Vref application test on a conventional ferroelectric memory.

  The ferroelectric memory test includes a Vref application test for applying a reference potential Vref to the memory cell MC. As shown in FIG. 16, the ferroelectric capacitor C has a distribution in the values of the potentials V0 and V1 due to variations in the manufacturing process. In order to examine this distribution state, a circuit for a Vref application test as shown in FIG. 17 is used.

  In the Vref application test, since the ferroelectric memory has the same circuit configuration regardless of whether it is the 1T1C type or the 2T2C type, the circuit configuration of the 2T2C type in FIG. 17 will be described.

  This Vref test circuit has one bit (hereinafter referred to as “bit”) of 2T2C type memory cells MC00 connected to the bit line bl and the complementary bit line blb, and one end of the bit line bl and the complementary bit line blb. The reference potential Vref is applied via the Vref control circuit 30, and the other ends of the bit line bl and the complementary bit line blb are connected to the digit line db and the complementary digit line dbb via the sense amplifier SA0. The Vref control circuit 30 includes a transfer gate CT00 that connects the bit line bl to the reference potential Vref, and a transfer gate CT01 that connects the complementary bit line blb to the reference potential Vref.

  The transfer gate CT00 is connected to and controlled in parallel with a PMOS that is turned on / off by a reverse-phase complementary control signal xvrebl ("x" at the beginning of this code means reverse phase, the same applies hereinafter). An NMOS that is turned on / off by a signal vrebl. Similarly, the transfer gate CT01 is a PMOS that is turned on / off by a reverse-phase complementary control signal xvreblb (“x” at the beginning of this code, “b” at the end means reverse phase, and so on). These are connected in parallel with each other and are configured to be turned on / off by a control signal vreblb.

(Operation of Vref application test; when the ferroelectric capacitor C0 is a normal cell)
18A and 18B are waveform diagrams for explaining the operation of the Vref application test for the ferroelectric memory of FIG. 17, and FIG. 18A shows a cell in which the ferroelectric capacitor C0 is normal. FIG.

  For example, the operation when the Vref application test is performed on the ferroelectric capacitor C0 of FIG. 17 will be described.

  Data “0” (that is, “0” for the ferroelectric capacitor C0 and “1” for C1) is written in the memory cell MC00 in advance. The operation when the ferroelectric capacitor C0 is a normal cell, that is, when the ferroelectric capacitor C0 is a ferroelectric capacitor that outputs the potential V0a of FIG. 16 at the time of “0” reading is described with reference to FIG. explain.

  When the complementary control signal xvreblb becomes “L” and the control signal vrefblb becomes “H” at time t1, the transfer gate CT01 is turned on, and the complementary bit line blb is connected to the reference potential Vref via the transfer gate CT01. . The reference potential Vref can be arbitrarily given from the outside of the chip via a pad. Since the potential Vref0 is given to the reference potential Vref, the potential of the complementary bit line blb becomes Vref0. Further, the word line wl0 and the plate line pl0 rise and the selection transistor T0 is turned on, so that the charge of the ferroelectric capacitor C0 is distributed to the bit line bl, and the potential of the bit line bl becomes V0a.

  At time t2, the sense amplifier enable signal sae rises to activate the sense amplifier SA0, and the potential difference between the bit line bl and the complementary bit line blb is amplified. At time t3, the column selection signal ysel becomes “H”, the bit line bl and the complementary bit line blb are connected to the digit line db and the complementary digit line dbb, and the data of the bit lines bl and blb are transferred to the digit lines db, Output to dbb. When the complementary digit line dbb is “H” and the digit line db is “L”, the data is read as data “0”. Therefore, the data “0” can be read with respect to the data “0” written first. The ferroelectric capacitor C0 is a normal cell.

(Operation of Vref application test; ferroelectric capacitor C0 is a defective cell)
FIG. 18B is a waveform diagram in the case where the ferroelectric capacitor C0 is a defective cell.

  A case where the ferroelectric capacitor C0 of FIG. 17 is a defective cell will be described. For example, the operation when the ferroelectric capacitor C0 is a ferroelectric capacitor that outputs the potential V0b of FIG. 16 when “0” is read will be described with reference to FIG. 18B.

  At time t1, the charge of the ferroelectric capacitor C0 is distributed to the bit line bl, and the potential of the bit line bl becomes V0b. At time t2, the sense amplifier SA0 is activated and the potential difference between the bit line bl and the complementary bit line blb is amplified, and is output to the digit lines db and dbb at time t3. When the digit line db is “H” and the complementary digit line dbb is “L”, the data is read as data “1”, which is different from the data “0” written at the beginning, so that the ferroelectric capacitor C0 is a defective cell. Can be recognized.

  A similar test is performed for data “1” to check whether the potential V1 is in a normal cell distribution. The ferroelectric capacitor C0 that deviates from the normal distribution also has a fast deterioration speed, so it must be found during the screening test. Further, the distribution of the device in FIG. 16 is also measured by changing the reference potential Vref to be applied and observing the operation of all the cells. As described above, the Vref application test is an indispensable test for the ferroelectric memory, and a circuit as shown in FIG. 17 is mounted.

(Configuration of Fate Test of Ferroelectric Memory)
FIG. 19 is a principle diagram of a fatigue test for a conventional ferroelectric memory, where the horizontal axis represents the potential V of the ferroelectric capacitor and the vertical axis represents the polarization amount of the ferroelectric capacitor. FIG. 20 is a configuration diagram of a fatigue test for a conventional ferroelectric memory.

  In the fatigue test, which is a fatigue test, the hysteresis curve of a ferroelectric capacitor is rewritten as shown by an arrow as shown in FIG. 19, and in an actual circuit, data “0” and “1” are rewritten alternately. To do.

  As shown in FIG. 20, the circuit for performing the fatigue test includes a plurality of array units AU0, AU1,... Each composed of a plurality of memory cells MC000, MC001,... And a plurality of sense amplifiers SA00, SA01,. , AUn, sense amplifier enable signals sae0, sae1, ..., saen connected to all sense amplifiers SA00, SA01, ..., SAn1 in the array units AU0, AU1, ..., AUn, and column selection signals ysel0, ysel1, ..., yseln and digit lines db0, db1, ... and complementary digit lines dbb0, dbb1, ... connected to sense amplifiers SA00, SA10, ..., SAn1 and digit lines db0 / dbb0, db1 / dbb1, ... are driven. Are composed of write drivers 40, 41,...

(Fatigue test operation)
In FIG. 20, in the normal write operation, only one array unit is selected from the array units AU0 to AUn by the column selection signals ysel0 to yseln, so one write driver (for example, 40) is one sense amplifier. Only drive (for example, SA00). On the other hand, in the fatigue test, since one ferroelectric capacitor must be rewritten 10 ¹⁰ times or more, the address is degenerated. In FIG. 20, in order to rewrite all the memory cells MC000,... In one operation, all the word lines wl0,... And the plate lines pl0, etc. are activated, and all the sense amplifier enable signals sae0,. ,... Are activated to activate all the sense amplifiers SA00,..., The bit lines bl0 / dbb0,. Do. The digit lines db and dbb and the bit lines bl and blb are driven so that the initial data is stabilized by the differential amplifier circuit 10 in the sense amplifier SA, and the drive capability of the write drivers 40,. Inverted.

Since the bit line bl, blb connected to a large number (in this case, n + 1 number) of sense amplifiers SA00,... Must be inverted by one write driver (for example, 40) during the fatigue test, the write driver 40 Needs to be increased, that is, the driver size. In some cases, even if the driver size is increased, the inversion cannot be performed due to the limit of the driving capability. In this case, since the ferroelectric memory as a device has to be rewritten by dividing it into a plurality of addresses, for example, when divided into four, the test time is four times longer. Also, when all the memory cells MC000,... Can be rewritten at the same time by increasing the driver size, the time to invert the bit lines bl, blb must be longer than the inversion time at the time of normal rewriting. The rewriting time during the fatigue test becomes longer than the time. In this way, the fatigue test is performed 10 ¹⁰ times or more, so reducing the time for one rewrite leads to a shortening of the fatigue test time.

  However, in the conventional semiconductor memory device and the test method thereof, in order to shorten the fatigue test time, it is necessary to increase the size of the write driver 40,... There are limits to shortening.

  The semiconductor memory device of the present invention includes a selection transistor that is turned on / off by a potential of a word line, and a ferroelectric capacitor, and the selection transistor and the ferroelectric capacitor are connected in series between a bit line and a plate line. And a switch for connecting / cutting off the bit line and the power line of the reference potential supplied from the outside through the pad.

  In the semiconductor memory device testing method of the present invention, the semiconductor memory device is used to apply the reference potential to the bit line by turning on the switch during a reference potential application test and to apply the switch to the bit line during a fatigue test. The plate line is activated while being turned on, and the data is rewritten to the ferroelectric capacitor.

  According to the semiconductor memory device and the test method thereof of the present invention, the switch for supplying the reference potential is used using the path used in the reference potential application test, and the reference potential is supplied from the outside of the chip through the pad. With this configuration, it is not necessary to consider the driving capability of the transistors formed inside the chip, such as the write buffer, for the potential supply for the fat test. Therefore, the fat test is performed while suppressing an increase in the chip area. Time can be shortened.

  The ferroelectric memory device includes a selection transistor that is turned on / off by a potential of a word line, and a ferroelectric capacitor, and the selection transistor and the ferroelectric capacitor are connected in series between a bit line and a plate line. The memory cell is connected, and a switch for connecting / cutting off the bit line and a power supply line of a reference potential supplied from the outside through a pad by performing an on / off operation. In the test method, using the ferroelectric memory device, the reference potential is applied to the bit line by turning on the switch during the reference potential application test, and the switch is turned on during the fatigue test. At the same time, the plate line is activated to rewrite data to the ferroelectric capacitor.

(Configuration of Example 1)
FIG. 1 is a configuration diagram of a 2T2C type ferroelectric memory which is a nonvolatile semiconductor memory device showing Embodiment 1 of the present invention. Elements common to those shown in FIGS. Is attached.

  The 2T2C ferroelectric memory according to the first embodiment includes an array block AB for storing data, a word line driver 50, a plate line driver 60, and a sense amplifier control circuit (hereinafter referred to as “amplifier block”) for driving and controlling the array block AB. And a reference potential control circuit (hereinafter referred to as “Vref control circuit”) 80-0 and 80-1.

  The array block AB is at the intersection of a plurality of bit lines bl0, bl1,... And a plurality of complementary bit lines blb0, blb1,..., A plurality of word lines wl0, wl1,. A plurality of connected 2T2C type memory cells MC00, MC01, MC10, MC11,... And a plurality of bit lines bl0, bl1,... And a plurality of complementary bit lines blb0, blb1,. , And a plurality of bit lines bl0, bl1,... And a plurality of sense amplifiers SA0, SA1,... Connected to the other ends of the plurality of complementary bit lines blb0, blb1,. Have.

  Each memory cell MC00,... Is composed of two select transistors T000, T001,... And two ferroelectric capacitors C000, C001,. Each of the Vref control circuits 30-0, 30-1,... Is turned on / off by the control signals vrebl, xvrebl and the respective bit lines bl0, bl1,. Potential) Each switch (for example, transfer gate) CT00, CT01,... For connecting to the power supply line of Vref and on / off operation by the control signals vrbeblb, xvreblb to set each bit line blb0, blb1,. Each switch (for example, transfer gate) CT10, CT11,. The reference potential Vref is supplied from the outside of the ferroelectric memory chip via a pad or a power supply line.

  Each sense amplifier SA0, SA1,... Is an equalizing transistor that equalizes each bit line bl0, bl1,... And each complementary bit line blb0, blb1,. Are activated by the sense amplifier enable signal sae, and each differential amplifier circuit that amplifies the potential difference between each bit line bl0, bl1,... And each complementary bit line blb0, blb1,. Each of the bit lines bl0, bl1,... And each complementary bit line blb0, blb1,... And each transfer line for connecting to each of the digit lines db0, db1,. Yes.

  The word line driver 50 is a circuit that is activated by the fatigue test mode signal tmfat and raises the word lines wl0, wl1,... Selected by the row address RA to “H”. The plate line driver 60 is a circuit that is activated by the fatigue test mode signal tmfat and raises the plate lines pl0, pl1,... Selected by the row address RA to “H”. The SA control circuit 70 is a circuit that outputs a sense amplifier enable signal sae, an equalize signal bleq, and a column selection signal ysel.

  The Vref control circuit 80-0 has a two-input OR gate (hereinafter referred to as “OR gate”) 81 for obtaining the OR of the input Vref application test mode signal tmvref and the fatigue test mode signal tmfat, and the OR gate 81. 2 input NAND gate (hereinafter referred to as “NAND gate”) 82 that outputs a control signal xvrebl by obtaining the NAND of the Vref connection enable signal venbl and the output signal of Vref, and the control signal xvrebl are inverted. And an inverter 83 that outputs a control signal vrebl.

  The Vref control circuit 80-1 is similar to the Vref control circuit 80-0 in that the Vref application test mode signal tmvref, which is a Vref application test signal, the fatigue test mode signal tmfat, which is a fatigue test signal, and a complementary Vref connection enable signal venblb. , And a control signal vrbeblb and a complementary control signal xvreblb are output from these logics.

(Operation of Fate Test of Example 1)
FIG. 2 shows the operation waveform during the fatigue test in the ferroelectric memory of FIG. 1 and the ferroelectric capacitors Cxx0 (C000, C010, C100, C110,...) Connected to the bit line bl and the complementary bit line blb. FIG. 6 is a diagram showing hysteresis curves of the ferroelectric capacitors Cxx1 (C001, C011, C101, C111,...), Where the horizontal axis represents time and the vertical axis represents potential. In addition, the arrow in a hysteresis curve has shown the moving direction of the polarization amount.

  Assume that “0” is written in the ferroelectric capacitor Cxx0 and “1” is written in the ferroelectric capacitor Cxx1 as an initial state.

  At time t1, when all word lines wl (wl0, wl1,...) Are raised by the word line driver 50 and all plate lines pl (pl0, pl1,...) Are raised by the plate line driver 60, the selection transistors T000, T010, Is turned on, and the charge of the ferroelectric capacitor Cxx0 (C000, C010,...) Is distributed to the bit line bl (bl0, bl1,...), And this bit line bl takes a potential Vfa higher than the ground potential VSS. (The polarization amount of Cxx0 moves down the hysteresis curve, and the polarization amount of Cxx1 moves down the hysteresis curve). At this time, when the complementary Vref connection enable signal venblb becomes “H”, the control signal vrbeblb output from the Vref control circuit 80-1 becomes “H”, the complementary control signal xvreblb becomes “L”, and the transfer gate CT10 , CT11,... Are turned on, whereby the complementary bit lines blb (blb0, blb1,...) And the reference potential Vref are connected. Since the reference potential Vref is the ground potential “0”, the potential of the complementary bit line blb is “0”.

  At time t2, the equalize signal sae becomes “H” by the SA control circuit 70, the differential amplifier circuit in the sense amplifier SA (SA0, SA1,...) Is activated, and the level of the bit line bl is “H”. (The polarization amount of Cxx0 moves to the data “0” in the upper right direction of the hysteresis curve).

  At time t3, the plate line pl falls by the plate line driver 60, and at time t4, the SA control circuit 70 sets the equalize signal bleq to “H” and the sense amplifier enable signal sae to “L”, so that the bit line bl Becomes “0” (the polarization amount of Cxx0 moves the hysteresis curve in the upper right direction, and the polarization amount of Cxx1 moves in the upper right direction of the hysteresis curve). At time t5, the word line wl falls by the word line driver 60 (the polarization amount of Cxx0 moves in the lower left direction). As a result, the ferroelectric capacitor Cxx0 in which “0” is written is rewritten to “1”, and the ferroelectric capacitor Cxx1 in which “1” is written is rewritten to “0”.

  Next, when all the word lines wl and all the plate lines pl rise at time t6 by the word line driver 50 and the plate line driver 60, the selection transistors T001, T011,. The charge of Cxx1 is distributed to the complementary bit line blb, and this complementary bit line blb takes a potential Vfa higher than the ground potential VSS. At this time, when the Vref connection enable signal venbl becomes “H”, the control signal vrebl output from the Vref control circuit 80-0 becomes “H”, the complementary control signal xvrebl becomes “L”, and the transfer gates CT00, When CT01,... Is turned on, the bit line bl and the reference potential Vref are connected. Since the reference potential Vref is the ground potential “0”, the potential of the bit line bl is “0” (the polarization amount of Cxx0 moves down the hysteresis curve, and the polarization amount of Cxx1 moves down the hysteresis curve ).

  At time t7, the equalize signal sae becomes “H” by the SA control circuit 70, the differential amplifier circuit in the sense amplifier SA is activated, and the level of the complementary bit line blb becomes “H” (the amount of polarization of Cxx1) Move the hysteresis curve to the upper right). At the time t8, the plate line pl falls by the plate line driver 60 (the polarization amount of Cxx1 moves the hysteresis curve in the upper right direction of the data “0”). At time t9, the SA control circuit 70 sets the equalize signal bleq to “H” and the sense amplifier enable signal sae to “L”, so that the complementary bit line blb becomes “0” (the polarization amount of Cxx0 is a hysteresis curve). The data “0” moves to the upper right direction, and the polarization amount of Cxx1 moves the hysteresis curve to the upper right direction). At time t10, the word line wl falls by the word line driver 50 (the polarization amount of Cxx1 moves the hysteresis curve in the lower left direction of the data “1”). As a result, the ferroelectric capacitor Cxx0 in which “1” is written is rewritten to “0”, and the ferroelectric capacitor Cxx1 in which “0” is written is rewritten to “1”.

  As described above, from time t1 to time t10, the ferroelectric capacitor Cxx0 is rewritten from “0” → “1” → “0”, and the ferroelectric capacitor Cxx1 is “1” → “0” → “1”. The data is rewritten. During this time, the column selection signal ysel is fixed at “L” (Fix), and the bit line bl and the complementary bit line blb are not connected to the digit line db and the complementary digit line dbb. A write driver for driving the complementary digit line dbb is not involved. Therefore, it is not necessary to increase the size of the write driver for the fatigue test.

(Effect of Example 1)
The first embodiment has the following effects (1) to (3).

  (1) By using the Vref application test circuit during the fatigue test, the increase in the area of the array block AB can be suppressed, and the potentials of the bit line bl and the complementary bit line blb should not be inverted during data rewriting. And by not using a write driver at the time of rewriting, the fatigue test time can be shortened, and the increase in the area of the write driver can be suppressed.

  That is, in the first embodiment, the transfer gates CT00, CT01,... That supply the reference potential Vref using the path used in the Vref application test are used, and the reference potential Vref is ferroelectric through the pad. Since this configuration is supplied from the outside of the memory chip, the potential supply for the fatigue test does not need to consider the driving capability of the transistors formed inside the ferroelectric memory chip such as a write buffer. The fatigue test time can be shortened while suppressing an increase in the area of the body memory chip.

  (2) In the first embodiment, all the ferroelectric capacitors Cxx0 and Cxx1 are tested by driving all the word lines wl and plate lines pl. However, by limiting the row address RA, It is also effective when performing a fatigue test by squeezing the wire wl and the plate wire pl.

(Configuration of Example 2)
FIG. 3 is a block diagram of a 1T1C type ferroelectric memory which is a nonvolatile semiconductor memory device showing Embodiment 2 of the present invention. FIG. 3 shows Embodiment 1 and FIGS. 1 and 2 and FIG. Elements common to these elements are denoted by common reference numerals.

  The 1T1C type ferroelectric memory according to the second embodiment includes a data storage array block AB having a configuration different from that of the first embodiment, and a word line substantially similar to the first embodiment for driving and controlling the array block AB. Driver 50, plate line driver 60, SA control circuit 70, Vref control circuits 80-0 and 80-1, newly added reference word line driver 51, reference plate line driver 61, reference cell write circuit 62, and And a reference control circuit 63.

  The array block AB is at the intersection of a plurality of bit lines bl0, bl1,..., A plurality of complementary bit lines blb0, blb1,..., A plurality of word lines wl0, wl1,. A plurality of connected 1T1C type memory cells MC00, MC01, MC10, MC11,..., A plurality of bit lines bl0, bl1,... And a plurality of complementary bit lines blb0, blb1,. .., And a plurality of Vref control circuits 30-0, 30-1,..., A plurality of bit lines bl0, bl1,... And a plurality of complementary bit lines blb0, blb1,. A plurality of sense amplifiers SA0, SA1,... Connected to the ends are provided.

  Each memory cell MC00,... Is configured by one select transistor T00, T01,... And one ferroelectric capacitor C00, C01,. Each Vref control circuit 30-0, 30-1,... Is a circuit for connecting each bit line bl0 / blb0, bl1 / blbl,... To the reference potential Vref as in the first embodiment. The reference potential Vref is supplied from the outside of the ferroelectric memory chip via the pad, as in the first embodiment. Each of the sense amplifiers SA0, SA1,... Has the same circuit configuration as that of the first embodiment.

  Each Vref generation circuit 20-0, 20-1,... Is driven and controlled by a reference word line driver 51, a reference plate line driver 61, and a reference cell write circuit 62 as in FIG. Is a circuit for generating a reference potential Vref to be applied to the lines bl0, bl1,... And the complementary bit lines blb0, blb1,..., And a plurality of reference memory cells RMC00, RMC01, RMC10, RMC11,. The cell write control circuits 21-0, 21-1,...

  Each of the reference memory cells RMC00, RMC01,... Has a circuit configuration similar to that of the 1T1C type memory cell MC00,..., And is a selection transistor RT00 composed of NMOS that is turned on / off by the potential of each reference word line rwl0, rwl1,. RT01, ... and ferroelectric capacitors RC00, RC01, ... between these bit lines bl0, bl1, ... or complementary bit lines blb0, blb1, ... and reference plate lines rpl0, rpl1, ... Connected in series. Each of the reference cell write control circuits 21-0,... Determines the potential of the storage nodes st0, stb0, st1, stb1,... Of each of the ferroelectric capacitors RC00, RC01,. This is a circuit for writing data to each of the ferroelectric capacitors RC00, RC01,.

  The reference word line driver 51 is activated by the fatigue test mode signal tmfat and is controlled by the reference cell control circuit 63 to raise the reference word lines rwl0, rwl1,... To “H”. The reference plate line driver 61 is activated by the fatigue test mode signal tmfat, and is controlled by the reference cell control circuit 63 to raise the reference plate lines rpl0, rpl1,... To “H”. The reference cell write circuit 62 is activated by the fatigue test mode signal tmfat and is controlled by the reference cell control circuit 63 to output the reference memory cell write signals rwodd and rweven.

(Operation of Fate Test of Example 2)
FIG. 4 shows an operation waveform at the time of a fatigue test in the ferroelectric memory of FIG. 3, a ferroelectric capacitor Cx0 (C00, C010,...) Connected to the bit line bl and a reference ferroelectric capacitor RCx0 (RC00, RC10). ,..., And a hysteresis curve of the ferroelectric capacitor Cx1 (C01, C11,...) And the reference ferroelectric capacitor RCx1 (RC01, RC11,...) Connected to the complementary bit line blb. The axis is time, and the vertical axis is potential. In addition, the arrow in a hysteresis curve has shown the moving direction of the polarization amount.

  Assume that “0” is written in the ferroelectric capacitor Cx0 and the reference ferroelectric capacitor RCx0, and “1” is written in the ferroelectric capacitor Cx1 and the reference ferroelectric capacitor RCx1 as an initial state.

  In a normal write / read operation, the reference word line rwl and the reference plate line rpl operate differently from the word line wl and the plate line pl, and are referenced from the Vref generation circuits 20-0, 20-1,. The potential Vref is generated, and writing is performed to the reference ferroelectric capacitors RCx0 and RCx1 at different timings from the normal memory cells MC00, MC01,... By the write signals rhodd and rweven output from the reference cell write circuit 62. .

  In the case of the second embodiment, during the fatigue test, the fatigue test mode signal tmfat rises to “H”, so that at the time t1, the reference word line driver 51, the reference plate line driver 61, the word line driver 50, and the plate line The driver 60 causes the reference word line rwl and the reference plate line rpl to rise at the same timing as the word line wl and the plate line pl, and the “L” write signals rwodd and rweven output from the reference cell write circuit 62 The reference cell write control circuits 21-0, 21-1,... Are deactivated, and the storage nodes st and stb of the reference ferroelectric capacitors RCx0 and RCx1 are brought into a floating state. By doing so, the data writing to the reference ferroelectric capacitors RCx0 and RCx1 is performed simultaneously with the data writing to the ferroelectric capacitors Cx0 and Cx1. In this way, at time t1 to t10, the same operation as that of the first embodiment is performed, so that data rewriting (“0” → “1” → “0”) of the reference ferroelectric capacitor RCx0 is made ferroelectric. Data rewriting (“1” → “0” → “1”) of the ferroelectric capacitor Cx0 and the reference ferroelectric capacitor RCx1 can be performed simultaneously with the ferroelectric capacitor Cx1. That is, the fatigue test of the reference ferroelectric capacitors RCx0 and RCx1 can be performed simultaneously with the ferroelectric capacitors Cx0 and Cx1.

(Effect of Example 2)
The second embodiment has substantially the same effect as the first embodiment. Further, in the fatigue test, the reference word line rwl and the reference plate line rpl are operated in the same manner as the normal word line wl and the plate line pl. , The reference cell write control circuits 21-0, 21-1,... Are deactivated by the reference cell write circuit 62 to which the fatigue test mode signal tmfat is input, thereby performing the fatigue test of the reference ferroelectric capacitors RCx0 and RCx1. This can be performed simultaneously with the normal ferroelectric capacitors Cx0 and Cx1.

(Configuration of Example 3)
FIG. 5 is a block diagram of a 2T2C type ferroelectric memory that is a nonvolatile semiconductor memory device showing Embodiment 3 of the present invention. Elements common to those in FIG. Is attached.

  In the 2T2C type ferroelectric memory of the third embodiment, the fatigue test mode signal tmfat is input to the SA control circuit 70 that outputs the sense amplifier enable signal sae, the equalize signal bleq, and the column selection signal ysel. The configuration is such that the sense amplifier enable signal sae, the equalize signal bleq, and the column selection signal ysel can be deactivated by the signal tmfat. Other configurations are the same as those of the first embodiment.

(Operation of Fate Test of Example 3)
FIG. 6 is a diagram showing an operating waveform at the time of a fatigue test in the ferroelectric memory of FIG. 5 and hysteresis curves of all ferroelectric capacitors Cxxx (C000, C010, C100,...). Is the potential. In addition, the arrow in a hysteresis curve has shown the moving direction of the polarization amount.

  For example, it is assumed that data “1” is written in all the ferroelectric capacitors Cxxx as an initial state.

  In the case of the third embodiment, during the fatigue test, as described later, the ferroelectric capacitor Cxx0 (C000, C010, C100, C110,...) And the ferroelectric capacitor Cxx1 (C001, C011, C101, C111,...) The same data is written instead of complementary data. When the fatigue test mode signal tmfat becomes “H”, the SA control circuit 70 sets the sense amplifier enable signal sae to “L”, the equalize signal bleq to “L”, and the column selection signal ysel to “L”. The sense amplifiers SA (SA0, SA1,...) Are deactivated, and all word lines wl (wl0, wl1,...) Are fixed to “H” by the word line driver 50.

  When all the plate lines pl (pl0, pl1,...) Rise by the plate line driver 60 at time t1, all the bit lines bl (bl0, bl1,...) And all the complementary bit lines blb (blb0, blb1,. Are connected to the reference potential Vref via the transfer gates CT00, CT01, CT10, CT11,..., And since this reference potential Vref is “0”, all ferroelectric capacitors Cxxx are “0”. Is written (the polarization amount of the hysteresis curve moves in the lower left direction).

  At time t2, all the plate lines pl fall by the plate line driver 60. When the reference potential Vref becomes “H” at time t3, “1” is written to all the ferroelectric capacitors Cxxx (the polarization amount of the hysteresis curve moves to the upper right direction of “0”). At time t4, the reference potential Vref becomes “0” (the amount of polarization of the hysteresis curve moves in the upper right direction). Thus, from time t1 to time t4, all the ferroelectric capacitors Cxxx are rewritten from “1” → “0” → “1”.

(Effect of Example 3)
The third embodiment has substantially the same effect as the first embodiment. Further, in the fatigue test, all the sense amplifiers SA are deactivated, all the word lines wl are raised, and the reference potential Vref is set to the bit. The bit line bl and the complementary bit line blb are controlled by the reference potential Vref without being connected to the line bl and the complementary bit line blb, and not via the write driver (not shown) that drives the sense amplifier SA and the digit lines db and dbb. By alternately raising / falling the plate line pl and the reference potential Vref, data can be written to the ferroelectric capacitor Cxxx at a faster speed than the normal write operation, and the ferroelectric capacitor Cxxx fatigue test time Can be shortened.

(Configuration of Example 4)
FIG. 7 is a configuration diagram of a 1T1C type ferroelectric memory which is a nonvolatile semiconductor memory device showing Embodiment 4 of the present invention. Elements common to the elements in FIG. Is attached.

  In the 1T1C type ferroelectric memory according to the fourth embodiment, the fatigue test mode signal tmfat is input to the SA control circuit 70 that outputs the sense amplifier enable signal sae, the equalize signal bleq, and the column selection signal ysel. The configuration is such that the sense amplifier enable signal sae, the equalize signal bleq, and the column selection signal ysel can be deactivated by the signal tmfat. Other configurations are the same as those of the second embodiment.

(Operation of Fate Test of Example 4)
FIG. 8 shows operation waveforms during the fatigue test in the ferroelectric memory of FIG. 7, all ferroelectric capacitors Cxx (C00, C01, C10,...) And all reference ferroelectric capacitors RCxx (RC00, RC01, RC10, ..)), And the horizontal axis represents time and the vertical axis represents potential. In addition, the arrow in a hysteresis curve has shown the moving direction of the polarization amount.

  Assume that “1” is written in all ferroelectric capacitors Cxx and all reference ferroelectric capacitors RCxx as an initial state.

  At the time of the fatigue test, when the fatigue test mode signal tmfat rises, the reference word line rwl (rwl0, rwl1,...) Is fixed to “H” by the reference word line driver 61, and at time t1, the reference plate line driver 61, And the plate line driver 60 causes the reference plate lines rpl (rpl0, rpl1,...) To rise at the same timing as the plate lines pl (pl0, pl1,...), And the write signals rwodd, rweven output from the reference cell write circuit 62. The reference cell write control circuits 21-0, 21-1,... Are deactivated (the polarization amounts of Cxx and RCxx move in the lower left direction of the hysteresis curve). By doing so, the data writing to the reference ferroelectric capacitor RCxx is performed simultaneously with the data writing to the ferroelectric capacitor Cxx.

  In this way, at time t1 to t5, by performing the same operation as in the third embodiment, rewriting of data of the reference ferroelectric capacitor RCxx (“1” → “0” → “1”) is made ferroelectric. Can be executed simultaneously with body capacitor Cxx. That is, the fatigue test of the reference ferroelectric capacitor RCxx can be performed simultaneously with the ferroelectric capacitor Cxx.

(Effect of Example 4)
The fourth embodiment has substantially the same effect as the first embodiment. Further, in the fat test, the sense amplifiers SA (SA0, SA1,...) Are inactivated, all the reference word lines rwl, and all the words. The line wl is raised, the reference potential Vref is connected to the bit line bl and the complementary bit line blb, and all the plate lines pl and the reference potential Vref are alternately raised / falled to make the reference ferroelectric The fatigue test of all the ferroelectric capacitors Cxx including the body capacitor RCxx can be performed simultaneously, and the fatigue test time can be shortened.

(Configuration of Example 5)
FIG. 9 is a block diagram of a 1T1C type ferroelectric memory which is a nonvolatile semiconductor memory device showing Embodiment 5 of the present invention. Elements common to those in FIG. Is attached.

  In the 1T1C type ferroelectric memory of the fifth embodiment, the Vref generation circuits 20-0, 20-1,..., The reference word line driver 51, the reference plate line driver 61, the reference cell write circuit 62, and the reference of the second embodiment. The cell control circuit 63 is omitted. Furthermore, instead of the reference potential Vref which is the reference potential in the second embodiment, the first and second pads supplied from the outside of the chip via the first and second pads and the first and second power lines connected thereto are provided. Second reference potentials (for example, complementary reference potentials) Vrefbl and Vrefblb are inputted, and equalizing transistors PET01, PET23, which newly connect two adjacent plate lines pl0 and pl1, pl2 and pl3,. … Is provided.

  Each of the equalizing transistors PET01, PET23,... Is configured by, for example, an NMOS that is turned on / off by a plate line equalize signal pleq. In each Vref control circuit 30-0, 30-1, ..., the internal transfer gates CT00, CT01, ... connect the bit lines bl0, bl1, ... to the reference potential Vrefbl, and the internal transfer gates CT10, CT11, ... Have a function of connecting the complementary bit lines blb0, blb1,... To the reference potential Vrefblb. Other configurations are the same as those of the second embodiment.

(Operation of Fate Test of Example 5)
FIG. 10 shows operation waveforms at the time of a fatigue test in the ferroelectric memory of FIG. 9, ferroelectric capacitors Cx0 (C00, C10,...), Cx2 (C02, C2 connected to bit lines bl (bl0, bl1,...). ... and hysteresis curves of ferroelectric capacitors Cx1 (C01, C11, ...), Cx3 (C03, C13, ...), ... connected to the complementary bit lines blb (blb0, blb1, ...) The horizontal axis represents time, and the vertical axis represents potential. In addition, the arrow in a hysteresis curve has shown the moving direction of the polarization amount.

  During the fatigue test, since the control signals vrefbl and vrefblb are “H” and the control signals xvrefbl and xvrefblb are “L”, all the transfer gates CT00, CT01,... Are turned on, and the bit line bl and the reference potential Vrefbl, The complementary bit line blb and the reference potential Vrefblb are always connected.

  At time t0, the plate lines pl0, pl2,... Are "H", the plate lines pl1, pl3, ... are "L", the reference potential Vrefbl is "L", and the reference potential Vrefblb is "H". “0” is written in the capacitors Cx0, Cx2,..., And “1” is written in the ferroelectric capacitors Cx1, Cx3,.

  At time t1, the reference potentials Vrefbl and Vrefblb and the plate line pl are inverted. Since the plurality of ferroelectric capacitors Cx0, Cx1, Cx2, Cx3,... Are connected to the plate line pl and the capacitance is large, the rise / fall time is delayed. Therefore, the inversion time of the plate line pl can be shortened by inputting a one-shot pulse to the plate line equalize signal bleq and executing charge recycling between the plate lines pl0 and pl1, pl2 and pl3,. . By performing these operations, “1” is written in the ferroelectric capacitors Cx0, Cx2,..., And “0” is written in the ferroelectric capacitors Cx1, Cx3,.

  At time t2, reverse data is written to the ferroelectric capacitors Cx0, Cx1, Cx2, Cx3,... By inverting the reference potentials Vrefbl and Vrefblb and the potential of the plate line pl. The fatigue test is performed by repeating these steps.

(Effect of Example 5)
The fifth embodiment has substantially the same effect as the first embodiment. Further, the reference potential Vref connected to the bit line bl and the complementary bit line blb is separated into the reference potential Vrefbl and Vrefblb, and the ferroelectric capacitor in the fatigue test is obtained. When rewriting the data of Cx0, Cx1, Cx2, Cx3, ..., the separated reference potentials Vrefbl and Vrefblb are alternately raised, and when adjacent plate lines pl0 and pl1, pl2 and pl3, ... are alternately raised, By performing charge recycling between the plate lines, the rise / fall time of the plate line pl can be increased, and the fatigue test time can be shortened.

  In addition, this invention is not limited to Examples 1-5, For example, you may comprise the array block AB using another transistor, or you may change into circuit structures other than illustration.

1 is a configuration diagram of a 2T2C type ferroelectric memory showing Embodiment 1 of the present invention. FIG. It is the operation | movement waveform and hysteresis curve figure of FIG. It is a block diagram of the 1T1C type ferroelectric memory which shows Example 2 of this invention. FIG. 4 is an operation waveform and hysteresis curve diagram of FIG. 3. It is a block diagram of 2T2C type ferroelectric memory which shows Example 3 of this invention. FIG. 6 is an operation waveform and hysteresis curve diagram of FIG. 5. It is a block diagram of the 1T1C type ferroelectric memory which shows Example 4 of this invention. FIG. 8 is an operation waveform and hysteresis curve diagram of FIG. 7. It is a block diagram of the 1T1C type ferroelectric memory which shows Example 5 of this invention. FIG. 10 is an operation waveform and hysteresis curve diagram of FIG. 9. It is a hysteresis characteristic view of a ferroelectric memory. It is a block diagram which shows the principal part of the conventional 2T2C type ferroelectric memory. FIG. 13 is a rewrite operation waveform diagram of FIG. 12. It is a block diagram which shows the principal part of the conventional 1T1C type ferroelectric memory. FIG. 15 is a rewrite operation waveform diagram of FIG. 14. FIG. 6 is a distribution diagram of potentials V0 and V1 in a conventional ferroelectric capacitor. It is a circuit block diagram for performing the Vref application test of the conventional ferroelectric memory. FIG. 18 is an operation waveform diagram of a Vref application test in the ferroelectric memory of FIG. 17. It is a principle diagram of a conventional fatigue test. It is a circuit block diagram for performing a fatigue test in a conventional ferroelectric memory.

Explanation of symbols

AB array block
MC00, MC01, ... Memory cells
SA0, SA1,... Sense amplifiers 20-0, 20-1 Vref generation circuit 30-0, 30-1 Vref control circuit 50 Word line driver 51 Reference word line driver 60 Plate line driver 61 Reference plate line driver 62 Reference cell Write circuit 63 Reference cell control circuit 70 SA control circuit 80-0, 80-1 Vref control circuit

Claims (18)

A selection transistor that is turned on / off by a potential of a word line, and a ferroelectric capacitor, wherein the selection transistor and the ferroelectric capacitor are connected in series between a bit line and a plate line;
A switch that performs on / off operation, and connects / disconnects the power line of the reference potential supplied from the outside through the pad and the bit line;
A semiconductor memory device comprising: First and second selection transistors that are turned on / off by a potential of a word line, and first and second ferroelectric capacitors, wherein the first selection transistor and the first ferroelectric capacitor are , Of the complementary first and second bit lines, connected in series between the first bit line and the plate line, and the second selection transistor and the second ferroelectric capacitor are: A memory cell connected in series between the second bit line and the plate line;
A sense amplifier for amplifying a potential difference between the first and second bit lines;
A first switch that performs an on / off operation to connect / cut off a power supply line of a reference potential supplied from the outside via a pad and the first bit line;
A second switch that is turned on / off to connect / cut off the power supply line and the second bit line;
A semiconductor memory device comprising: A first select transistor that is turned on / off by a potential of a first word line; and a first ferroelectric capacitor, wherein the first select transistor and the first ferroelectric capacitor are complementary to each other. A first memory cell connected in series between the first bit line and the first plate line of the first and second bit lines;
A second select transistor that performs an on / off operation according to a potential of a second word line; and a second ferroelectric capacitor, wherein the second select transistor and the second ferroelectric capacitor include the second select transistor and the second ferroelectric capacitor. A second memory cell connected in series between the two bit lines and the second plate line;
A sense amplifier for amplifying a potential difference between the first and second bit lines;
A first switch that performs an on / off operation to connect / cut off a power supply line of a reference potential supplied from the outside via a pad and the first bit line;
A second switch that is turned on / off to connect / cut off the power supply line and the second bit line;
A semiconductor memory device comprising:   4. The semiconductor memory device according to claim 1, further comprising a reference potential control circuit that controls on / off of the switch based on a reference potential application test signal and a fatigue test signal. Using the semiconductor memory device according to any one of claims 1 to 4,
During a reference potential application test, the switch is turned on and the reference potential is applied to the bit line,
A testing method for a semiconductor memory device, wherein, during a fatigue test, the switch is turned on and the plate line is activated to rewrite data in the ferroelectric capacitor. Using the semiconductor memory device according to claim 2,
In the fatigue test, the reference potential is set to the ground potential, the first or second switch on the side where data “0” is written is turned on, and the sense amplifier is activated to activate the first and second switches. A test method for a semiconductor memory device, comprising: amplifying a potential difference between two bit lines and writing data to the first and second ferroelectric capacitors. A selection transistor that is turned on / off by a potential of a word line, and a ferroelectric capacitor, wherein the selection transistor and the ferroelectric capacitor are connected in series between a bit line and a plate line;
A reference selection transistor that is turned on / off by a potential of a reference word line; and a reference ferroelectric capacitor, wherein the reference selection transistor and the reference ferroelectric capacitor are the bit line and the reference plate line. A reference memory cell connected in series between
A switch that performs on / off operation, and connects / disconnects the power line of the reference potential supplied from the outside through the pad and the bit line;
A semiconductor memory device comprising: A first select transistor that is turned on / off by a potential of a first word line; and a first ferroelectric capacitor, wherein the first select transistor and the first ferroelectric capacitor are complementary to each other. A first memory cell connected in series between the first bit line and the first plate line of the first and second bit lines;
A second select transistor that performs an on / off operation according to a potential of a second word line; and a second ferroelectric capacitor, wherein the second select transistor and the second ferroelectric capacitor include the second select transistor and the second ferroelectric capacitor. A second memory cell connected in series between the two bit lines and the second plate line;
A first reference selection transistor that is turned on / off by a potential of a first reference word line; and a first reference ferroelectric capacitor, the first reference selection transistor and the first reference selection transistor; A first reference memory cell in which a reference ferroelectric capacitor is connected in series between the first bit line and the first reference plate line;
A second reference selection transistor that is turned on / off by the potential of the second reference word line; and a second reference ferroelectric capacitor, wherein the second reference selection transistor and the second reference selection transistor A second reference memory cell in which a reference ferroelectric capacitor is connected in series between the second bit line and a second reference plate line;
A sense amplifier for amplifying a potential difference between the first and second bit lines;
A first switch that performs an on / off operation to connect / cut off a power supply line of a reference potential supplied from the outside via a pad and the first bit line;
A second switch that is turned on / off to connect / cut off the power supply line and the second bit line;
A semiconductor memory device comprising:   9. The semiconductor memory device according to claim 7, further comprising a reference word line driver that drives the reference word line at the same timing as the word line by a fatigue test signal.   9. The semiconductor memory device according to claim 7, further comprising a reference plate line driver that drives the reference plate line at the same timing as the plate line by a fatigue test signal. A reference cell write control circuit for controlling writing of data to the reference ferroelectric capacitor;
A reference cell write circuit that inactivates the reference cell write control circuit by a fatigue test signal;
The semiconductor memory device according to claim 7, wherein the semiconductor memory device is provided. Using the semiconductor memory device according to any one of claims 7 to 11,
During the fatigue test, the switch is turned on and the plate line and the reference plate line are activated to simultaneously rewrite the data on the ferroelectric capacitor and the reference ferroelectric capacitor. A test method for a semiconductor memory device. Using the semiconductor memory device according to claim 2 or 3,
A testing method of a semiconductor memory device, wherein, during a fatigue test, the sense amplifier is deactivated, and data is written to the ferroelectric capacitor by the potential of the power supply line and the potential of the plate line.   14. The semiconductor memory device testing method according to claim 13, wherein a fatigue test is performed on the plurality of ferroelectric capacitors by using all the plate lines and the power supply lines. Using the semiconductor memory device according to claim 8,
A semiconductor memory device, wherein the sense amplifier is deactivated during a fatigue test, and data is written to the reference ferroelectric capacitor by the potential of the power supply line and the potential of the reference plate line Test method.   The power supply line includes a first power supply line having a first reference potential supplied from the outside through a first pad and a second power supply having a second reference potential supplied from the outside through a second pad. 4. The power supply line according to claim 3, wherein the first power supply line is connected to the first switch, and the second power supply line is connected to the second switch. Semiconductor memory device. A semiconductor memory device according to claim 16,
The first ferroelectric capacitor connected to the first bit line connected to the first switch, and the second ferroelectric connected to the second bit line connected to the second switch. A test method for a semiconductor memory device, wherein data “0” and “1” are alternately written in a body capacitor. A semiconductor memory device according to claim 16,
A charge recycling transistor is connected between the adjacent first and second plate lines;
A test of a semiconductor memory device characterized in that when the first and second plate lines are alternately raised, the first and second plate lines are raised and lowered using charge recycling. Method.

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