JP4648830B2 - Optical sensor circuit - Google Patents

Description

  The present invention relates to an optical sensor circuit, and more particularly to an optical sensor circuit suitable for detecting weak light with high sensitivity by amplifying a photocurrent from a photoelectric conversion element that converts an optical signal into an electrical signal by a CMOS inverter.

  Conventionally, as a photosensor circuit that detects weak optical signals by converting them into electrical signals with high sensitivity, it uses a CMOS (Complementary Metal Oxide Semiconductor) inverter to amplify the photocurrent output from a photodiode, which is a photoelectric conversion element. An optical sensor circuit configured to do this is known (Patent Document 1). The CMOS inverter is used as the amplifying means because the circuit configuration is simple and it is easy to manufacture an integrated circuit as the image sensor chip. This CMOS inverter is constituted by a kind of push-pull circuit using P-channel and N-channel enhancement type MOS transistors.

  6 and 7 show the circuit configuration of the CMOS inverter. FIG. 6 shows an electric circuit of a main part of one pixel of the image sensor, that is, one photosensor circuit. One photosensor circuit 101 includes a photodiode PD and a capacitor C that is a parasitic capacitance connected in parallel between the anode and the cathode of the photodiode PD. A power supply 102 (Vdd) is connected between the cathode of the photodiode PD and the ground. The enhancement type MOS transistor 103 is connected to the anode side of the photodiode PD. The anode of the photodiode PD is connected to two gates of the enhancement type MOS transistor 103, and a sensor signal is input to the enhancement type MOS transistor 103. A terminal 103 a connected to the two gates is an input terminal of the enhancement type MOS transistor 103. The terminal 103b of the enhancement type MOS transistor 103 is an output terminal for outputting a sensor signal. The drain and source of the MOS type switching transistor 104 are connected to the input terminal 103a and the output terminal 103b of the enhancement type MOS transistor 103 in parallel connection relation. Further, the voltage VDD (= 5 V) is applied to the upper terminal in FIG. 6 of the enhancement type MOS transistor 103, and the lower terminal is connected to the ground.

  When the enhancement type MOS transistor 103 shown in FIG. 6 is expressed as a CMOS inverter IA, the electric circuit is as shown in FIG. In FIG. 7, the same elements as those described in FIG. In the circuit configuration shown in FIG. 7, the MOS switching transistor 104 connects or disconnects the input terminal and the output terminal of the CMOS inverter IA. When the MOS type switching transistor 104 is on (the gate voltage is Lo level), the input terminal and the output terminal of the CMOS inverter IA are connected (short circuit), and when the MOS type switching transistor 104 is off (the gate voltage is Hi level), the CMOS inverter The input terminal and output terminal of the IA are blocked. The operating point (bias point) of the CMOS inverter IA and the photodiode PD is set by setting the gate voltage of the MOS switching transistor 104 to the Lo level and short-circuiting the input terminal and the output terminal of the CMOS inverter IA. The operating point (bias point) of the CMOS inverter IA is set as an intersection between the input / output characteristic curve of the CMOS inverter IA and a straight line satisfying the relationship of input voltage (Vin) = output voltage (Vout) (see Patent Document 1). (See FIG. 4). The operating point of the CMOS inverter IA is set approximately near the center of the linear linear region at the center of the input / output characteristic curve. Near the center of the linear region is the place with the largest amplification factor (gain). As described above, when the MOS switching transistor 104 is switched from on (connected) to off (cut off), the voltage change at the output terminal of the photodiode PD can be amplified with a high amplification factor and read out to the output terminal. It becomes possible to detect faint light with high sensitivity.

  By preparing a large number of optical sensor circuits 101 having the circuit configuration as described above and arranging them in a matrix, a two-dimensional image sensor that captures an image can be made.

Such an optical sensor circuit 101 has a characteristic that it can be detected with high sensitivity even with a small amount of light, and its application to photographing in a dark place such as at night is under study.
JP-A-11-220657

  In the image sensor disclosed in Patent Document 1 described above, the photocurrent converted by the photodiode is amplified using the linear region of the input / output characteristic curve of the CMOS inverter. Since saturation occurs, the dynamic range is limited to the linear region, and there is a problem that the dynamic range is narrow. For this reason, there is a problem that it is difficult to shoot a bright and dark image.

  In view of the above problems, an object of the present invention is to provide an optical sensor circuit capable of expanding a dynamic range of an input / output characteristic curve of a CMOS inverter in an optical sensor circuit that amplifies photocurrent with a CMOS inverter.

  The optical sensor circuit according to the present invention is configured as follows in order to achieve the above object.

A first photosensor circuit (corresponding to claim 1) includes a capacitive element connected in parallel between two electrodes, and a photoelectric conversion element that converts incident light into a current signal, and one of the photoelectric conversion elements Current signal according to the operating point indicated by the intersection of the input / output characteristic curve showing the relationship between the input side potential and the output side potential and the straight line when the input side potential and the output side potential are equal Controls the connection or disconnection between the CMOS inverter that amplifies and the input end and output end of the CMOS inverter, and moves the operating point for the input side potential to the high potential side due to capacitive coupling at the input side potential of the CMOS inverter at the time of disconnection a PMOS-type switching transistor for controlling to make a pixel selection transistor connected to the output side of the CMOS inverter, PMOS-type switching transistor The gate voltage when turned off, and a voltage control means for setting to a value greater than the difference between the threshold voltage of the potential and PMOS-type switching transistor operating point of the CMOS inverter, the voltage control means, PMOS type controls the gate voltage of the switching transistor, when it is operating in a sub-threshold state of the PMOS-type switching transistor, configured to switch the output of the CMOS inverter to the logarithmic response characteristic output from the straight-line response characteristic output Is done.

  In the above optical sensor circuit, the gate voltage when turning off the PMOS switching transistor that selects connection or disconnection between the input terminal and the output terminal of the CMOS inverter is set to be a predetermined voltage by the voltage control means. The dynamic range of the input / output characteristic curve of the CMOS inverter can be expanded.

A second optical sensor circuit (corresponding to claim 2) includes a capacitive element connected in parallel between two electrodes, a photoelectric conversion element that converts incident light into a current signal, and a photoelectric conversion element The input side is connected to one of the electrodes, and the current follows the operating point indicated by the intersection of the input / output characteristic curve indicating the relationship between the input side potential and the output side potential and the straight line when the input side potential and the output side potential are equal. a CMOS inverter for amplifying the signal, and controls the connection or disconnection between the input and output terminals of CMOS inverter, the operating point for the input voltage at the time of cut-off due to capacitive coupling at the input side potential of the CMOS inverter to the low potential side and NMOS switching transistor for controlling to move to, and a pixel selection transistor connected to the output side of the CMOS inverter, NMOS switching transients scan The gate voltage for turning off the, and a voltage control means for setting a value smaller than the sum of the threshold voltage of the potential and NMOS switching transistor operating point of the CMOS inverter, the voltage control means, controls the gate voltage of the NMOS switching transistor, when it is operating in a sub-threshold state of the NMOS switching transistor, to switch the output of the CMOS inverter to the logarithmic response characteristic output from the straight-line response characteristic output Configured.

  In the above optical sensor circuit, the gate voltage when turning off the NMOS type switching transistor that selects connection or disconnection between the input terminal and the output terminal of the CMOS inverter is set to a predetermined voltage by the voltage control means. The dynamic range of the input / output characteristic curve of the CMOS inverter can be expanded.

  According to the present invention, the gate voltage when turning off the PMOS-type or NMOS-type switching transistor that selects connection or disconnection between the input terminal and the output terminal of the CMOS inverter is set to a predetermined voltage by the voltage control means. Therefore, the linear response characteristic is used for weak light, the logarithmic conversion response characteristic is used for strong light, and the dynamic range of the input / output characteristic curve of the CMOS inverter can be expanded during amplification.

  DESCRIPTION OF EMBODIMENTS Preferred embodiments (examples) of the present invention will be described below with reference to the accompanying drawings.

  A first embodiment of an optical sensor circuit according to the present invention will be described with reference to FIGS. FIG. 1 shows an electric circuit showing one photosensor circuit (pixel) according to the present embodiment. In FIG. 1, elements that are substantially the same as those described in FIG. FIG. 2 is a graph showing a change state of the operating point (bias point) of the CMOS inverter included in the photosensor circuit.

  In FIG. 1, one photosensor circuit 10 includes a photodiode PD and a capacitor C, which is a parasitic capacitance, connected in parallel between the anode 11a and the cathode 11b of the photodiode PD. The photodiode PD converts the light L1 incident on the light receiving surface into a current signal. This current signal is accumulated in the capacitor C when the output side of the photodiode PD is in an open state.

  The anode 11a of the photodiode PD is connected to the ground. On the other hand, the input terminal of the CMOS inverter IA is connected to the cathode 11b of the photodiode PD. The CMOS inverter IA is a kind of push-pull circuit using P-channel and N-channel enhancement type MOS transistors. The drain and the source of the PMOS switching transistor 12 are connected to the input terminal and the output terminal of the CMOS inverter IA in parallel connection relation.

  The PMOS switching transistor 12 connects or disconnects the input terminal and the output terminal in the CMOS inverter IA. When the PMOS type switching transistor 12 is on (the gate voltage is Lo level), the input terminal and the output terminal of the CMOS inverter IA are connected (short circuited), and when the PMOS type switching transistor 12 is off (the gate voltage is Hi level), the CMOS inverter The input terminal and output terminal of the IA are blocked. The operating point (bias point) of the CMOS inverter IA and the photodiode PD is set by switching the gate voltage of the PMOS switching transistor 12 from the Hi level to the Lo level and short-circuiting the input terminal and the output terminal of the CMOS inverter IA. As shown in FIG. 2, the operating point (bias point) of the CMOS inverter IA is an intersection P1 between the input / output characteristic curve C1 of the CMOS inverter IA and a straight line C2 that satisfies the relationship of input voltage (Vin) = output voltage (Vout). Set as

  The operating point of the CMOS inverter IA is set near the center of the linear linear region at the center of the input / output characteristic curve C1. Near the center of the linear region is the place with the largest amplification factor (gain). When the PMOS switching transistor 12 is switched from on (connected) to off (cut off) as described above, the voltage change at the output terminal of the photodiode PD can be amplified with a high amplification factor and read out to the output terminal. It becomes possible to detect faint light with high sensitivity.

  A gate voltage for controlling the on / off operation of the PMOS switching transistor 12 is supplied from the voltage control unit 13. The state of the gate voltage of the PMOS switching transistor 12 is more precisely controlled by the voltage control unit 13 as will be described later.

  Further, a MOS transistor 14 for pixel selection is connected to the output terminal of the CMOS inverter IA. An output terminal is drawn from the NMOS transistor 14.

  According to the configuration of the optical sensor circuit 20 described above, the following operation occurs. A PMOS type switching transistor 12 is used as a switching means for connecting or disconnecting an input terminal and an output terminal in the CMOS inverter IA. In order to accumulate photoelectric charge in the capacitor C of the photodiode PD, when the PMOS switching transistor 12 is turned off and the MOS inverter IA is shut off, the direction of change due to capacitive coupling at the input side potential of the CMOS inverter IA is reversed, The position of the operating point of the CMOS inverter IA can be moved to the high potential side with respect to the input terminal side potential. This state is indicated by an arrow AR11 in FIG. Further, when the photodiode PD subsequently undergoes a photoelectric conversion action and the potential on the cathode 11b side drops due to the incidence of the light L1 (accumulation), the operating point of the CMOS inverter IA is conversely low in terms of the input end side potential. To the side. This state is indicated by an arrow AR12 (during accumulation) in FIG. As a result, according to the photosensor circuit 10, the accumulation of photocharge in the photodiode PD is started in a state where the input terminal side potential after the PMOS switching transistor 12 is turned off is lowered. As a result, the linear region of the input / output characteristic curve C1 of the CMOS inverter IA can be used effectively, and the response region can be expanded by effectively utilizing the dynamic range of the linear region.

  Further, in the present embodiment, the voltage control unit 13 controls the gate voltage of the PMOS type switching transistor 12 that connects / disconnects the input / output end of the CMOS inverter IA, thereby providing knee characteristics (logarithmic conversion). I am doing so. The operating conditions are as follows.

  When the PMOS switching transistor 12 is turned off (turned off), the gate voltage is set by the voltage control unit 13 to be within a predetermined range. The lower limit value of the range is made larger than the difference between the potential of the operating point (P1) of the CMOS inverter IA and the threshold voltage of the PMOS switching transistor 12. This is because the gate voltage value for operating the PMOS switching transistor 12 is set. The upper limit of the above range is not particularly limited, but generally, the voltage value of the power supply (Vdd) is used.

  As a result, in the output characteristic of the CMOS inverter IA as shown in FIG. 3, the linear response characteristic C21 can be switched to the logarithmic response characteristic C22 with a certain threshold value. This phenomenon is because a photocurrent flows in the photodiode PD, but this photocurrent is supplied through the PMOS switching transistor 12, and the CMOS inverter IA tends to fall to a stable point. In particular, when the potential difference is equal to or lower than the threshold voltage value, the PMOS switching transistor 12 is almost in an OFF state, so that the first change is linear, and on the other hand, when the flowing current increases, the PMOS switching transistor 12 The output in the sub-threshold state exhibits logarithmic characteristics. Thereby, the dynamic range of the input / output characteristics of the optical sensor circuit 10 can be expanded.

  As described above, when the PMOS switching transistor 12 is turned off and the CMOS inverter IA is shut off, the position of the operating point of the CMOS inverter IA moves toward the high potential side toward the end of the linear region. It depends on the transistor characteristics of the type switching transistor 12. After that, when the photodiode PD causes a photoelectric conversion action, the potential on the cathode 11b side is lowered, so that the input voltage of the CMOS inverter IA falls to the low potential side.

  According to the optical sensor circuit 10, when the photoelectric charge generated in the photodiode PD is small, that is, when the light L1 has low illuminance, linear operation is performed using the linear region of the CMOS inverter IA. . When the illuminance of the light L1 increases and the photocharge increases, a logarithmic conversion operation is performed using the above knee characteristics of the PMOS switching transistor 12 to obtain a logarithmic output. By keeping the gate voltage value of the PMOS switching transistor 12 within a predetermined range as described above, the linear operation region becomes narrower as the lower limit value of the predetermined range is approached, and the logarithmic conversion operation becomes wider as the upper limit value is approached. .

  As described above, the dynamic range can be expanded by keeping the value of the gate voltage of the PMOS switching transistor 12 within the predetermined range as described above.

  Next, a second embodiment of the optical sensor circuit according to the present invention will be described with reference to FIGS. 4 is a view similar to FIG. 1, and FIG. 5 is a view similar to FIG. 4 and 5, the same elements as those described in FIGS. 1 and 2 are denoted by the same reference numerals.

  The photosensor circuit 20 according to this embodiment includes a photodiode PD and a capacitor C connected in parallel between the anode 11a and the cathode 11b of the photodiode PD. A voltage Vdd is applied to the cathode 11b of the photodiode PD. The input terminal of the CMOS inverter IA is connected to the anode 11a of the photodiode PD. The drain and source of the NMOS switching transistor 21 are connected to the input terminal and the output terminal of the CMOS inverter IA in a parallel connection relationship.

  The NMOS switching transistor 21 connects or disconnects the input terminal and the output terminal in the CMOS inverter IA. When the NMOS switching transistor 21 is on (the gate voltage is high level Hi), the input terminal and the output terminal of the CMOS inverter IA are connected (short-circuited), and when the NMOS type switching transistor 21 is off (the gate voltage is low level Lo) The input terminal and output terminal of the CMOS inverter IA are cut off. The gate voltage when the NMOS switching transistor 21 is cut off (turned off) is set by the voltage control unit 13 so as to be within a predetermined range. The lower limit value of the range is generally ground, and the upper limit value is the total value of the potential of the operating point (P1) of the CMOS inverter IA and the threshold voltage of the NMOS switching transistor 21. The other functions of the NMOS switching transistor 21 are the same as the functions of the PMOS switching transistor 12 described in the first embodiment. Other circuit configurations are the same as those of the optical sensor circuit 10 of the first embodiment.

  According to the configuration of the optical sensor circuit 20 described above, the following operation occurs. An NMOS type switching transistor 21 is used as a switching means for connecting or blocking the input terminal and the output terminal in the CMOS inverter IA. Therefore, when the NMOS switching transistor 21 is turned off and the MOS inverter IA is cut off in order to accumulate photocharge in the capacitor C of the photodiode PD, the direction of change due to capacitive coupling at the input side potential of the CMOS inverter IA is reversed. The position of the operating point of the CMOS inverter IA can be moved to the low potential side with respect to the input terminal side potential. This state is indicated by an arrow AR21 in FIG. Further, when the photodiode PD subsequently undergoes a photoelectric conversion action and the potential on the cathode 11b side rises due to the incidence of the light L1 (at the time of accumulation), the operating point of the CMOS inverter IA is oppositely high in terms of the input end side potential. To the side. This state is indicated by an arrow AR22 (during accumulation) in FIG.

  Furthermore, according to the photosensor circuit 20, when the photocharge generated in the photodiode PD is small, that is, when the light L1 has low illuminance, linear operation is performed using the linear region of the CMOS inverter IA. I do. When the illuminance of the light L1 increases and the photocharge increases, a logarithmic conversion operation is performed using the above knee characteristics of the NMOS switching transistor 21 to obtain a logarithmic output.

  As described above, according to the photosensor circuit 20 of the present embodiment, the accumulation of photocharge in the photodiode PD (the increase in the input side potential of the CMOS inverter IA) is the input after the NMOS switching transistor 21 is turned off. This is started in a state where the end side potential is lowered. As a result, the linear region of the input / output characteristic curve of the CMOS inverter IA can be used effectively, and the response region can be expanded by effectively utilizing the dynamic range of the linear region. Furthermore, the dynamic range can be expanded by keeping the value of the gate voltage of the NMOS switching transistor 21 within the predetermined range as described above.

  The optical sensor circuit according to the present invention can be modified as follows. In the photosensor circuit of the first embodiment, a P / N-MOS type switching transistor can be used instead of using a PMOS type switching transistor. In the photosensor circuit of the second embodiment, a P / N-MOS type switching transistor can be used instead of using an NMOS type switching transistor. According to the configuration of these modified embodiments, it is possible to eliminate changes during switching in addition to the above-described operational effects.

  An image sensor that captures a two-dimensional image can be made by preparing a large number of optical sensor circuits of the respective embodiments having the circuit configuration as described above and arranging them in a matrix.

  The configurations, shapes, sizes, and arrangement relationships described in the above embodiments are merely schematically shown to the extent that the present invention can be understood and implemented. Therefore, the present invention is not limited to the described embodiments, and can be variously modified without departing from the scope of the technical idea shown in the claims.

  INDUSTRIAL APPLICABILITY The present invention is used as an optical sensor circuit of an image sensor that can detect faint light with high sensitivity, can widely use a dynamic range in a linear region, and can further expand the dynamic range.

1 is an electric circuit diagram showing a first embodiment of an optical sensor circuit according to the present invention. It is a graph which shows the operation characteristic of the photosensor circuit concerning a 1st embodiment. It is a graph which shows the output characteristic of the CMOS inverter of the optical sensor circuit which concerns on 1st Embodiment. It is an electric circuit diagram which shows 2nd Embodiment of the optical sensor circuit based on this invention. It is a graph which shows the operation characteristic of the photosensor circuit concerning a 2nd embodiment. It is an electric circuit diagram which shows the concrete circuit structure of the conventional optical sensor circuit. It is a circuit diagram which shows the conventional photosensor circuit by the expression of a CMOS inverter.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Photosensor circuit 12 PMOS type switching transistor 13 Voltage control part 14 Pixel selection MOS type transistor 20 Photosensor circuit 21 NMOS type switching transistor PD Photodiode IA CMOS inverter

Claims (2)

A photoelectric conversion element that includes a capacitive element connected in parallel between the two electrodes, and converts incident light into a current signal;
The input side is connected to one of the electrodes of the photoelectric conversion element, an input / output characteristic curve indicating a relationship between the input side potential and the output side potential, and a straight line when the input side potential and the output side potential are in the same relationship A CMOS inverter that amplifies the current signal according to the operating point indicated by the intersection, and connection or disconnection between the input terminal and the output terminal of the CMOS inverter, and capacitive coupling at the input side potential of the CMOS inverter at the time of disconnection A PMOS type switching transistor that performs control to move the operating point with respect to the input side potential to a high potential side ,
A pixel selection transistor connected to the output side of the CMOS inverter;
Voltage control means for setting a gate voltage when turning off the PMOS type switching transistor to a value larger than a difference between the potential of the operating point of the CMOS inverter and the threshold voltage of the PMOS type switching transistor. ,
The voltage control means includes
The controls the gate voltage, the sub when it is operating in a threshold state, several pairs of output of the CMOS inverter from linearity response output response characteristic of the PMOS-type switching transistor of the PMOS type switching transistor An optical sensor circuit characterized by switching to an output. A photoelectric conversion element that includes a capacitive element connected in parallel between the two electrodes, and converts incident light into a current signal;
The input side is connected to one of the electrodes of the photoelectric conversion element, an input / output characteristic curve indicating a relationship between the input side potential and the output side potential, and a straight line when the input side potential and the output side potential are in the same relationship A CMOS inverter that amplifies the current signal according to the operating point indicated by the intersection;
Controls the connection or disconnection between the input and output terminals of said CMOS inverter, a control for moving the operating point to the low potential side with respect to the input side potential due to capacitive coupling at the input side potential of the CMOS inverter at blocking NMOS type switching transistor to perform ,
A pixel selection transistor connected to the output side of the CMOS inverter;
Voltage control means for setting a gate voltage when turning off the NMOS switching transistor to a value smaller than a total value of the potential of the operating point of the CMOS inverter and the threshold voltage of the NMOS switching transistor; Prepared,
The voltage control means includes
The controls the gate voltage, the sub when it is operating in a threshold state, several pairs of output of the CMOS inverter from linearity response output response characteristic of the NMOS switching transistor of the NMOS-type switching transistor An optical sensor circuit characterized by switching to an output.

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