JP2007158702A - Optical sensor circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an optical sensor circuit capable of widely utilizing a dynamic range of a linear region of an input output characteristic curve of a CMOS inverter by effectively using the linear region in the optical sensor circuit for using the CMOS inverter to amplify an optical current. <P>SOLUTION: The optical sensor circuit 10 includes: a photodiode PD including a capacitor C connected between the anode 11a and the cathode 11b in parallel with the photodiode PD and converting incident light L1 into a current signal; the CMOS inverter IA whose input side is connected to one terminal electrode of the photodiode PD; a MOS switching transistor (12, 21) used to select connection or interruption between an input terminal and an output terminal of the CMOS inverter and for reversing a changing direction of an input side electric potential of the CMOS inverter by capacitive coupling at the interruption; and a pixel selection transistor 13 connected to an output side of the CMOS inverter. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an optical sensor circuit, and more particularly to an optical sensor circuit suitable for detecting weak light with high sensitivity by amplifying a photocurrent from a photoelectric conversion element that converts an optical signal into an electrical signal by a CMOS inverter.

  Conventionally, as a photosensor circuit that detects weak optical signals by converting them into electrical signals with high sensitivity, a photocurrent output from a photodiode, which is a photoelectric conversion element, is amplified using a CMOS (Complementary Metal Oxide Semiconductor) inverter. An optical sensor circuit configured to do this is known (Patent Document 1). The CMOS inverter is used as the amplifying means because the circuit configuration is simple and it is easy to manufacture an integrated circuit as the image sensor chip. This CMOS inverter is constituted by a kind of push-pull circuit using P-channel and N-channel enhancement type MOS transistors.

  7 and 8 show the circuit configuration of the CMOS inverter. FIG. 7 shows an electric circuit of a main part of one pixel of the image sensor, that is, one photosensor circuit. One photosensor circuit 101 includes a photodiode PD and a capacitor C that is a parasitic capacitance connected in parallel between the anode and the cathode of the photodiode PD. A power supply 102 (Vdd) is connected between the cathode of the photodiode PD and the ground. The enhancement type MOS transistor 103 is connected to the anode side of the photodiode PD. The anode of the photodiode PD is connected to two gates of the enhancement type MOS transistor 103, and a sensor signal is input to the enhancement type MOS transistor 103. A terminal 103 a connected to the two gates is an input terminal of the enhancement type MOS transistor 103. The terminal 103b of the enhancement type MOS transistor 103 is an output terminal for outputting a sensor signal. The drain and source of the MOS type switching transistor 104 are connected to the input terminal 103a and the output terminal 103b of the enhancement type MOS transistor 103 in parallel connection relation. Further, the voltage VDD (= 5 V) is applied to the upper terminal of the enhancement type MOS transistor 103 in FIG. 7, and the lower terminal is connected to the ground.

  When the enhancement type MOS transistor 103 shown in FIG. 7 is expressed as a CMOS inverter IA, the electric circuit is as shown in FIG. In FIG. 8, the same elements as those described in FIG. 7 are denoted by the same reference numerals. In the circuit configuration shown in FIG. 8, the MOS switching transistor 104 connects or disconnects the input terminal and the output terminal in the CMOS inverter IA. When the MOS type switching transistor 104 is on (the gate voltage is Lo level), the input terminal and the output terminal of the CMOS inverter IA are connected (short circuit), and when the MOS type switching transistor 104 is off (the gate voltage is Hi level), the CMOS inverter The input terminal and output terminal of the IA are blocked. The operating point (bias point) of the CMOS inverter IA and the photodiode PD is set by setting the gate voltage of the MOS switching transistor 104 to the Lo level and short-circuiting the input terminal and the output terminal of the CMOS inverter IA. The operating point (bias point) of the CMOS inverter IA is set as an intersection between the input / output characteristic curve of the CMOS inverter IA and a straight line satisfying the relationship of input voltage (Vin) = output voltage (Vout) (see Patent Document 1). (See FIG. 4). The operating point of the CMOS inverter IA is set approximately near the center of the linear linear region at the center of the input / output characteristic curve. Near the center of the linear region is the place with the largest amplification factor (gain). As described above, when the MOS switching transistor 104 is switched from on (connected) to off (cut off), the voltage change at the output terminal of the photodiode PD can be amplified with a high amplification factor and read out to the output terminal. It becomes possible to detect faint light with high sensitivity.

  By preparing a large number of optical sensor circuits 101 having the circuit configuration as described above and arranging them in a matrix, a two-dimensional image sensor that captures an image can be made.

Such an optical sensor circuit 101 has a characteristic that it can be detected with high sensitivity even with a small amount of light, and its application to photographing in a dark place such as at night is under study.
JP-A-11-220657

  In each photosensor circuit 101 of the image sensor disclosed in Patent Document 1, the MOS type switching transistor 104 has a PMOS type structure. For this reason, when the MOS type switching transistor 104 is turned off and the photoelectric charge is accumulated in the capacitor C of the photodiode PD, the position of the operating point of the CMOS inverter IA is high with respect to the input terminal side potential by capacitive coupling based on the off operation. The phenomenon of moving to the side occurs. In other words, the potential at the input terminal of the CMOS inverter IA rises due to capacitive coupling due to the off operation (when shutting off) of the MOS switching transistor 104. Furthermore, the potential on the anode side of the photodiode PD also rises upon light incidence (during accumulation). As a result, during this accumulation, the operating point of the CMOS inverter IA shifts to a higher potential side in terms of the input end side potential. This state is shown in FIG. In the graph of FIG. 9, the horizontal axis represents the input voltage (Vin), and the vertical axis represents the output voltage (Vout). The operating point (bias point) of the CMOS inverter IA is set as an intersection P1 between the input / output characteristic curve C1 of the CMOS inverter IA and the straight line C2 that satisfies the relationship of input voltage (Vin) = output voltage (Vout). In FIG. 9, the arrow AR <b> 1 indicates a potential increase during the above-mentioned “cut-off”, and the arrow AR <b> 2 indicates a potential increase during the “accumulation”.

  As described above, the accumulation of photoelectric charges in the photodiode PD is started in a state where the input terminal side potential after the MOS-type switching transistor 104 is turned off is increased. As a result, there is a problem that the linear region of the input / output characteristic curve C1 of the CMOS inverter IA can hardly be used, and the dynamic range of the linear region is extremely lowered.

  In view of the above problems, an object of the present invention is to effectively use the linear region of the input / output characteristic curve of the CMOS inverter and widely use the dynamic range of the linear region in an optical sensor circuit that amplifies photocurrent with a CMOS inverter. It is to provide an optical sensor circuit.

  The optical sensor circuit according to the present invention is configured as follows in order to achieve the above object.

  A first photosensor circuit (corresponding to claim 1) includes a capacitive element connected in parallel between two electrodes (anode, cathode), and a photoelectric conversion element (converting incident light into a current signal) Photodiode), a CMOS inverter whose input side is connected to one electrode of the photoelectric conversion element, and a connection or disconnection between the input end and the output end of the CMOS inverter, and at the input side potential of the CMOS inverter at the time of disconnection A MOS type switching transistor that reverses the direction of change due to capacitive coupling and a pixel selection transistor connected to the output side of the CMOS inverter are provided.

  In the above optical sensor circuit, a CMOS switching transistor that selects connection or disconnection between a CMOS inverter input terminal and an output terminal that amplifies an output signal of a photoelectric conversion element that converts an incident optical signal into a current signal is turned off when a CMOS switching transistor is cut off. Since the inverter has a characteristic that reverses the direction of change due to capacitive coupling at the input side potential, the linear region of the input / output characteristic curve of the CMOS inverter can be used effectively during amplification, and the dynamic range of the linear region is widely used. It becomes possible to do.

  In the second photosensor circuit (corresponding to claim 2), the electrode of the photoelectric conversion element to which the input side of the CMOS inverter is connected is preferably an anode, and the MOS type switching transistor is an NMOS type switching transistor. It is characterized by being.

  In the third photosensor circuit (corresponding to claim 3), preferably, the electrode of the photoelectric conversion element connected to the input side of the CMOS inverter is a cathode, and the MOS type switching transistor is a PMOS type switching transistor. It is characterized by being.

  According to the present invention, photoelectric charge accumulation in the photoelectric conversion element in the optical sensor circuit is determined by the input side potential of the CMOS inverter after the cutoff operation of the MOS type switching transistor that connects or shuts off the input terminal and the output terminal of the CMOS inverter. Since the direction of change due to capacitive coupling is reversed, the operating point is optimally set during charge accumulation, the linear region of the input / output characteristic curve of the CMOS inverter can be used effectively, and the dynamic range of the linear region is effectively utilized Thus, the response area can be expanded.

  DESCRIPTION OF EMBODIMENTS Preferred embodiments (examples) of the present invention will be described below with reference to the accompanying drawings.

  A first embodiment of an optical sensor circuit according to the present invention will be described with reference to FIGS. FIG. 1 shows an electric circuit showing one photosensor circuit (pixel) according to the first embodiment, and FIG. 2 shows a graph of a change state of an operating point (bias point) of a CMOS inverter included in the photosensor circuit. The electric circuit shown in FIG. 1 is basically the same as the electric circuit described in FIG. 8, and the graph shown in FIG. 2 is the same as the graph described in FIG. 1 and 2, the same elements as those described in FIGS. 8 and 9 are denoted by the same reference numerals.

  In FIG. 1, one photosensor circuit 10 includes a photodiode PD and a capacitor C, which is a parasitic capacitance, connected in parallel between the anode 11a and the cathode 11b of the photodiode PD. The photodiode PD converts the light L1 incident on the light receiving surface into a current signal. This current signal is accumulated in the capacitor C when the output side of the photodiode PD is in an open state.

  A voltage Vdd is applied to the cathode 11b of the photodiode PD. The input terminal of the CMOS inverter IA is connected to the anode 11a of the photodiode PD. The CMOS inverter IA is a kind of push-pull circuit using P-channel and N-channel enhancement type MOS transistors. The drain and source of the MOS type switching transistor 12 are connected to the input terminal and the output terminal of the CMOS inverter IA in a parallel connection relationship.

  The MOS type switching transistor 12 connects or disconnects the input terminal and the output terminal in the CMOS inverter IA. When the MOS type switching transistor 12 is on (the gate voltage is high level Hi), the input terminal and the output terminal of the CMOS inverter IA are connected (short-circuited), and when the MOS type switching transistor 12 is off (the gate voltage is low level Lo) The input terminal and output terminal of the CMOS inverter IA are cut off. By switching the gate voltage of the MOS switching transistor 12 from a low level (Lo) to a high level (Hi) and short-circuiting the input terminal and the output terminal of the CMOS inverter IA, the operating points (bias) of the CMOS inverter IA and the photodiode PD are biased. Point). As shown in FIG. 2, the operating point (bias point) of the CMOS inverter IA is an intersection P1 between the input / output characteristic curve C1 of the CMOS inverter IA and a straight line C2 that satisfies the relationship of input voltage (Vin) = output voltage (Vout). Set as

  The operating point of the CMOS inverter IA is set near the center of the linear linear region at the center of the input / output characteristic curve C1. Near the center of the linear region is the place with the largest amplification factor (gain). As described above, when the MOS type switching transistor 12 is switched from off (blocking) to on (connection), the voltage change at the output terminal of the photodiode PD can be amplified with a high amplification factor and read out to the output terminal. It becomes possible to detect faint light with high sensitivity.

  The MOS type switching transistor 12 is an NMOS type switching transistor.

  Further, a MOS transistor 13 for pixel selection is connected to the output terminal of the CMOS inverter IA. An output terminal is drawn from the MOS transistor 13.

  According to the configuration of the optical sensor circuit 10 described above, the following operation occurs. An NMOS type switching transistor 12 is used as a switching means for connecting or blocking the input terminal and the output terminal in the CMOS inverter IA. Therefore, when the NMOS switching transistor 12 is turned off and the MOS inverter IA is shut off in order to accumulate photoelectric charge in the capacitor C of the photodiode PD, the direction of change due to capacitive coupling at the input side potential of the CMOS inverter IA is reversed. Thus, the position of the operating point of the CMOS inverter IA can be moved to the low potential side with respect to the input terminal side potential. This state is indicated by an arrow AR11 in FIG. Further, when the photodiode PD subsequently undergoes a photoelectric conversion action and the potential on the anode 11a side rises upon incidence of the light L1 (during accumulation), the operating point of the CMOS inverter IA is on the contrary high potential in terms of the input end side potential. To the side. This state is indicated by an arrow AR12 (during accumulation) in FIG.

  As described above, according to the photosensor circuit 10 of the present embodiment, accumulation of photocharge in the photodiode PD is started in a state where the input terminal side potential after the NMOS switching transistor 12 is turned off is lowered. It will be. As a result, the linear region of the input / output characteristic curve C1 of the CMOS inverter IA can be used effectively, and the response region can be expanded by effectively utilizing the dynamic range of the linear region.

  Next, a second embodiment of the optical sensor circuit according to the present invention will be described with reference to FIGS. 3 is a view similar to FIG. 1, and FIG. 4 is a view similar to FIG. 3 and 4, the same elements as those described in FIGS. 1 and 2 are denoted by the same reference numerals.

  One photosensor circuit 20 includes a photodiode PD and a capacitor C connected in parallel between the anode 11a and the cathode 11b of the photodiode PD. The anode 11a of the photodiode PD is connected to the ground. On the other hand, the input terminal of the CMOS inverter IA is connected to the cathode 11b of the photodiode PD. The drain and source of the PMOS switching transistor 21 are connected to the input terminal and the output terminal of the CMOS inverter IA in a parallel connection relationship.

  The PMOS switching transistor 21 connects or disconnects the input terminal and the output terminal in the CMOS inverter IA. When the PMOS type switching transistor 21 is on (the gate voltage is Lo level), the input terminal and the output terminal of the CMOS inverter IA are connected (short-circuited), and when the PMOS type switching transistor 21 is off (the gate voltage is Hi level), the CMOS inverter The input terminal and output terminal of the IA are blocked. The function of the PMOS switching transistor 21 is the same as that of the NMOS switching transistor 12 of the first embodiment. Other circuit configurations are the same as those of the optical sensor circuit 10 of the first embodiment.

  According to the configuration of the optical sensor circuit 20 described above, the following operation occurs. A PMOS switching transistor 21 is used as a switching means for connecting or blocking the input terminal and the output terminal in the CMOS inverter IA. Therefore, in order to accumulate photocharge in the capacitor C of the photodiode PD, when the PMOS switching transistor 21 is turned off and the MOS inverter IA is shut off, the direction of change due to capacitive coupling at the input side potential of the CMOS inverter IA is reversed. The position of the operating point of the CMOS inverter IA can be moved to the high potential side with respect to the input terminal side potential. This state is indicated by an arrow AR21 (when shut off) in FIG. Further, when the photodiode PD subsequently undergoes a photoelectric conversion action and the potential on the cathode 11b side drops due to the incidence of the light L1 (accumulation), the operating point of the CMOS inverter IA is conversely low in terms of the input end side potential. To the side. This state is indicated by an arrow AR22 (during accumulation) in FIG.

  As described above, according to the photosensor circuit 20 of the present embodiment, the photoelectric charge accumulation (potential drop) in the photodiode PD is caused by an increase in the input terminal side potential after the PMOS switching transistor 21 is turned off. Will be started in the state. As a result, the linear region of the input / output characteristic curve C1 of the CMOS inverter IA can be used effectively, and the response region can be expanded by effectively utilizing the dynamic range of the linear region.

  FIG. 5 shows a third embodiment of the photosensor circuit of the present invention, and this photosensor circuit 30 is a modification of the first embodiment. A characteristic configuration of the optical sensor circuit 30 is that a P / N-MOS type switching transistor 31 is used instead of using the NMOS type switching transistor 12 to connect or block the input terminal and the output terminal in the CMOS inverter IA. . Other circuit configurations are the same as those of the first embodiment. According to the configuration of this embodiment, in addition to the above-described effects, changes during switching can be eliminated.

  FIG. 6 shows a fourth embodiment of the photosensor circuit of the present invention, and this photosensor circuit 40 is a modification of the second embodiment. The characteristic configuration of the optical sensor circuit 40 is that a P / N-MOS type switching transistor 41 is used instead of using the PMOS type switching transistor 21 to connect or block the input terminal and the output terminal in the CMOS inverter IA. . Other circuit configurations are the same as those of the second embodiment. According to the configuration of this embodiment, in addition to the above-described effects, changes during switching can be eliminated.

  An image sensor that captures a two-dimensional image can be made by preparing a large number of optical sensor circuits of the respective embodiments having the circuit configuration as described above and arranging them in a matrix.

  Further, the detection sensitivity of the photosensor circuit can be arbitrarily adjusted by changing the accumulation time of “during accumulation” in the photosensor circuit of each embodiment described above.

  The configurations, shapes, sizes, and arrangement relationships described in the above embodiments are merely schematically shown to the extent that the present invention can be understood and implemented. Therefore, the present invention is not limited to the described embodiments, and can be variously modified without departing from the scope of the technical idea shown in the claims.

  INDUSTRIAL APPLICABILITY The present invention is used as an optical sensor circuit of an image sensor that can detect weak light with high sensitivity and can widely use a dynamic range in a linear region.

1 is an electric circuit diagram showing a first embodiment of an optical sensor circuit according to the present invention. It is a graph which shows the operation characteristic of the photosensor circuit concerning a 1st embodiment. It is an electric circuit diagram which shows 2nd Embodiment of the optical sensor circuit based on this invention. It is a graph which shows the operation characteristic of the photosensor circuit concerning a 2nd embodiment. It is an electric circuit diagram which shows 3rd Embodiment of the optical sensor circuit based on this invention. It is an electric circuit diagram which shows 4th Embodiment of the optical sensor circuit based on this invention. It is an electric circuit diagram which shows the concrete circuit structure of the conventional optical sensor circuit. It is a circuit diagram which shows the conventional photosensor circuit by the expression of a CMOS inverter. It is a graph which shows the operating characteristic of the conventional optical sensor circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Photosensor circuit 12 NMOS type switching transistor 13 Pixel selection MOS type transistor 20 Photosensor circuit 21 PMOS type switching transistor 30 Photosensor circuit 40 Photosensor circuit PD Photodiode IA CMOS inverter

Claims (3)

A photoelectric conversion element that includes a capacitive element connected in parallel between the two electrodes, and converts incident light into a current signal;
A CMOS inverter whose input side is connected to one of the electrodes of the photoelectric conversion element;
A MOS type switching transistor that selects connection or disconnection between the input end and output end of the CMOS inverter and reverses the direction of change due to capacitive coupling at the input side potential of the CMOS inverter at the time of disconnection;
A pixel selection transistor connected to the output side of the CMOS inverter;
An optical sensor circuit comprising:   2. The optical sensor circuit according to claim 1, wherein the electrode of the photoelectric conversion element to which the input side of the CMOS inverter is connected is an anode, and the MOS type switching transistor is an NMOS type switching transistor.   2. The optical sensor circuit according to claim 1, wherein the electrode of the photoelectric conversion element connected to the input side of the CMOS inverter is a cathode, and the MOS type switching transistor is a PMOS type switching transistor.

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