201041382 五、 本案若魏學式時，請齡最_娜觸徵的化學式 六、 發明說明： 【發明所屬之技術領域】 本發明係有關互補金屬氧化半導體（CM〇s)影像感 測器，特別是一種具較小面積之CMOS Θ3a ? 1像感測器的像素 漬出電路（pixelreadGuteircuit)’以及—種具迴授（或 切換）電容之像素讀出電路。 / 【先前技術】 CMOS影像感測器係一種擷取影像的電子裝置，例如 用於照相機中，將光強度轉換為電荷，再將其轉換為電壓 並颉取出來。第一 A圖顯示被動式像素感測器（passive Pixel sensor，PPS)，其為傳統CM〇s影像感測器之一 種。為了便於說明，於圖式中僅顯示像素陣列當中的二個 像素。每一像素含有一個光電二極體（photodiode) D及 一存取電晶體（或開關）Macc。字元線（例如WLi)連接 至同一列的像素’而位元線（例如BL )則連接至同一行的 像素。位於每一位元線BL的末端有一放大器1〇。 201041382 ❹ ❹ 第一 B圖顯示主動式像素感測器（actiVe pixel sensor，APS)的像素電路。每一個像素包含一個光電二 極體D及三個電晶體一Mm、Msf、Msel，因此這類感測器 一般稱為CMOS影像感測器之3T像素電路。當電晶體 Mrst被重置信號rst開啟（turn on)時，會將光電二極 體D重置為一重置參考電壓（例如電源VDD)。電晶體 sf係作為源極追隨器（)，其可用以緩 衝，大光電二極體D的累積（integrated)光信號。當 曰體Msel被子元線信號WL開啟時，則允許像素传 讀取。由於3T像素電路中的各個源極追隨器I及電晶體 機分散’因此可以減輕被動式像素感測器 之條次缺卩㈢。然而，3T像素電路之光電二極體 高漏電流。再者，較純缺陷減輕了， 卩^ 會產生Μ雜訊，其中，雜散電容值Cp非常:“ KT/CP雜訊的值會很大。 P非常小’因此 每1二，Μ動式像素感測11的另一種像素電路 每一像素包含-個光電二極 崎素電路。201041382 V. In the case of Wei Xue, the age of the most _ Na touches the chemical formula, the invention: [Technical field of the invention] The present invention relates to a complementary metal oxide semiconductor (CM〇s) image sensor, in particular It is a pixel readout circuit (pixelreadGuteircuit) with a small area of CMOS Θ3a ? 1 image sensor and a pixel readout circuit with feedback (or switching) capacitance. / [Prior Art] A CMOS image sensor is an electronic device that captures images, for example, used in a camera to convert light intensity into electric charge, convert it into a voltage, and extract it. The first A picture shows a passive Pixel sensor (PPS), which is one of the traditional CM〇s image sensors. For ease of illustration, only two of the pixel arrays are shown in the figure. Each pixel contains a photodiode D and an access transistor (or switch) Macc. A word line (e.g., WLi) is connected to a pixel of the same column, and a bit line (e.g., BL) is connected to a pixel of the same line. There is an amplifier 1 at the end of each bit line BL. 201041382 ❹ ❹ The first B diagram shows the pixel circuit of the active pixel sensor (APS). Each pixel contains a photodiode D and three transistors - Mm, Msf, Msel, so such sensors are generally referred to as 3T pixel circuits of CMOS image sensors. When the transistor Mrst is turned on by the reset signal rst, the photodiode D is reset to a reset reference voltage (e.g., power supply VDD). The transistor sf acts as a source follower () which can be used to buffer the integrated optical signal of the large photodiode D. When the body Msel is turned on by the sub-line signal WL, the pixel is allowed to read. Since each of the source followers I and the crystallizer in the 3T pixel circuit are dispersed, the stripping of the passive pixel sensor can be alleviated (3). However, the photodiode of the 3T pixel circuit has a high leakage current. Furthermore, the purer defects are alleviated, and 卩^ will generate noise. Among them, the stray capacitance value Cp is very: "The value of KT/CP noise will be very large. P is very small, so every 1 2, turbulent Another pixel circuit of pixel sensing 11 includes one photodiode circuit.
Mrst、Msi、Msel)，因此這類感測器一(Mtx、 感測器之4T像素電路。47像 叙稱為CMOS影像 3T像素電路，然而當額 β <配置及功能類似於 敗時，可用以傳送光電二極:二，被傳送信號開 絲號。此竹後 201041382 素電路可用於執行關聯雙重取樣（correlated double sampling, CDS)以避免像素之間因製程變動差異所產生 的差異特性。此外，當浮動擴散（floating diffusion, FD) 區域的容量夠大時，光電二極體可充分地將累積電荷傳送 出去。藉此，關聯雙重取樣（CD S )可將KT/ Cp雜訊完 全去除，使得時間相關（temporal)雜訊位準變得很低， 且光電二極體所造成的暗（dark)電流也很少。 第一 C圖之像素電路會佔用相當的晶片面積，因此’並 不適於現代的高密度CMOS影像感測器。鑑於此，因此亟 需提出一種CMOS影像感測器之像素讀出電路’用以有效 降低CMOS影像感測器之像素陣列的面積。 【發明内容】 鑑於上述，本發明的目的之一係實質地降低CM0S影像 感測器之像素陣列的面積。 本發明的另一目的在於提出一種CMOS影像感測器之 像素電路，用以減低雜散電容’且不會犧牲其效能及共用 於CMOS影像感測器的像素數目。 201041382 根據本發明實施例之一，使用至少二傳送電晶體以分別 傳送相對應光檢器之累積光信號至第一卽點。浮動擴散區 域連接至第一節點。使用一重置電晶體以重置第一節點使 其為第二節點之預設重置電壓；且使用一源極追隨器以緩 衝累積光信號。其中，重置電晶體及源極追隨器共用於該 至少二光檢器。根據本發明另一實施例，一電容連接於第 一節點與第二節點之間，用以減小有效電容的影響。 Ο 【實施方式】 第二A圖顯示本發明實施例之互補金屬氧化半導體 (CMOS)影像感測器的四電晶體（4T)像素電路，其被 四個像素所共用（shared)(4S)。本實施例可降低CMOS 影像感測器的像素陣列之整體面積，或者可挪出較多的空 Q 間給光電二極體。於本實施例（及本說明書中的其他實施 例）中，像素電路係被四個像素所共用’但不限定於四個； 再者，本發明之像素電路也不限定於含有四個電晶體 (4T)，例如也可以為5T或更多的電晶體。於例示的4T4S 像素電路中，四像素所對應的四個光檢器 (photodetector )(例如釘扎光電二極體（pinned photodiode) 分別連接至傳送電晶體Mtxi-Mtx4。 於本實施例中，傳送電晶體Mtxl-Mtx4係為η型金屬氧化 201041382 半導體（imos)電晶體4電二極體〜叫被反向偏廢， 亦即，將其陽極接地而陰極職接至料電晶體1爲4 的源/汲極之-。傳送電晶體Mtxi_Mtx4的另一源^極係 連接在-S，再連接至浮動擴散（fl〇atingdiffusi〇n)區 域FD (或第$點）及源極追隨器（例如為腹㈤ 電晶體）的閘極。 雖然4T4S像素電路中光電二極體DA所累積電荷q 可大幅增加，但是，位元線BL所讀出之電壓（Q/Cp xAsf， 其中Cp為節點p的雜散電容，Asf為源極追隨器Μα的增 益，一般值為0.8-0.9)則會受到共用像素所產生之雜散 電容所影響。為了讓像素電壓最大化，〇?的有效電容值必 須保持於最小，但又必須大到足以容納光電二極體Di_D4 所傳送來的電荷。此種設計上的矛盾使得於最佳化電容Cp 的同時卻也限制了共用於一個電路的像素數目。為了解決 此問題，因而提出以下的實施例。 第二B圖顯示本發明另一實施例之互補金屬氧化半導 體（CMOS)影像感測器的4T4S像素電路，其包含四個 電晶體（4T)，且被四個像素所共用（shared) ( 4S)。於 本實施例中，傳送電晶體Mtxl_Mtx4連接在一起，再連接 至浮動擴散區域FD (或第一節點）及源極追隨器Msf (例 201041382 如為NMOS電晶體）的閘極。電容Cf連接於浮動擴散區 域FD與節點S (第二節點）之間。電容Cp為有效電容， 其至少包含浮動擴散區域FD的擴散電容、源極追隨器I 的閘極電容及各像素的雜散電容。於節點3與地之間，源 極追隨器Msf串聯於列選擇電晶體Msei (例如nm〇s電晶 體）。熟悉本技術領域者可以知道串聯之源極追隨器μ^、 列選擇電晶體Msel_序調換後並*㈣響其功能。重置 Ο 電晶體Mrst位於節點S與浮動擴散區域FD之間。一電源 電路或電流源20連接於電源Vdd與節點s之間。於本實 施例中，電流源20係由二串聯p型金屬氧化半導體 (PMOS )電晶體Pu所組成。PM〇s電晶體&的問極 給予適當的偏壓（未顯示於圖式中）。 ❾ 第二B圖之4T 4S像素電路的操作共分為下列三個階 段。首先，於重置階段，重置電晶體Mm被重置信號RST 開啟，傳送電晶體Mtxi-MtX4也分別被傳送信號τχρ4開 啟。藉此，光電二極體Dl-D4被重置為”釘扎（pinning) 電壓”，其值小於節點S之預設參考電壓，其又小於電源 Vdd，因此光電二極體D”D4被完全空乏（depleted)。 於本實施例中，電流源20將電源vDD下拉至一預設值， 用以提供所需的重置參考電壓給光電二極體Di_D4。接下 來’於累積（integration 或 accumuiati〇ri)階段，重置 201041382 電晶體Mrst及傳送電日日體Mtxi-Mtx4關閉（turned off)， 接著照射光線於光電二極體D1-D4。光電二極體Di-D4的 跨壓將隨著照射光線強度的增加而降低（放電）。於第三 階段’重置電晶體Mrst重被開啟一段時間，於這段時間内 浮動擴散區域FD被重置為上述的預設電壓，接著開啟列 選擇電晶體Msei以讀取重置（或暗（dark))電壓。接下 來，傳送電晶體Mtxi-MtX4其中一個被開啟（並保持列選 擇電晶體Msel的開啟）’用以讀取FD的光電二極體D1-D4 之累積光信號。重置電壓與累積光信號之差值（該差值係 由一外部電路所產生，未顯示於本圖式中，但將於以下討 論）將被用於執行關聯雙重取樣（correlated double sampling，CDS)。熟悉本技術領域者可以知道，如果不 需要執行關聯雙重取樣（CDS)，則上述第三步驟中浮動 擴散區域FD的重置就可以省略。 光電二極體DrD#可以依據特別目的而予以作特殊的 配置。例如，在一個實施例中’光電二極體D i、d2、D3、 D4分別用以偵測紅光（R)、綠光（G)、紅光（R)、綠 光（G )。於操作時，傳送信號TX1、TX3同時開啟傳送 電晶體Mtxi、Mw ’而傳送信號TX2、TX4則同時開啟傳 送電晶體Mw、Mw。此操作一般稱為像素階層的，，電荷重 合（binning) ”。藉此，可以有效增加（倍增）紅光及綠 201041382 光的偵測面積，因而得以增強低亮度環境下的工作效能。 若於像素内使用迴授電容，則可讓更多像素來進行電荷重 合’更為增強低亮度環境下的工作效能。 第二A圖顯示本發明又一實施例之互補金屬氧化半導 體（CMOS)影像感測器的四電晶體（4T)像素電路’其 被四個像素所共用（shared) (4S)。於本實施例中，光電Mrst, Msi, Msel), therefore, such a sensor one (Mtx, 4T pixel circuit of the sensor. 47 is called a CMOS image 3T pixel circuit, but when the amount of β < configuration and function is similar to defeat, It can be used to transmit photodiode: Second, the transmitted signal is opened. This bamboo 201041382 circuit can be used to perform correlated double sampling (CDS) to avoid the difference characteristics between pixels due to process variation. In addition, when the capacity of the floating diffusion (FD) region is large enough, the photodiode can sufficiently transfer the accumulated charge. Thereby, the correlated double sampling (CD S ) can completely remove the KT/Cp noise. Therefore, the temporal correlation noise level becomes very low, and the dark current caused by the photodiode is also small. The pixel circuit of the first C diagram occupies a considerable wafer area, so 'and It is not suitable for modern high-density CMOS image sensors. Therefore, it is necessary to provide a pixel readout circuit of a CMOS image sensor to effectively reduce the area of the pixel array of the CMOS image sensor. SUMMARY OF THE INVENTION In view of the above, one of the objects of the present invention is to substantially reduce the area of a pixel array of a CMOS image sensor. Another object of the present invention is to provide a pixel circuit of a CMOS image sensor for reducing spurs. Capacitor' does not sacrifice its performance and the number of pixels commonly used for CMOS image sensors. 201041382 According to one embodiment of the present invention, at least two transfer transistors are used to respectively transmit the accumulated optical signals of the corresponding photodetectors to the first The floating diffusion region is connected to the first node. A reset transistor is used to reset the first node to be the preset reset voltage of the second node; and a source follower is used to buffer the accumulated optical signal. Wherein, the reset transistor and the source follower are commonly used for the at least two photodetectors. According to another embodiment of the invention, a capacitor is connected between the first node and the second node to reduce the influence of the effective capacitance.实施 [Embodiment] FIG. 2A shows a four-transistor (4T) pixel circuit of a complementary metal oxide semiconductor (CMOS) image sensor according to an embodiment of the present invention, which is imaged by four Shared (4S). This embodiment can reduce the overall area of the pixel array of the CMOS image sensor, or can remove more space Q to the photodiode. In this embodiment (and this specification) In other embodiments, the pixel circuit is shared by four pixels, but is not limited to four. Further, the pixel circuit of the present invention is not limited to including four transistors (4T), and for example, 5T or more transistors. In the illustrated 4T4S pixel circuit, four photodetectors corresponding to four pixels (for example, pinned photodiodes) are respectively connected to the transfer transistor Mtxi-Mtx4 . In this embodiment, the transfer transistor Mtxl-Mtx4 is an n-type metal oxide 201041382 semiconductor (imos) transistor 4 electric diode ~ is called reverse biased, that is, its anode is grounded and the cathode is connected to the material. Transistor 1 is the source/drain of -4. The other source of the transfer transistor Mtxi_Mtx4 is connected at -S, and then connected to the floating diffusion (fl〇atingdiffusi〇n) region FD (or the $point) and the source follower (for example, the abdomen (five) transistor) Gate. Although the charge q accumulated by the photodiode DA in the 4T4S pixel circuit can be greatly increased, the voltage read by the bit line BL (Q/Cp xAsf, where Cp is the stray capacitance of the node p, and Asf is the source follow-up The gain of the device Μα, which is generally 0.8-0.9), is affected by the stray capacitance generated by the shared pixel. In order to maximize the pixel voltage, the effective capacitance value of 〇 must be kept to a minimum, but must be large enough to accommodate the charge transferred by the photodiode Di_D4. This design contradiction makes it possible to optimize the capacitance Cp while limiting the number of pixels used in one circuit. In order to solve this problem, the following embodiments have been proposed. 2B is a 4T4S pixel circuit of a complementary metal oxide semiconductor (CMOS) image sensor according to another embodiment of the present invention, which includes four transistors (4T) and is shared by four pixels (4S). ). In this embodiment, the transfer transistors Mtxl_Mtx4 are connected together and connected to the gates of the floating diffusion region FD (or the first node) and the source follower Msf (for example, 201041382 as an NMOS transistor). The capacitor Cf is connected between the floating diffusion region FD and the node S (second node). The capacitor Cp is an effective capacitor including at least a diffusion capacitance of the floating diffusion region FD, a gate capacitance of the source follower I, and a stray capacitance of each pixel. Between node 3 and ground, source follower Msf is connected in series with column select transistor Msei (e.g., nm 〇s electro-crystal). Those skilled in the art can know that the source follower μ^ of the series, the column selection transistor Msel_, and the function of the (4) ring. Reset Ο The transistor Mrst is located between the node S and the floating diffusion region FD. A power supply circuit or current source 20 is coupled between the power supply Vdd and the node s. In the present embodiment, current source 20 is comprised of two series p-type metal oxide semiconductor (PMOS) transistors Pu. The polarity of the PM〇s transistor & is given an appropriate bias (not shown in the figure).操作 The operation of the 4T 4S pixel circuit of Figure 2B is divided into the following three stages. First, in the reset phase, the reset transistor Mm is turned on by the reset signal RST, and the transfer transistors Mtxi-MtX4 are also turned on by the transfer signal τ χ ρ4, respectively. Thereby, the photodiode D1-D4 is reset to a "pinning voltage" whose value is smaller than the preset reference voltage of the node S, which is smaller than the power supply Vdd, so the photodiode D"D4 is completely In the present embodiment, the current source 20 pulls the power supply vDD down to a preset value to provide the required reset reference voltage to the photodiode Di_D4. Next 'integration (actegration or accumuiati) 〇ri) stage, reset 201041382 transistor Mrst and transmit electricity day body Mtxi-Mtx4 turned off, and then illuminate the light in the photodiode D1-D4. The voltage across the photodiode Di-D4 will follow In the third stage, the reset transistor Mrst is turned on for a period of time, during which the floating diffusion region FD is reset to the above-mentioned preset voltage, and then the column is turned on. The transistor Msei is selected to read the reset (or dark) voltage. Next, one of the transfer transistors Mtxi-MtX4 is turned on (and keeps the column selection transistor Msel turned on)' Cumulative optical signal of diode D1-D4 The difference between the reset voltage and the accumulated optical signal (which is generated by an external circuit, not shown in this figure but will be discussed below) will be used to perform correlated double sampling (CDS) It will be appreciated by those skilled in the art that the reset of the floating diffusion region FD in the third step described above can be omitted if it is not necessary to perform correlated double sampling (CDS). The photodiode DrD# can be used for special purposes. A special configuration. For example, in one embodiment, the photodiodes D i, d2, D3, and D4 are used to detect red (R), green (G), red (R), and green light, respectively. (G). In operation, the transfer signals TX1, TX3 simultaneously turn on the transfer transistors Mtxi, Mw' and the transfer signals TX2, TX4 simultaneously turn on the transfer transistors Mw, Mw. This operation is generally referred to as pixel level, and the charge is coincident. (binning)". In this way, the detection area of the red and green 201041382 light can be effectively increased (multiplied), thereby enhancing the work efficiency in a low-brightness environment. If a feedback capacitor is used in the pixel, more pixels can be used for charge recombination to enhance the performance in a low-brightness environment. Figure 2A shows a four-transistor (4T) pixel circuit of a complementary metal oxide semiconductor (CMOS) image sensor of another embodiment of the present invention, which is shared (4S) by four pixels. In this embodiment, photoelectric
〇 二極體Di_D4、傳送電晶體Mtxl-Mtx4、電容Cp和第二B 圖相同’因此省略其相關說明。於電源VDD與地之間，源 極追隨器Msf串聯於列選擇電晶體Msel(例如NMOS電晶 體）。The 〇 diode Di_D4, the transfer transistor Mtxl-Mtx4, the capacitance Cp, and the second B picture are the same', and thus the related description is omitted. Between the power supply VDD and ground, the source follower Msf is connected in series with the column selection transistor Msel (e.g., NMOS transistor).
涵蓋源極追隨器Msf之放大器3〇於浮動擴散區域FD (或第節點）接收輸入電壓。放大器30的輸出節點V。 迴授連接至迴授電容Cf的第二端。重置電晶體M⑼位於 與放大器30的輸出之間。於本實施例中，放大器3〇 ^標準^動放大器°放大器30也可以採用其他組成形式， /、hi、反相信號及具足夠之開回路增益，以符合所需 之閉回路增益精確度。 _ A圖之像素電路的操作共分為下列m。第三b 圖顯不相關時相，第三C關减大器30的簡化等效 201041382 方塊圖、迴授電容Cf及關聯雙重取樣（CDS)電路32。 首先’於重置階段，重置電晶體Mrst於時間U被重置信號 RST開啟’傳送電晶體Mtxl-MtX4也分別被傳送信號TX 開啟。藉此，光電二極體Di-De被重置為”釘扎（pinning) 電壓”，其值小於參考電壓VRST。第三D圖顯示第三A圖 於重置階段的簡化等效方塊圖。此階段的總電荷Qi等於電 容Cp的電荷（亦即，（VRST-0) .CP)。總電荷Qi可表 不為.The amplifier 3, which covers the source follower Msf, receives the input voltage in the floating diffusion region FD (or the node). The output node V of amplifier 30. The feedback is connected to the second end of the feedback capacitor Cf. The reset transistor M(9) is located between the output of the amplifier 30. In this embodiment, the amplifier 3 标准 ^ standard amplifier amplifier 30 can also take other forms, /, hi, inverted signals and have sufficient open loop gain to meet the required closed loop gain accuracy. _ A pixel circuit operation is divided into the following m. The third b shows the uncorrelated phase, the simplified equivalent of the third C off-subtractor 30 201041382 block diagram, the feedback capacitor Cf, and the associated double sampling (CDS) circuit 32. First, in the reset phase, the reset transistor Mrst is turned on by the reset signal RST at time U. The transfer transistors Mtxl-MtX4 are also turned on by the transfer signal TX, respectively. Thereby, the photodiode Di-De is reset to a "pinning voltage" whose value is smaller than the reference voltage VRST. The third D-picture shows a simplified equivalent block diagram of the third A picture in the reset phase. The total charge Qi at this stage is equal to the charge of the capacitor Cp (i.e., (VRST-0) .CP). The total charge Qi can be expressed as.
Qi = (Vrst-〇) · Cp 接下來，於累積（integration 或 accumulation)階 段，重置電晶體Mrst及傳送電晶體Mtxi-MtX4關閉（turned off)，接著照射光線於光電二極體D1-D4。光電二極體 Di-D4的跨壓將隨著照射光線強度的增加而降低（放電）。 第三E圖顯示第三A圖之放大器30、迴授電容Cf於累積 階段的簡化等效方塊圖。此階段的總電荷Q2等於電容Cp 的電荷（亦即，（VRST-0) .Cp)加上電容Cf的電荷（亦 即，（VRST-V。）· Cf)。總電荷Q2可表示為： Q2=Vrst · Cp + (VrsT-V〇) · Cf 於第三階段，重置電晶體Mrst重被開啟一段時間（時間 t3與t4之間），於這段時間内浮動擴散區域FD被重置為 12 201041382 上述的預設電壓，接著開啟列選擇電晶體Msel以取樣 (sample)及保持（hold)該重置（或暗（dark))電 壓，該取樣/保持係藉由控制信號SHR閉合（cl〇se)開關 sWi來完成的。接下來，傳送電晶體Mtxl_Mtx4其中一個 於時間ts被開啟（並保持列選擇電晶體Msel的開啟），用 以取樣（sample)及保持（hold)浮動擴散區域FE)的光 電二極體Di-D4之累積光信號（累積電荷為Qimg)，該取 © 樣/保持係藉由控制信號SHS閉合（close)開關SW2來 完成的。輸出電壓V。可以下式表示： ,=-^img X £e1£j__ , Qimg CP+Cf Cf ~ cf 藉此’轉換増益（conversion gain)可以由本實施例 的迴授電容Cf來控制，此可避免受到浮動擴散區域fd電 ❹ 容及共用像素之雜散電容的影響。迴授電容Cf可以根據需 求加以設計調整’用以增加輸出電壓v〇範圍以及像素敏感 度。 根據上述實施例，輸出電壓V。主要係由迴授電容Cf來 控制，幾乎不會受到雜散電容的影響。因而，導體繞線幾 乎不會影響到輸出電壓。在一實施例中，此發明優點可用 以增加共用像素之數目而不會影響輸出電壓。在另一實施 13 201041382 例中，可利用此發明優點以増加列（丽）的數目而不會 影響輸出電壓’使得於1框（frame )當中進行不同時 間之曝光，用以增加其動態範圍（dynamicrange)。 以上所述僅為本發明之較佳實施例而已，並非用以限定 本發明之申请專利範圍；凡其它未脫離發明所揭示之精神 下所完成之等效改變或修飾，均應包含在下述之申請專利 範圍内。 【圖式簡單說明】 第一 A圖顯示傳統被動式像素感測器。 第一 B圖顯示傳統主動式像素感測器的3T像素電路。 第一 C圖顯示傳統主動式像素感測器的4Τ像素電路。 第二Α圖顯示本發明實施例之互補金屬氧化半導體 (CMOS)影像感測器的四電晶體（4T)像素電路，其被 四個像素所共用（shared) (4S)。 第二B圖顯示本發明另一實施例之CMOS影像感測器的 四電晶體（4T)像素電路，其被四個像素所共用（4S)。 第三A圖顯示本發明又一實施例之CMOS影像感測器的四 電晶體（4T)像素電路，其被四個像素所共用（4S)。 第三B圖顯示第三A圖的相關時序圖。 201041382 第三C圖顯示第三A圖的放大器的簡化等效方塊圖、迴授 電容及關聯雙重取樣（CDS)電路。 第三D圖顯示第三A圖於'重置階段的簡化等效方塊圖。 第三E圖顯示第三A圖之放大器、迴授電容於累積階段的 簡化等效方塊圖。 【主要元件符號說明】 _ 10 放大器 〇 2 0 電流源 30 放大器 32 關聯雙重取樣（CDS)電路 D 光電二極體 Μ acc 存取電晶體 BL 位元線 ❹ WL 字元線 .Vdd 電源 RST重置信號 Mrst重置電晶體 Msf 源極追隨器電晶體 Msel列選擇電晶體 TX 傳送信號 Mtx 傳送電晶體 15 201041382 FD 浮動擴散區域 S 節點 Cp 有效點容 Cf 迴授電容 Vi 輸入節點（電壓） V。 輸出節點（電壓） SWi、SW2 開關Qi = (Vrst-〇) · Cp Next, in the accumulation (actegration) phase, the reset transistor Mrst and the transfer transistor Mtxi-MtX4 are turned off, and then the light is applied to the photodiode D1-D4. . The voltage across the photodiode Di-D4 will decrease (discharge) as the intensity of the illumination increases. The third E diagram shows a simplified equivalent block diagram of the amplifier 30 of the third A diagram and the feedback capacitor Cf in the accumulation phase. The total charge Q2 at this stage is equal to the charge of the capacitor Cp (i.e., (VRST-0).Cp) plus the charge of the capacitor Cf (i.e., (VRST-V.)·Cf). The total charge Q2 can be expressed as: Q2=Vrst · Cp + (VrsT-V〇) · Cf In the third stage, the reset transistor Mrst is turned on for a period of time (between times t3 and t4) during this time. The floating diffusion region FD is reset to the preset voltage described above at 12 201041382, and then the column selection transistor Msel is turned on to sample and hold the reset (or dark) voltage, the sample/hold system This is done by the control signal SHR closing (cl〇se) the switch sWi. Next, one of the transfer transistors Mtxl_Mtx4 is turned on at time ts (and the turn-on of the column selection transistor Msel is held), and the photodiode Di-D4 for sampling and holding the floating diffusion region FE) The accumulated optical signal (accumulated charge is Qimg) is obtained by closing the switch SW2 by the control signal SHS. Output voltage V. It can be expressed as follows: , =-^img X £e1£j__ , Qimg CP+Cf Cf ~ cf By this, the conversion gain can be controlled by the feedback capacitor Cf of this embodiment, which can avoid floating diffusion. The influence of the area fd capacitance and the stray capacitance of the shared pixel. The feedback capacitor Cf can be designed and adjusted according to requirements to increase the output voltage v〇 range and pixel sensitivity. According to the above embodiment, the voltage V is output. Mainly controlled by the feedback capacitor Cf, it is hardly affected by stray capacitance. Thus, the conductor winding will hardly affect the output voltage. In one embodiment, the advantages of this invention can be used to increase the number of shared pixels without affecting the output voltage. In another embodiment 13, 201041382, the advantage of this invention can be utilized to increase the dynamic range of the array by not affecting the output voltage' for different time exposures in a frame ( Dynamicrange). The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application. [Simple description of the diagram] The first A diagram shows a conventional passive pixel sensor. The first B diagram shows the 3T pixel circuit of a conventional active pixel sensor. The first C-picture shows a 4-inch pixel circuit of a conventional active pixel sensor. The second diagram shows a four-transistor (4T) pixel circuit of a complementary metal-oxide-semiconductor (CMOS) image sensor of the embodiment of the present invention, which is shared (4S) by four pixels. Figure 2B shows a four-transistor (4T) pixel circuit of a CMOS image sensor according to another embodiment of the present invention, which is shared by four pixels (4S). Figure 3A shows a four-electrode (4T) pixel circuit of a CMOS image sensor according to still another embodiment of the present invention, which is shared by four pixels (4S). The third B diagram shows the relevant timing diagram of the third A picture. 201041382 The third C diagram shows a simplified equivalent block diagram, feedback capacitor, and associated double sampling (CDS) circuit for the amplifier of Figure A. The third D-figure shows a simplified equivalent block diagram of the third A-picture in the 'reset phase. The third E diagram shows a simplified equivalent block diagram of the amplifier and feedback capacitor of the third A diagram in the accumulation phase. [Main component symbol description] _ 10 Amplifier 〇 2 0 Current source 30 Amplifier 32 Associated double sampling (CDS) circuit D Photodiode Μ acc Access transistor BL bit line WL WL word line. Vdd Power RST reset Signal Mrst Reset Transistor Msf Source Follower Transistor Msel Column Select Transistor TX Transmit Signal Mtx Transmit Transistor 15 201041382 FD Floating Diffusion Region S Node Cp Effective Point Capacity Cf Feedback Capacitance Vi Input Node (Voltage) V. Output node (voltage) SWi, SW2 switch