JP4639194B2 - 透明マルチモードpamインタフェース - Google Patents
透明マルチモードpamインタフェース Download PDFInfo
- Publication number
- JP4639194B2 JP4639194B2 JP2006538301A JP2006538301A JP4639194B2 JP 4639194 B2 JP4639194 B2 JP 4639194B2 JP 2006538301 A JP2006538301 A JP 2006538301A JP 2006538301 A JP2006538301 A JP 2006538301A JP 4639194 B2 JP4639194 B2 JP 4639194B2
- Authority
- JP
- Japan
- Prior art keywords
- pam
- mode
- clock
- symbol
- receiver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0002—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission rate
- H04L1/0003—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission rate by switching between different modulation schemes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
- H04L27/08—Amplitude regulation arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/14—Two-way operation using the same type of signal, i.e. duplex
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/14—Two-way operation using the same type of signal, i.e. duplex
- H04L5/1438—Negotiation of transmission parameters prior to communication
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
- H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
- H04L2025/03535—Variable structures
- H04L2025/03547—Switching between time domain structures
- H04L2025/03566—Switching between time domain structures between different tapped delay line structures
- H04L2025/03585—Modifying the length
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/028—Arrangements specific to the transmitter end
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0292—Arrangements specific to the receiver end
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Computer Security & Cryptography (AREA)
- Dc Digital Transmission (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US51517903P | 2003-10-27 | 2003-10-27 | |
| US10/805,413 US7308058B2 (en) | 2003-10-27 | 2004-03-19 | Transparent multi-mode PAM interface |
| PCT/US2004/035990 WO2005046156A2 (en) | 2003-10-27 | 2004-10-26 | Transparent multi-mode pam interface |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2007510377A JP2007510377A (ja) | 2007-04-19 |
| JP2007510377A5 JP2007510377A5 (https=) | 2007-06-07 |
| JP4639194B2 true JP4639194B2 (ja) | 2011-02-23 |
Family
ID=34527096
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006538301A Expired - Lifetime JP4639194B2 (ja) | 2003-10-27 | 2004-10-26 | 透明マルチモードpamインタフェース |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7308058B2 (https=) |
| EP (1) | EP1712055B1 (https=) |
| JP (1) | JP4639194B2 (https=) |
| KR (1) | KR20060120160A (https=) |
| WO (1) | WO2005046156A2 (https=) |
Families Citing this family (105)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7124221B1 (en) | 1999-10-19 | 2006-10-17 | Rambus Inc. | Low latency multi-level communication interface |
| US7135899B1 (en) * | 2003-06-27 | 2006-11-14 | Cypress Semiconductor Corp. | System and method for reducing skew in complementary signals that can be used to synchronously clock a double data rate output |
| US7792196B2 (en) * | 2004-12-28 | 2010-09-07 | Intel Corporation | Single conductor bidirectional communication link |
| US20070009267A1 (en) * | 2005-06-22 | 2007-01-11 | Crews Darren S | Driving a laser using an electrical link driver |
| US7279950B2 (en) * | 2005-09-27 | 2007-10-09 | International Business Machines Corporation | Method and system for high frequency clock signal gating |
| US20070086354A1 (en) * | 2005-10-17 | 2007-04-19 | Erickson Bruce A | Method and apparatus for performing a bit error rate test, and for configuring the receiving or transmitting end of a communication link |
| US8570881B2 (en) * | 2006-03-28 | 2013-10-29 | Advanced Micro Devices, Inc. | Transmitter voltage and receiver time margining |
| US7817727B2 (en) * | 2006-03-28 | 2010-10-19 | GlobalFoundries, Inc. | Hybrid output driver for high-speed communications interfaces |
| US7986727B2 (en) * | 2006-03-28 | 2011-07-26 | Globalfoundries Inc. | In-band method to configure equalization levels |
| US7822127B1 (en) * | 2006-05-15 | 2010-10-26 | Super Micro Computer, Inc. | Method and apparatus for minimizing signal loss in transit |
| US8565105B2 (en) * | 2008-09-29 | 2013-10-22 | Broadcom Corporation | Method and system for ethernet switching, conversion, and PHY optimization based on link length in audio/video systems |
| US20100115306A1 (en) * | 2008-11-05 | 2010-05-06 | Wael William Diab | Method and system for control of energy efficiency and associated policies in a physical layer device |
| WO2008106626A1 (en) * | 2007-02-28 | 2008-09-04 | Finisar Corporation | Multi-mode integrated circuit for use in optoelectronic devices |
| US7738486B2 (en) * | 2007-02-28 | 2010-06-15 | Finisar Corporation | Multi-mode integrated circuit for use in optoelectronic devices |
| US7920597B2 (en) * | 2007-03-12 | 2011-04-05 | Broadcom Corporation | Method and system for low power idle signal transmission in ethernet networks |
| US7962670B2 (en) * | 2007-06-06 | 2011-06-14 | Lantiq Deutschland Gmbh | Pin multiplexing |
| KR100915814B1 (ko) * | 2007-09-07 | 2009-09-07 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 데이터 출력 드라이버 제어회로 |
| US20090097401A1 (en) * | 2007-10-12 | 2009-04-16 | Wael William Diab | Method and system for configurable data rate thresholds for energy efficient ethernet |
| US8588254B2 (en) * | 2007-12-17 | 2013-11-19 | Broadcom Corporation | Method and system for energy efficient signaling for 100mbps Ethernet using a subset technique |
| US8194548B2 (en) * | 2007-12-17 | 2012-06-05 | Broadcom Corporation | Method and system for duty cycling portions of a network device based on aggregate throughput of the device |
| US8098661B2 (en) | 2008-04-04 | 2012-01-17 | Doron Handelman | Methods and apparatus for enabling communication between network elements that operate at different bit rates |
| US9277487B2 (en) * | 2008-08-01 | 2016-03-01 | Qualcomm Incorporated | Cell detection with interference cancellation |
| US7898991B2 (en) * | 2008-10-16 | 2011-03-01 | Finisar Corporation | Serializer/deserializer test modes |
| US8149643B2 (en) | 2008-10-23 | 2012-04-03 | Cypress Semiconductor Corporation | Memory device and method |
| US8982753B2 (en) * | 2008-11-05 | 2015-03-17 | Broadcom Corporation | Method and system for low latency state transitions for energy efficiency |
| US8373357B2 (en) * | 2009-01-26 | 2013-02-12 | Microchip Technology Incorporated | Modulator module in an integrated circuit device |
| US8358508B2 (en) | 2009-03-19 | 2013-01-22 | Panduit Corp. | Active patch panel |
| US8230240B2 (en) * | 2009-04-08 | 2012-07-24 | Broadcom Corporation | Method and system for energy efficient networking over a serial communication channel based on forward error correction support |
| WO2010146699A1 (ja) * | 2009-06-19 | 2010-12-23 | 株式会社日立製作所 | 電子計算機、電子計算機の信号補正方法 |
| MX2012003150A (es) * | 2009-09-14 | 2012-06-12 | Directv Group Inc | Metodo y sistema para distribuir contenido. |
| US9137485B2 (en) | 2010-01-21 | 2015-09-15 | Cadence Design Systems, Inc. | Home network architecture for delivering high-speed data services |
| US8973062B2 (en) * | 2010-01-21 | 2015-03-03 | Cadence Design Systems, Inc. | Multimode physical layer module for supporting delivery of high-speed data services in home multimedia networks |
| US8594262B2 (en) * | 2010-06-17 | 2013-11-26 | Transwitch Corporation | Apparatus and method thereof for clock and data recovery of N-PAM encoded signals using a conventional 2-PAM CDR circuit |
| US8208578B2 (en) * | 2010-06-21 | 2012-06-26 | North Carolina State University | Systems, methods, and computer readable media for fractional pre-emphasis of multi-mode interconnect |
| US8452189B2 (en) | 2011-01-19 | 2013-05-28 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Source-multiplexed pulse amplitude modulation (PAM) optical data communication system and method |
| US9071243B2 (en) | 2011-06-30 | 2015-06-30 | Silicon Image, Inc. | Single ended configurable multi-mode driver |
| US8760188B2 (en) * | 2011-06-30 | 2014-06-24 | Silicon Image, Inc. | Configurable multi-dimensional driver and receiver |
| US8873963B2 (en) | 2012-07-25 | 2014-10-28 | Doron Handelman | Apparatus and methods for generating and receiving optical signals at substantially 100Gb/s and beyond |
| US8885766B2 (en) * | 2012-09-11 | 2014-11-11 | Inphi Corporation | Optical communication interface utilizing N-dimensional double square quadrature amplitude modulation |
| US9648273B2 (en) | 2012-09-21 | 2017-05-09 | Panasonic Intellectual Property Management Co., Ltd. | Transmission system for transmitting high-resolution video signal by performing multi-value transmission changing in amplitude direction |
| US8873606B2 (en) | 2012-11-07 | 2014-10-28 | Broadcom Corporation | Transceiver including a high latency communication channel and a low latency communication channel |
| US8964818B2 (en) * | 2012-11-30 | 2015-02-24 | Broadcom Corporation | Use of multi-level modulation signaling for short reach data communications |
| US9054955B2 (en) | 2012-12-30 | 2015-06-09 | Doron Handelman | Apparatus and methods for enabling recovery from failures in optical networks |
| CN105122688B (zh) * | 2013-03-08 | 2017-06-30 | 颖飞公司 | 使用正交调幅的光学通信接口 |
| US9049075B2 (en) * | 2013-08-21 | 2015-06-02 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Adaptive modal PAM2/PAM4 in-phase (I) quadrature (Q) phase detector for a receiver |
| US9184841B2 (en) | 2013-09-06 | 2015-11-10 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Multi-level decoder with skew correction |
| US8989300B1 (en) | 2013-09-06 | 2015-03-24 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Multi-level coding and distortion compensation |
| US9344187B2 (en) | 2013-09-17 | 2016-05-17 | Doron Handelman | Apparatus and methods for enabling recovery in optical networks |
| US9246598B2 (en) * | 2014-02-06 | 2016-01-26 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Efficient pulse amplitude modulation integrated circuit architecture and partition |
| US20150256363A1 (en) * | 2014-03-04 | 2015-09-10 | Lsi Corporation | Integrated PAM4/NRZ N-Way Parallel Digital Unrolled Decision Feedback Equalizer (DFE) |
| TWI555404B (zh) * | 2014-03-28 | 2016-10-21 | 晨星半導體股份有限公司 | 多通道串列連線信號接收系統 |
| US9519604B2 (en) | 2014-04-11 | 2016-12-13 | Qualcomm Incorporated | Systems and methods for frequency control on a bus through superposition |
| US9674025B2 (en) | 2014-07-01 | 2017-06-06 | International Business Machines Corporation | 4-level pulse amplitude modulation transmitter architectures utilizing quadrature clock phases |
| US9252997B1 (en) | 2014-07-10 | 2016-02-02 | Qualcomm Incorporated | Data link power reduction technique using bipolar pulse amplitude modulation |
| US9331188B2 (en) | 2014-09-11 | 2016-05-03 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Short-circuit protection circuits, system, and method |
| US9660847B2 (en) * | 2014-11-26 | 2017-05-23 | Rambus Inc. | Equalized multi-signaling mode driver |
| US9621332B2 (en) | 2015-04-13 | 2017-04-11 | Qualcomm Incorporated | Clock and data recovery for pulse based multi-wire link |
| CN106921436B (zh) * | 2015-12-26 | 2019-11-05 | 华为技术有限公司 | 用于对多种速率的数据进行处理的方法及装置 |
| US11507529B2 (en) | 2016-03-28 | 2022-11-22 | Marvell Asia Pte, Ltd. | Multi-chip module with configurable multi-mode serial link interfaces |
| US11088876B1 (en) | 2016-03-28 | 2021-08-10 | Marvell Asia Pte, Ltd. | Multi-chip module with configurable multi-mode serial link interfaces |
| US10572416B1 (en) | 2016-03-28 | 2020-02-25 | Aquantia Corporation | Efficient signaling scheme for high-speed ultra short reach interfaces |
| US10447506B1 (en) | 2016-04-01 | 2019-10-15 | Aquantia Corp. | Dual-duplex link with independent transmit and receive phase adjustment |
| US9699009B1 (en) * | 2016-06-30 | 2017-07-04 | International Business Machines Corporation | Dual-mode non-return-to-zero (NRZ)/ four-level pulse amplitude modulation (PAM4) receiver with digitally enhanced NRZ sensitivity |
| US9954576B2 (en) | 2016-09-23 | 2018-04-24 | Dell Products, Lp | System and method for PAM-4 transmitter bit equalization for improved channel performance |
| US9825730B1 (en) * | 2016-09-26 | 2017-11-21 | Dell Products, Lp | System and method for optimizing link performance with lanes operating at different speeds |
| US9935682B1 (en) | 2016-12-22 | 2018-04-03 | Dell Products, Lp | System and method for PAM-4 transmitter bit equalization for improved channel performance |
| US10212010B2 (en) * | 2017-07-13 | 2019-02-19 | Zte Corporation | Unequally spaced pulse amplitude modulation scheme |
| US10277435B2 (en) * | 2017-08-07 | 2019-04-30 | Micron Technology, Inc. | Method to vertically align multi-level cells |
| US10530617B2 (en) | 2017-08-07 | 2020-01-07 | Micron Technology, Inc. | Programmable channel equalization for multi-level signaling |
| US10425260B2 (en) | 2017-08-07 | 2019-09-24 | Micron Technology, Inc. | Multi-level signaling in memory with wide system interface |
| US10447512B2 (en) | 2017-08-07 | 2019-10-15 | Micron Technology, Inc. | Channel equalization for multi-level signaling |
| US10277441B2 (en) | 2017-08-07 | 2019-04-30 | Micron Technology, Inc. | Uniformity between levels of a multi-level signal |
| US10403337B2 (en) | 2017-08-07 | 2019-09-03 | Micron Technology, Inc. | Output driver for multi-level signaling |
| US10355893B2 (en) | 2017-10-02 | 2019-07-16 | Micron Technology, Inc. | Multiplexing distinct signals on a single pin of a memory device |
| US10446198B2 (en) | 2017-10-02 | 2019-10-15 | Micron Technology, Inc. | Multiple concurrent modulation schemes in a memory system |
| US10725913B2 (en) | 2017-10-02 | 2020-07-28 | Micron Technology, Inc. | Variable modulation scheme for memory device access or operation |
| US10490245B2 (en) | 2017-10-02 | 2019-11-26 | Micron Technology, Inc. | Memory system that supports dual-mode modulation |
| US11403241B2 (en) * | 2017-10-02 | 2022-08-02 | Micron Technology, Inc. | Communicating data with stacked memory dies |
| US10128842B1 (en) * | 2018-03-23 | 2018-11-13 | Micron Technology, Inc. | Output impedance calibration for signaling |
| US11159153B2 (en) | 2018-03-29 | 2021-10-26 | Nvidia Corp. | Data bus inversion (DBI) on pulse amplitude modulation (PAM) and reducing coupling and power noise on PAM-4 I/O |
| US11966348B2 (en) | 2019-01-28 | 2024-04-23 | Nvidia Corp. | Reducing coupling and power noise on PAM-4 I/O interface |
| US10657094B2 (en) * | 2018-03-29 | 2020-05-19 | Nvidia Corp. | Relaxed 433 encoding to reduce coupling and power noise on PAM-4 data buses |
| US10599606B2 (en) | 2018-03-29 | 2020-03-24 | Nvidia Corp. | 424 encoding schemes to reduce coupling and power noise on PAM-4 data buses |
| DE102018205264B3 (de) * | 2018-04-09 | 2019-10-10 | Continental Automotive Gmbh | Verfahren zum Betreiben eines Ethernet-Bordnetzes eines Kraftfahrzeugs, Steuereinheit und Ethernet-Bordnetz |
| US10623200B2 (en) | 2018-07-20 | 2020-04-14 | Nvidia Corp. | Bus-invert coding with restricted hamming distance for multi-byte interfaces |
| US10998011B2 (en) | 2018-08-21 | 2021-05-04 | Micron Technology, Inc. | Drive strength calibration for multi-level signaling |
| US11113212B2 (en) * | 2018-10-23 | 2021-09-07 | Micron Technology, Inc. | Multi-level receiver with termination-off mode |
| US11194726B2 (en) * | 2019-02-25 | 2021-12-07 | Micron Technology, Inc. | Stacked memory dice for combined access operations |
| US11609865B2 (en) * | 2019-04-17 | 2023-03-21 | Micron Technology, Inc. | Method and apparatus for signal path biasing in a memory system |
| US10581652B1 (en) | 2019-05-01 | 2020-03-03 | Dell Products, Lp | System and method for PAM-4 transmitter bit equalization for improved channel performance beyond 32 Gbps |
| US10904998B2 (en) | 2019-05-01 | 2021-01-26 | Dell Products, L.P. | System and method for via optimization in a printed circuit board |
| CN110401486B (zh) * | 2019-08-07 | 2022-06-24 | 青岛海信宽带多媒体技术有限公司 | 一种光模块及光发射控制方法 |
| KR102780227B1 (ko) | 2020-08-11 | 2025-03-14 | 삼성전자주식회사 | 메모리 시스템, 이의 구동 방법 및 이를 이용한 스토리지 장치 |
| KR102824213B1 (ko) | 2020-08-21 | 2025-06-26 | 삼성전자주식회사 | 메모리 장치, 그것을 제어하는 제어기, 그것을 포함하는 메모리 시스템 및 그것의 동작 방법 |
| KR102909764B1 (ko) * | 2020-10-16 | 2026-01-09 | 삼성전자주식회사 | 테스트용 멀티 레벨 신호 생성 장치 및 이를 포함하는 메모리 장치 |
| CN114697261A (zh) * | 2020-12-30 | 2022-07-01 | 华为技术有限公司 | 基带数据传输的方法和系统 |
| US12347508B2 (en) | 2021-02-12 | 2025-07-01 | Nvidia Corp. | Error detection pin encoding scheme to avoid maximum transitions and further improve signal integrity on high speed graphic memory interfaces |
| US11632275B2 (en) * | 2021-04-28 | 2023-04-18 | Nvidia Corp. | CMOS signaling front end for extra short reach links |
| US12155923B2 (en) | 2021-07-09 | 2024-11-26 | Semiconductor Components Industries, Llc | Communications channel with multi-level signal transmission |
| US12002541B2 (en) * | 2021-12-08 | 2024-06-04 | Advanced Micro Devices, Inc. | Read clock toggle at configurable PAM levels |
| US11854602B2 (en) | 2021-12-08 | 2023-12-26 | Advanced Micro Devices, Inc. | Read clock start and stop for synchronous memories |
| US12132590B2 (en) | 2022-03-18 | 2024-10-29 | Nvidia, Corp. | Hardware-efficient PAM-3 encoder and decoder |
| US12135607B2 (en) | 2022-03-18 | 2024-11-05 | Nvidia Corp. | Hardware-efficient PAM-3 encoder and decoder |
| KR102766773B1 (ko) * | 2022-06-23 | 2025-02-13 | 고려대학교산학협력단 | 패턴 기반의 클럭 및 데이터 복원 회로를 이용하는 pam-4 수신기 |
| US12015413B2 (en) | 2022-09-15 | 2024-06-18 | Apple Inc. | Coding for pulse amplitude modulation with an odd number of output levels |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5115450A (en) | 1989-07-06 | 1992-05-19 | Advanced Micro Devices, Inc. | High speed digital to analog to digital communication system |
| US7124221B1 (en) * | 1999-10-19 | 2006-10-17 | Rambus Inc. | Low latency multi-level communication interface |
| US7072415B2 (en) * | 1999-10-19 | 2006-07-04 | Rambus Inc. | Method and apparatus for generating multi-level reference voltage in systems using equalization or crosstalk cancellation |
| DE20122739U1 (de) * | 2000-01-06 | 2007-08-23 | Rambus Inc., Los Altos | Kommunikationsschnittstelle mit mehrstufiger niedriger Verzögerung |
| US7061973B1 (en) | 2000-02-03 | 2006-06-13 | General Electric Capital Corporation | Data mode signaling system for PCM modem adaptation |
-
2004
- 2004-03-19 US US10/805,413 patent/US7308058B2/en not_active Expired - Lifetime
- 2004-10-26 EP EP04796742A patent/EP1712055B1/en not_active Expired - Lifetime
- 2004-10-26 KR KR1020067010360A patent/KR20060120160A/ko not_active Withdrawn
- 2004-10-26 WO PCT/US2004/035990 patent/WO2005046156A2/en not_active Ceased
- 2004-10-26 JP JP2006538301A patent/JP4639194B2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| WO2005046156A2 (en) | 2005-05-19 |
| WO2005046156A3 (en) | 2006-11-23 |
| US7308058B2 (en) | 2007-12-11 |
| EP1712055B1 (en) | 2013-01-30 |
| US20050089126A1 (en) | 2005-04-28 |
| JP2007510377A (ja) | 2007-04-19 |
| EP1712055A2 (en) | 2006-10-18 |
| KR20060120160A (ko) | 2006-11-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4639194B2 (ja) | 透明マルチモードpamインタフェース | |
| US10812297B2 (en) | Selectable-tap equalizer | |
| US5777567A (en) | System and method for serial to parallel data conversion using delay line | |
| EP1618597B1 (en) | Partial response receiver | |
| US7308048B2 (en) | System and method for selecting optimal data transition types for clock and data recovery | |
| US8861578B1 (en) | Transition time measurement of PAM4 transmitters | |
| US9942063B2 (en) | Apparatus for improved encoding and associated methods | |
| WO2014209681A1 (en) | Transition time measurement of pam4 transmitters | |
| US8861667B1 (en) | Clock data recovery circuit with equalizer clock calibration | |
| US11153129B1 (en) | Feedforward equalizer with programmable roaming taps | |
| US7362800B1 (en) | Auto-configured equalizer | |
| CN105515727B (zh) | 用于改进编码的设备以及相关方法 | |
| US7426235B1 (en) | Method of adaptive equalization for high-speed NRZ and multi-level signal data communications | |
| WO2004008490A2 (en) | A selectable-tap equalizer, auto-configured equalizer, receiving circuit having an equalizer calibration function, and system having grouped reflection characteristics | |
| US11962301B2 (en) | Ring oscillator using multi-phase signal reassembly | |
| US6806817B2 (en) | Means and method of data encoding and communication at rates above the channel bandwidth |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20070316 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20071025 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100604 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100609 |
|
| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20100908 |
|
| A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20100915 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101012 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20101105 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20101129 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131203 Year of fee payment: 3 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 4639194 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| EXPY | Cancellation because of completion of term |