JP4624754B2 - Ceramic substrate for thin film electronic component, manufacturing method thereof, and thin film electronic component using the same - Google Patents

Description

  The present invention relates to a ceramic substrate for a thin film electronic component, a method for manufacturing the same, and a thin film electronic component using the same. More specifically, the present invention relates to a ceramic substrate used for a thin film electronic component that requires excellent smoothness, a manufacturing method thereof, and a thin film electronic component using the same.

  In recent years, many thin-film electronic components using thin films such as small-sized and large-capacity thin-film capacitors have been demanded. In these thin film electronic components, for example, thin film capacitors, it is necessary to reduce the thickness of the conductor layer and the dielectric layer as much as possible. For this reason, a thin film forming technique such as a sputtering method, a CVD method, or a sol-gel method is mainly used for forming each layer. However, the formation of this thin layer is greatly influenced by the surface state of the substrate serving as the base. If the substrate surface is not sufficiently flat, desired characteristics cannot be stably obtained, and various problems such as insufficient insulation between layers in the conductor layer occur. As a substrate capable of obtaining a flat surface with particularly high accuracy, a glazed ceramic substrate in which the surface of a ceramic substrate is glass-coated is known as shown in Patent Document 1 and Patent Document 2 below.

Japanese Patent Laid-Open No. 2001-040773 JP 2003-017301 A

Patent Document 1 states that a flattening film such as a glass coating may be deposited to improve flatness. Similarly, Patent Document 2 shows that a flat surface can be obtained by using a glazed alumina substrate. However, in the conventional glazed ceramic substrate, as shown in Patent Document 2, even if a high-purity alumina substrate of 99.5% or more is used, the arithmetic average roughness Ra on the surface of the glazed ceramic substrate is at least 30 nm. Degree. According to the recent demand for thin film electronic components, a flat surface with higher accuracy is required, but it is difficult with the conventional technique.
The present invention has been made in view of the above, and in particular, a ceramic substrate for thin-film electronic components, a thin film using the same, and a thin-film electronic component ceramic substrate capable of obtaining a flat surface with high accuracy reliably and easily and further at low cost. The purpose is to provide electronic components.

As a result of studies on the glazed substrate, the present inventors have found that the flattening of the glazed substrate is greatly influenced by bubbles that are easily contained in glass. In a glazed substrate, after applying a glass paste, the applied glass paste is heated to layer the glass. However, the viscosity of the molten glass is high, and it has been difficult to heat the paste without burning the organic matter in the paste without enclosing bubbles. In addition, for example, a structure in which a conductor layer is directly arranged on the formed glass surface is also conceivable, so that the glass composition cannot be selected only from the viewpoint of heating and defoaming.
Therefore, the present inventors have studied a method for manufacturing a flat surface with higher accuracy in a glazed ceramic substrate in a reliable and easy manner and further capable of selecting a wide range of materials, and heating the applied glass paste. We thought about solving the problem by pressurizing at the same time. As a result, it has been found that a flat surface with surprisingly high accuracy can be obtained as compared with the surface roughness of the conventional glazed ceramic substrate. Furthermore, it has been found that in this method, even if a general-purpose inexpensive substrate having a large surface roughness is used as a substrate for forming the glaze layer, a flat surface with high accuracy can be obtained without any problems. The present invention has been completed based on these findings.

That is, the present invention is as follows.
(1) A ceramic substrate for a thin film electronic component comprising: a base ceramic substrate; and a glaze layer formed on at least one side of the base ceramic substrate,
The glass layer formed on the surface of the base ceramic substrate is heated and pressurized to form a glaze layer on the base ceramic substrate, and the surface of the glaze layer is planarized and polished.
The heating temperature in the heating and pressing treatment is 750 to 1000 ° C., the pressing pressure is 0.5 to 200 MPa,
Arithmetic average roughness Ra of the surface of the glaze layer is less than 0.02 [mu] m, and the maximum height Ry is I der 0.25μm or less,
A ceramic substrate for a thin film electronic component, wherein the glaze layer does not have a pore .
(2) The ceramic substrate for thin film electronic components according to (1), wherein the glaze layer has a thickness of 10 to 100 μm.
(3) The glass which comprises the said glaze layer is a ceramic substrate for thin film electronic components as described in said (1) or (2) which has Si, Al, B, Ca, and O as a main component.
(4) The ceramic substrate for thin-film electronic components according to any one of (1) to (3) , which includes a wiring pattern therein.
(5) A thin film electronic component comprising the ceramic substrate for thin film electronic components according to any one of (1) to (4 ) above.
(6) A capacitor portion in which a capacitor conductor layer and a capacitor dielectric layer are laminated on the ceramic substrate for thin film electronic components is provided, and the capacitor portion is disposed between the two opposing capacitor conductor layers. The thin-film electronic component according to (5) , wherein the capacitor conductor layers and the capacitor dielectric layers are alternately stacked so that the capacitor dielectric layers are disposed.
(7) a base ceramic substrate, and a glaze layer formed on at least one side of the base ceramic substrate,
The glass layer formed on the surface of the base ceramic substrate is heated and pressurized to form a glaze layer on the base ceramic substrate, and the surface of the glaze layer is planarized and polished.
The arithmetic average roughness Ra of the surface of the glaze layer is 0.02 μm or less, and the maximum height Ry is 0.25 μm or less,
A method of manufacturing a ceramic substrate for a thin film electronic component comprising a wiring pattern therein ,
A resist layer forming step of forming a resist layer on the surface of the base ceramic substrate having an internal wiring pattern with an end face exposed on the surface;
Patterning the resist layer to form a patterning hole leading to the end face of the internal wiring pattern; and
An internal wiring pattern end forming step of filling the patterning hole with a conductive material to form an internal wiring pattern end connected to the end face of the internal wiring pattern;
A resist layer removing step of removing the patterned resist layer;
So that at least a portion of the internal wiring pattern end portion is buried, the glass layer forming step of forming the glass layer on the surface of the ceramic substrate for the base portion,
Subjected to heat and pressure treatment, a heating and pressurizing treatment step of forming the glaze layer on the surface of the ceramic substrate for the base portion,
A method for producing a ceramic substrate for a thin-film electronic component, comprising: a planarizing and polishing step for polishing the surface of the glaze layer flatly to expose an end portion of the internal wiring pattern.
(8) A base ceramic substrate, and a glaze layer formed on at least one side of the base ceramic substrate,
The glass layer formed on the surface of the base ceramic substrate is heated and pressurized to form a glaze layer on the base ceramic substrate, and the surface of the glaze layer is planarized and polished.
The arithmetic average roughness Ra of the surface of the glaze layer is 0.02 μm or less, and the maximum height Ry is 0.25 μm or less,
A method of manufacturing a ceramic substrate for a thin film electronic component comprising a wiring pattern therein ,
A glass layer forming step of forming the glass layer on the surface of the ceramic substrate for the base comprising an internal wiring pattern end surface is exposed on the surface,
Subjected to heat and pressure treatment, a heating and pressurizing treatment step of forming the glaze layer on a ceramic substrate for the base portion,
A resist layer forming step of forming a resist layer on the glaze layer;
Patterning the resist layer to form a patterning hole that leads to the end face of the internal wiring pattern; and
An etching step of etching the glaze layer from the patterning hole to form an etching hole leading to the end face of the internal wiring pattern;
A resist layer removing step for removing the patterned resist layer, and an internal wiring that fills the etching hole with a conductive material to form an end portion of the internal wiring pattern connected to the end face of the internal wiring pattern A pattern edge forming step;
A method for producing a ceramic substrate for a thin-film electronic component, comprising: a planarizing and polishing step for polishing the surface of the glaze layer flatly to expose an end portion of the internal wiring pattern.

According to the ceramic substrate for a thin film electronic component of the present invention, since it has a highly accurate flat surface, a highly reliable thin film electronic component can be obtained stably. In addition, a highly reliable thin film electronic component can be obtained at low cost.
When the thickness of the glaze layer is 10 to 100 μm, a flat surface with particularly high accuracy can be obtained, and a highly reliable thin film electronic component can be stably obtained.
When the glass constituting the glass layer is mainly composed of Si, Al, B, Ca and O, a flat surface with particularly high accuracy can be obtained, and a conductor layer can be directly formed on the glaze surface, which is highly reliable. Thin film electronic components can be obtained stably.
When the wiring pattern is provided inside, it is possible to provide a ceramic substrate for a thin film electronic component that contributes to downsizing of the component, for example, another electronic component can be mounted on the obtained thin film electronic component.

The thin film electronic component of the present invention is excellent in accuracy and reliability because a substrate having a flat surface with high accuracy is used.
According to the thin film electronic component having the predetermined capacitor portion on the ceramic substrate for the thin film electronic component of the present invention, stable electrical characteristics can be exhibited, no short circuit or the like occurs, and the capacitor function has high reliability. be able to.
According to the method for manufacturing a ceramic substrate for thin film electronic components according to the first aspect of the present invention, a ceramic substrate for thin film electronic components having a flat surface with high accuracy can be obtained reliably and easily.
According to the method for manufacturing a ceramic substrate for thin film electronic components according to the second aspect of the present invention, a ceramic substrate for thin film electronic components having a flat surface with high accuracy can be obtained reliably and easily.

The present invention will be described in detail below.
[1] Ceramic substrate for thin film electronic component The ceramic substrate for thin film electronic component of the present invention comprises a base ceramic substrate and a glaze layer formed on at least one side of the base ceramic substrate. The glass layer formed on the surface is heated and pressurized to form a glaze layer on the base ceramic substrate, and the surface of the glaze layer is flattened and polished . The heating temperature in the heating and pressing process is 750 to 1000. a ° C., applied pressure is 0.5～200MPa, arithmetic average roughness Ra of the surface of the glaze layer is less than 0.02 [mu] m, and the maximum height Ry is I der 0.25μm or less, The glaze layer is characterized by having no pores .

The “base ceramic substrate” is a ceramic substrate that forms the base of a ceramic substrate for thin film electronic components. Moreover, it is a board | substrate which supports the glaze layer mentioned later. This base ceramic substrate may be composed of only one layer or may be composed of two or more layers. In addition, a wiring pattern may or may not be provided inside.
Although the ceramic component which comprises a base ceramic substrate is not specifically limited, What is excellent in heat resistance and mechanical strength is preferable. Among such ceramic components, the main ceramic component (hereinafter simply referred to as “main ceramic component”, usually 40% by mass or more based on the total) is exemplified by alumina, zirconia, silica and magnesia. Etc. Of these, alumina is preferable. This is because it has excellent insulating properties, heat resistance, mechanical strength, thermal stability, etc., is highly versatile and can be obtained at low cost.
When alumina is contained as the main ceramic component, the content is not particularly limited, except for the glass ceramic mixed layer (mixed layer formed by glass permeating the surface of the base ceramic substrate), and further, In the case of providing an internal wiring pattern or the like, it is preferably 40% by mass or more (more preferably 70 to 99% by mass, further preferably 85 to 98% by mass) when the entire ceramic portion excluding these is 100% by mass. . If it is 40 mass% or more, the said property with which alumina is provided can fully be exhibited.

  Further, in addition to the main ceramic component, magnesia, calcia, silica, boric acid and the like can be contained as a sub-ceramic component (usually contained in an amount of less than 40% by mass with respect to the whole). However, the main ceramic component and the sub ceramic component are different. In addition to the main ceramic component and the sub ceramic component, other ceramic components derived from a sintering aid or the like may be contained. Each of these main ceramic component, sub-ceramic component and other ceramic component may be contained alone or in combination of two or more.

  Furthermore, any substrate may be used as the base substrate (substrate before forming the glaze layer) constituting the base ceramic substrate. That is, for example, a ceramic substrate, a glass ceramic substrate, and other substrates can be used. Among these, a base substrate that does not contain glass or a base substrate that contains a small amount of glass is preferable. When glass is contained in this base substrate, the content is 40% by volume or less (more preferably 20% by volume or less, more preferably 15% by volume or less) when the whole base substrate is 100% by volume. It is preferable. Furthermore, it is more preferable that the glass constituting the glaze layer has a higher yield point (for example, preferably higher than 100 ° C.), and further the softening point is higher than that of the glass contained in the base substrate. Particularly preferred is glass (for example, preferably 100 ° C. or higher). Thereby, even when used as a substrate for a capacitor, a thin film electronic component that can withstand a manufacturing process at a high temperature, exhibits sufficient mechanical strength, and has high durability can be obtained.

  Furthermore, the surface roughness of the surface on which the glaze layer of the base ceramic substrate is formed is not particularly limited as long as the surface roughness is not exposed from the glaze layer described later. That is, at least the maximum height Ry should be smaller than the thickness of the glaze layer (usually, the thickness after polishing). For example, when the thickness of the glaze layer is 50 μm, Ry on the surface of the base ceramic substrate may be less than 50 μm. Further, the shape and size of the base ceramic substrate are not particularly limited. Moreover, although the thickness is not specifically limited, Usually, it is 200 micrometers or more (preferably 200-2000 micrometers, More preferably, it is 300-1000 micrometers). If it is 200 micrometers or more, sufficient mechanical strength can be provided to the ceramic substrate for thin layer electronic components.

  The “glaze layer” is a layer made of glass having an arithmetic average roughness Ra of 0.02 μm or less and a maximum height Ry of 0.25 μm or less. This glaze layer may be formed on only one surface of the base ceramic substrate, or may be formed on both surfaces of the base ceramic substrate. Further, it can be set to Ra 0.015 μm or less and Ry 0.25 μm or less, particularly Ra 0.010 μm or less and Ry 0.20 μm or less. The polishing method for obtaining this surface is not limited, and for example, mechanical polishing, chemical mechanical polishing, chemical polishing and the like can be used.

  Moreover, this glaze layer does not have a pore. Not having pores means that pores having a major axis of 0.2 μm or more are not recognized in any 100 μm square region in at least 10 different cross sections in the stacking direction. That is, it is a very dense dense glaze layer having few pores in the glaze layer. However, the “cross-section in the stacking direction” is a cross-section perpendicular to the direction in which the glaze layer is stacked on the ceramic substrate for the substrate, and “observation” is usually performed in an image magnified 2000 times or more. Is. This glaze layer may be formed on only one surface of the base ceramic substrate, or may be formed on both surfaces of the base ceramic substrate.

The glaze layer having no pores can be obtained by subjecting the glass layer to heat and pressure treatment. This heating and pressurizing treatment is performed at a temperature 100 ° C. lower than the yield point of the glass used (hereinafter, this temperature is also referred to as “Td- ₁₀₀ ”) and higher (this temperature is “Td− ₁₀₀ or more”). Up to 0.5 to 200 MPa, preferably 0.5 to 50 MPa. It should be noted that the glaze layer may be obtained by directly subjecting a layer containing glass powder (a layer that becomes a glass layer when baked) to a heat-pressing treatment without being baked.

Further, the ceramic substrate for thin-film electronic components of the present invention, the glaze layer has no pores as described above but is intended (on the surface to the inside), as a reference example, for example, the pores in the interior However, it is also possible to form a layer made of glass having a surface roughness in the above predetermined range without having pores on the surface . The method for forming this glaze layer (with pores inside but without pores on the surface) is not particularly limited, but the layer containing the glass powder is heated to a temperature equal to or higher than the softening point of the glass (baking). You can get it. The heating temperature is preferably 800 to 1200 ° C. (more preferably 900 to 1100 ° C.) for a glass having a yield point of about 700 to 780 ° C., for example. When pores are observed on the surface of the glass layer after heating, the pores on the surface can be removed by further heating.

  The glass constituting the glaze layer is not particularly limited, but is preferably excellent in heat resistance, insulation and mechanical strength. As a glass component constituting this glass, for example, usually, at least Si, Al and O are contained. Furthermore, as other elements, B, Ca, Mg, Sr, Ba, V, Cr, Mn, Co, Ni, Ga, Y, Zr, Nb, Mo, Tc, In, Sn, Ta, W, Re, Bi Each lanthanoid element and each actinoid element can be contained. Among these other elements, B, Ca, Mg, Ba and the like are preferable, and B and Ca are more preferable. These other elements may contain only 1 type and 2 or more types may contain. Each of these elements may be contained as a double oxide containing two or more metal elements among the above elements. On the other hand, it is preferable that an alkali metal element, P, Pb and the like are not substantially contained. Furthermore, when it is set as the glass excellent in insulation especially, it is preferable not to contain the transition metal of the above-mentioned.

In particular, Si, Al, B, Ca, and O are preferably used as main components. That is, when the entire glaze layer is 100 mass%, the total content of Si converted to SiO ₂ , Al converted to Al ₂ O ₃ , B converted to B ₂ O ₃ , and Ca converted to CaO is 80 mass% or more ( More preferably, it is 90% by mass, and still more preferably 95% by mass or more.
Furthermore, when the entire glass is 100 mass%, 50 to 70 wt% of Si in terms of SiO ₂ (more preferably 55 to 65 wt%), and 3 to 15 mass Al in terms _{of Al} 2 _{O 3} % (More preferably 5 to 10% by mass), and in addition, B is 10 to 30% by mass (more preferably 15 to 25% by mass) in terms of B ₂ O ₃ , and Ca is added. It can contain 3-20 mass% (more preferably 5-15 mass%) in conversion of CaO.

The transition point of the glass is not particularly limited, but is preferably 600 ° C. or higher (more preferably 630 ° C. or higher, usually 700 ° C. or lower).
The softening point of the glass is not particularly limited, but is preferably 750 ° C. or higher (more preferably 800 ° C. or higher, usually 1200 ° C. or lower).

Further, the yield point of the glass is not particularly limited, but is preferably 750 ° C. or higher (more preferably 800 ° C. or higher, usually 1200 ° C. or lower). The working temperature applied when manufacturing a thin film electronic component using the ceramic substrate for thin film electronic components is usually about 700 ° C. is the highest. For this reason, if the yield point is 750 ° C. or higher, the flatness of the glaze layer surface can be sufficiently maintained. That is, it is particularly suitable for the case where the glass constituting the glaze layer is heated to 700 ° C. or higher in the subsequent step. Examples of such a process include a capacitor part forming process using a sol-gel method. In addition, the yield point of this glass should just be 700 degreeC or more, for example, a thing with a yield point of 700-800 degreeC can be used.
Therefore, a highly accurate flat surface can be obtained, and a highly reliable thin film electronic component can be obtained stably. Further, since flatness is maintained even at a working temperature normally applied when forming a thin film electronic component using this, a highly reliable thin film electronic component can be stably obtained.

In particular, the glass constituting the glaze layer is mainly composed of Si, Al, B, Ca and O, does not contain alkali metal elements, P, Pb and transition metals, and has a yield point of 750 ° C. or higher (700 ° C. or higher). However, high temperature heat resistance can be exhibited. In addition, high migration resistance can be exhibited particularly at high temperatures and further in long-term use. For this reason, in the thin film electronic component using the ceramic substrate for thin film electronic components of this invention, the further outstanding reliability can be exhibited. Incidentally, the above-mentioned “not containing alkali metal element, P, Pb and transition metal” means that when the entire glaze layer is 100 mass%, the alkali metal (assumed as A) is 0.02 mass in terms of A ₂ O. % Or less, P is 0.02 mass% or less in terms of P ₂ O ₅ , Pb is 0.02 mass% or less in terms of PbO ₂ , and the transition metal is 0.02 mass in terms of the oxide having the most stable oxidation number. % Or less.

  Further, the shape and size of the glaze layer are not particularly limited. Further, the thickness is not particularly limited, but it is preferably 100 μm or less (more preferably 70 μm or less, further preferably 50 μm or less, usually 10 μm or more). The surface of the glaze layer is flattened by polishing, but the thickness of the glaze layer may be such that the base ceramic substrate is not exposed by this polishing. Usually, a thickness of at least 10 μm or more is required in view of polishing accuracy. Further, when the thickness of the glaze layer is within the above range, the height of the end portion of the internal wiring pattern formed in the glaze layer can be suppressed when the wiring pattern is provided inside as described later.

This ceramic substrate for thin film electronic components can have a wiring pattern inside. The “wiring pattern” is formed at least inside the ceramic substrate for thin film electronic components. An example of such a wiring pattern is a via wiring (21 in FIG. 14) formed on a ceramic substrate for thin film electronic components. The via wiring is, for example, a wiring pattern that conducts between the front surface side and the back surface side of the ceramic substrate for thin film electronic components. The conductive material constituting the via wiring is not particularly limited, and for example, tungsten, molybdenum, gold, platinum, silver, palladium, copper, nickel, and the like can be used. These conductive materials may use only 1 type and may use 2 or more types.
Further, the shape of the via wiring is not particularly limited, but is usually a cylindrical shape penetrating each layer in the stacking direction. Moreover, the diameter is not particularly limited, but may be, for example, 50 to 200 μm.
In addition to the above-described via wiring, a wiring pattern formed in the plane direction can be provided in the same manner as the electrode layer constituting the thin film electronic component. That is, for example, normal conduction wiring, resistance wiring, inductance wiring, bonding pads, and the like can be given.

The ceramic substrate for thin-film electronic components of the present invention is a method in which a glass layer formed on the surface of the base ceramic substrate is heated and pressurized to form a glaze layer on the base ceramic substrate, and the surface of the glaze layer is planarized and polished. Do it.

As the base ceramic substrate, a fired ceramic substrate may be used as it is, but it is preferable to use it after polishing and leveling to such an extent that undulations caused by warpage or the like peculiar to ceramics are removed.
The glaze layer is a layer obtained through a heat and pressure treatment.
As for the surface roughness of this glaze layer, Ra can be 0.02 μm or less (more preferably 0.015 μm or less, particularly 0.010 μm or less). Ry can be set to 0.25 μm or less (further 0.20 μm or less). Furthermore, it can be set to Ra 0.02 μm or less and Ry 0.25 μm or less (further Ra 0.015 μm or less and Ry 0.25 μm or less, particularly Ra 0.010 μm or less and Ry 0.20 μm or less). Furthermore, it may be a glass layer in which pores having a major axis of 0.2 μm or more are not recognized in any 100 μm square region in at least 10 different cross sections in the stacking direction.

The “glass layer” is a layer made of glass that has not been heated and pressurized. This glass layer usually has voids (synonymous with pores) inside. That is, it differs from the glaze layer that has been heated and pressurized in that it has pores. Glass constituting the glass layer, said a "glass forming the glaze layer" can be applied as it is. Moreover, the shape and magnitude | size of this glass layer are not specifically limited. Although not limited particularly also the thickness thereof, it is preferable that the thickness of the solidified state is what the 10μm or more thick glass layer than the maximum height Ry of the ceramic substrate for the base. For example, it can be set to 0.05 to 1 mm. The method for forming this glass layer is not particularly limited, and can be obtained, for example, by baking a layer containing glass powder described later.

  Baking means heating the layer containing the glass powder to a temperature equal to or higher than the softening point of the glass constituting the glass powder to make the glass layered. This baking temperature is an appropriate temperature depending on the composition of the glass used. For example, in a glass having a yield point of about 700 to 780 ° C., the baking temperature is 800 to 1200 ° C. (more preferably 900 to 1100 ° C.). Is preferred. Also, the baking atmosphere is not particularly limited, and it is preferable that the baking atmosphere is appropriately selected depending on the conductor material constituting the internal wiring pattern included in the base ceramic substrate. That is, for example, when the conductor material is mainly composed of gold and platinum, it is preferably performed in an air atmosphere, and when the conductor material is easily oxidized such as copper, nickel, tungsten and molybdenum, it is non-oxidizing. It is preferably performed in an atmosphere.

The shape, size, and thickness of the layer containing the glass powder are not particularly limited. Glass powder contained in the layer is a powder consisting of "glass forming the glaze layer" of the. The shape of this powder is not particularly limited. Moreover, although a magnitude | size is not specifically limited, Usually, a thing with an average particle diameter of 0.1-100 micrometers is used. If it is this range, it will be easy to soften or workability | operativity is also good.
The formation method of the layer containing this glass powder is not specifically limited. For example, it can be obtained by applying a paste containing glass powder (hereinafter simply referred to as “glass paste”). Alternatively, the base ceramic substrate is placed in the slurry in which the glass powder is dispersed and the glass powder is precipitated and deposited, and then taken out from the slurry and dried. Furthermore, it can be obtained by directly sprinkling glass powder to form a layer consisting only of glass powder. Among these methods, it is preferable from the viewpoint of workability and the like to obtain by applying a glass paste.

When this glass paste is used, the glass paste usually contains an organic component in addition to the glass powder. This organic component mainly imparts moldability and the like to the glass paste. As the organic component, a binder is usually contained. Examples of the binder include ethyl cellulose resin, butyral resin, acrylic resin, and the like. These may use only 1 type and may use 2 or more types together. In addition, a plasticizer, a dispersant, a solvent, and the like can be contained. Only 1 type may contain these and 2 or more types may contain. Moreover, this glass paste can contain a dispersing agent, a leveling agent component, a lubricant component, an antifoaming agent component, an antioxidant component, etc. irrespective of whether it is an inorganic component or an organic component. Only 1 type may contain these and 2 or more types may contain.
Although the viscosity of this glass paste is not specifically limited, For example, it can be 1-1000 Pa * s (more preferably 20-500 Pa * s).
The method for applying the glass paste is not particularly limited, and is preferably selected as appropriate depending on the viscosity and properties of the glass paste. For example, when the glass paste has a viscosity of 1 to 1000 Pa · s as described above, it can be applied by screen printing, doctor blade method, curtain coater printing, or the like. Of these, screen printing and doctor blade methods are preferred. Further, when the viscosity is less than the lower limit of the above viscosity range, it can also be carried out by spin coating, dip coating, spray coating (including inkjet method and thermal method) and the like.

The “heating and pressurizing process” is a process of applying pressure while heating the glass layer. This heating method and pressurizing method are not particularly limited. For example, isotropic pressurization or uniaxial pressurization may be used. Further, the pressure medium may be any of gas, powder and liquid. Of these, isotropic pressurization is preferred, and the pressure medium is preferably a gas. An example of such a method is a hot isostatic pressing method (hereinafter simply referred to as “HIP method”).
In addition, when the glass layer is subjected to heat and pressure treatment, the substantially solidified glass layer may be subjected to heat and pressure treatment, but the glass layer is preheated in advance to have fluidity. It is preferable. By setting this fluid state, voids can be effectively produced from the glass layer. The state having fluidity is usually heated at a temperature higher than the temperature (Td- ₁₀₀ ) lower by 100 ° C. from the yield point of the glass constituting the glass layer (this temperature is “Td− ₁₀₀ or more”). It shall mean the state of being.
When the layer containing the glass powder described above is used, the preheating before the heating and pressurizing treatment may be performed continuously with a step of baking the layer containing the glass powder to form a glass layer, or in a separate step. May be. Further, the preheating may be performed continuously with the heat and pressure treatment or in a separate process.

The heating temperature in this heat pressure treatment, it is preferable that the appropriate temperature depending on the characteristics of the glass used is 750 to 1000 ° C., preferably from 750 to 900 ° C.. Further, it is preferable that the appropriate pressure by the characteristics of the glass used also applied pressure is 0.5～200MPa, preferably 0.5 to 50. Furthermore, it is preferable that the heating temperature is 750 to 900 ° C. and the pressing pressure is 0.5 to 50 MPa. If it is this range, a highly accurate flat surface will be obtained and a highly reliable thin film electronic component can be obtained stably.

  The “flattening polishing” is to flatly polish the surface of the glaze layer obtained by the heat and pressure treatment. This polishing method is not particularly limited, and may be mechanical polishing, chemical mechanical polishing, or chemical polishing.

The ceramic substrate for thin film electronic components according to the present invention includes a base ceramic substrate, a glaze layer formed on at least one side of the base ceramic substrate, and a wiring formed inside the base ceramic substrate and the glaze layer. A pattern, and
One end of the wiring pattern is exposed on the glaze layer of the surface of the ceramic substrate for thin film electronic components, and the other end is exposed on the other surface of the ceramic substrate for thin film electronic components. be able to.

One end of the wiring pattern is exposed on the glaze layer of the surface of the ceramic substrate for thin film electronic components, and the other end is exposed on the other surface of the ceramic substrate for thin film electronic components. That is , for example, when the ceramic substrate for thin film electronic components is provided with a glaze layer only on one surface, the other end of the wiring pattern may be exposed on the back surface of the base ceramic substrate. It may be exposed on the side of the. Furthermore, when the ceramic substrate for thin film electronic components includes a glaze layer on both surfaces thereof, the other end of the wiring pattern can be exposed on the glaze layer surface on the back surface side. That is, the wiring pattern may be formed so as to penetrate the ceramic substrate for thin film electronic components on the front and back, and may be formed so as to communicate with the surface side including the glaze layer and the side surface of the base ceramic substrate. Internal wiring pattern in the other respects, can be applied as the "internal wiring pattern" in the thin-film electronic components ceramic substrate.

[2] Thin Film Electronic Component The thin film electronic component of the present invention includes the ceramic substrate for thin film electronic component of the present invention.
The above-mentioned “ceramic substrate for thin film electronic components” can be applied as it is the ceramic substrate for thin film electronic components of the present invention. The overall thickness of the ceramic substrate for thin film electronic components is not particularly limited, but is usually 200 to 2000 μm (preferably 300 to 1000 μm).
Examples of the thin film electronic component of the present invention include a thin film capacitor and an electronic component unit on which the thin film capacitor is mounted.

The electronic component includes a capacitor portion in which a capacitor conductor layer and a capacitor dielectric layer are laminated on a ceramic substrate for a thin film electronic component, and the capacitor portion is located between two opposing capacitor conductor layers. The conductor layers for capacitors and the dielectric layers for capacitors can be alternately stacked so that the dielectric layers for capacitors are disposed.
That is, a thin film capacitor and an electronic component unit on which the thin film capacitor is mounted.

The “capacitor portion” has a structure in which a capacitor conductor layer and a capacitor dielectric layer are laminated on a ceramic substrate for a thin film electronic component, and the capacitor dielectric layer is disposed between two opposing capacitor conductor layers. As shown, the capacitor conductor layers and the capacitor dielectric layers are alternately stacked (see FIG. 14).
The “capacitor conductor layer” is a conductor layer constituting the capacitor portion. This capacitor conductor layer is a conductive thin film facing through a capacitor dielectric layer, which will be described later, and may consist of only one layer or two or more layers. In general, the lowermost layer and the uppermost layer of the laminated portion of the capacitor conductor layer and the capacitor dielectric layer are capacitor conductor layers. The capacitor conductor layer only needs to have conductivity (for example, 10 μΩ · cm or less), and the material is not particularly limited. For example, platinum, gold, copper, silver, nickel, titanium, molybdenum, chromium, cobalt, and the like Tungsten or the like can be used. These materials may be used alone or in combination of two or more. Further, the shape and size of the capacitor conductor layer are not particularly limited, and the thickness thereof is not particularly limited, but is usually 1 μm or less. The thicknesses of these conductor layer materials and capacitor conductor layers are preferably selected as appropriate according to the desired resistance and productivity, and further according to the production cost.

The “capacitor dielectric layer” is a portion that constitutes a capacitor portion and insulates between the capacitor conductive layers. The capacitor dielectric layer only needs to have insulating properties (for example, 10 ¹⁰ Ω · m or more), and the material thereof is not particularly limited. For example, titanates (barium titanate, strontium titanate and lead titanate) Etc.), tantalum oxide, titanium oxide, and the like can be used. These materials may be used alone or in combination of two or more. Furthermore, when using 2 or more types, a mixture may be sufficient and a solid solution may be sufficient. Further, the shape and size of the capacitor dielectric layer are not particularly limited, and the thickness is not particularly limited, but is usually 1 μm or less. The thicknesses of these dielectric layer materials and capacitor dielectric layers depend on the desired electrostatic capacity, electrical characteristics such as insulation and withstand voltage, and productivity. It is preferable to select as appropriate.

Further, when the thin film electronic component of the present invention is manufactured, the method for forming the capacitor conductor layer is not particularly limited. For example, a sputtering method, a CVD method, a CSD method (Chemical Solution Deposition Method), etc. It can be formed using a thin film formation technique. If necessary, the obtained conductor layer can be patterned by etching or the like to form a capacitor conductor layer. A known photolithography method or the like can be used for etching.
Furthermore, the method for forming the capacitor dielectric layer is not particularly limited. For example, the CSD method is used. That is, this is a method of obtaining a capacitor dielectric layer by applying a dielectric material containing a metal element that will constitute the target capacitor dielectric layer to the formation surface and then heat-treating it. The dielectric material used in this CSD method is not particularly limited, but it is preferable to contain a metal organic compound containing a metal element constituting the target capacitor dielectric layer. As the organometallic compound, an alkoxide, an acetic acid compound, an oxalic acid compound, or the like can be used. Examples of the alkoxide include titanium alkoxides such as titanium isopropoxide, barium alkoxides obtained by dissolving metal barium in an alcohol-based organic solvent, and strontium alkoxides such as strontium-n-butoxide. These alkoxides may be polymerized by adding a predetermined amount of pure water. Examples of the alcohol organic solvent include a mixed solvent of ethanol and acetylacetone, 2-ethoxyethanol, and an alcohol organic solvent containing a chemical species capable of forming a chelate with a target metal species.
The dielectric material can be applied after being uniformed by heating or the like. Furthermore, the coating method of the dielectric material is not particularly limited, and for example, spin coating, dip coating, spray coating (including ink jet method and thermal method) and the like can be used. The obtained dielectric layer can be patterned by etching or the like as required to form a capacitor dielectric layer.

[3] Method for Producing Ceramic Substrate for Thin Film Electronic Component The method for obtaining the ceramic substrate for thin film electronic component of the present invention having an internal wiring pattern is not particularly limited, but can be obtained by the production method of the present invention. That is, in the ceramic substrate for thin film electronic components, since the base ceramic substrate is a ceramic substrate, when obtaining the unfired body, the unfired body is laminated and subjected to patterning and wiring formation on each layer, By baking, a substrate having a wiring pattern inside can be easily obtained. This is a great advantage over glass substrates and single crystal substrates. However, it is difficult to pattern the above glaze layer in an unsintered stage like the other ceramic layers. For this reason, it is necessary to manufacture using a special method. Hereafter, the manufacturing method of the ceramic substrate for thin film electronic components of this invention is demonstrated.

  A method for manufacturing a ceramic substrate for a thin film electronic component according to a first aspect of the present invention includes a resist layer forming step, a patterning step, an internal wiring pattern edge forming step, a resist layer removing step, and a glass layer forming step. The heating and pressurizing treatment step and the flattening polishing step are provided in this order.

The “resist layer forming step” is a step of forming a resist layer on the surface of the base ceramic substrate having the internal wiring pattern whose end face is exposed on the surface. This resist layer is a resist layer that prevents the formation of conductors in the internal wiring pattern edge forming step described later. Any resist may be used as the resist layer, but a photoresist is preferably used so that the resist layer described later can be easily removed.
The “patterning step” is a step of patterning the resist layer formed in the resist layer forming step to form a patterning hole leading to the end face of the internal wiring pattern. This patterning may be performed by any means, but is usually performed by photolithography. That is, for example, by placing a mask on the surface of the resist layer, exposing so that unnecessary portions (portions to be removed after the patterning step) are exposed, and then removing unnecessary portions that are not cured. Can do.

The “internal wiring pattern end forming step” is a step of filling the patterning hole with a conductive material to form the internal wiring pattern end connected to the end face of the internal wiring pattern. The method of forming the end portion of the internal wiring pattern (hereinafter also simply referred to as “end pattern”) is not particularly limited. For example, it can be formed using an electrolytic plating method and an electroless plating method. That is, when one end side is exposed on the surface of the base ceramic substrate and the other end side is exposed anywhere on the base ceramic substrate, electrolytic plating can be performed using both ends of the internal wiring pattern. it can. In the case of having a plurality of internal wiring patterns, an end pattern can be formed at a time by short-circuiting them. Further, when the other end side of the internal wiring pattern is not exposed from the surface of the base ceramic substrate, the end pattern can be formed by using an electroless plating method.
The “resist layer removing step” is a step of removing the patterned resist layer. Since the resist layer is a resist layer necessary for forming the end pattern as described above, it can be removed after the end pattern is formed. The removing means and the like are not particularly limited, and when the above-described photoresist is used, it can be removed by using a predetermined stripping solution.

The “glass layer forming step” is a step of forming a glass layer on the surface of the base ceramic substrate so that at least a part of the end pattern is buried. When the resist layer is removed in the resist layer removing step, the end pattern formed in the patterning hole in the resist layer protrudes from the surface of the base ceramic substrate. For example, the glass layer can be formed by applying a glass paste so that at least a part of the projected end pattern is buried and baking it. However, the end pattern may be entirely buried in the glass layer, or only a part may be buried. For the method for forming the glass layer and the like, the method for the ceramic substrate for thin film electronic components according to the present invention can be applied as it is.
The “heat-pressing treatment step” is a step of performing a heat-pressing treatment to form a glaze layer on the surface of the base ceramic substrate. About this heat pressurization process, the heat pressurization process in the ceramic substrate for thin film electronic components which concerns on the said invention can be applied as it is.
The “flattening polishing step” is a step of flatly polishing the surface of the glaze layer formed in the heating and pressing step to expose the end pattern. However, when the edge pattern is not completely buried in the glass layer forming process as described above, the edge pattern is already exposed before the planarization polishing, but the edge pattern is not removed even after the planarization polishing. Exposed. As for the flattening polishing, the flattening polishing in the ceramic substrate for thin film electronic components according to the present invention can be applied as it is.

  Moreover, the manufacturing method of the ceramic substrate for thin film electronic components which concerns on the 2nd viewpoint of this invention consists of a glass layer formation process, a heat-and-press treatment process, a resist layer formation process, a patterning process, an etching process, and a resist. A layer removing step, an internal wiring pattern end forming step, and a planarization polishing step are provided in this order.

The “glass layer forming step” is a step of forming a glass layer on the surface of the base ceramic substrate having the internal wiring pattern with the end face exposed on the surface. In this step, the same step in the manufacturing method according to the first aspect can be applied as it is, except that the end pattern is not formed on the surface of the base ceramic substrate that is the coated surface.
The “heat-pressing treatment step” is a step of applying a heat-pressing treatment to form a glaze layer on the base ceramic substrate. For this step, the same step in the production method according to the first aspect can be applied as it is, except that the glass layer to be heated and pressurized does not have an end pattern.
The “resist layer forming step” is a step of forming a resist layer on the glaze layer. This process can be applied as it is in the manufacturing method according to the first aspect except that the end face of the internal wiring pattern is not exposed on the formation surface.
The “patterning step” is a step of patterning the resist layer to form a patterning hole that leads to the end face of the internal wiring pattern. “To be connected to the end face of the internal wiring pattern” means that the patterning hole is connected to the end face of the internal wiring pattern exposed on the surface of the base ceramic substrate through the etching hole through an etching process described later. Means that. The same process in the manufacturing method according to the first aspect can be applied as it is, except that this patterning does not directly connect to the end face of the internal wiring pattern.

The “etching step” is a step of etching the glaze layer from the patterning hole to form an etching hole leading to the end face of the internal wiring pattern. The chemicals and conditions used for etching are not particularly limited and are preferably selected as appropriate depending on the glass constituting the glaze layer. For example, the glaze layer can be etched by using a hydrofluoric acid-based etchant.
The “resist layer removing step” is a step of removing the patterned resist layer, and the “internal wiring pattern end forming step” is a process of filling the etching hole with a conductive material to form an end surface of the internal wiring pattern. And forming an end pattern connected to the.
The “planarization polishing step” is a step of polishing the surface of the glaze layer to expose the end portions of the internal wiring pattern. This step can be applied as it is in the manufacturing method according to the first aspect, except that the end pattern is already exposed from the surface of the glaze layer before the flattening polishing.

Hereinafter, the present invention will be described specifically by way of examples.
[1] Fabrication of ceramic substrate for thin-film electronic components (without internal wiring pattern)
(1) Fabrication of ceramic substrate for base part Alumina powder (Al ₂ O ₃ purity 90% or more) having an average particle diameter of 3 to 5 μm, and flux powder (baked) containing Al ₂ O ₃ , SiO ₂ and CaO as main components When the total mixed powder is 100% by mass, the mixed powder is obtained by mixing so that the alumina powder is 90 to 95% by mass and the flux powder is 5 to 10% by mass. . A slurry obtained using this mixed powder was formed into a sheet shape having a thickness of 200 μm by a doctor blade method, and then cut into a desired size to obtain an unfired sheet. Three green sheets were laminated to obtain a green ceramic sheet for base having a thickness of 600 μm. The base unfired ceramic sheet was fired to obtain a base ceramic substrate. When the surface roughness of the base ceramic substrate was measured using a stylus type surface roughness meter (manufactured by Tokyo Seimitsu Co., Ltd., model “SURFCOM 1400D”), Ra was 0.24 μm and Ry was 5.7 μm. Met. FIG. 6 shows an image obtained by magnifying the surface of the base ceramic substrate that was not flattened and polished by 200 times, and FIG. 7 shows an image obtained by magnifying the surface by 2000 times.

  Thereafter, the surface of the obtained base ceramic substrate was polished to be flat and flattened. When the surface roughness of the polished base ceramic substrate was measured in the same manner, Ra was 0.078 μm and Ry was 0.97 μm. An image obtained by enlarging the surface of the base ceramic substrate subjected to this polishing 200 times is shown in FIG. 8, and an image obtained by enlarging 2000 times is shown in FIG.

(2) Formation of glaze layer After dissolving acrylic resin (binder) in terpineol (solvent), glass powder was mixed to obtain a glass paste. In the glass powder, each of Si, B, Al, and Ca is converted into SiO ₂ , B ₂ O ₃ , Al ₂ O _3, and CaO, where the total amount is 100 mol%, Si is 55 to 65 mol%, A glass powder having an average particle diameter of about 3 μm and containing 15 to 25 mol% B, 5 to 15 mol% Al, and 5 to 15 mol% Ca was used. This glass paste was applied onto a base ceramic substrate by screen printing, dried, and then baked at 1000 ° C. in an air atmosphere.
When the surface roughness of the glass layer after baking was measured in the same manner after polishing, Ra was 0.60 μm and Ry was 13.0 μm. An image obtained by enlarging the glass layer surface 200 times is shown in FIG. 10, and an image obtained by enlarging 2000 times is shown in FIG.

Then, the ceramic substrate for base | substrates in which the glass layer was formed was mounted in the HIP furnace, the temperature in the furnace was raised to 800 degreeC without pressurizing, and the glass layer was fully softened. Thereafter, the pressure was increased from 800 ° C. to 5 MPa in a nitrogen atmosphere, the furnace temperature was increased to 950 ° C., and the heat and pressure treatment was performed for 15 minutes.
Thereafter, the base ceramic substrate on which the glaze layer was formed was taken out of the HIP furnace and flattened and polished. The flattening polishing was performed by mechanical polishing using a diamond paste. Further, as the diamond paste used, different diamond pastes were used so that the diameter of the diamond abrasive grains in the paste gradually decreased, and the last diamond paste having an average particle diameter of 2 μm or less was used.
When the surface roughness of the obtained glaze layer after flattening polishing was measured using the stylus type surface roughness meter, Ra was 0.0079 μm and Ry was 0.18 μm. Further, FIG. 12 shows an image obtained by enlarging the surface of the glaze layer subjected to the flattening polishing 200 times, and FIG. 13 shows an image obtained by enlarging it 2000 times.

(3) Evaluation From this result, the surface of the base ceramic substrate has a Ra of 0.24 μm and a large Ry of 5.7 μm. Further, even if this base ceramic substrate was polished, the surface roughness could be improved only to Ra of 0.078 μm and Ry of 0.97 μm. 6 to 9, it is understood that the surface roughness of the base ceramic substrate cannot be sufficiently reduced due to pores observed on the surface. The surface roughness of the flattened and polished surface of the glass layer not subjected to the heat and pressure treatment was Ra of 0.6 μm and Ry of 13.0 μm. That is, it can be seen that the surface roughness is lower than the polished surface of the base ceramic substrate. 10 and 11 also show that the number of pores is greatly reduced by the formation of the glass layer. However, pores larger than those seen in FIG. 8 are seen in FIG. That is, it can be seen that the surface roughness cannot be sufficiently reduced because the large pores are formed.

On the other hand, the surface flattened and polished after the heat and pressure treatment according to the present invention had Ra of 0.0079 μm and Ry of 0.18 μm. That is, both Ra and Ry are reduced by 97% from the surface of the base ceramic substrate. Moreover, Ra is reduced by 90% and Ry is reduced by 81% even from the surface of the base ceramic substrate that has been flattened and polished. Furthermore, both Ra and Ry are reduced by 99% from the surface of the glaze layer that has not been subjected to the heat and pressure treatment that has been flattened and polished. It can also be seen that no pores are observed in FIGS.
That is, according to the present invention, it is understood that the surface roughness can be reduced by at least 81% even when a general-purpose ceramic substrate having many pores is used.

[2] Fabrication of ceramic substrate for thin film electronic component having wiring pattern 1
Hereinafter, the production of the ceramic substrate (1) for a thin film electronic component having the wiring pattern (21) shown in FIG. 1 will be described with reference to FIGS. However, FIG. 2 is a process following FIG.
(1) Production of Base Ceramic Substrate (2) In the same manner as in the above [1] (1), an unfired ceramic sheet for base having a thickness of 600 μm was obtained. A via hole having a diameter of 120 μm (a diameter after firing of 100 μm) was formed on the obtained unfired ceramic sheet for base using a CO ₂ laser. Next, a conductive filler (mainly an internal wiring pattern after firing) containing tungsten powder, ethyl cellulose (binder) and butyl carbitol (solvent) as main components was prepared, and printed and filled in the previously formed via holes. Thereafter, the green body thus obtained was cut into a desired size and then fired to obtain a base ceramic substrate (2) having an internal wiring pattern (211) penetrating the front and back.

(2) Resist layer forming step and patterning step A photosensitive resist is spin-coated on the surface of the base ceramic substrate (2) obtained in (1) above to form a photoresist layer (22) having a thickness of 50 μm. did. Thereafter, a photomask obtained by inverting the pattern of the internal wiring pattern (211) in the base ceramic substrate (2) was placed on the photoresist layer (22) and irradiated with ultraviolet rays. Subsequently, the part which was not hardened with a developing solution was removed, and the patterning hole (221) was formed. The end face of the internal wiring pattern was exposed at the bottom of the patterning hole (221).

(3) Internal wiring pattern edge forming step and resist layer removing step All internal wiring patterns (211) exposed on the back side of the base ceramic substrate (2) are short-circuited and immersed in an electrolytic plating bath. In the patterning hole (221) formed in (2), an end pattern (212) made of copper was deposited to a thickness of about 50 μm (a thickness similar to that of the photoresist layer). Thereafter, the unnecessary photoresist layer (22) was completely removed with a solvent. As a result, the end pattern (212) formed in the internal wiring pattern end forming step protruded from the surface of the base ceramic substrate (2).

(4) Glass layer forming step, heating and pressurizing step, and flattening polishing step The glass paste obtained in the same manner as in the above [1] (2) is applied on the base ceramic substrate (2) and dried. A glass paste layer (23) made of a glass paste having a dry thickness of 250 μm was formed. Then, this glass paste layer (23) was baked at 1000 ° C. in a non-oxidizing atmosphere composed of N ₂ —H ₂ —H ₂ O to form a glass layer (24) having a thickness of 100 μm. Subsequently, the glaze layer (3) was formed by HIP treatment in the same manner as in the above [1] (2). Thereafter, planarization polishing is performed in the same manner as in the above [1] (2), the wiring pattern (21) of the present invention is provided, and a glaze layer (3) having a surface roughness Ra of 0.01 μm or less and Ry 0.2 μm or less is provided. A ceramic substrate (1) for thin-film electronic components was obtained.

[3] Fabrication of ceramic substrate for thin film electronic component having wiring pattern 2
Hereinafter, the production of a ceramic substrate for a thin film electronic component having a wiring pattern (21) will be described with reference to FIGS. However, FIG. 4 is a process following FIG.
(1) Production of Base Ceramic Substrate (2) A base ceramic substrate (2) having an internal wiring pattern (211) penetrating front and back was obtained in the same manner as in [2] (1) above.
(2) Glass layer forming step and heating and pressing step The glass paste obtained in the same manner as in [1] and (2) above is applied on the base ceramic substrate (2), dried, and dried at a thickness of 250 μm. A glass paste layer (23) made of glass paste was formed. Thereafter, this glass paste layer (23) was baked in the same manner as in the above [2] (4) to form a glass layer (24). Subsequently, the glaze layer (3) was formed by HIP treatment in the same manner as in the above [1] (2).

(3) Resist layer forming step and patterning step A photoresist layer (22) was formed on the surface of the base ceramic substrate (2) obtained in (2) in the same manner as in [2] (2) above. (However, the thickness of the photoresist layer was several μm). Further, a patterning hole (221) was formed in the same manner. The glaze layer (3) was exposed at the bottom in the patterning hole (221).

(4) Etching process and resist layer removing process Using the patterning hole (221) formed in (3) above, the glaze layer (3) is patterned in the glaze layer (3) using hydrofluoric acid. Etching holes (31) leading from (221) to the surface of the base ceramic substrate (2) were formed. The end face of the internal wiring pattern (211) was exposed at the bottom of the etching hole (31). Thereafter, the unnecessary photoresist layer (22) was completely removed with acetone.

(5) Internal wiring pattern edge forming step and planarization polishing step All internal wiring patterns (211) exposed on the back side of the base ceramic substrate (2) obtained up to (4) above are short-circuited, An end pattern (212) made of copper was deposited in the etching hole (31) previously formed by dipping in an electrolytic plating bath. Thereafter, planarization polishing is performed in the same manner as in the above [1] (2), the wiring pattern (21) of the present invention is provided, and a glaze layer (3) having a surface roughness Ra of 0.01 μm or less and Ry 0.2 μm or less is provided. A ceramic substrate (1) for thin-film electronic components was obtained.

[4] Fabrication of thin-film electronic components (fabrication of thin-film capacitors)
Hereinafter, the production of the thin film capacitor 100 will be described with reference to FIGS. 15 to 17 illustrate the right half of the thin layer capacitor 100 of FIG. Moreover, the code | symbol before and behind baking was made the same for convenience. Refer to FIG. 15 for the following (1-a) to (1-d), refer to FIG. 16 for the following (1-e) to (1-i), and (1-j) to (1-m) below. See FIG.

(1-a) A capacitor conductor layer (4) made of 0.2 μm platinum was formed on one surface of the ceramic substrate (1) for thin film electronic components obtained in [2] above by sputtering. The capacitor conductor layer (4) mainly serves as a lower electrode in the capacitor.
(1-b) Next, in order to pattern the capacitor conductor layer (4), an etching resist (5) was formed on a portion of the capacitor conductor layer that does not require etching.
(1-c) Thereafter, etching was performed using ion milling to pattern the capacitor conductor layer (4), and then the etching resist (5) was removed.
(1-d) Next, a capacitor conductor layer obtained by patterning a dielectric material (6) obtained by dissolving titanium isopropoxide, strontium-n-butoxide, and metal barium in 2-ethoxyethanol. The substrate surface having (4) was spin coated. Thereafter, the applied dielectric material (6) was dried and then heat-treated at 700 ° C. to obtain a capacitor dielectric layer (6) having a thickness of 0.2 μm.
(1-e) In order to pattern the obtained capacitor dielectric layer (6), an etching resist (7) was formed on a portion of the capacitor dielectric layer that did not require etching.

(1-f) Thereafter, the capacitor dielectric layer (6) is etched using buffered hydrofluoric acid to pattern the capacitor dielectric layer (6), and then the etching resist (7) is removed. did.
(1-g) Next, a capacitor conductor layer (8) made of platinum having a thickness of 0.2 μm was formed on the surface of the patterned capacitor dielectric layer (6) by sputtering. The capacitor conductor layer (8) mainly serves as an upper electrode in the capacitor.
(1-h) Thereafter, in order to pattern the capacitor conductor layer (8), the portion of the capacitor conductor layer that does not require etching (the back side of the ceramic substrate for thin film electronic components on the side where the capacitor portion is not formed is also etched). An etching resist (9) was formed on the resist).
(1-i) Next, etching was performed using ion milling to pattern the capacitor conductor layer (8), and then the etching resist (9) was removed.

(1-j) Thereafter, a solder resist layer (10) was formed.
(1-k) Next, the solder resist layer (10) was patterned (the surface of the via conductor was exposed by this patterning).
(1-l) Thereafter, a nickel-gold plating layer (11) was formed on the surface of the via conductor (21) expressed in (1-k) above by electroless plating.
(1-m) Next, solder balls (12) were formed on the surface of the nickel-gold plating layer (11) formed in the above (1-1) to obtain a thin film capacitor (100).

[5] Manufacture of thin film electronic components 2 (Manufacture of thin film capacitors 2)
Hereinafter, production of a thin film electronic component (101) different from the above [4] (production of a thin film capacitor) will be described with reference to FIGS. However, FIG. 18 is the process following FIG. 19, FIG. 19 is the process following FIG. 20, FIG. 20 is the process following FIG. 21, FIG. 21 is the process following FIG. In this method, as the ceramic substrate for thin film electronic components, a method corresponding to Production 1 of the ceramic substrate for thin film electronic components having the wiring pattern [2] is used.

(1) Formation and patterning of connection pattern resist layer The surface of the base ceramic substrate (2) obtained in the same manner as in [2] (1) above is spin-coated with a photosensitive resist to form a photoresist layer (22b ) Was formed. Thereafter, a photomask obtained by inverting the pattern of the internal wiring pattern (211) in the base ceramic substrate (2) was placed on the photoresist layer (22b) and irradiated with ultraviolet rays. Next, the portion that was not cured by the developer was removed to form a patterning hole (221b). The end face of the internal wiring pattern is exposed at the bottom in the patterning hole (221b), and the diameter of the patterning hole (221b) is formed larger than the diameter of the internal wiring pattern.

(2) Connection pattern formation step The lower connection pattern (213) made of titanium was deposited by sputtering in the patterning hole (221b) on the surface side of the base ceramic substrate (2). Next, an upper connection pattern (214) made of copper was further deposited.

(3) Connection Pattern Resist Layer Removal Step The photoresist layer (22b) that became unnecessary after performing the above (2) was completely removed with a stripping solution.

(4) Short-Circuit Layer on Back Side of Base Ceramic Substrate A lower short-circuit layer (215) made of titanium was deposited on the back side of the base ceramic substrate by sputtering. Next, an upper short-circuit layer (216) made of copper was further deposited to short-circuit the internal wiring pattern (211) exposed from the back side of the base ceramic substrate.

(5) Resist layer forming step and patterning step On the surface of the base ceramic substrate (2) obtained in (4) above, a photosensitive resist is spin-coated to form a photoresist layer (22a) having a thickness of 50 μm. did. Thereafter, a photomask obtained by inverting the pattern of the internal wiring pattern (211) in the base ceramic substrate (2) was placed on the photoresist layer (22a) and irradiated with ultraviolet rays. Next, the portion that was not cured by the developer was removed to form a patterning hole (221a). The end face of the connection pattern (upper connection pattern and lower connection pattern) was exposed at the bottom of the patterning hole (221a).

(6) Internal wiring pattern edge forming step Using the internal wiring pattern (211) short-circuited in (4) above, the base ceramic substrate (2) is immersed in an electrolytic plating bath, and in (5) above In the formed patterning hole (221a), an end pattern (212) made of copper was deposited to a thickness of about 50 μm (a thickness similar to that of the photoresist layer).

(7) Removal of resist layer and short-circuit layer The photoresist layer (22a) that became unnecessary after the above (6) was completely removed with a stripping solution. As a result, the end pattern (212) formed in the internal wiring pattern end forming step protruded from the surface of the base ceramic substrate (2). On the other hand, the short-circuit layer on the back side formed in the above (4) was removed by polishing.

(8) Glass paste application step and baking step The glass paste obtained in the same manner as in the above [1] (2) is applied in the same manner, dried, and the surface side made of glass paste having a dry thickness of 250 μm on the surface side A glass paste layer was formed, and a back side glass paste layer made of glass paste having a dry thickness of 100 μm was formed on the back side. Then, these glass paste layers were baked and vitrified at 1000 ° C. in a non-oxidizing atmosphere composed of N ₂ —H ₂ —H ₂ O, and a surface side glass layer (24a) having a thickness of 100 μm and a back surface having a thickness of 40 μm. A side glass layer (24b) was formed.

(9) Heating and pressing step HIP treatment was performed in the same manner as in the above [1] and (2) to form the front side glaze layer (3a) and the back side glaze layer (3b).

(10) Flattening and polishing step Flattening and polishing are performed in the same manner as in the above [1] and (2), the wiring pattern (21) of the present invention is exposed (exposed on the surface), the surface roughness Ra is 0.01 μm or less, and Ry0. A ceramic substrate (1) for a thin film electronic component having a surface side glaze layer (3a) of 2 μm or less was obtained.

(11) Capacitor conductor layer forming step On the surface side of the ceramic substrate for thin film electronic components (1) obtained in (10) above, a capacitor conductor lower layer (4b) made of 0.02 μm tantalum was formed by sputtering. . Thereafter, a capacitor conductor upper layer (4a) made of 0.2 μm platinum was formed by sputtering. That is, the capacitor conductor layer (4) includes a capacitor conductor lower layer (4b) and a capacitor conductor upper layer (4a).

(12) Step of forming resist layer for patterning capacitor conductor layer In order to pattern the capacitor conductor layer (4) formed in the above (11), an etching resist is applied to a portion of the capacitor conductor layer that does not require etching. (5) was formed.

(13) Patterning process of capacitor conductor layer Etching was performed using ion milling to pattern the capacitor conductor layer (4).

(14) Step of removing resist layer for patterning of conductor layer for capacitor The etching resist (5) used in the above (13) was removed.

(15) Step of forming SiO ₂ layer On the capacitor conductor layer patterned in the above (14), a layer of SiO ₂ (13) was formed using a plasma CVD method.

(16) Capacitor conductor layer forming step In the same manner as in (11) above, a capacitor conductor layer (8) comprising a capacitor conductor lower layer (8b) made of tantalum and a capacitor conductor upper layer (8a) made of platinum. Formed.

(17) Step of forming resist layer for patterning capacitor conductor layer In order to pattern the capacitor conductor layer (8) formed in (17) in the same manner as in the above (12), the capacitor conductor layer An etching resist (9) was formed in a portion that did not require the etching.

(18) Capacitor conductor layer patterning step The capacitor conductor layer (8) formed in the above (17) is etched using ion milling in the same manner as in the above (13) to obtain a capacitor conductor layer ( The patterning of 8) was performed.

(19) Step of removing resist layer for patterning of conductor layer for capacitor The etching resist (9) used in the above (13) was removed.

(20) Formation of Dielectric Layer for Capacitor A capacitor obtained by patterning a dielectric material (6) obtained by dissolving titanium isopropoxide, strontium-n-butoxide, and barium metal in 2-ethoxyethanol The substrate surface having the conductive layer (8) was spin coated. Thereafter, the applied dielectric material (6) was dried and then heat-treated at 700 ° C. to obtain a capacitor dielectric layer (6) having a thickness of 0.2 μm.

(21) Step of forming resist layer for patterning of SiO ₂ layer and capacitor dielectric layer SiO ₂ layer (13) obtained in (15) and capacitor dielectric layer (6) obtained in (20) above ) Was patterned, an etching resist (7) was formed on the portion of the capacitor dielectric layer that did not require etching.

(22) the SiO ₂ layer (13) and a dielectric layer for a capacitor (6) is etched using the patterned buffered hydrofluoric acid of the SiO ₂ layer and the capacitor dielectric layer, performing a patterning each layer It was. In addition, this patterning process can also be performed by the ion milling method.

(23) after passing through the SiO ₂ layer and the resist layer removing step above for patterning the capacitor dielectric layer (22), removing the resist layer for patterning the SiO ₂ layer and the capacitor dielectric layer.

(24) Resist Layer Forming Step for Forming Capacitor Dielectric Layer Resist for Protecting Portion which Does Not Need to Form Capacitor Conductor Layer (14), which will be described later, on the Surface Side of the Base Ceramic Substrate that has Passed (23) Layer (15) was formed.

(25) Capacitor Conductor Layer Formation Step A capacitor conductor upper layer (14) made of platinum was formed on the surface side of the base ceramic substrate having undergone the above (24).

(26) Step of removing resist layer for forming conductor layer for capacitor The conductor layer for capacitor (14) was patterned by removing the resist layer (15) used in (25) above.

(27) Backside glaze layer removal step After protecting the thin film laminate on the front side with a protective tape (not shown), the backside glaze layer (3b) formed in (9) above is the same as (10) above Then, polishing was performed to remove the wiring pattern (221) from the back surface.

(28) Resist layer formation for solder ball connection pattern In order to form a solder ball connection pattern (17) for improving the connectivity of the solder ball (12) on the back side, which will be described later, in the same manner as (1) above. The resist layer (16) was formed.

(29) Solder ball connection pattern forming step A connection pattern (17) made of platinum was deposited by sputtering on the back side of the base ceramic substrate having undergone the above (28).

(30) Resist layer removal process for solder ball connection pattern The resist layer (16) which became unnecessary after performing the above (29) was completely removed with a solvent.

(31) Solder resist layer forming step After peeling off the protective tape formed in the above (27), the portion that does not require the formation of solder balls on the surface side of the base ceramic substrate through the above (30) is selectively formed by patterning. A solder resist layer (10) was removed. Incidentally, on the back surface side, the exposed portion exposed by polishing and removing the glaze layer (3b) in the above (27) and not covered with the solder ball connection pattern (17) in the above (29) is the solder. Functions as a resist. For this reason, it is not necessary to form the same solder resist layer as the surface side.

(32) Solder ball forming step The portion of the base ceramic substrate that has undergone the above (31) where the resist layer (10) is not formed, the surface of the solder ball connection pattern (17) on the back side, and solder A ball (12) was formed to obtain a thin film capacitor (101).

  The present invention can be widely used in the field of electronic components. The ceramic substrate for a thin film electronic component of the present invention is used as any substrate including a thin film electronic component (such as a thin film capacitor), and is particularly suitable for a capacitor of a wiring built-in substrate. Further, the thin film electronic component of the present invention is suitably used as a thin film capacitor and a wiring board provided with the thin film capacitor.

It is sectional drawing which shows typically the cross section of the ceramic substrate for thin film electronic components of this invention. It is explanatory drawing which shows typically the manufacturing process of an example of the ceramic substrate for thin film electronic components of this invention. It is explanatory drawing which shows typically the manufacturing process of an example of the ceramic substrate for thin film electronic components of this invention. It is explanatory drawing which shows typically the manufacturing process of the other example of the ceramic substrate for thin film electronic components of this invention. It is explanatory drawing which shows typically the manufacturing process of the other example of the ceramic substrate for thin film electronic components of this invention. It is a 200 times magnified image of the ceramic substrate surface for bases which has not performed planarization grinding | polishing. It is a 2000 times enlarged image of the ceramic substrate surface for bases which has not performed planarization grinding | polishing. It is a 200 times enlarged image of the ceramic substrate surface for bases after planarization grinding | polishing. It is 2000 times enlarged image of the ceramic substrate surface for bases after planarization grinding | polishing. It is a 200 times enlarged image of the glass layer surface after planarization grinding | polishing. It is a 2000 times enlarged image of the glass layer surface after planarization grinding | polishing. It is a 200 times enlarged image of the glaze layer surface after planarization grinding | polishing. It is a 2000 times enlarged image of the glaze layer surface after planarization grinding | polishing. It is sectional drawing which shows typically the cross section of the thin film electronic component (thin film capacitor) of this invention. It is explanatory drawing which shows typically the manufacturing process of the thin film capacitor of this invention. It is explanatory drawing which shows typically the manufacturing process of the thin film capacitor of this invention. It is explanatory drawing which shows typically the manufacturing process of the thin film capacitor of this invention. It is explanatory drawing which shows typically the manufacturing process of the thin film capacitor of this invention. It is explanatory drawing which shows typically the manufacturing process of the thin film capacitor of this invention. It is explanatory drawing which shows typically the manufacturing process of the thin film capacitor of this invention. It is explanatory drawing which shows typically the manufacturing process of the thin film capacitor of this invention. It is explanatory drawing which shows typically the manufacturing process of the thin film capacitor of this invention. It is explanatory drawing which shows typically the manufacturing process of the thin film capacitor of this invention. It is explanatory drawing which shows typically the manufacturing process of the thin film capacitor of this invention.

Explanation of symbols

1; Ceramic substrate for thin-film electronic components, 2; Ceramic substrate for base, 21; Wiring pattern (via conductor), 211; Internal wiring pattern, 212; End of internal wiring pattern, 213; Lower connection pattern, 214; , Lower shorting layer (215), upper shorting layer (216), 22 and 22a; photoresist layer, 221 and 221a; patterning hole, 22b; resist layer for connection pattern, 221b; patterning hole for connection pattern, 23; Glass paste layer, 24; Glass layer, 24a; Front side glass layer, 24b; Back side glass layer, 241; Void (pore), 3; Glaze layer, 3a; Front side glaze layer, 3b; Back side glaze layer, 31 Etching hole, 100 and 101; Thin film capacitor (thin film electronic component), 4; Capacitor conductor layer, 5; Etching resist (for conductor layer), 6; Capacitor dielectric layer (dielectric material), 7; Etching resist (dielectric Layer for), 8; conductor layer capacitor, 9; for an etching resist (conductor layer) 10; the solder resist layer, 11; nickel - gold plating layer, 12; solder balls, 13; SiO ₂ layer, 14; capacitors Conductor layer, 15; resist layer, 16; resist layer for connection pattern, 17: connection pattern.

Claims (8)

A ceramic substrate for a thin film electronic component comprising: a base ceramic substrate; and a glaze layer formed on at least one side of the base ceramic substrate,
The glass layer formed on the surface of the base ceramic substrate is heated and pressurized to form a glaze layer on the base ceramic substrate, and the surface of the glaze layer is planarized and polished.
The heating temperature in the heating and pressing treatment is 750 to 1000 ° C., the pressing pressure is 0.5 to 200 MPa,
Arithmetic average roughness Ra of the surface of the glaze layer is less than 0.02 [mu] m, and the maximum height Ry is I der 0.25μm or less,
A ceramic substrate for a thin film electronic component, wherein the glaze layer does not have a pore .   The ceramic substrate for a thin film electronic component according to claim 1, wherein the glaze layer has a thickness of 10 to 100 μm. The ceramic substrate for thin film electronic components according to claim 1 or 2 , wherein the glass constituting the glaze layer is mainly composed of Si, Al, B, Ca and O. The ceramic substrate for thin film electronic components according to any one of claims 1 to 3 , comprising a wiring pattern therein. A thin film electronic component comprising the ceramic substrate for a thin film electronic component according to any one of claims 1 to 4 . A capacitor portion is formed by laminating a capacitor conductor layer and a capacitor dielectric layer on the ceramic substrate for thin film electronic components, and the capacitor portion is disposed between the two opposing capacitor conductor layers. 6. The thin film electronic component according to claim 5 , wherein the capacitor conductor layers and the capacitor dielectric layers are alternately laminated so that the dielectric layers are disposed. A base ceramic substrate, and a glaze layer formed on at least one side of the base ceramic substrate,
The glass layer formed on the surface of the base ceramic substrate is heated and pressurized to form a glaze layer on the base ceramic substrate, and the surface of the glaze layer is planarized and polished.
The arithmetic average roughness Ra of the surface of the glaze layer is 0.02 μm or less, and the maximum height Ry is 0.25 μm or less,
A method of manufacturing a ceramic substrate for a thin film electronic component comprising a wiring pattern therein ,
A resist layer forming step of forming a resist layer on the surface of the base ceramic substrate having an internal wiring pattern with an end face exposed on the surface;
Patterning the resist layer to form a patterning hole leading to the end face of the internal wiring pattern; and
An internal wiring pattern end forming step of filling the patterning hole with a conductive material to form an internal wiring pattern end connected to the end face of the internal wiring pattern;
A resist layer removing step of removing the patterned resist layer;
So that at least a portion of the internal wiring pattern end portion is buried, the glass layer forming step of forming the glass layer on the surface of the ceramic substrate for the base portion,
Subjected to heat and pressure treatment, a heating and pressurizing treatment step of forming the glaze layer on the surface of the ceramic substrate for the base portion,
A method for producing a ceramic substrate for a thin-film electronic component, comprising: a planarizing and polishing step for polishing the surface of the glaze layer flatly to expose an end portion of the internal wiring pattern. A base ceramic substrate, and a glaze layer formed on at least one side of the base ceramic substrate,
The glass layer formed on the surface of the base ceramic substrate is heated and pressurized to form a glaze layer on the base ceramic substrate, and the surface of the glaze layer is planarized and polished.
The arithmetic average roughness Ra of the surface of the glaze layer is 0.02 μm or less, and the maximum height Ry is 0.25 μm or less,
A method of manufacturing a ceramic substrate for a thin film electronic component comprising a wiring pattern therein ,
A glass layer forming step of forming the glass layer on the surface of the ceramic substrate for the base comprising an internal wiring pattern end surface is exposed on the surface,
Subjected to heat and pressure treatment, a heating and pressurizing treatment step of forming the glaze layer on a ceramic substrate for the base portion,
A resist layer forming step of forming a resist layer on the glaze layer;
Patterning the resist layer to form a patterning hole that leads to the end face of the internal wiring pattern; and
An etching step of etching the glaze layer from the patterning hole to form an etching hole leading to the end face of the internal wiring pattern;
A resist layer removing step for removing the patterned resist layer, and an internal wiring that fills the etching hole with a conductive material to form an end portion of the internal wiring pattern connected to the end face of the internal wiring pattern A pattern edge forming step;
A method for producing a ceramic substrate for a thin-film electronic component, comprising: a planarizing and polishing step for polishing the surface of the glaze layer flatly to expose an end portion of the internal wiring pattern.