JP4619288B2 - データ処理システムにおける処理動作マスキング - Google Patents
データ処理システムにおける処理動作マスキング Download PDFInfo
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
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- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
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- G06F9/3875—Pipelining a single stage, e.g. superpipelining
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- G09C1/00—Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system
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Description
EP-A-1,1,158,384が開示しているプロセッサパイプラインでは、ランダムに選ばれたコードシーケンスがレジスタに書き込み中のこれらのシーケンスに対する結果と共に命令パイプラインに挿入される。これらはプロセッサの状態を変えない。
結果データ値を発生するデータ処理命令を実行するプロセッサコア(4)と、
結果データが書き込まれるプロセッサコアの状態を定義するデータ値を保持するデータ処理レジスタ(12)とを含み、
プロセッサコアにより実行される少なくとも1個のデータ処理命令が条件付きコード(26)を符号化する条件付き書き込みデータ処理命令であり、条件付きコードは、プロセッサコアの状態の変化をもたらすために、条件付き書き込みデータ処理命令がデータを書き込むのを許可するか否かという条件を特定し、
さらに、条件付き書き込みデータ処理命令の中の条件コードが、プロセッサコアの状態の変化をもたらすための書き込みを許さないとき、条件付き書き込みデータ処理命令の実行時にデータ処理レジスタの替わりに結果データ値を書き込むことができるトラッシュレジスタ(51)を含む、データ処理装置である。
データ処理命令のプロセッサコア(4)による実行時に結果データ値を発生するステップを含み、該ステップは実行される少なくとも1個のデータ処理命令が条件付きコード(26)を符号化する条件付き書き込みデータ処理命令であり、条件付きコードは、プロセッサコアの状態の変化をもたらすために、条件付き書き込みデータ処理命令がデータを書き込むのを許可するか否かという条件を特定し、
さらに、条件付き書き込みデータ処理命令の中の条件コードが、プロセッサコアの状態の変化をもたらすための書き込みを許さないとき、プロセッサコアの状態を定義するデータ値を保持するデータ処理レジスタに結果データ値が書き込まれず、替わりにトラッシュレジスタ(51)に結果データ値が書き込まれる、データ処理方法である。
図1はプロセッサコア4、コプロセッサ6およびメモリ8を含むデータ処理システム2を示す。
動作時に、プロセッサコア4はメモリ8から命令とデータとを取込む。命令は命令パイプライン10に送られ、そこで命令は例えば、取込み、デコード、実行、記憶およびライトバックのようなパイプラインステージを、連続的な処理サイクルで次々と実行する。パイプライン式のプロセッサ自体は、処理性能を改善するために、部分的にオーバーラップしながらいくつかのプログラムの命令を効率的に実行する方法としてよく知られている。
Claims (8)
- データ処理装置において、
データ処理命令を実行して結果データ値を発生するプロセッサコア(4)と、
前記結果データ値が書き込まれるデータ処理レジスタ(12)であって、前記プロセッサコアの状態はデータ処理レジスタに保持されるデータ値によって定められる、データ処理レジスタと、
を含み、
前記プロセッサコアにより実行される少なくとも1つのデータ処理命令は条件付き書き込みデータ処理命令であり、条件付き書き込みデータ処理命令は、前記プロセッサコアの状態の変化をもたらすデータの書き込みを許可するか否かを指定する条件を符号化した条件コード(26)を含み、
さらに、前記データ処理装置はトラッシュレジスタ(51)を含み、
前記条件付き書き込みデータ処理命令の実行時に、前記条件付き書き込みデータ処理命令の中の前記条件コードが前記プロセッサコアの状態の変化をもたらす書き込みを許可しないことを指定している場合に、結果データ値はデータ処理レジスタではなくトラッシュレジスタに書き込まれ前記プロッセッサコアの状態を変化させない、データ処理装置。 - 請求項1記載の装置において、結果データが書き込まれる複数のデータレジスタを有するレジスタバンク(12)を含む、データ処理装置。
- 請求項2記載の装置において、前記トラッシュレジスタ(51)は前記レジスタバンクの一部であって、前記トラッシュレジスタがプログラム命令によって特定されないように、前記トラッシュレジスタはレジスタ番号にマップされていない、データ処理装置。
- データ処理装置において、
データ処理命令を実行して結果データ値を発生するプロセッサコア(4)と、
前記結果データ値が書き込まれるデータ処理レジスタ(12)であって、前記プロセッサコアの状態はデータ処理レジスタに保持されるデータ値によって定められる、データ処理レジスタと、
を含み、
前記プロセッサコアにより実行される少なくとも1つのデータ処理命令は条件付き書き込みデータ処理命令であり、条件付き書き込みデータ処理命令は、前記プロセッサコアの状態の変化をもたらすデータの書き込みを許可するか否かを指定する条件を符号化した条件コード(26)を含み、
さらに、前記データ処理装置はトラッシュレジスタ(51)を含み、
前記条件付き書き込みデータ処理命令の実行時に、前記条件付き書き込みデータ処理命令の中の前記条件コードが前記プロセッサコアの状態の変化をもたらす書き込みを許可しないことを指定している場合に、結果データ値はデータ処理レジスタではなくトラッシュレジスタに書き込まれ前記プロッセッサコアの状態を変化させない、
前記トラッシュレジスタ(51)は、トラッシュレジスタ制御信号によって、書き込みができないようにプログラムされ、前記トラッシュレジスタ制御信号はシステム・コンフィギュレーション・レジスタに記憶される、
データ処理装置。 - プロセッサコア(4)によって、データ処理命令の実行時に結果データ値を発生するステップを備え、
前記プロセッサコアにより実行される少なくとも1つのデータ処理命令は条件付き書き込みデータ処理命令であり、条件付き書き込みデータ処理命令は、データ処理レジスタに保持されるデータ値によって定められる前記プロセッサコアの状態の変化をもたらすデータの書き込みを許可するか否かを指定する条件を符号化した条件コード(26)を含み、
前記プロセッサコア(4)による前記条件付き書き込みデータ処理命令の実行時に、前記条件付き書き込みデータ処理命令の中の前記条件コードが前記プロセッサコアの状態の変化をもたらす書き込みを許可しないことを指定している場合に、結果データ値は前記データ処理レジスタではなくトラッシュレジスタに書き込まれ前記プロッセッサコアの状態を変化させない、
データ処理方法。 - 請求項5記載の方法において、前記データ処理レジスタは結果データが書き込まれる複数のデータレジスタを有するレジスタバンクの一部である、データ処理方法。
- 請求項6記載の方法において、前記トラッシュレジスタは前記レジスタバンクの一部であって、前記トラッシュレジスタがプログラム命令によって特定されないように、前記トラッシュレジスタはレジスタ番号にマップされていない、データ処理方法。
- プロセッサコア(4)によって、データ処理命令の実行時に結果データ値を発生するステップを備え、
前記プロセッサコアにより実行される少なくとも1つのデータ処理命令は条件付き書き込みデータ処理命令であり、条件付き書き込みデータ処理命令は、データ処理レジスタに保持されるデータ値によって定められる前記プロセッサコアの状態の変化をもたらすデータの書き込みを許可するか否かを指定する条件を符号化した条件コード(26)を含み、
前記プロセッサコア(4)による前記条件付き書き込みデータ処理命令の実行時に、前記条件付き書き込みデータ処理命令の中の前記条件コードが前記プロセッサコアの状態の変化をもたらす書き込みを許可しないことを指定している場合に、結果データ値は前記データ処理レジスタではなくトラッシュレジスタに書き込まれ前記プロッセッサコアの状態を変化させず、
前記プロセッサコア(4)が、前記トラッシュレジスタ(51)をトラッシュレジスタ制御信号によって書き込みができないようにプログラムすることができ、前記トラッシュレジスタ制御信号はシステム・コンフィギュレーション・レジスタに記憶される、
データ処理方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GBGB0229068.2A GB0229068D0 (en) | 2002-12-12 | 2002-12-12 | Instruction timing control within a data processing system |
GBGB0302646.5A GB0302646D0 (en) | 2002-12-12 | 2003-02-05 | Processing activity masking in a data processing system |
GBGB0302650.7A GB0302650D0 (en) | 2002-12-12 | 2003-02-05 | Processing activity masking in a data processing system |
GB0307823A GB2396229B (en) | 2002-12-12 | 2003-04-04 | Processing activity masking in a data processing system |
PCT/GB2003/004261 WO2004053662A2 (en) | 2002-12-12 | 2003-10-06 | Processing activity masking in a data processing system |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2010185224A Division JP2010282651A (ja) | 2002-12-12 | 2010-08-20 | データ処理システムにおける処理動作マスキング |
Publications (3)
Publication Number | Publication Date |
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JP2006522375A JP2006522375A (ja) | 2006-09-28 |
JP2006522375A5 JP2006522375A5 (ja) | 2006-11-09 |
JP4619288B2 true JP4619288B2 (ja) | 2011-01-26 |
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JP2005502327A Expired - Lifetime JP4619288B2 (ja) | 2002-12-12 | 2003-10-06 | データ処理システムにおける処理動作マスキング |
JP2005502328A Expired - Lifetime JP3848965B2 (ja) | 2002-12-12 | 2003-10-06 | データ処理装置内の命令タイミング制御 |
JP2005502326A Expired - Fee Related JP4511461B2 (ja) | 2002-12-12 | 2003-10-06 | データ処理システムでの処理動作マスキング |
JP2005502329A Pending JP2006510998A (ja) | 2002-12-12 | 2003-10-06 | データ処理システム内の処理アクティビティのマスキング |
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JP2005502328A Expired - Lifetime JP3848965B2 (ja) | 2002-12-12 | 2003-10-06 | データ処理装置内の命令タイミング制御 |
JP2005502326A Expired - Fee Related JP4511461B2 (ja) | 2002-12-12 | 2003-10-06 | データ処理システムでの処理動作マスキング |
JP2005502329A Pending JP2006510998A (ja) | 2002-12-12 | 2003-10-06 | データ処理システム内の処理アクティビティのマスキング |
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US (4) | US7134003B2 (ja) |
JP (4) | JP4619288B2 (ja) |
GB (3) | GB2406684B (ja) |
WO (4) | WO2004053685A1 (ja) |
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JP4619288B2 (ja) * | 2002-12-12 | 2011-01-26 | エイアールエム リミテッド | データ処理システムにおける処理動作マスキング |
US7949883B2 (en) * | 2004-06-08 | 2011-05-24 | Hrl Laboratories, Llc | Cryptographic CPU architecture with random instruction masking to thwart differential power analysis |
US9246728B2 (en) | 2004-07-29 | 2016-01-26 | Qualcomm Incorporated | System and method for frequency diversity |
KR100925911B1 (ko) * | 2004-07-29 | 2009-11-09 | 콸콤 인코포레이티드 | 다이버시티 인터리빙을 위한 시스템 및 방법 |
US20070081484A1 (en) * | 2004-07-29 | 2007-04-12 | Wang Michael M | Methods and apparatus for transmitting a frame structure in a wireless communication system |
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US20080317142A1 (en) * | 2005-07-29 | 2008-12-25 | Qualcomm Incorporated | System and method for frequency diversity |
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JP4889235B2 (ja) * | 2005-04-27 | 2012-03-07 | 株式会社デンソー | プログラム制御プロセッサ |
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US9391751B2 (en) * | 2005-07-29 | 2016-07-12 | Qualcomm Incorporated | System and method for frequency diversity |
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US8074059B2 (en) | 2005-09-02 | 2011-12-06 | Binl ATE, LLC | System and method for performing deterministic processing |
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GB2406943A (en) | 2005-04-13 |
WO2004053683A3 (en) | 2004-08-05 |
US20060155962A1 (en) | 2006-07-13 |
GB2406684B (en) | 2005-08-24 |
WO2004053685A1 (en) | 2004-06-24 |
JP2006510126A (ja) | 2006-03-23 |
WO2004053662A2 (en) | 2004-06-24 |
JP3848965B2 (ja) | 2006-11-22 |
GB2406684A (en) | 2005-04-06 |
US7134003B2 (en) | 2006-11-07 |
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