JP4613720B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device in which a logic circuit region and a protection element region are arranged on a surface layer portion of a semiconductor substrate.

  A semiconductor device in which a logic circuit area constituting a logic circuit and a protection element area constituting a protection element are arranged on a surface layer portion of a semiconductor substrate is disclosed in, for example, Japanese Patent Laid-Open No. 10-150149 (Patent Document 1), It is disclosed in JP-A-11-135645 (Patent Document 2) and JP-A-9-64288 (Patent Document 3).

  In the semiconductor device, the protection element disposed together with the logic circuit is connected to an input pad or the like of the semiconductor device to prevent the logic circuit from being destroyed by external noise such as electrostatic discharge (ESD) or surge. Used for.

  In recent years, with the demand for miniaturization of the periphery of the input pad, the distance between the protection element region connected to the input pad and constituting the protection element and the logic circuit region constituting the logic circuit tends to be shortened. is there. For this reason, latch-up is likely to occur in the logic circuit due to the surge current leaked from the protection element region.

  In order to prevent the occurrence of latch-up in this logic circuit, in the semiconductor device disclosed in Patent Document 1, a second protection diode formed between a first N-type region formed on a P-type substrate and an internal circuit are provided with a second An N-type region is formed and a positive potential is applied. Thus, when a negative surge is applied, free electrons supplied from the first N-type region of the negative protection diode are absorbed by the second N-type region, and the free electrons reach the semiconductor element of the internal circuit. Without being a latch-up trigger.

  In the semiconductor device of Patent Document 2, a first conductivity type substrate is used so that an internal circuit is surrounded between a chip peripheral portion where an external interface circuit is disposed and a chip central portion where an internal circuit is disposed. A second conductivity type well that is not electrically connected to any potential is formed. Thus, by forming the second conductivity type well in an electrically floating state, the substrate resistance is increased and the latch-up resistance is increased.

In the semiconductor device of Patent Document 3, a guard ring composed of an N well region is provided around the input / output protection circuit, and a power supply terminal is provided in the P well region where the input / output protection circuit is formed. P + connected A semiconductor region is provided adjacent to the guard ring and parallel to the guard ring. As a result, holes and electrons generated in the input / output protection circuit are captured by the P + semiconductor region and the guard ring, respectively, and diffusion of holes and electrons into the internal circuit can be prevented. The occurrence of latch-up is suppressed.
JP-A-10-150149 JP 11-135645 A JP-A-9-64288

  Each of the semiconductor devices disclosed in Patent Documents 1 to 3 can improve the latch-up breakdown voltage, but has a disadvantage that the area occupied by the periphery of the input pad increases. For example, the semiconductor device disclosed in Patent Document 1 has a drawback that the surge current cannot be captured unless the area of the negative protection diode formed of the first N-type region formed on the P-type substrate is increased. In the semiconductor device of Patent Document 2, the ESD resistance is reduced unless the area of the second conductivity type well is increased. The semiconductor device disclosed in Patent Document 3 tries to capture not only minority carriers due to surges but also majority carriers that diffuse the substrate. However, by providing a P + semiconductor region, the main cause of latch-up is as follows. The area for capturing some minority carriers will be cut.

  Accordingly, the present invention provides a semiconductor device in which a logic circuit region and a protection element region are arranged on a surface layer portion of a semiconductor substrate, and can sufficiently suppress the occurrence of latch-up in a logic circuit due to a surge or the like. An object of the present invention is to provide a semiconductor device capable of suppressing an increase in the occupied area around the input pad.

According to the first aspect of the present invention, in the surface layer portion of the first conductivity type semiconductor substrate, a second conductivity type logic circuit region that constitutes a logic circuit therein, and each region of the first conductivity type and the second conductivity type A protection element region constituting the protection element is disposed, and is formed between the logic circuit region and the protection element region separately from the first conductivity type region constituting the protection element, A substrate contact region that is one conductivity type and has a higher impurity concentration than the semiconductor substrate and is set to a ground potential; and a potential that contains impurities of the second conductivity type and carriers leaked from the protection element region into the semiconductor substrate flow into the semiconductor substrate. a carrier vent region set to have, the substrate contact region in the protection device region side, and positioning the carrier vent region in the logic circuit region side, not characterized by comprising disposed .

And have you in the semiconductor device, formed by formed separately from the first conductivity type region constituting the protective element, the substrate contact region of a high impurity concentration in the first conductivity type, generally, the first conductivity type semiconductor substrate This is a region used for a contact for setting a potential. By arranging this substrate contact region between the logic circuit region and the protection element region and setting it to the ground (ground, GND) potential, minority carriers due to surge leaking from the protection element region to the semiconductor substrate are released to the ground. be able to.

The second conductivity type carrier extraction region in the semiconductor device is used to forcibly extract minority carriers from the semiconductor substrate due to a surge leaked from the protection element region to the semiconductor substrate. For example, when the minority carrier due to surge is an electron, a positive potential is applied to the N-conducting carrier extraction region to capture electrons that cannot be absorbed by the P-conducting semiconductor substrate, forcibly from the semiconductor substrate. Can be removed.
The semiconductor device does not immediately remove minority carriers due to surge leaking from the protection element region in the second conductivity type carrier extraction region, but runs the first conductivity type semiconductor substrate as much as possible to eliminate it. The substrate contact region is arranged on the protection element region side and the carrier extraction region is arranged on the logic circuit region side so that the trapping efficiency by the carrier extraction region is improved.

As described above, the semiconductor device, by combining a substrate contact region and the carrier vent region in the prime applicable, can escape minority carriers due to the surge is a major cause of latch-up efficiently from the semiconductor substrate. Therefore, the semiconductor device is a semiconductor device in which the logic circuit region and the protection element region are arranged on the surface layer portion of the semiconductor substrate, and sufficiently suppresses the occurrence of latch-up in the logic circuit due to a surge or the like. In addition, the semiconductor device is capable of suppressing an increase in the area occupied at the periphery of the input pad.

  According to a second aspect of the present invention, in the semiconductor device, the carrier extraction region is positioned such that the center of the carrier extraction region is located closer to the logic circuit region than the center of the distance between the end portions of the logic circuit region and the protection element region. It is preferable that a blanking region is arranged. In addition, as described in claim 3, it is more preferable that the carrier extraction region is disposed adjacent to the logic circuit region.

According to the result of the simulation regarding the arrangement of the carrier extraction region, the breakdown voltage between the logic circuit region and the carrier extraction region is guaranteed in the semiconductor device in which the carrier extraction region is arranged between the logic circuit region and the protection element region. As far as possible, as the carrier extraction region is arranged as close as possible to the logic circuit region, a higher latch-up breakdown voltage can be secured. As described above , the minority carriers due to the surge leaking from the protection element region are not immediately extracted in the second conductivity type carrier extraction region, but are caused to disappear by running the first conductivity type semiconductor substrate as much as possible. This is probably because the trapping efficiency by the carrier removal region is improved.

  According to a fourth aspect of the present invention, in the semiconductor device, the depth of the tip of the carrier extraction region is preferably set deeper than the depth of the tip of the logic circuit region.

  In the semiconductor device, the junction (interface) area between the semiconductor substrate and the carrier extraction region increases in the depth direction. For this reason, the capture efficiency of minority carriers due to a surge that cannot be absorbed by the semiconductor substrate can be increased without increasing the occupied area. Therefore, it is possible to provide a semiconductor device that sufficiently suppresses the occurrence of latch-up in a logic circuit due to a surge or the like and suppresses an increase in the area occupied in the periphery of the input pad.

  The carrier extraction region set deeper than the front end of the logic circuit region as described above forms a trench deeper than the front end of the logic circuit region in the surface layer portion of the semiconductor substrate, for example, as in claim 5, It can be diffused and formed around the trench. Further, as described in claim 6, impurities may be formed by ion implantation deeper than the tip of the logic circuit region by high acceleration ion implantation.

  On the other hand, when the carrier extraction region cannot be deepened as described above, an uneven portion having a rougher surface than the periphery is formed on the surface layer portion of the semiconductor substrate as described in claim 7, You may make it form around the said uneven | corrugated | grooved part by spreading | diffusion.

  In this case, the bonding area between the semiconductor substrate and the carrier extraction region can be increased even if the occupation area is the same as compared with the case where the uneven portion is not formed. Therefore, as compared with the case where the concavo-convex portion is not formed, the trapping efficiency of minority carriers due to the surge that cannot be absorbed by the semiconductor substrate can be increased, and the latch-up resistance of the semiconductor device can be increased.

  In the semiconductor device, the carrier extraction region is divided into a plurality of portions, and the plurality of carrier extraction regions are set to different potentials. You may make it do.

  Thereby, the arrangement of the carrier extraction region and the setting of the potential can be optimized in accordance with the arrangement of the logic circuit region, and the number of minority carriers flowing into the carrier extraction region can be maximized.

  For example, as described in claim 9, the carrier extraction region divided into a plurality of carriers is sequentially arranged between the logic circuit region and the protection element region, and the carrier extraction region close to the protection element region. The absolute value of the potential may be set larger.

  In this case, since the low energy minority carriers that try to flow from the protection element region toward the logic circuit region are pulled back to the carrier extraction region closer to the protection element region, minority carriers due to a surge toward the logic circuit region. The number of decreases. Therefore, this can also increase the latch-up resistance.

  In the semiconductor device, the first conductivity type may be an N conductivity type and the second conductivity type may be a P conductivity type, but the first conductivity type may be a P conductivity type as claimed in claim 10. When the second conductivity type is an N conductivity type, the logic circuit can be driven with a positive potential by grounding the semiconductor substrate.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a schematic cross-sectional view of a semiconductor device 10 as an example of the semiconductor device of the present invention.

  In the semiconductor device 10 shown in FIG. 1, in the surface layer portion (which may be a P conductivity type well) of a P conductivity type semiconductor substrate 1 p, an N conductivity type logic circuit region 2 n constituting a logic circuit therein, Protective element regions 3p and 3n that are composed of P conductive type (P +) and N conductive type regions and constitute protective elements are arranged. Further, between the logic circuit region 2n and the protection element regions 3p and 3n (distance L between the end portions), a substrate contact region 4p having a P conductivity type and an impurity concentration higher than that of the semiconductor substrate 1p and set to a ground potential; A carrier extraction region 5n containing impurities of N conductivity type and set to a potential at which carriers leaked from the protection element regions 3p and 3n to the semiconductor substrate 1p flow is arranged. In the semiconductor device 10, the protection elements (regions 3 p and 3 n) arranged together with the logic circuit (region 2 n) are connected to an input pad or the like of the semiconductor device 10, so that electrostatic discharge (Electro Static Discharge, ESD), surge, etc. Used to prevent logic circuit destruction due to external noise. The protection elements (regions 3p and 3n) in the semiconductor device 10 of FIG. 1 are provided for negative surge input.

  A substrate contact region 4p of P conductivity type and high impurity concentration (P +) in the semiconductor device 10 of FIG. 1 is generally a region used as a contact for setting the potential of the semiconductor substrate 1p of P conductivity type. By disposing the substrate contact region 4p between the logic circuit region 2n and the protection element regions 3p and 3n and using the ground (ground, GND) potential, the substrate contact region 4p leaks from the protection element regions 3p and 3n to the semiconductor substrate 1p. Minority carriers due to surges can escape to the ground.

  1 is used to forcibly remove minority carriers from the semiconductor substrate 1p due to a surge leaked from the protective element regions 3p and 3n to the semiconductor substrate 1p. It is done. For example, in the semiconductor device 10 of FIG. 1, minority carriers due to a negative surge leaking from the protection element regions 3p and 3n to the P-conductivity type semiconductor substrate 1p are electrons. In the semiconductor device 10, a positive potential (Vcc) is applied to the N-conduction type carrier extraction region 5n, and electrons that cannot be absorbed by the P-conduction type semiconductor substrate 1p are captured to forcibly form the semiconductor substrate. It can be extracted from 1p.

  As described above, in the semiconductor device 10 of FIG. 1, the substrate contact region 4p and the carrier extraction region 5n are suitably combined as shown below, so that minority carriers due to surge, which is the main cause of latch-up, can be efficiently obtained. It can escape from the semiconductor substrate 1p. Accordingly, the semiconductor device 10 is a semiconductor device in which the logic circuit region 2n and the protection element regions 3p and 3n are arranged in the surface layer portion of the semiconductor substrate 1p, and it is sufficient to generate latch-up in the logic circuit due to a surge or the like. Thus, the semiconductor device can suppress the increase of the occupied area in the periphery of the input pad.

  FIG. 2 is a diagram showing a simulation result related to the arrangement of the carrier extraction region 5n. FIG. 2A is a schematic cross-sectional view of the semiconductor device 11 used in the simulation, and FIG. 2B is a simulation result showing the relationship between the position of the carrier extraction region 5n and the latch-up breakdown voltage. In the semiconductor device 11 of FIG. 2A, the same parts as those of the semiconductor device 10 of FIG.

  In the semiconductor device 11 of FIG. 2A used for the simulation, the substrate contact region 4p is disposed between the logic circuit region 2n and the protection element regions 3p and 3n. Further, the carrier extraction region 5n is located on the logic circuit region 2n side with respect to the connection point of the substrate contact region 4p located substantially in the center of the distance L between the end portions of the logic circuit region 2n and the protection element regions 3p and 3n. Are arranged as follows.

  As shown in FIG. 2B, according to the simulation result, the higher the latch-up breakdown voltage can be secured as the carrier extraction region 5n is arranged as close as possible to the logic circuit region 2n. When the carrier extraction region 5n is disposed adjacent to the logic circuit region 2n, the latch-up breakdown voltage is higher than that when the carrier extraction region 5n is disposed at the center of the distance L between the end portions of the logic circuit region 2n and the protection element regions 3p and 3n. It will be improved by an order of magnitude. This is because minority carriers (electrons in FIG. 2) due to surges leaking from the protective element regions 3p and 3n are not extracted immediately in the N-conducting type carrier extraction region 5n, but as much as possible to the P-conducting type semiconductor substrate 1p. It is considered that the trapping efficiency by the carrier removal region 5n is improved when it is made to run and disappear.

  From the simulation results regarding the arrangement of the carrier extraction region 5n described above, in the semiconductor devices 10 and 11 of FIG. 1 and FIG. 2A in which the carrier extraction region 5n is arranged between the logic circuit region 2n and the protection element regions 3p and 3n. The carrier extraction region 5n may be arranged so that the center of the carrier extraction region 5n is located on the logic circuit region 2n side from the center of the distance L between the end portions of the logic circuit region 2n and the protection element regions 3p and 3n. preferable. Further, it is more preferable that the carrier extraction region 5n be arranged as close as possible to the logic circuit region 2n as long as the breakdown voltage between the logic circuit region 2n and the carrier extraction region 5n can be guaranteed.

  Further, as shown in the semiconductor device 10 of FIG. 1, the depth d5 of the tip of the carrier extraction region 5n is preferably set deeper than the depth d2 of the tip of the logic circuit region 2n.

  In this case, the junction (interface) area between the semiconductor substrate 1p and the carrier extraction region 5n increases in the depth direction. For this reason, the capture efficiency of minority carriers due to a surge that cannot be absorbed by the semiconductor substrate 1p can be increased without increasing the occupied area of the carrier extraction region 5n. Therefore, it is possible to provide a semiconductor device that sufficiently suppresses the occurrence of latch-up in a logic circuit due to a surge or the like and suppresses an increase in the area occupied in the periphery of the input pad.

  The carrier extraction region 5n set deeper than the tip of the logic circuit region 2n may be formed as a well with large thermal diffusion as in the semiconductor device 10 of FIG. It may be formed by a method.

  3A and 3B are schematic cross-sectional views of other semiconductor devices 12 and 13 in which the depth d5 of the tip of 5n is set deeper than the depth d2 of the tip of the logic circuit region 2n. It is. In addition, in the semiconductor devices 12 and 13 in FIGS. 3A and 3B, the same reference numerals are given to the same portions as those in the semiconductor device 10 in FIG.

  In the semiconductor device 12 of FIG. 3A, a trench 5h that is deeper than the tip of the logic circuit region 2n is formed in the surface layer portion of the semiconductor substrate 1p, and impurities are diffused from the surface of the trench 5h, and from the tip of the logic circuit region 2n. A deep carrier extraction region 5n is formed around the trench 5h. In the semiconductor device 13 of FIG. 3B, impurities are ion-implanted deeper than the tip of the logic circuit region 2n by high acceleration ion implantation to form a carrier extraction region 5n deeper than the tip of the logic circuit region 2n.

  In each of the semiconductor devices 12 and 13 shown in FIGS. 3A and 3B, a large junction (interface) area is ensured between the semiconductor substrate 1 p and the carrier extraction region 5 n with the carrier extraction region 5 n having a small occupation area. Therefore, the occurrence of latch-up in a logic circuit due to a surge or the like can be sufficiently suppressed, and a semiconductor device in which an increase in the occupied area around the input pad is suppressed.

  On the other hand, when the carrier extraction region 5n cannot be deepened as described above, the carrier extraction region may have a different structure as in the following semiconductor device.

  FIG. 4 is a schematic cross-sectional view of the semiconductor device 14 having a carrier extraction region 5n having another structure. Also in the semiconductor device 14 of FIG. 4, the same reference numerals are given to the same parts as those of the semiconductor device 10 of FIG.

  In the semiconductor device 14 of FIG. 4, an uneven portion 5 s whose surface is rougher than the surroundings is formed on the surface layer portion of the semiconductor substrate 1 p, and impurities are diffused from the surface of the uneven portion 5 s, so that the carrier extraction region 5 n Forms around.

  The carrier extraction region 5n of the semiconductor device 14 shown in FIG. 4 has a larger junction (interface) area between the semiconductor substrate 1p and the carrier extraction region 5n even when the occupation area is the same as compared with the case where the uneven portion 5s is not formed. It has become. Therefore, compared with the case where the uneven portion 5s is not formed, the efficiency of capturing minority carriers due to a surge that cannot be absorbed by the semiconductor substrate 1p can be increased, and the latch-up resistance of the semiconductor device can be increased.

  FIG. 5 is a schematic cross-sectional view of another semiconductor device 15.

  In the semiconductor device 15 of FIG. 5, the carrier extraction region 5n divided into two parts is sequentially arranged side by side between the logic circuit region 2n and the protection element regions 3p, 3n, and is close to the protection element regions 3p, 3n. The absolute value of the potential is set to be larger in the carrier extraction region (in the semiconductor device 15 in FIG. 5, the positive potential is Vcc1> Vcc2).

  In the semiconductor device 15 of FIG. 5, low energy minority carriers (electrons in the semiconductor device 15 of FIG. 5) that are about to flow from the protection element regions 3p and 3n toward the logic circuit region 2n are transferred to the protection element regions 3p and 3n. Since it is pulled back to the carrier extraction region 5n on the side close to 3n, the number of minority carriers due to the surge toward the logic circuit region 2n is reduced. Therefore, this can also increase the latch-up resistance.

  In addition to the semiconductor device 15 of FIG. 5, the carrier extraction region 5n is divided into an arbitrary plurality and appropriately arranged, and the plurality of carrier extraction regions 5n are respectively set to different potentials. May be. Thus, the arrangement of the carrier extraction region 5n and the potential setting can be optimized in accordance with the arrangement of the logic circuit region 2n, and the number of minority carriers flowing into the carrier extraction region 5n can be maximized.

  The semiconductor devices 10 to 15 shown in FIGS. 1 to 5 described above correspond to a negative surge input, and form an N conductivity type carrier extraction region 5n in the surface layer portion of the P conductivity type semiconductor substrate 1p. Was. In this case, the logic circuit can be driven with a positive potential by grounding the P-conductivity type semiconductor substrate 1p. However, the semiconductor device of the present invention is not limited to this, and may be a semiconductor device in which the conductivity types of all regions are reversed in the semiconductor devices 10 to 15 shown in FIGS. In this case, a P-conductivity type carrier extraction region is formed in the surface layer portion of the N-conductivity type semiconductor substrate, and it is possible to cope with positive surge input.

  As described above, the semiconductor device of the present invention is a semiconductor device in which the logic circuit region and the protection element region are arranged in the surface layer portion of the semiconductor substrate, and latch-up occurs in the logic circuit due to a surge or the like. The semiconductor device can be sufficiently suppressed and can suppress an increase in the occupied area in the periphery of the input pad.

1 is a schematic cross-sectional view of a semiconductor device 10 as an example of the semiconductor device of the present invention. It is a figure which shows the simulation result regarding arrangement | positioning of the carrier extraction area | region 5n, (a) is typical sectional drawing of the semiconductor device 11 used for simulation, (b) is the position of the carrier extraction area | region 5n, and a latch-up breakdown voltage. It is a simulation result which shows this relationship. (A), (b) is a schematic cross section of another semiconductor device 12, 13 in which the depth d5 of the tip of the carrier extraction region 5n is set deeper than the depth d2 of the tip of the logic circuit region 2n. FIG. It is typical sectional drawing of the semiconductor device 14 which has the carrier extraction area | region 5n of another structure. 6 is a schematic cross-sectional view of another semiconductor device 15. FIG.

Explanation of symbols

10 to 15 Semiconductor device 1p Semiconductor substrate 2n Logic circuit region 3p, 3n Protection element region 4p Substrate contact region 5n Carrier extraction region

Claims (10)

In the surface layer portion of the semiconductor substrate of the first conductivity type, a protection circuit comprising a second conductivity type logic circuit region that constitutes a logic circuit and each region of the first conductivity type and the second conductivity type, and constituting a protection element An element region, and
The first conductivity type is formed between the logic circuit region and the protection element region separately from the first conductivity type region constituting the protection element, and has a higher impurity concentration than the semiconductor substrate and is set to a ground potential. A substrate contact area to be
A carrier extraction region containing impurities of a second conductivity type and set to a potential at which carriers leaked from the protection element region to the semiconductor substrate flow;
A semiconductor device, wherein the substrate contact region is disposed on the protection element region side, and the carrier extraction region is disposed on the logic circuit region side .   2. The carrier extraction region is arranged such that the center of the carrier extraction region is located closer to the logic circuit region than the center of the distance between the end portions of the logic circuit region and the protection element region. A semiconductor device according to 1.   The semiconductor device according to claim 2, wherein the carrier extraction region is disposed adjacent to the logic circuit region.   4. The semiconductor device according to claim 1, wherein a depth of a tip of the carrier extraction region is set deeper than a depth of a tip of the logic circuit region. 5. A trench is formed in a surface layer portion of the semiconductor substrate,
The semiconductor device according to claim 4, wherein the carrier extraction region is formed around the trench by impurity diffusion.   The semiconductor device according to claim 4, wherein the carrier extraction region is formed by high acceleration ion implantation. In the surface layer portion of the semiconductor substrate, an uneven portion having a rougher surface than the surroundings is formed,
4. The semiconductor device according to claim 1, wherein the carrier extraction region is formed around the uneven portion by impurity diffusion. 5. The carrier removal region is divided into a plurality of locations,
The semiconductor device according to claim 1, wherein the plurality of carrier extraction regions are set to different potentials. The carrier extraction region divided into a plurality is sequentially arranged between the logic circuit region and the protection element region,
9. The semiconductor device according to claim 8, wherein the absolute value of the potential is set to be larger in the carrier extraction region closer to the protection element region.   The semiconductor device according to claim 1, wherein the first conductivity type is a P conductivity type, and the second conductivity type is an N conductivity type.

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