JP2009016736A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance electrostatic protection capability in an N-type MOS transistor for short-circuit used in a power supply clamping method. <P>SOLUTION: The semiconductor integrated circuit has a MOS transistor in which a drain electrode or a source electrode is connected to a highest potential electrode, the source electrode or the drain electrode is connected to the lowest potential electrode, and an electrostatic pulse is input to a gate electrode. The semiconductor integrated circuit operates as a MOS transistor when voltage between an electrode connected to the highest potential electrode and a conductive well opposite from the electrode is equal to or less than voltage that causes breakdown, and operates as a bipolar transistor when the voltage between the electrode and the opposite conductive well is equal to or higher than the voltage that causes breakdown. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit including a short-circuit MOS transistor used for a power supply clamping method.

  Conventionally, as an electrostatic protection configuration of a semiconductor integrated circuit, a diode is inserted into each of the highest potential electrode and the lowest potential electrode with respect to a pad to which an electrostatic pulse is applied (FIG. 8).

  However, the gate oxide film thickness of MOS transistors has become several tens of kilometers due to the recent progress of semiconductor technology, especially the miniaturization. In general, the breakdown voltage of an oxide film is 8 to 10 × 10E6 V / cm. For example, a dielectric breakdown occurs at approximately 5 V in an oxide film thickness of 50 mm.

  A conventional electrostatic protection structure using a diode will be described with reference to FIG.

  In FIG. 8, when negative static electricity is applied to the lowest potential, the protection diode D2 is biased in the forward direction, and the pad potential is clamped to the forward voltage of the protection diode. In this case, since the gate potential of the internal MOS transistor is lower than the gate oxide breakdown voltage, the gate oxide film is protected.

  On the other hand, when a positive electrostatic pulse with respect to the minimum potential is applied to the pad, the pad potential and the gate potential are held at the breakdown voltage of the diode.

  In general, the breakdown voltage of the PN junction is 6 to 7 V. For example, a voltage equal to or higher than the breakdown voltage is applied to an oxide film having a thickness of 50 mm, and the oxide film may be damaged.

  For this reason, in recent years, an electrostatic protection configuration using a power supply clamp method that uses snapback characteristics from an electrostatic protection configuration using a protective diode or short-circuits between the highest potential and the lowest potential with an active element has been used. .

  FIG. 9 is a diagram showing a static electricity protection configuration when the snapback characteristic is used. FIG. 10 is a graph showing snapback characteristics. FIG. 11 is a circuit diagram showing a configuration example of electrostatic protection (Non-Patent Document 1) by a clamping method.

  An electrostatic protection method using the snapback characteristic uses a parasitic NPN transistor of an N-type MOS transistor.

  In the N-type MOS transistor structure used, the drain electrode, the source electrode, and the gate electrode are generally configured in a comb shape. This structure is called multi-finger. The operation is as follows.

  When an electrostatic pulse is applied to the pad, breakdown occurs at the junction between the drain electrode of the N-type MOS transistor connected to the pad and the P-type well, and electron-hole pairs are generated by impact ionization.

  Electrons are attracted to the positive electric field of the drain electrode, and holes are attracted to the P-type well connected to the lowest potential. At this time, the P-type well potential is increased by the current due to the holes.

  When this potential rise becomes larger than the forward threshold voltage of the PN junction formed by the N-type diffusion layer and the P-type well constituting the N-type MOS transistor, the following operation is performed. That is, the N-type MOS transistor is an NPN transistor operation in which the source electrode is an emitter, the P-type well is a base, and the drain electrode is a collector.

  In the case of a P-type MOS transistor, it is composed of a P-type diffusion layer and an N-type well.

  The electrostatic energy is consumed by the ON resistance of the NPN transistor.

  On the other hand, in the power clamp method, electrostatic energy is consumed by the ON resistance of the N-type MOS transistor connected between the highest potential and the lowest potential by using an electrostatic pulse as a trigger without breaking down the N-type MOS transistor.

In general, it is said that it is necessary for electrostatic protection to be able to withstand the application of electrostatic energy of HBM (Human Body Model) 2 kV. The peak value of the current at this time is about 1.33 A, and the element that consumes electrostatic energy is designed to allow this current value to flow.
Meril, R. and Issaq, E, “ESD Protection ON Methodology”, Proc. EOS / ESD Symp., 1993, pp. 233-237

  However, when the snapback characteristic is used, only a part of the NPN transistor may operate if the potential rise of the P-type well serving as the base of the NPN transistor is not uniform. In this case, the electrostatic pulse current is concentrated on the operating NPN transistor, and the semiconductor junction may be thermally destroyed.

  In addition, a desired ON resistance cannot be obtained by operating only some of the NPN transistors, and the oxide film may be destroyed due to an electric field overstress due to a potential increase due to the ON resistance.

  Regarding the power clamp method, since the N-type MOS transistor is used in an active state, the original ON resistance of the N-type MOS transistor is used instead of the ON resistance of the NPN transistor.

  Therefore, a large N-type MOS transistor is required as shown in FIG. 11 of the prior art in order to pass a current due to static electricity and prevent breakdown due to a potential increase due to the ON resistance. This increases the chip area.

  Therefore, an object of the present invention is to improve electrostatic protection capability in a short-circuit N-type MOS transistor used for a power supply clamping method.

  The present invention relates to a semiconductor integrated circuit having a MOS transistor having one main electrode connected to the highest potential electrode, the other main electrode connected to the lowest potential electrode, and driven by an electrostatic pulse input to the gate electrode. The MOS transistor has a breakdown voltage between the one main electrode connected to the highest potential electrode and a well having the opposite conductivity type to the one main electrode and the one main electrode formed therein. When the voltage is lower than the voltage causing the breakdown, the transistor operates as a MOS transistor, and when the voltage between the one main electrode and the well is higher than the voltage causing the breakdown, the transistor operates as a bipolar transistor.

  According to the present invention, when an electrostatic pulse is applied, it is easy to shift from an operation as a MOS transistor to a snapback operation using a parasitic NPN transistor, and electrostatic protection capability can be enhanced.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS The best mode for carrying out the present invention will be described below with reference to the accompanying drawings.

  First, the principle of the present invention will be described.

  The present invention solves the following three problems which are problems of the prior art.

(1) Junction breakdown due to current concentration when using snapback characteristics (2) Oxide film breakdown due to electric field overstress when using snapback characteristics (3) MOS transistor when using power supply clamp method Increase in area due to the size of power supply Basically, a power clamp method is used.

  The structure of the short-circuit MOS transistor arranged between the highest potential and the lowest potential is a structure in which the well potential as the back gate is likely to rise.

  When an electrostatic pulse is applied, the gate electrode of the shorting MOS transistor is driven. Then, an electrostatic pulse current flows from the drain electrode as the main electrode connected to the highest potential to the source electrode as the main electrode connected to the lowest potential through the ON resistance of the MOS transistor.

  The ON resistance of the MOS transistor is set to a value that causes breakdown at the drain-well junction when a peak current 1.33 A corresponding to, for example, HBM 2 kV flows.

  Further, by forming the short-circuit MOS transistor so as to be surrounded by the diffusion layer of the opposite conductivity type, the resistance component from the back gate electrode to the substrate contact is increased, and the back gate potential is easily increased. The diffusion layer is surrounded by a diffusion layer connected to the lowest potential electrode of the same conductivity type as the substrate.

  Further, the back gate electrode of the MOS transistor is not connected to the lowest potential electrode inside the diffusion layer of the conductivity type opposite to the substrate.

  With such a structure, the impact ionization due to breakdown causes the MOS transistor to shift from the MOS operation to the operation of the bipolar transistor, that is, the snapback characteristic.

  Unlike the case where the conventional snapback characteristic is used, the MOS transistor is already in an operating state by the power clamp method, and therefore, only a part of the bipolar transistors does not operate when shifting to the snapback characteristic.

[First Embodiment]
1 to 3 are views showing a first embodiment of the present invention.

  FIG. 1 is a circuit diagram showing a power supply clamp circuit according to a first embodiment of the present invention.

  As shown in FIG. 1, the back gate electrode of N-Shunt, which is a short-circuiting N-type MOS transistor that is normally grounded to the lowest potential, is connected to the CMOS inverter output composed of P1 and N1 in the previous stage.

  R1 and N2 are controlled so that the power clamp circuit does not operate during normal operation.

  C1 responds when an electrostatic pulse appears on the highest potential line, and operates so that the electrostatic pulse is applied to N2 depending on the ratio to the parasitic capacitance of the node to which the gate electrode of N2 is connected.

  N2 is instantaneously activated by an electrostatic pulse, and reduces the input voltage of the N1 and P1 CMOS inverters during the period of the electrostatic pulse.

  As a result, the P-type MOS transistor P1 is turned on, the power supply short-circuiting N-type MOS transistor N-Shunt is turned on, and an electrostatic pulse current starts to flow.

  In FIG. 1, only one N-Shunt MOS transistor is configured, but a plurality of N-Shunt MOS transistors are actually formed.

  The structure of this N-Shunt is as shown in FIGS.

  FIG. 2 is a plan view showing the structure of the N-Shunt MOS transistor of this embodiment, and FIG. 3 is a cross-sectional view showing the structure of the N-Shunt MOS transistor of this embodiment.

  Although not shown in FIGS. 2 and 3, the MOS transistor of the present embodiment is formed in a P-type substrate and a P-type well in a P-type epi region formed in the P-type substrate.

  When the MOS transistor is a P-type MOS transistor, it is formed in an N-type substrate and an N-type well in an N-type epi region formed on the N-type substrate.

  In this embodiment mode, the substrates are not electrically connected.

  When the gate electrode is driven by P1, it operates as an N-type MOS transistor. However, if the ON resistance is large, the drain voltage increases and an avalanche breakdown occurs at the drain electrode and the P-well junction.

  At this time, the potential of the N-Shunt back gate is increased by the inverters P1 and N1, and the back gate potential is further increased by the holes of the electron-hole pairs generated by impact ionization due to avalanche breakdown.

  By this phenomenon, the N-Shunt can change the mode from the N-type MOS transistor operation to the parasitic lateral NPN operation, and the electrostatic pulse current can flow with a lower ON resistance.

[Second Embodiment]
4 to 6 are views showing a second embodiment of the present invention.

  The difference from the first embodiment is that the back gate electrode of the N-Shunt N-type MOS transistor for power supply short circuit is connected to the lowest potential via P-epi.

  The back gate potential rise at the time of avalanche breakdown can be obtained by the resistance component of P-epi, and the back gate potential rise is the resistance value of P-epi, that is, the distance to the substrate contact as compared with the first embodiment. Will depend on.

  FIG. 7 is a graph showing TLP characteristics in the present embodiment.

  It can be seen from the change in the ON resistance of the element that the snap-back operation is performed through the avalanche breakdown from the region where the N-type MOS transistor operates due to the power clamp circuit operation, and the parasitic NPN transistor operates.

  The change in the leakage current does not change even when the TLP current> 2A, and the electrostatic protection capability equivalent to 3 kV or more can be confirmed by HBM.

  In the above embodiment, only the case of an N-type MOS transistor as the short-circuit MOS transistor has been described, but the same effect can be obtained even if a P-type MOS transistor is used as the short-circuit MOS transistor.

  The present invention is applicable to a semiconductor integrated circuit in which a diode and a transistor are integrated.

1 is a circuit diagram illustrating a power clamp circuit according to a first embodiment of the present invention. It is a top view which shows the structure of the N-Shunt MOS transistor of the 1st Embodiment of this invention. It is sectional drawing which shows the structure of the N-Shunt MOS transistor of the 1st Embodiment of this invention. It is a circuit diagram which shows the power supply clamp circuit of the 2nd Embodiment of this invention. It is a top view which shows the structure of the N-Shunt MOS transistor of the 2nd Embodiment of this invention. It is sectional drawing which shows the structure of the N-Shunt MOS transistor of the 2nd Embodiment of this invention. It is a graph which shows the TLP characteristic in the 2nd Embodiment of this invention. It is a circuit diagram which shows the electrostatic protection structure of the conventional semiconductor integrated circuit. It is a figure which shows the electrostatic protection structure at the time of utilizing a snapback characteristic. It is a graph which shows a snapback characteristic. It is a circuit diagram which shows the electrostatic protection structural example (nonpatent literature 1) by a clamp method.

Explanation of symbols

C1 capacitor R1 resistor R2 resistor P1 P-type MOS transistor N1 N-type MOS transistor N2 N-type MOS transistor N3 N-type MOS transistor N-Shunt N-type MOS transistor for short-circuit

Claims (14)

In a semiconductor integrated circuit having a MOS transistor connected to one main electrode to the highest potential electrode, the other main electrode connected to the lowest potential electrode, and driven by an electrostatic pulse input to the gate electrode,
The MOS transistor has a breakdown voltage between the one main electrode connected to the highest potential electrode and a well having the opposite conductivity type to the one main electrode and the one main electrode formed therein. Operates as a MOS transistor
A semiconductor integrated circuit which operates as a bipolar transistor when a voltage between the one main electrode and the well is equal to or higher than a voltage causing breakdown. 2. The semiconductor integrated circuit according to claim 1, wherein the MOS transistor is an N-type MOS transistor. 2. The semiconductor integrated circuit according to claim 1, wherein the MOS transistor is a P-type MOS transistor. 4. The semiconductor integrated circuit according to claim 1, wherein one main electrode, the other main electrode, and the gate electrode of the MOS transistor are formed in a comb shape. The N-type MOS transistor is formed in a P-type substrate and a P-type well in a P-type epi region formed in the P-type substrate,
3. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is surrounded by an N-type diffusion layer that is not electrically connected, and the N-type diffusion layer is surrounded by a P-type diffusion layer connected to the lowest potential electrode. The P-type MOS transistor is formed in an N-type substrate and an N-type well in an N-type epi region formed in the N-type substrate,
4. The semiconductor integrated circuit according to claim 3, wherein the semiconductor integrated circuit is surrounded by a P-type diffusion layer that is not electrically connected, and the P-type diffusion layer is surrounded by an N-type diffusion layer connected to the lowest potential electrode. 6. The semiconductor integrated circuit according to claim 5, wherein the back gate electrode of the MOS transistor is not connected to the lowest potential electrode inside the N-type diffusion layer. 7. The semiconductor integrated circuit according to claim 6, wherein the back gate electrode of the MOS transistor is not connected to the lowest potential electrode inside the P-type diffusion layer. 2. A plurality of the MOS transistors are formed, and a back gate electrode of the MOS transistor is disposed between the MOS transistors and is electrically connected to the gate electrode of the MOS transistor. The semiconductor integrated circuit as described. 9. The semiconductor integrated circuit according to claim 7, wherein the back gate electrode of the MOS transistor is electrically connected to the gate electrode of the MOS transistor and is connected to a circuit driven by electrostatic pulses. A P-type substrate;
A P-type epi region formed on the P-type substrate;
An N-type well formed in the P-type epi region;
A P-type well formed in the N-type well,
The N-type MOS transistor is formed in the P-type well and is surrounded by a non-electrically connected N-type diffusion layer, and the N-type diffusion layer is surrounded by a P-type diffusion layer connected to the lowest potential electrode. The semiconductor integrated circuit according to claim 2. An N-type substrate;
An N-type epi region formed on the N-type substrate;
A P-type well formed in the N-type epi region;
An N-type well formed in the P-type well,
The P-type MOS transistor is formed in the N-type well and surrounded by a P-type diffusion layer that is not electrically connected. The P-type diffusion layer is surrounded by an N-type diffusion layer connected to the lowest potential electrode. The semiconductor integrated circuit according to claim 3. 12. The semiconductor integrated circuit according to claim 11, wherein the back gate electrode of the N-type MOS transistor is not connected to the lowest potential electrode inside the N-type diffusion layer. 13. The semiconductor integrated circuit according to claim 12, wherein the back gate electrode of the P-type MOS transistor is not connected to the lowest potential electrode inside the P-type diffusion layer.

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