JP4598905B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP4598905B2
JP4598905B2 JP02098299A JP2098299A JP4598905B2 JP 4598905 B2 JP4598905 B2 JP 4598905B2 JP 02098299 A JP02098299 A JP 02098299A JP 2098299 A JP2098299 A JP 2098299A JP 4598905 B2 JP4598905 B2 JP 4598905B2
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Prior art keywords
wafer
bumps
chip
thermoplastic resin
bump
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JP2000223602A (en
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義男 岡田
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NXP USA Inc
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NXP USA Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731Location prior to the connecting process
    • H01L2224/73101Location prior to the connecting process on the same surface
    • H01L2224/73103Bump and layer connectors
    • H01L2224/73104Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

【0001】
【産業上の利用分野】
本発明は一般に半導体素子の製造方法に関し、さらに詳細にはフリップチップ接合からなる半導体素子の製造方法に関する。
【0002】
【従来の技術】
近年、プロセス技術の発展に伴い、半導体素子の性能が著しく向上しており、その性能を十二分に生かすインターコネクトの技術として、ワイヤー・ボンディング技術に代わり、フリップ・チップ接合技術が応用される機会が増加している。フリップ・チップ接合とは、チップの能動素子面(主面)を基板に向けて接続する方式をいう。
【0003】
通常、最初にウエハの主面上に半田バンプを形成する。次に、ウエハの裏面をバックグラインド(裏面研削)する。次に、ダイシングしてウエハを小片(チップ)化する。チップを裏返して基板の位置に合わせた後、半田を溶かして電気的接続を得た後、最後に熱硬化性樹脂でチップを封止する。
【0004】
バンプはチップの周囲だけでなく、チップの任意の位置に配置できるため、例えば100×100マトリックスとした場合は1万個のI/O数が取れる。また、小型携帯情報電子機器やICカード等の分野においては、実装面積の小型化に加え、実装容積の低減が要求され、チップ自体の薄型化の必要がある。
【0005】
チップの薄型化のためにウエハのバックグラインドが重要な工程となる。従来、ウェハのバックグラインドは、薄い接着層とベースフィルムの二層または三層構造のテープを用いて、ウエハの補強とウエハの主面を保護し実施されていた。
また、電解の金バンプのように15〜30μmの高さのバンプを有するウエハではバンプ形成後に通常の2層または3層構造のテープを用いてバックグラインドを行っていた。
【0006】
【解決すべき課題】
30〜40μmまでの高さの半田バンプを有するウエハでは、従来の方法でバックグラインドが可能であるが、100μm程度の高さのバンプを有するウエハのバックグラインドでは、バンプのダメージ、厚みおよび厚みむらの制御が困難であった。
【0007】
一方、チップと基板とのストレスを緩和するため高いバンプを用いるのが有利である。また、封止用の樹脂の注入の容易性を向上するためにも、高いバンプを用いる必要性が増大している。そこで、40μm以上の高いバンプを有するウエハを均一にかつウエハを損傷することなく、所定の厚みにバックグラインドすることは重要な課題である。
【0008】
また、高いバンプを有する大口径のウエハを薄い接着層とベースフィルムからなる多層構造のテープを用いてバックグラインドすると、ウエハの厚みむら、厚み制御性の低下、バンプの損傷が生じるという問題点があった。
【0009】
このバンプ損傷の問題点を回避するため、バックグラインド後にバンプを形成する方法があるが、ウエハのハンドリングを考慮すると最終的な厚みに限界があり、この方法ではチップ自体の薄型化を図れないという問題点があった。
【0010】
したがって、本発明の一目的は、高さが40μm以上、特に100μm以上のバンプを有するウエハを均一にかつウエハへの損傷がなく、目的の厚みにバックグラインドが可能な半導体素子の製造方法を提供することである。
【0011】
さらに本発明の一目的は、ボンディング工程においてチップをアライメントし、リフローするだけで、樹脂封止されたフリップチップ接合を容易に形成する半導体素子の製造方法を提供することである。
【0012】
さらに本発明の一目的は、大口径のウエハにおいても上記目的が達成可能な半導体素子の製造方法を提供することである。
【0013】
【課題を解決するための手段】
前記のおよびその他の目的は、半導体素子の製造方法であって、主面および裏面を有するウエハ(11)を用意する段階、ウエハの主面上の所定領域に100μm以上の高さを有する複数のバンプ(21)を形成する段階(20)、ウエハの主面上であって複数のバンプ間に、各バンプの融点以下で可塑化する熱可塑性樹脂(31)を塗布する段階であって、熱可塑性樹脂をバンプの頂部が40μm以下露出するように塗布する段階(30)、ウエハの厚みが350μm未満となるようにウエハの裏面を研削する段階(50)、ウエハを小片化してチップ(71)を形成する段階(70)、基板(81)を用意する段階およびチップを基板の所定の位置に配置し、チップ、複数のバンプおよび基板を熱可塑性樹脂で封止する段階(80)から構成されることを特徴とする半導体素子の製造方法によって実現される。
【0014】
【実施例】
図1は、本願の一実施例による、ウエハ11の断面図を示す。ウエハ11はチップの能動素子面(主面)と裏面を有する。ウエハの口径は問わないが、大口径(8インチ以上のウエハ)であっても本願は適用可能である。
【0015】
図2は、図1の段階10のウエハ11の主面上にバンプ21を形成した段階20を示す断面図である。バンプの数は説明の簡略化のために数個とするが、その数に限定はない。バンプの高さは40μm以上、さらには100μm以上が好適である。バンプの高さは、ストレスの緩和、ウエハの信頼性、樹脂注入の容易性のためには高い程よいが、チップの薄型化、バンプの数が制限されることを考慮すると120〜130μmが最も好適である。バンプの材質は、一般的にはPb/Sn系半田であるが、Au,Ni,Cuなどをコアとすることも可能であり限定するものではない。さらにはSn/Ag,Sn/Bi等の鉛フリーの半田にも適用可能である。半田バンプの接続方法はC4(Controlled Collapse Chip Connection)あるいはCCB(Controlled Collapse Bonding)と呼ばれる方法が用いられるが、本願を限定するものではない。バンプの構造も本願では特に限定されない。 図3は、図2の段階20の基板の主面上のバンプ間に樹脂31を塗布した段階30を示す断面図である。樹脂の塗布は、共晶Pb/Sn半田を用いる場合には、段階20の基板の主面上に183℃以下、好適には150℃程度で可塑化する熱可塑性の樹脂をバンプの頭が40μm以下程度露出するように塗布する。塗布は、樹脂に十分な流動性を持たせるため、熱可塑性樹脂をその溶融温度である240℃〜250℃まで加熱し、基板の主面上に滴下することにより行う。このときバンプが溶けないように基板をバンプの融点(183℃)未満に保持することが望ましい。次に熱可塑性樹脂をその可塑化温度以上であってバンプの融点未満(150℃〜183℃)の高温で暫く放置する。このように温度を制御し、高温で放置することにより、熱可塑性樹脂がバンプ上に被膜することなく基板の主面上に均一に塗布することが可能である。
熱可塑性樹脂とは、加熱によって軟化成型した後、その外力を取り去ってもその外形を保持している樹脂をいう。一般に、線状あるいは分枝状の高分子からなる化学構造をもち、加熱により分子間化学反応を起こさせない樹脂である。本願において例えば、ポリエチレン,ポリスチレン,ポリ塩化ビニル,ポリアドミなどを用いることができる。この樹脂は、ウエハのハンドリングの際やバックグラインドの際の補強材として働くとともにフリップ接合の際には封止材として機能するものである。樹脂の可塑化温度の上限は、バンプの材質により変更可能であり、バンプの材質の融点以下であれば183℃に限定されない。バンプの頭の露出する高さは、後述のボンディング段階でチップと基板の接合に適した厚みであれば40μmに限定されるものではない。
【0016】
図4は、図3の段階30の樹脂31およびバンプ21上にテープ41を貼った段階40を示す断面図である。テープは従来と同じベースフルムと接着層からなるテープを使用することができる。表面保護,バンプの固定,テープの剥離の容易性のための特殊な多層テープを用いる必要はない。本願では、樹脂を段階30において既に塗布してあるため樹脂が補強材として機能するため、テープはバックグラインドの際の表面を保護することを主目的として貼るものである。
【0017】
図5は、図4の段階40のウエハ11の裏面をバックグラインドした段階50を示す断面図である。段階20でバンプを形成済みであり、さらに段階40で、バンプは樹脂で十分に固定され、ウエハは補強されているため、所望の厚みまでウエハをバックグラインドすることが可能である。従来技術では高いバンプを形成した場合も、ウエハはテープのベースフィルム層で補強されるのみなので、ウエハの厚みのむら、厚みの制御性、バンプの損傷等の問題が発生し、350μmの厚みですら、うまく制御してバックグラインドすることができなかった。一方、本願の一実施例では、8インチウエハにバンプ高が130μmの半田バンプを形成した場合であっても、樹脂が補強材として働くため、バンプを損傷させることなく、均一の厚みで100μm程度までバックグラインドすることが可能である。このように、高さの高いバンプを用いても、ウエハを従来より薄くバックグラインド可能なため、最終的には従来よりチップの薄型化を図ることができる。
【0018】
図6は、図5の段階50にテープを剥離した段階60を示す断面図である。本願では従来のテープと同一のテープを用いても、バンプ間には樹脂を塗布してあるため、バンプを損傷することなく、テープを容易に剥離することが可能である。ただし、紫外線感光層を有するテープを用い、紫外線(UV)照射によりテープの剥離をさらに容易にすることも可能である。
【0019】
図7は、図6の段階60をダイシング(小片化)する段階70を示す断面図およびそのダイシング後のチップ71の拡大断面図である。ダイシングは、ウエハを個々のチップ分離する工程である。図7では、説明のため一方向のダイシングのみを示すが、X方向のダイシングが終了すると、ウエハを90°回転し、Y方向のダイシングを行い、個々のチップ分離する。チップ71は、ウエハ11に対し上下逆方向にして裏面を上向きにした状態を示す。
【0020】
図8は、チップ71を基板81にフリップチップボンディングした段階90を示す断面図である。ボンディング後、外部力や湿気、汚染物などの環境からチップを保護する。従来技術では、この段階においてチップ表面に熱硬化性樹脂を封止する。この熱硬化性樹脂は一般低粘度の液体であり、毛細管現象を利用してチップと基板の間に注入後、加熱して硬化させる。本願では、段階30において熱可塑性樹脂を予め塗布してあり、この熱可塑性樹脂は工程中の補強材として働くほか、封止材として機能する。従って、この段階においてチップに熱硬化性樹脂で封止する必要はない。バンプの先端に半田ペーストを転写するか、基板上のフラックスをディスペンスした後、チップをアライメントし、リフローするだけで、樹脂封止されたフリップチップ接合が容易に形成される。さらに、本願では熱可塑性樹脂を用いるため、リフローの際、熱可塑性樹脂から露出したバンプの頭部のみならず熱可塑性樹脂自身も柔らかくなり、バンプにストレスをかけることなく樹脂封止が可能である。
【0021】
【発明の効果】
本発明は、以下に記載されるような効果を奏する。
【0022】
本発明は、高さが40μm以上、特に100μm以上のバンプを有するウエハを均一にかつウエハへの損傷がなく、目的の厚みにバックグラインドが可能な半導体素子の製造方法を提供することができる。
【0023】
さらに本発明は、補強材と封止材を兼ねる熱可塑性樹脂を用いることにより、ボンディング工程においてチップをアライメントし、リフローするだけで、樹脂封止されたフリップチップ接合を容易に形成することが可能である。
【0024】
さらに本発明は、大口径のウエハにおいても上記目的が達成可能である。
【0025】
ここでは特定の実施例について本発明の構造を説明してきたが、当該技術分野に通じたものであれば本発明の構造を変形、変更することができるであろう。しかしながら、本発明の構造はここで開示された特定の実施例に限定されるものではない。例えば、マッシュルーム型,ストレートウォール型等のバンプの形状、熱可塑性樹脂の種類についても特定を意図するものではない。さらにソルダレジスト層やその他の保護層の形成の段階等の説明は、説明の簡略化のために省略しているが、本願を限定する意図ではない。そのような記載のないフリップチップボンディングの製造工程は通常の方法により行うものとする。そのような変形、変更されたものも本発明の技術思想の範疇であり、特許請求の範囲に含まれるものである。
【図面の簡単な説明】
【図1】本願の一実施例による、ウエハ11の断面図を示す。
【図2】図1の段階10のウエハ11の主面上にバンプ21を形成した段階20を示す断面図である。
【図3】図2の段階20の基板の主面上のバンプ間に樹脂31を塗布した段階30を示す断面図である。
【図4】図3の段階30のソルダレジスト層上にテープ41を貼った段階40を示す断面図である。
【図5】図4の段階40のウエハ11の裏面をバックグラインドした段階50を示す断面図である。
【図6】図5の段階50にテープを剥離した段階60を示す断面図である。
【図7】図6の段階60をダイシング(小片化)する段階70を示す断面図およびそのダイシング後のチップ71の拡大図である。
【図8】チップ71を基板81にフリップチップボンディングした段階80を示す断面図である。
【符号の説明】
11 ウエハ
21 バンプ
31 熱可塑性樹脂
41 テープ
71 チップ
81 基板
[0001]
[Industrial application fields]
The present invention generally relates to the production how the semiconductor device, and more particularly relates to the production how a semiconductor device comprising a flip-chip bonding.
[0002]
[Prior art]
In recent years, with the development of process technology, the performance of semiconductor devices has improved remarkably, and as an interconnect technology that takes full advantage of its performance, the opportunity to apply flip chip bonding technology instead of wire bonding technology Has increased. Flip-chip bonding refers to a method in which an active element surface (main surface) of a chip is connected to a substrate.
[0003]
Usually, solder bumps are first formed on the main surface of the wafer. Next, the back surface of the wafer is back-ground (back surface grinding). Next, the wafer is diced into small pieces (chips). After turning the chip over and aligning with the position of the substrate, the solder is melted to obtain electrical connection, and finally the chip is sealed with a thermosetting resin.
[0004]
Since the bumps can be arranged not only around the chip but also at any position of the chip, for example, when a 100 × 100 matrix is used, 10,000 I / O numbers can be obtained. In the fields of small portable information electronic devices and IC cards, in addition to reducing the mounting area, a reduction in mounting volume is required, and the chip itself needs to be thinned.
[0005]
Wafer back grinding is an important process for thinning the chip. Conventionally, wafer backgrinding has been performed by using a thin adhesive layer and a two-layer or three-layer tape of a base film to reinforce the wafer and protect the main surface of the wafer.
Further, in the case of a wafer having a bump having a height of 15 to 30 μm, such as an electrolytic gold bump, back grinding is performed using a normal two-layer or three-layer tape after the bump formation.
[0006]
【task to solve】
A wafer having solder bumps with a height of 30 to 40 μm can be back-ground by a conventional method. However, in a back-grind of a wafer having bumps with a height of about 100 μm, the damage, thickness and unevenness of the bumps are reduced. It was difficult to control.
[0007]
On the other hand, it is advantageous to use high bumps to relieve stress between the chip and the substrate. In addition, the necessity of using high bumps is increasing in order to improve the ease of injection of the sealing resin. Therefore, it is an important problem to uniformly grind a wafer having high bumps of 40 μm or more to a predetermined thickness without damaging the wafer.
[0008]
In addition, if a large-diameter wafer having high bumps is back-ground using a multi-layered tape composed of a thin adhesive layer and a base film, the wafer thickness unevenness, thickness controllability, and bump damage may occur. there were.
[0009]
In order to avoid this problem of bump damage, there is a method of forming bumps after back grinding. However, there is a limit to the final thickness in consideration of wafer handling, and this method cannot reduce the thickness of the chip itself. There was a problem.
[0010]
Accordingly, an object of the present invention is 40μm or height, in particular uniformly and without damage to the wafer is a wafer having the above bumps 100 [mu] m, the manufacturing method of the semiconductor element capable of back grinding the thickness of the object Is to provide.
[0011]
Further an object of the present invention is to align the chip in the bonding step, just reflow, it is to provide a manufacturing how the semiconductor device to easily form the flip-chip bonding resin-sealed.
[0012]
Further an object of the present invention is also to provide a manufacturing how the semiconductor device above-mentioned object is achievable in a large-diameter wafer.
[0013]
[Means for Solving the Problems]
The above and other objects are a method for manufacturing a semiconductor device, comprising a step of preparing a wafer (11) having a main surface and a back surface, and a plurality of regions having a height of 100 μm or more in a predetermined region on the main surface of the wafer. A step (20) of forming a bump (21), and a step of applying a thermoplastic resin (31) which is plasticized below the melting point of each bump on the main surface of the wafer and between the plurality of bumps, The step of applying thermoplastic resin so that the top of the bump is exposed to 40 μm or less (30), the step of grinding the back surface of the wafer so that the thickness of the wafer is less than 350 μm (50), and the chip (71 ) Forming step (70), preparing the substrate (81), placing the chip at a predetermined position on the substrate, and sealing the chip, the plurality of bumps and the substrate with a thermoplastic resin (80). This is realized by a method for manufacturing a semiconductor device.
[0014]
【Example】
FIG. 1 shows a cross-sectional view of a wafer 11 according to one embodiment of the present application. The wafer 11 has an active element surface (main surface) and a back surface of the chip. The diameter of the wafer is not limited, but the present application can be applied even when the diameter is large (wafer of 8 inches or more).
[0015]
FIG. 2 is a cross-sectional view showing step 20 in which bumps 21 are formed on the main surface of wafer 11 in step 10 of FIG. The number of bumps is several for simplicity of explanation, but the number is not limited. The height of the bump is preferably 40 μm or more, more preferably 100 μm or more. The height of the bump is preferably as high as possible for stress relaxation, wafer reliability, and ease of resin injection. However, considering that the chip is thin and the number of bumps is limited, 120 to 130 μm is most preferable. It is. The material of the bump is generally Pb / Sn solder, but Au, Ni, Cu or the like can be used as a core and is not limited. Furthermore, the present invention can also be applied to lead-free solders such as Sn / Ag and Sn / Bi. As a method for connecting the solder bumps, a method called C4 (Controlled Collapse Chip Connection) or CCB (Controlled Collapse Bonding) is used, but the present invention is not limited thereto. The structure of the bump is not particularly limited in the present application. FIG. 3 is a cross-sectional view illustrating a step 30 in which a resin 31 is applied between the bumps on the main surface of the substrate in step 20 of FIG. When eutectic Pb / Sn solder is used for the resin application, a thermoplastic resin that is plasticized at 183 ° C. or lower, preferably about 150 ° C., is formed on the main surface of the substrate in step 20 with a bump head of 40 μm. Apply so that it is exposed to the following extent. The application is performed by heating the thermoplastic resin to a melting temperature of 240 ° C. to 250 ° C. and dropping it onto the main surface of the substrate in order to give the resin sufficient fluidity. At this time, it is desirable to keep the substrate below the melting point of the bump (183 ° C.) so that the bump does not melt. Next, the thermoplastic resin is allowed to stand for a while at a temperature higher than its plasticizing temperature and lower than the melting point of the bump (150 ° C. to 183 ° C.). By controlling the temperature in this way and leaving it at a high temperature, the thermoplastic resin can be uniformly applied on the main surface of the substrate without being coated on the bumps.
A thermoplastic resin refers to a resin that retains its outer shape after being softened and molded by heating and then removing its external force. Generally, it is a resin that has a chemical structure composed of a linear or branched polymer and does not cause an intermolecular chemical reaction by heating. In the present application, for example, polyethylene, polystyrene, polyvinyl chloride, polyadomi and the like can be used. This resin functions as a reinforcing material during wafer handling and back grinding, and also functions as a sealing material during flip bonding. The upper limit of the plasticizing temperature of the resin can be changed depending on the material of the bump, and is not limited to 183 ° C. as long as it is not higher than the melting point of the material of the bump. The height at which the heads of the bumps are exposed is not limited to 40 μm as long as the thickness is suitable for bonding the chip and the substrate in the bonding stage described later.
[0016]
4 is a cross-sectional view showing a stage 40 in which a tape 41 is pasted on the resin 31 and the bump 21 in the stage 30 of FIG. As the tape, it is possible to use a tape made of the same base film and adhesive layer as in the past. There is no need to use special multi-layer tape for surface protection, bump fixing, and ease of tape peeling. In this application, since the resin has already been applied in step 30 and the resin functions as a reinforcing material, the tape is applied mainly for the purpose of protecting the surface during back grinding.
[0017]
FIG. 5 is a cross-sectional view showing a stage 50 in which the back surface of the wafer 11 in the stage 40 of FIG. 4 is back-ground. In step 20, bumps have been formed, and in step 40, the bumps are sufficiently fixed with resin, and the wafer is reinforced, so that it is possible to back grind the wafer to a desired thickness. Even when high bumps are formed with the conventional technology, the wafer is only reinforced with the base film layer of the tape, which causes problems such as uneven thickness of the wafer, controllability of the thickness, damage to the bumps, and even a thickness of 350 μm. Could not control, back grind well. On the other hand, in one embodiment of the present application, even when a solder bump having a bump height of 130 μm is formed on an 8-inch wafer, the resin acts as a reinforcing material, so that the bump is not damaged and the thickness is about 100 μm with a uniform thickness. It is possible to back grind up to. Thus, even if bumps having a high height are used, the wafer can be back-ground thinner than before, so that the chip can finally be made thinner than before.
[0018]
FIG. 6 is a cross-sectional view showing step 60 where the tape is peeled off at step 50 of FIG. In this application, even if the same tape as the conventional tape is used, since the resin is applied between the bumps, the tape can be easily peeled without damaging the bumps. However, it is also possible to use a tape having an ultraviolet photosensitive layer and further facilitate the peeling of the tape by ultraviolet (UV) irradiation.
[0019]
FIG. 7 is a cross-sectional view showing a step 70 of dicing (dividing) the step 60 of FIG. 6 and an enlarged cross-sectional view of the chip 71 after the dicing. Dicing is a step of separating the wafer into individual chips. In FIG. 7, only dicing in one direction is shown for explanation, but when dicing in the X direction is completed, the wafer is rotated by 90 °, and dicing in the Y direction is performed to separate individual chips. The chip 71 shows a state where the back surface is turned upside down with respect to the wafer 11.
[0020]
FIG. 8 is a cross-sectional view showing a stage 90 in which the chip 71 is flip-chip bonded to the substrate 81. After bonding, the chip is protected from external forces, moisture, and contaminants. In the prior art, a thermosetting resin is sealed on the chip surface at this stage. This thermosetting resin is generally a low-viscosity liquid, and is cured by heating after being injected between the chip and the substrate using capillary action. In the present application, a thermoplastic resin is preliminarily applied in step 30, and this thermoplastic resin functions as a reinforcing material in the process and also functions as a sealing material. Therefore, it is not necessary to seal the chip with a thermosetting resin at this stage. After transferring the solder paste to the tip of the bump or dispensing the flux on the substrate, the chip is aligned and reflowed to easily form a resin-sealed flip chip joint. Further, since a thermoplastic resin is used in the present application, not only the bump head exposed from the thermoplastic resin but also the thermoplastic resin itself becomes soft during reflow, and the resin can be sealed without applying stress to the bump. .
[0021]
【The invention's effect】
The present invention has the following effects.
[0022]
The present invention is 40μm or height, in particular no damage to uniformly and wafer wafer having the above bump 100 [mu] m, it is possible to provide a manufacturing how the back-grinding is possible semiconductor elements on the thickness of the object .
[0023]
Furthermore, the present invention can easily form a resin-sealed flip chip joint by simply aligning and reflowing the chip in the bonding process by using a thermoplastic resin that serves as both a reinforcing material and a sealing material. It is.
[0024]
Further, the present invention can achieve the above object even for a large-diameter wafer.
[0025]
Although the structure of the present invention has been described herein with reference to specific embodiments, modifications and variations of the structure of the present invention will occur to those skilled in the art. However, the structure of the present invention is not limited to the specific embodiments disclosed herein. For example, the shape of bumps such as mushroom type and straight wall type, and the type of thermoplastic resin are not intended to be specified. Further, description of the stage of forming the solder resist layer and other protective layers is omitted for simplification of description, but is not intended to limit the present application. The manufacturing process of flip chip bonding without such a description shall be performed by a normal method. Such modifications and changes are also within the scope of the technical idea of the present invention and are included in the scope of the claims.
[Brief description of the drawings]
FIG. 1 shows a cross-sectional view of a wafer 11 according to one embodiment of the present application.
2 is a cross-sectional view showing a step 20 in which bumps 21 are formed on the main surface of the wafer 11 in the step 10 of FIG. 1;
3 is a cross-sectional view showing a step 30 in which a resin 31 is applied between bumps on the main surface of the substrate in the step 20 of FIG. 2;
4 is a cross-sectional view showing a stage 40 in which a tape 41 is pasted on the solder resist layer in stage 30 of FIG. 3;
5 is a cross-sectional view showing a stage 50 in which the back surface of the wafer 11 in the stage 40 in FIG. 4 is back-ground. FIG.
6 is a cross-sectional view showing a step 60 where the tape is peeled off at a step 50 in FIG. 5;
7 is a cross-sectional view showing a step 70 of dicing (dividing) the step 60 of FIG. 6 and an enlarged view of a chip 71 after the dicing.
8 is a cross-sectional view showing a stage 80 in which a chip 71 is flip-chip bonded to a substrate 81. FIG.
[Explanation of symbols]
11 Wafer 21 Bump 31 Thermoplastic Resin 41 Tape 71 Chip 81 Substrate

Claims (5)

半導体素子の製造方法であって:
主面および裏面を有するウエハ(11)を用意する段階(10);
前記ウエハの主面上の所定領域に100μm以上の高さを有する複数のバンプ(21)を形成する段階(20);
前記ウエハの主面上であって前記複数のバンプ間に、前記各バンプの融点以下で可塑化する熱可塑性樹脂(31)を塗布する段階であって、前記熱可塑性樹脂を前記各バンプの頂部が40μm以下露出するように塗布する段階(30);
前記ウエハの厚みが350μm未満となるように前記ウエハの裏面を研削する段階(50);
前記ウエハを小片化してチップ(71)を形成する段階(70);
基板(81)を用意する段階;および
前記チップを前記基板の所定の位置に配置し、前記チップ、前記複数のバンプおよび前記基板を前記熱可塑性樹脂で封止する段階(80);
から構成されることを特徴とする半導体素子の製造方法。
A method for manufacturing a semiconductor device comprising:
Providing a wafer (11) having a main surface and a back surface (10);
Forming a plurality of bumps (21) having a height of 100 μm or more in a predetermined region on the main surface of the wafer (20);
Applying a thermoplastic resin (31) that is plasticized below the melting point of each bump on the main surface of the wafer and between the plurality of bumps, the thermoplastic resin being applied to the top of each bump (30) which is applied so as to be exposed to 40 μm or less;
Grinding the back surface of the wafer so that the thickness of the wafer is less than 350 μm (50);
Crushing the wafer to form chips (71) (70);
Providing a substrate (81); and disposing the chip at a predetermined position of the substrate and sealing the chip, the plurality of bumps, and the substrate with the thermoplastic resin (80);
A method for manufacturing a semiconductor device, comprising:
前記複数のバンプ間に熱可塑性樹脂を塗布する段階(30)は、
前記熱可塑性樹脂を加熱する段階;
前記熱可塑性樹脂を前記ウエハの主面上に滴下する段階;および
前記ウエハを高温で保持する段階;
を含むことを特徴とする請求項1記載の半導体素子の製造方法。
Applying a thermoplastic resin between the plurality of bumps (30),
Heating the thermoplastic resin;
Dropping the thermoplastic resin onto a major surface of the wafer; and holding the wafer at a high temperature;
The method of manufacturing a semiconductor device according to claim 1, comprising:
前記チップ,前記複数のバンプおよび前記基板を前記熱可塑性樹脂で封止する段階(80)は、前記チップ,前記複数のバンプおよび前記基板を加熱することを含むことを特徴とする請求項1または2記載の半導体素子の製造方法。  The step of sealing (80) the chip, the plurality of bumps, and the substrate with the thermoplastic resin includes heating the chip, the plurality of bumps, and the substrate. 3. A method for producing a semiconductor device according to 2. 前記複数のバンプ(21)を形成する段階(20)は、120μm〜130μmの高さの複数のバンプを形成することを含むことを特徴とする請求項1ないし3の何れか1項に記載の半導体素子の製造方法。  4. The step (20) of forming the plurality of bumps (21) includes forming a plurality of bumps having a height of 120 [mu] m to 130 [mu] m. A method for manufacturing a semiconductor device. 前記熱可塑性樹脂は183℃以下で可塑化することを含むことを特徴とする請求項1ないし4の何れか1項に記載の半導体素子の製造方法。  The method for manufacturing a semiconductor element according to claim 1, wherein the thermoplastic resin includes plasticizing at 183 ° C. or lower.
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JP5090610B2 (en) * 2000-10-17 2012-12-05 スリーエム イノベイティブ プロパティズ カンパニー Solvent burnishing of pre-underfilled solder bump wafers for flip chip bonding
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