JP2000223602A - Bonding structure of chip to substrate and manufacture of the structure - Google Patents
Bonding structure of chip to substrate and manufacture of the structureInfo
- Publication number
- JP2000223602A JP2000223602A JP2098299A JP2098299A JP2000223602A JP 2000223602 A JP2000223602 A JP 2000223602A JP 2098299 A JP2098299 A JP 2098299A JP 2098299 A JP2098299 A JP 2098299A JP 2000223602 A JP2000223602 A JP 2000223602A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- chip
- bumps
- substrate
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は一般に半導体素子および
その製造方法に関し、さらに詳細にはフリップチップ接
合からなる半導体素子およびその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device formed by flip chip bonding and a method of manufacturing the same.
【0002】[0002]
【従来の技術】近年、プロセス技術の発展に伴い、半導
体素子の性能が著しく向上しており、その性能を十二分
に生かすインターコネクトの技術として、ワイヤー・ボ
ンディング技術に代わり、フリップ・チップ接合技術が
応用される機会が増加している。フリップ・チップ接合
とは、チップの能動素子面(主面)を基板に向けて接続
する方式をいう。2. Description of the Related Art In recent years, with the development of process technology, the performance of semiconductor devices has been remarkably improved. As an interconnect technology that makes full use of the performance, instead of wire bonding technology, flip chip bonding technology has been adopted. The opportunities for application are increasing. Flip chip bonding refers to a method in which the active element surface (main surface) of a chip is connected to a substrate.
【0003】通常、最初にウエハの主面上に半田バンプ
を形成する。次に、ウエハの裏面をバックグラインド
(裏面研削)する。次に、ダイシングしてウエハを小片
(チップ)化する。チップを裏返して基板の位置に合わ
せた後、半田を溶かして電気的接続を得た後、最後に熱
硬化性樹脂でチップを封止する。Usually, first, solder bumps are formed on the main surface of a wafer. Next, the back surface of the wafer is back ground (back surface grinding). Next, the wafer is cut into small pieces (chips) by dicing. After the chip is turned over and aligned with the position of the substrate, the solder is melted to obtain an electrical connection, and finally the chip is sealed with a thermosetting resin.
【0004】バンプはチップの周囲だけでなく、チップ
の任意の位置に配置できるため、例えば100×100
マトリックスとした場合は1万個のI/O数が取れる。
また、小型携帯情報電子機器やICカード等の分野にお
いては、実装面積の小型化に加え、実装容積の低減が要
求され、チップ自体の薄型化の必要がある。Since bumps can be arranged not only around the chip but also at any position on the chip, for example, 100 × 100
In the case of a matrix, 10,000 I / O numbers can be obtained.
In the fields of small portable information electronic devices and IC cards, the mounting area is required to be reduced, and the mounting volume is required to be reduced.
【0005】チップの薄型化のためにウエハのバックグ
ラインドが重要な工程となる。従来、ウェハのバックグ
ラインドは、薄い接着層とベースフィルムの二層または
三層構造のテープを用いて、ウエハの補強とウエハの主
面を保護し実施されていた。また、電解の金バンプのよ
うに15〜30μmの高さのバンプを有するウエハでは
バンプ形成後に通常の2層または3層構造のテープを用
いてバックグラインドを行っていた。[0005] Back grinding of a wafer is an important step for thinning chips. Conventionally, back grinding of a wafer has been performed by using a tape having a two-layer or three-layer structure of a thin adhesive layer and a base film to reinforce the wafer and protect the main surface of the wafer. On a wafer having bumps of 15 to 30 μm in height, such as electrolytic gold bumps, back-grinding is performed using a normal two-layer or three-layer tape after bump formation.
【0006】[0006]
【解決すべき課題】30〜40μmまでの高さの半田バ
ンプを有するウエハでは、従来の方法でバックグライン
ドが可能であるが、100μm程度の高さのバンプを有
するウエハのバックグラインドでは、バンプのダメー
ジ、厚みおよび厚みむらの制御が困難であった。In a wafer having solder bumps having a height of 30 to 40 μm, back grinding can be performed by a conventional method. However, in a back grinding of a wafer having a bump having a height of about 100 μm, the back grinding can be performed. It was difficult to control the damage, thickness and thickness unevenness.
【0007】一方、チップと基板とのストレスを緩和す
るため高いバンプを用いるのが有利である。また、封止
用の樹脂の注入の容易性を向上するためにも、高いバン
プを用いる必要性が増大している。そこで、40μm以
上の高いバンプを有するウエハを均一にかつウエハを損
傷することなく、所定の厚みにバックグラインドするこ
とは重要な課題である。On the other hand, it is advantageous to use high bumps to reduce stress between the chip and the substrate. Also, in order to improve the ease of injecting the sealing resin, the necessity of using high bumps is increasing. Therefore, it is an important subject to back-grind a wafer having a high bump of 40 μm or more to a predetermined thickness uniformly and without damaging the wafer.
【0008】また、高いバンプを有する大口径のウエハ
を薄い接着層とベースフィルムからなる多層構造のテー
プを用いてバックグラインドすると、ウエハの厚みむ
ら、厚み制御性の低下、バンプの損傷が生じるという問
題点があった。Further, when a large-diameter wafer having high bumps is back-ground using a multilayer tape composed of a thin adhesive layer and a base film, unevenness in the thickness of the wafer, reduction in thickness controllability, and damage to the bumps occur. There was a problem.
【0009】このバンプ損傷の問題点を回避するため、
バックグラインド後にバンプを形成する方法があるが、
ウエハのハンドリングを考慮すると最終的な厚みに限界
があり、この方法ではチップ自体の薄型化を図れないと
いう問題点があった。In order to avoid the problem of bump damage,
There is a method of forming bumps after back grinding,
Considering the handling of the wafer, the final thickness is limited, and this method has a problem that the chip itself cannot be made thin.
【0010】したがって、本発明の一目的は、高さが4
0μm以上、特に100μm以上のバンプを有するウエ
ハを均一にかつウエハへの損傷がなく、目的の厚みにバ
ックグラインドが可能な半導体素子およびその製造方法
を提供することである。Therefore, one object of the present invention is to provide
An object of the present invention is to provide a semiconductor device capable of uniformly grinding a wafer having bumps of 0 μm or more, particularly 100 μm or more, without damaging the wafer, and capable of back grinding to a desired thickness, and a method of manufacturing the same.
【0011】さらに本発明の一目的は、ボンディング工
程においてチップをアライメントし、リフローするだけ
で、樹脂封止されたフリップチップ接合を容易に形成す
る半導体およびその製造方法を提供することである。It is still another object of the present invention to provide a semiconductor which can easily form a resin-sealed flip-chip junction simply by aligning and reflowing a chip in a bonding step, and a method of manufacturing the same.
【0012】さらに本発明の一目的は、大口径のウエハ
においても上記目的が達成可能な半導体素子およびその
の製造方法を提供することである。It is still another object of the present invention to provide a semiconductor device capable of achieving the above object even with a large-diameter wafer, and a method of manufacturing the same.
【0013】[0013]
【課題を解決するための手段】前記のおよびその他の目
的は、半導体素子であって、主面および裏面を有するウ
エハ(11)を用意する段階、ウエハの主面上の所定領
域にバンプ(21)を形成する段階(20)、ウエハの
主面上のバンプ間に樹脂(31)を塗布する段階であっ
て、樹脂をバンプの頂部が所定の厚み露出するように塗
布する段階(30)、ウエハの裏面を所望の厚みまで研
削する段階(50)、ウエハを小片化してチップ(7
1)とする段階(70)、基板(81)を用意する段階
およびチップを基板の所定の位置にアライメントし、リ
フローすることにより封止する段階(80)から構成さ
れることを特徴とする半導体素子によって実現される。The above and other objects are to provide a semiconductor device having a wafer (11) having a main surface and a back surface, wherein a bump (21) is formed in a predetermined region on the main surface of the wafer. Forming a resin (31) between the bumps on the main surface of the wafer, wherein the resin is applied so that the tops of the bumps are exposed to a predetermined thickness (30); Grinding the back surface of the wafer to a desired thickness (50);
A semiconductor comprising: (1) a step (70), a step of preparing a substrate (81), and a step (80) of aligning a chip at a predetermined position on the substrate and reflow-sealing the chip. Implemented by elements.
【0014】[0014]
【実施例】図1は、本願の一実施例による、ウエハ11
の断面図を示す。ウエハ11はチップの能動素子面(主
面)と裏面を有する。ウエハの口径は問わないが、大口
径(8インチ以上のウエハ)であっても本願は適用可能
である。FIG. 1 shows a wafer 11 according to one embodiment of the present application.
FIG. The wafer 11 has a chip active element surface (main surface) and a back surface. The diameter of the wafer is not limited, but the present invention is applicable to a large diameter wafer (8 inch or larger wafer).
【0015】図2は、図1の段階10のウエハ11の主
面上にバンプ21を形成した段階20を示す断面図であ
る。バンプの数は説明の簡略化のために数個とするが、
その数に限定はない。バンプの高さは40μm以上、さ
らには100μm以上が好適である。バンプの高さは、
ストレスの緩和、ウエハの信頼性、樹脂注入の容易性の
ためには高い程よいが、チップの薄型化、バンプの数が
制限されることを考慮すると120〜130μmが最も
好適である。バンプの材質は、一般的にはPb/Sn系
半田であるが、Au,Ni,Cuなどをコアとすること
も可能であり限定するものではない。さらにはSn/A
g,Sn/Bi等の鉛フリーの半田にも適用可能であ
る。半田バンプの接続方法はC4(Controlle
d Collapse Chip Connectio
n)あるいはCCB(Controlled Coll
apse Bonding)と呼ばれる方法が用いられ
るが、本願を限定するものではない。バンプの構造も本
願では特に限定されない。図3は、図2の段階20の基
板の主面上のバンプ間に樹脂31を塗布した段階30を
示す断面図である。樹脂の塗布は、共晶Pb/Sn半田
を用いる場合には、段階20の基板の主面上に183℃
以下、好適には150℃程度で可塑化する熱可塑性の樹
脂をバンプの頭が40μm以下程度露出するように塗布
する。塗布は、樹脂に十分な流動性を持たせるため、熱
可塑性樹脂をその溶融温度である240℃〜250℃ま
で加熱し、基板の主面上に滴下することにより行う。こ
のときバンプが溶けないように基板をバンプの融点(1
83℃)未満に保持することが望ましい。次に熱可塑性
樹脂をその可塑化温度以上であってバンプの融点未満
(150℃〜183℃)の高温で暫く放置する。このよ
うに温度を制御し、高温で放置することにより、熱可塑
性樹脂がバンプ上に被膜することなく基板の主面上に均
一に塗布することが可能である。熱可塑性樹脂とは、加
熱によって軟化成型した後、その外力を取り去ってもそ
の外形を保持している樹脂をいう。一般に、線状あるい
は分枝状の高分子からなる化学構造をもち、加熱により
分子間化学反応を起こさせない樹脂である。本願におい
て例えば、ポリエチレン,ポリスチレン,ポリ塩化ビニ
ル,ポリアドミなどを用いることができる。この樹脂
は、ウエハのハンドリングの際やバックグラインドの際
の補強材として働くとともにフリップ接合の際には封止
材として機能するものである。樹脂の可塑化温度の上限
は、バンプの材質により変更可能であり、バンプの材質
の融点以下であれば183℃に限定されない。バンプの
頭の露出する高さは、後述のボンディング段階でチップ
と基板の接合に適した厚みであれば40μmに限定され
るものではない。FIG. 2 is a sectional view showing a step 20 in which the bumps 21 are formed on the main surface of the wafer 11 in the step 10 in FIG. The number of bumps will be several for simplicity of explanation,
The number is not limited. The height of the bump is preferably at least 40 μm, more preferably at least 100 μm. The height of the bump is
The higher the value, the better the stress is, the reliability of the wafer, and the ease of resin injection. However, the thickness is most preferably 120 to 130 μm in consideration of the thinning of the chip and the limitation of the number of bumps. The material of the bump is generally a Pb / Sn-based solder, but Au, Ni, Cu or the like can be used as the core, and is not limited. Furthermore, Sn / A
It can be applied to lead-free solders such as g and Sn / Bi. The connection method of the solder bump is C4 (Controlle
d Collapse Chip Connection
n) or CCB (Controlled Coll)
A method called “apse bonding” is used, but the present invention is not limited to this method. The structure of the bump is not particularly limited in the present application. FIG. 3 is a cross-sectional view illustrating a step 30 of applying resin 31 between the bumps on the main surface of the substrate in step 20 of FIG. In the case of using eutectic Pb / Sn solder, the resin is applied at 183 ° C.
Hereinafter, a thermoplastic resin that is preferably plasticized at about 150 ° C. is applied so that the head of the bump is exposed to about 40 μm or less. The coating is performed by heating the thermoplastic resin to a melting temperature of 240 ° C. to 250 ° C. and dropping it on the main surface of the substrate so that the resin has sufficient fluidity. At this time, the substrate is set at the melting point of the bump (1
(83 ° C.). Next, the thermoplastic resin is left for a while at a high temperature that is equal to or higher than the plasticization temperature and lower than the melting point of the bump (150 ° C. to 183 ° C.). By controlling the temperature in this way and leaving it at a high temperature, it is possible to apply the thermoplastic resin uniformly on the main surface of the substrate without coating the bumps. The thermoplastic resin refers to a resin that retains its external shape even after removing its external force after softening and molding by heating. Generally, it is a resin having a chemical structure of a linear or branched polymer and not causing an intermolecular chemical reaction by heating. In the present application, for example, polyethylene, polystyrene, polyvinyl chloride, polyadmi, and the like can be used. This resin functions as a reinforcing material at the time of wafer handling and back grinding, and also functions as a sealing material at the time of flip bonding. The upper limit of the plasticization temperature of the resin can be changed depending on the material of the bump, and is not limited to 183 ° C. as long as it is lower than the melting point of the material of the bump. The exposed height of the bump head is not limited to 40 μm as long as it is suitable for bonding the chip and the substrate in the bonding step described later.
【0016】図4は、図3の段階30の樹脂31および
バンプ21上にテープ41を貼った段階40を示す断面
図である。テープは従来と同じベースフルムと接着層か
らなるテープを使用することができる。表面保護,バン
プの固定,テープの剥離の容易性のための特殊な多層テ
ープを用いる必要はない。本願では、樹脂を段階30に
おいて既に塗布してあるため樹脂が補強材として機能す
るため、テープはバックグラインドの際の表面を保護す
ることを主目的として貼るものである。FIG. 4 is a sectional view showing a step 40 in which a tape 41 is applied on the resin 31 and the bumps 21 in the step 30 in FIG. As the tape, a tape composed of the same base film and adhesive layer as in the related art can be used. It is not necessary to use a special multilayer tape for surface protection, fixing of bumps, and easy peeling of the tape. In the present application, since the resin has already been applied in step 30 and the resin functions as a reinforcing material, the tape is mainly applied to protect the surface during back grinding.
【0017】図5は、図4の段階40のウエハ11の裏
面をバックグラインドした段階50を示す断面図であ
る。段階20でバンプを形成済みであり、さらに段階4
0で、バンプは樹脂で十分に固定され、ウエハは補強さ
れているため、所望の厚みまでウエハをバックグライン
ドすることが可能である。従来技術では高いバンプを形
成した場合も、ウエハはテープのベースフィルム層で補
強されるのみなので、ウエハの厚みのむら、厚みの制御
性、バンプの損傷等の問題が発生し、350μmの厚み
ですら、うまく制御してバックグラインドすることがで
きなかった。一方、本願の一実施例では、8インチウエ
ハにバンプ高が130μmの半田バンプを形成した場合
であっても、樹脂が補強材として働くため、バンプを損
傷させることなく、均一の厚みで100μm程度までバ
ックグラインドすることが可能である。このように、高
さの高いバンプを用いても、ウエハを従来より薄くバッ
クグラインド可能なため、最終的には従来よりチップの
薄型化を図ることができる。FIG. 5 is a cross-sectional view showing a step 50 in which the back surface of the wafer 11 in step 40 of FIG. 4 is back ground. In step 20, bumps have been formed, and step 4
At 0, the bumps are sufficiently fixed with resin and the wafer is reinforced, so that the wafer can be back ground to a desired thickness. In the prior art, even when a high bump is formed, the wafer is only reinforced with the base film layer of the tape, so that problems such as uneven thickness of the wafer, controllability of the thickness, damage to the bump, and even a thickness of 350 μm occur. Couldn't backgrind with good control. On the other hand, in one embodiment of the present application, even when solder bumps having a bump height of 130 μm are formed on an 8-inch wafer, the resin acts as a reinforcing material, so that the bumps are not damaged and a uniform thickness of about 100 μm. It is possible to back grind. As described above, even if a tall bump is used, the wafer can be back-ground thinner than before, so that the chip can be finally made thinner than before.
【0018】図6は、図5の段階50にテープを剥離し
た段階60を示す断面図である。本願では従来のテープ
と同一のテープを用いても、バンプ間には樹脂を塗布し
てあるため、バンプを損傷することなく、テープを容易
に剥離することが可能である。ただし、紫外線感光層を
有するテープを用い、紫外線(UV)照射によりテープ
の剥離をさらに容易にすることも可能である。FIG. 6 is a cross-sectional view showing a step 60 in which the tape has been peeled in step 50 of FIG. In the present application, even if the same tape as the conventional tape is used, since the resin is applied between the bumps, the tape can be easily peeled without damaging the bumps. However, it is also possible to use a tape having an ultraviolet light-sensitive layer, and to further facilitate peeling of the tape by irradiation with ultraviolet light (UV).
【0019】図7は、図6の段階60をダイシング(小
片化)する段階70を示す断面図およびそのダイシング
後のチップ71の拡大断面図である。ダイシングは、ウ
エハを個々のチップの分離する工程である。図7では、
説明のため一方向のダイシングのみを示すが、X方向の
ダイシングが終了すると、ウエハを90°回転し、Y方
向のダイシングを行い、個々のチップの分離する。チッ
プ71は、ウエハ11に対し上下逆方向にして裏面を上
向きにした状態を示す。FIG. 7 is a sectional view showing a step 70 for dicing (slicing) the step 60 of FIG. 6 and an enlarged sectional view of the chip 71 after the dicing. Dicing is the process of separating wafers into individual chips. In FIG.
For the sake of explanation, only dicing in one direction is shown, but when dicing in the X direction is completed, the wafer is rotated by 90 °, dicing in the Y direction is performed, and individual chips are separated. The chip 71 is shown in a state in which the back surface of the chip 71 is turned upside down with respect to the wafer 11.
【0020】図8は、チップ71を基板81にフリップ
チップボンディングした段階90を示す断面図である。
ボンディング後、外部力や湿気、汚染物などの環境から
チップを保護する。従来技術では、この段階においてチ
ップ表面に熱硬化性樹脂を封止する。この熱硬化性樹脂
は一般低粘度の液体であり、毛細管現象を利用してチッ
プと基板の間に注入後、加熱して硬化させる。本願で
は、段階30において熱可塑性樹脂を予め塗布してあ
り、この熱可塑性樹脂は工程中の補強材として働くほ
か、封止材として機能する。従って、この段階において
チップに熱硬化性樹脂で封止する必要はない。バンプの
先端に半田ペーストを転写するか、基板上のフラックス
をディスペンスした後、チップをアライメントし、リフ
ローするだけで、樹脂封止されたフリップチップ接合が
容易に形成される。さらに、本願では熱可塑性樹脂を用
いるため、リフローの際、熱可塑性樹脂から露出したバ
ンプの頭部のみならず熱可塑性樹脂自身も柔らかくな
り、バンプにストレスをかけることなく樹脂封止が可能
である。FIG. 8 is a sectional view showing a stage 90 in which the chip 71 is flip-chip bonded to the substrate 81.
After bonding, the chip is protected from the environment such as external force, moisture, and contaminants. In the prior art, a thermosetting resin is sealed on the chip surface at this stage. This thermosetting resin is generally a liquid having a low viscosity, and is injected between the chip and the substrate by utilizing the capillary phenomenon, and then cured by heating. In the present application, a thermoplastic resin is applied in advance in step 30, and this thermoplastic resin functions as a reinforcing material during the process and also functions as a sealing material. Therefore, it is not necessary to seal the chip with a thermosetting resin at this stage. After transferring the solder paste to the tip of the bump or dispensing the flux on the substrate, the chip is aligned and reflowed, so that resin-sealed flip chip bonding is easily formed. Furthermore, since a thermoplastic resin is used in the present application, at the time of reflow, not only the head of the bump exposed from the thermoplastic resin but also the thermoplastic resin itself is softened, and the resin can be sealed without applying stress to the bump. .
【0021】[0021]
【発明の効果】本発明は、以下に記載されるような効果
を奏する。The present invention has the following effects.
【0022】本発明は、高さが40μm以上、特に10
0μm以上のバンプを有するウエハを均一にかつウエハ
への損傷がなく、目的の厚みにバックグラインドが可能
な半導体素子およびその製造方法を提供することができ
る。According to the present invention, the height is preferably 40 μm or more, particularly 10 μm.
It is possible to provide a semiconductor element capable of uniformly grinding a wafer having bumps of 0 μm or more without damage to the wafer and capable of back grinding to a desired thickness, and a method of manufacturing the same.
【0023】さらに本発明は、補強材と封止材を兼ねる
熱可塑性樹脂を用いることにより、ボンディング工程に
おいてチップをアライメントし、リフローするだけで、
樹脂封止されたフリップチップ接合を容易に形成するこ
とが可能である。Further, according to the present invention, by using a thermoplastic resin which also serves as a reinforcing material and a sealing material, alignment and reflow of a chip in a bonding step are performed.
It is possible to easily form a resin-sealed flip chip bonding.
【0024】さらに本発明は、大口径のウエハにおいて
も上記目的が達成可能である。Further, the present invention can achieve the above object even for a large-diameter wafer.
【0025】ここでは特定の実施例について本発明の構
造を説明してきたが、当該技術分野に通じたものであれ
ば本発明の構造を変形、変更することができるであろ
う。しかしながら、本発明の構造はここで開示された特
定の実施例に限定されるものではない。例えば、マッシ
ュルーム型,ストレートウォール型等のバンプの形状、
熱可塑性樹脂の種類についても特定を意図するものでは
ない。さらにソルダレジスト層やその他の保護層の形成
の段階等の説明は、説明の簡略化のために省略している
が、本願を限定する意図ではない。そのような記載のな
いフリップチップボンディングの製造工程は通常の方法
により行うものとする。そのような変形、変更されたも
のも本発明の技術思想の範疇であり、特許請求の範囲に
含まれるものである。Although the structure of the invention has been described herein with reference to specific embodiments, those skilled in the art will recognize that the structure of the invention may be modified or changed. However, the structure of the present invention is not limited to the specific embodiments disclosed herein. For example, bump shapes such as mushroom type and straight wall type,
It is not intended to specify the type of the thermoplastic resin. Further, description of the steps of forming the solder resist layer and other protective layers and the like are omitted for simplification of description, but are not intended to limit the present application. The manufacturing process of the flip chip bonding without such description is performed by a normal method. Such modifications and changes are also within the scope of the technical idea of the present invention, and are included in the scope of the claims.
【図1】本願の一実施例による、ウエハ11の断面図を
示す。FIG. 1 shows a cross-sectional view of a wafer 11 according to one embodiment of the present application.
【図2】図1の段階10のウエハ11の主面上にバンプ
21を形成した段階20を示す断面図である。FIG. 2 is a cross-sectional view showing a step 20 of forming bumps 21 on the main surface of the wafer 11 in step 10 of FIG.
【図3】図2の段階20の基板の主面上のバンプ間に樹
脂31を塗布した段階30を示す断面図である。3 is a cross-sectional view showing a step 30 of applying resin 31 between bumps on the main surface of the substrate in step 20 of FIG. 2;
【図4】図3の段階30のソルダレジスト層上にテープ
41を貼った段階40を示す断面図である。FIG. 4 is a cross-sectional view illustrating a step 40 in which a tape 41 is applied on the solder resist layer in the step 30 of FIG. 3;
【図5】図4の段階40のウエハ11の裏面をバックグ
ラインドした段階50を示す断面図である。FIG. 5 is a cross-sectional view showing a step 50 in which the back surface of the wafer 11 is back-ground in step 40 of FIG.
【図6】図5の段階50にテープを剥離した段階60を
示す断面図である。FIG. 6 is a cross-sectional view showing a step 60 in which the tape is peeled in step 50 of FIG. 5;
【図7】図6の段階60をダイシング(小片化)する段
階70を示す断面図およびそのダイシング後のチップ7
1の拡大図である。FIG. 7 is a cross-sectional view showing a step 70 of dicing (slicing) the step 60 of FIG. 6 and the chip 7 after the dicing.
1 is an enlarged view of FIG.
【図8】チップ71を基板81にフリップチップボンデ
ィングした段階80を示す断面図である。FIG. 8 is a cross-sectional view showing a stage 80 in which a chip 71 is flip-chip bonded to a substrate 81.
11 ウエハ 21 バンプ 31 熱可塑性樹脂 41 テープ 71 チップ 81 基板 11 Wafer 21 Bump 31 Thermoplastic Resin 41 Tape 71 Chip 81 Substrate
Claims (14)
る構造であって:前記チップと前記基板との間に電気的
導通を形成するための複数のバンプ(21);および前
記チップ,前記基板および前記複数のバンプ間に配置さ
れた熱可塑性樹脂(31);から構成されることを特徴
とするチップを基板に接合する構造。1. A structure for joining a chip (71) to a substrate (81), comprising: a plurality of bumps (21) for forming electrical continuity between the chip and the substrate; A structure for joining a chip to a substrate, comprising: a thermoplastic resin (31) disposed between the substrate and the plurality of bumps.
記裏面は、研削されていることを特徴とする請求項1記
載のチップを基板に接合する構造。2. The structure according to claim 1, wherein the chip has a main surface and a back surface, and the back surface is ground.
削することを特徴とする請求項2記載のチップを基板に
接合する構造。3. The structure for bonding a chip to a substrate according to claim 2, wherein said chip is ground to a thickness of less than 350 μm.
以下で可塑化することを特徴とする請求項1ないし3記
載のチップを基板に接合する構造。4. The structure for bonding a chip to a substrate according to claim 1, wherein the thermoplastic resin is plasticized at a melting point of the bump or lower.
有するウエハ(11)を用意する段階(10);前記ウ
エハの主面上の所定領域にバンプ(21)を形成する段
階(20);前記ウエハの主面上であって前記バンプ間
に熱可塑性樹脂(31)を塗布する段階であって、前記
熱可塑性樹脂をバンプの頂部が所定の厚み露出するよう
に塗布する段階(30);前記ウエハの裏面を所望の厚
みまで研削する段階(50);前記ウエハを小片化して
チップ(71)とする段階(70);基板(81)を用
意する段階;および前記チップを前記基板の所定の位置
に配置し、前記チップ,前記バンプおよび前記基板を前
記熱可塑性樹脂で封止する段階(80);から製造され
ることを特徴とする半導体素子。5. A semiconductor device comprising: preparing a wafer (11) having a main surface and a back surface (10); and forming (20) a bump (21) in a predetermined region on the main surface of the wafer. Applying a thermoplastic resin (31) on the main surface of the wafer and between the bumps, wherein the thermoplastic resin is applied such that a top of the bump is exposed to a predetermined thickness (30). Grinding the back surface of the wafer to a desired thickness (50); slicing the wafer into chips (71) (70); preparing a substrate (81); A step of disposing the chip, the bumps and the substrate in a predetermined position and sealing the chip, the bumps and the substrate with the thermoplastic resin (80).
以下で可塑化することを特徴とする請求項5記載の半導
体素子。6. The semiconductor device according to claim 5, wherein the thermoplastic resin is plasticized at a melting point of the bump or lower.
よび裏面を有するウエハ(11)を用意する段階(1
0);前記ウエハの主面上の所定領域にバンプ(21)
を形成する段階(20);前記ウエハの主面上であって
前記バンプ間に樹脂(31)を塗布する段階であって、
前記樹脂をバンプの頂部が所定の厚み露出するように塗
布する段階(30);前記ウエハを小片化してチップ
(71)とする段階(70);基板(81)を用意する
段階;および前記チップを前記基板の所定の位置に配置
し、前記チップ,前記バンプおよび前記基板を前記樹脂
で封止する段階(80);から構成されることを特徴と
する半導体素子の製造方法。7. A method for manufacturing a semiconductor device, comprising: providing a wafer (11) having a main surface and a back surface (1).
0); bumps (21) on predetermined areas on the main surface of the wafer
Forming (20); applying a resin (31) on the main surface of the wafer and between the bumps,
Applying the resin such that the tops of the bumps are exposed to a predetermined thickness (30); slicing the wafer into chips (71) (70); preparing a substrate (81); Disposing at a predetermined position on the substrate, and sealing the chip, the bumps, and the substrate with the resin (80).
間に樹脂(31)を塗布する段階(30)と、前記ウエ
ハを小片化してチップ(71)とする段階(70)の間
に前記ウエハの裏面を所望の厚みまで研削する段階(5
0)をさらに含むことを特徴とする請求項7記載の半導
体素子の製造方法。8. Between a step (30) of applying a resin (31) on the main surface of the wafer and between the bumps, and a step (70) of fragmenting the wafer into chips (71). Grinding the back surface of the wafer to a desired thickness (5).
8. The method for manufacturing a semiconductor device according to claim 7, further comprising:
0)は、熱可塑性樹脂を塗布する段階を含むことを特徴
とする請求項7および8記載の半導体素子の製造方法。9. A step of applying a resin between the bumps (3).
9. The method for manufacturing a semiconductor device according to claim 7, wherein 0) includes a step of applying a thermoplastic resin.
(30)は、 前記樹脂を加熱する段階;前記樹脂を
前記ウエハの主面上に滴下する段階;および前記ウエハ
を高温で保持する段階;を含むことを特徴とする請求項
7ないし9記載の半導体素子の製造方法。10. The step of applying a resin between the bumps (30): heating the resin; dropping the resin on a main surface of the wafer; and holding the wafer at a high temperature; 10. The method for manufacturing a semiconductor device according to claim 7, comprising:
点以下で可塑化することを特徴とする請求項7ないし1
0記載の半導体素子の製造方法。11. The method according to claim 7, wherein the thermoplastic resin is plasticized at a melting point of the bump or lower.
0. A method for manufacturing a semiconductor device according to item 0.
は、前記ウエハの厚さを350μm未満に研削すること
を特徴とする請求項8ないし11記載の半導体素子の製
造方法。12. The step of grinding the back surface of the wafer (50).
12. The method according to claim 8, wherein the thickness of the wafer is ground to less than 350 μm.
板を前記樹脂で封止する段階(80)は、それらを加熱
することを含むことを特徴とする請求項7ないし12記
載の半導体素子の製造方法。13. The method according to claim 7, wherein the step (80) of sealing the chip, the bump and the substrate with the resin includes heating them. .
/またはウエハの補強材として用いるフリップチップ接
合からなる半導体素子。14. A semiconductor device comprising flip-chip bonding using a thermoplastic resin as a sealing material and / or as a reinforcing material for a wafer.
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JP2004512684A (en) * | 2000-10-17 | 2004-04-22 | スリーエム イノベイティブ プロパティズ カンパニー | Solvent burnishing of pre-underfilled solder bump wafers for flip chip bonding |
KR100682238B1 (en) | 2004-12-30 | 2007-02-15 | 매그나칩 반도체 유한회사 | Method for fabricating module of semiconductor chip |
CN1333462C (en) * | 2003-07-11 | 2007-08-22 | 日东电工株式会社 | Laminated sheet |
JP2009260230A (en) | 2008-03-21 | 2009-11-05 | Hitachi Chem Co Ltd | Method of manufacturing semiconductor device |
US8035202B2 (en) | 2003-10-06 | 2011-10-11 | Nec Corporation | Electronic device having a wiring substrate |
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JP2004512684A (en) * | 2000-10-17 | 2004-04-22 | スリーエム イノベイティブ プロパティズ カンパニー | Solvent burnishing of pre-underfilled solder bump wafers for flip chip bonding |
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