JP4593162B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

 The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a built-in resistance element and a manufacturing method thereof.

Along with the downsizing competition among companies for devices, semiconductor devices such as transistors are also required to be ultra-miniaturized by forming peripheral components such as bias resistors on the same semiconductor substrate.
2. Description of the Related Art Conventionally, in an individual electronic component such as a transistor device incorporating at least one resistance element, in order to form a resistance element having a larger resistance value in a limited area semiconductor device part, the shape of the resistance element part is a current path. Has a meandering shape (a zigzag folded shape) that turns.

    9A to 9E are views showing a method for manufacturing a resistance element portion of a conventional semiconductor device in the order of steps. First, as shown in FIG. 9A, a silicon oxide film 11 is formed as an insulating film on a semiconductor substrate 10 in which an element region is formed, and then polycrystalline ( A poly) silicon film 12 is formed, and then N-type or P-type impurity ions 13 are implanted on the polycrystalline silicon film 12 as shown in FIG. 9B. Then, as shown in FIG. 9C, a resist film R1 is applied on the polycrystalline silicon film 12 and patterned into a desired shape by photolithography, and as shown in FIG. 9D, the resist film R1 is formed. A desired pattern is formed by selectively etching the polycrystalline silicon film 12 as a mask. Further, as shown in FIG. 9E, the resist film R1 is removed by ashing. Through the above steps, a resistance element portion formed of a polycrystal silicon pattern having a predetermined width and a zigzag shape is formed.

  In this semiconductor device, a pattern 12 of a predetermined width made of polycrystalline silicon is wired in a limited area of the semiconductor device 1 as shown in FIG. Yes. A pattern 12 is arranged in a zigzag pattern at a predetermined interval in a portion corresponding to the resistance element portion 2, and a desired resistance value is realized by an impurity concentration, a cross-sectional area and a length of the pattern 12.

  Here, the semiconductor device having the conventional resistance element has the following problems. FIG. 11 is a schematic view showing a current path of a resistance element portion of a conventional semiconductor device, and FIG. 11A shows a normal current path 22. FIG. 11B shows a state in which a high voltage such as static electricity is applied from the outside. As in the case where the resistance value of the virtual resistor 23 is small, the closest corner from the corner A without passing through the normal current path. Since the short circuit path 24 is formed and flows to the corner portion A ′, there is a problem that the semiconductor device causes surge destruction. Further, as shown in a perspective view of the resistance element portion in FIG. 12, the surge resistance and the distance between AA 'are related to the characteristics of the insulating oxide film, etc. As an improvement method, the distance between the corner portions AA ′ of the resistance element pattern may be increased. However, there is a limit to the area where the resistance element portion on the semiconductor device can be formed, and the pattern thickness t1 is increased. A method of narrowing the width t2 is also conceivable, but a new problem of reliability such as step breakage occurs. As a method for solving such a problem, for example, there is a technique described in Patent Document 1. According to Patent Document 1, a protrusion for forming a narrow gap is provided in a part of a resistance element portion on a semiconductor substrate. The presence of the protrusions discharges in the gap before surge breakdown occurs, thereby protecting the semiconductor device.

JP 08-316414 A

  However, in the example of Patent Document 1 as well, as a countermeasure when a high voltage such as static electricity is applied from the outside, in order to improve surge resistance so that the semiconductor device does not cause surge breakdown, a narrow gap is formed. However, since this structure is provided, the area occupied by the resistor element is increased, and the size of the semiconductor device itself is increased.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device capable of improving surge resistance without increasing the area occupied by a resistance element portion and a method for manufacturing the same.

In order to achieve this object, a semiconductor device of the present invention is a semiconductor device having a resistor pattern formed of a semiconductor layer, which is a corner edge portion of the resistor pattern and is closest to an adjacent pattern. A region of a reverse conductivity type is formed at a position to constitute a PN junction.
With this configuration, since the PN junction is formed in a portion where a short circuit is likely to occur, the short circuit is prevented by the barrier due to the PN junction. Further, since the corner edge portion is a region where the width of the current path increases, the resistance value of the resistor pattern is not increased by forming a PN junction here.

The semiconductor device of the present invention includes a semiconductor device in which the resistor pattern is a zigzag folded pattern and forms a PN junction at least at a position closest to the adjacent pattern.
With this configuration, a short circuit with an adjacent pattern is prevented.

In the semiconductor device of the present invention, the resistor pattern is a zigzag folded pattern and includes a semiconductor region having a reverse conductivity type so that a PN junction is formed on the entire periphery.
With this configuration, a short circuit from the peripheral edge is reliably prevented.

In the semiconductor device of the present invention, the resistor pattern includes a silicon conductive film pattern doped to a desired conductivity type.
According to this configuration, it is only necessary to introduce a reverse conductivity type impurity, so that it is easy to form a PN junction.

The semiconductor device of the present invention includes a semiconductor device that forms a PNP junction by forming a semiconductor region of a reverse conductivity type inside the outermost periphery of the corner edge portion.
According to this configuration, since it is possible to form two PN junctions by introducing impurities once, it is possible to obtain a semiconductor device that is easy to manufacture and has a high short-circuit prevention effect.

The method of manufacturing a semiconductor device according to the present invention includes a step of forming a first conductive type semiconductor layer on a semiconductor substrate on which an insulating film is formed, patterning the first conductive type semiconductor layer, and a resistor pattern And a step of forming a PN junction by forming a semiconductor layer of the second conductivity type in a corner edge portion of the resistor pattern and at a position closest to the adjacent pattern .
According to this method, it is possible to easily prevent a short circuit without increasing the area only by forming the semiconductor layer of the second conductivity type.

  In the method of manufacturing a semiconductor device according to the present invention, the step of forming the resistor pattern includes forming a semiconductor layer, forming a first resist pattern on the semiconductor layer, and using the resist pattern as a mask. Forming a resistor pattern by patterning a semiconductor layer into a desired shape; removing the first resist pattern; forming a second resist pattern; and implanting impurities using the second resist pattern as a mask And a step of forming a second conductivity type region at a corner edge portion of the resistor pattern.

  According to this method, a reliable short-circuit prevention function can be realized only by forming the second resist pattern and introducing impurities.

  In the method of manufacturing a semiconductor device according to the present invention, the step of forming the resistor pattern includes a step of forming a semiconductor layer, a first resist pattern is formed on the semiconductor layer, and the resist pattern is used as a mask. A step of patterning a semiconductor layer in a desired shape to form a resistor pattern; a step of heat-treating and shrinking the first resist pattern; and implanting impurities using the shrunk first resist pattern as a mask; And a step of forming a second conductivity type region on the periphery of the resistor pattern.

  According to this method, since the resist pattern for forming the resistor pattern is left as it is by heat treatment while the resist pattern remains, the second conductivity type region is formed using the contracted resist pattern as a mask. A PN junction can be formed over the entire periphery of the resistor pattern without requiring new mask alignment.

  As described above, according to the semiconductor device of the present invention, the semiconductor device includes a configuration in which a diode is formed to prevent a short circuit at an edge portion such as a corner portion of a resistance element pattern formed in a zigzag shape. The surge resistance of the semiconductor device against application of a high voltage such as static electricity can be improved without increasing the occupation area.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 shows a manufacturing process of a resistor pattern constituting a resistance element of a semiconductor device of the present invention.
This semiconductor device is characterized in that a diode is formed by forming a PN junction at the corner portion of the resistor pattern, and the formed diode acts as a barrier, and the current is formed by the resistor pattern. Therefore, the short circuit can be prevented.
This manufacturing method also includes a P-type impurity having a reverse conductivity type in a resistor pattern corner portion composed of an N-type polycrystalline silicon layer formed in a folded manner on a semiconductor substrate on which an insulating film such as a silicon oxide film is formed. And a step of ion implantation.

  First, as shown in FIG. 1A, base diffusion is performed on the surface of an N-type silicon substrate serving as a collector to form a P layer, and an N-type impurity serving as an emitter is implanted into the P layer to form an N layer. A silicon oxide film 51 and an N-type polycrystalline silicon film 52 are formed on the surface of the silicon substrate (semiconductor substrate) 50 by a CVD method to a thickness of 0.4 μm, for example.

  Next, as shown in FIG. 1B, a photoresist R1 is patterned on the polycrystalline silicon film 52. As shown in FIG. 1C, the polycrystalline R film is selectively polycrystalline using the photoresist R1 as a mask. The silicon film 52 is etched to form a resistor pattern.

  Next, as shown in FIG. 1D, a photoresist R2 is patterned on the polycrystalline silicon film 52, which is a patterned resistor pattern, and P-type (boron) impurities are ionized using the photoresist R2 as a mask. Implantation is performed to form a P-type region 53. As a result, the P-type region 53 is formed at the corner edge portion, thereby forming two PN junctions.

In this way, as shown in FIG. 1E, the photoresist R2 is removed and a resistor pattern is formed.
As described above, the resistance element pattern having the diode 32 at the corner edge portion of the resistor pattern is formed by the semiconductor device manufacturing method described above.

Next, FIG. 2 is a top view of the resistance element portion of the semiconductor device according to the embodiment of the present invention.
The resistor pattern has a zigzag shape, and a diode 32 is provided at the corner of the resistor pattern. In FIG. 2, the enlarged view of the corner part 30 is shown in FIG. In FIG. 3, the base is composed of N-type impurities. As shown in FIG. 3, a P-type impurity having a reverse conductivity type is applied to each corner portion of the resistor pattern made of N-type polycrystalline silicon and 5 to 20 μm from the corner portion end point 33 using the photoresist R2 as a mask. A P-type impurity region 31 is formed at a position of 5 by introducing it over a width of 5 to 15 μm using ion implantation. Thereby, two PN junctions are formed in the resistance element pattern corner portion, and the diode 32 is formed.

  The operation of the resistance element portion of the semiconductor device of the present embodiment configured as described above will be described with reference to the schematic diagram of FIG. As shown in FIG. 4, even when a high voltage is applied to the polycrystalline silicon film 52 constituting the resistor pattern, the diode 32 formed at the resistor pattern corner serves as a barrier, and the virtual resistance The resistance value of 36 becomes larger than the conventional one, and the flow of current along the resistance element pattern which is a normal current path can be promoted to prevent a short circuit. This action makes it possible to improve the surge resistance of the semiconductor device.

  In the above example, the resistor pattern is N-type. However, it is needless to say that the present invention can also be applied to a P-type resistor pattern. In the above embodiment, the example in which the resistor element is formed in the transistor has been described. However, the present invention can be applied to a semiconductor device in which the resistor element is formed in another semiconductor element such as a diode.

(Embodiment 2)
In the first embodiment, two PN junctions are formed at each corner edge portion. However, in this embodiment, as shown in FIGS. 5 and 6, a P-type region 31 is formed at the corner edge portion, One PN junction is formed at the corner edge portion to suppress an increase in occupied area. As is clear from the comparison between FIG. 1 (e) and FIG. 6 and the comparison between FIG. 3 and FIG. 5, a double PN junction is formed, whereas a single PN junction is formed. To do.

  In this structure, since the P-type region only needs to be formed on the outermost periphery, the area occupied by the diode is small. Furthermore, when the P-type impurity is implanted, the mask alignment of the resist pattern only needs to be performed on a part of the outer periphery of the corner portion, so that the mask alignment is easy.

However, when the P-type ions are implanted by deviating the resistor pattern due to the displacement of the mask, impurity ions are introduced into the silicon oxide film and may be slightly conductive.
Therefore, if the impurity concentration is reduced toward the outside, a short circuit due to doping of the silicon oxide film can be prevented.

(Embodiment 3)
In the first and second embodiments, the second resist pattern for forming the PN junction is formed again, but in this embodiment, the resist pattern used for forming the resistor pattern is not peeled off. It is used as it is, and is contracted by heat treatment to expose the outer peripheral portion of the original resistor pattern, and using the contracted resist pattern as a mask, the reverse conductivity type impurity region (P-type region 53: see FIG. 8). ), A PN junction, and a diode 32 over the entire outer periphery.

  This semiconductor device is characterized in that a diode is formed by forming a PN junction not only on the zigzag corner portion of the resistor pattern but also on the entire periphery of the resistor pattern, and the formed diode serves as a barrier. The current follows the path of the resistive element pattern and does not cause a short circuit.

FIG. 7 shows a manufacturing process of a resistance element pattern of this semiconductor device.
In addition, this manufacturing method is a P-type that has a reverse conductivity type over the entire outer periphery of a resistor pattern made of an N-type polycrystalline silicon layer formed in a zigzag shape on a semiconductor substrate on which an insulating film such as a silicon oxide film is formed. The method includes a step of ion-implanting impurities.

  First, as shown in FIGS. 7A to 7C, as in the steps of FIGS. 1A to 1C described in the first embodiment, polycrystal is selectively formed using the photoresist R1 as a mask. The silicon film 52 is etched to form a resistor pattern.

  Next, as shown in FIG. 7D, a heat treatment is performed on the polycrystalline silicon film 52, which is a patterned resistor pattern, with the photoresist R1 remaining, and the photoresist R1 is shrunk. P-type (boron) impurities are ion-implanted using the shrunk photoresist R1S as a mask to form a P-type region 53. As a result, the P-type region 53 is formed on the entire outer periphery of the resistor pattern, thereby forming a PN junction along the outer periphery.

In this manner, as shown in FIG. 7E, the photoresist R1S is removed, and a resistive element pattern is formed.
As described above, the resistance element pattern having the diode 32 on the entire outer periphery of the resistor pattern is formed by the semiconductor device manufacturing method described above. According to this configuration, it is possible to more reliably prevent a short circuit.

FIG. 8 is a top view of the resistance element portion of the semiconductor device according to the present embodiment.
The resistive element pattern has a zigzag shape, and a P-type region 53 is formed along the outer periphery of the resistor pattern to form the diode 32.

  In the above embodiment, polycrystalline silicon is used as the resistor pattern, but other silicon-based conductive films such as amorphous silicon may be used.

  Semiconductor device manufacturing method of the present invention Semiconductor device using it, without increasing the occupation area of the semiconductor device, without installing a new device for high static electricity countermeasures to the inspection device, insert machine, This is useful for improving the surge resistance of the semiconductor device when a high voltage is applied.

It is sectional drawing which shows the manufacturing process of the resistor pattern of the semiconductor device of Embodiment 1 of this invention. It is a top view of the resistance element part of the semiconductor device of Embodiment 1 of this invention. It is the top view to which the resistive element part of the semiconductor device of Embodiment 1 of this invention was expanded. It is a schematic diagram of the resistance element part of the semiconductor device of Embodiment 1 of this invention. It is the top view to which the resistance element part of the semiconductor device of Embodiment 2 of this invention was expanded. It is sectional drawing of the resistance element part of the semiconductor device of Embodiment 2 of this invention. It is sectional drawing which shows the manufacturing process of the resistor pattern of the semiconductor device of Embodiment 3 of this invention. It is the pattern figure seen from the upper surface of the semiconductor device of Embodiment 3 of this invention. It is sectional drawing which shows the manufacturing process of the resistor pattern of the semiconductor device of a prior art example. It is a top view of the conventional semiconductor device. It is a schematic diagram of the resistance element part of the conventional semiconductor device. It is a perspective view of the resistance element part of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2, 20 Resistance element part 3, 21 Pattern 10 Semiconductor substrate 11 Silicon oxide film 12 Polycrystalline silicon film R1, R2 Resist film 30 Corner part 31 P-type impurity 32 Diode 33, 34 Corner part end point 50 Semiconductor substrate 51 Oxidation Silicon film 52 Polycrystalline silicon film R1, R2 Photo resist 53 P-type region

Claims (8)

A semiconductor device having a resistor pattern formed of a semiconductor layer,
In the corner edge portion of the resistor pattern, a region of reverse conductivity type is formed at the closest position to the adjacent pattern ,
A semiconductor device configured to constitute a PN junction. The semiconductor device according to claim 1,
The resistor pattern, a semiconductor device which is a zigzag pattern. The semiconductor device according to claim 1,
2. The semiconductor device according to claim 1, wherein the resistor pattern is a zigzag fold pattern, and a reverse conductivity type semiconductor region is formed so as to form a PN junction over the entire periphery. The semiconductor device according to claim 1,
2. The semiconductor device according to claim 1, wherein the resistor pattern is a pattern of a silicon conductive film doped to a desired conductivity type. The semiconductor device according to claim 1,
A semiconductor device comprising a PNP junction by forming a reverse conductivity type semiconductor region inside the outermost periphery of the corner edge portion. Forming a semiconductor layer of a first conductivity type on a semiconductor substrate on which an insulating film is formed;
Patterning the first conductive type semiconductor layer to form a resistor pattern;
Forming a PN junction by forming a semiconductor layer of a second conductivity type at a corner edge portion of the resistor pattern and closest to the adjacent pattern . A method of manufacturing a semiconductor device according to claim 6,
The step of forming the resistor pattern includes:
Forming a semiconductor layer;
Forming a first resist pattern on the semiconductor layer, patterning the semiconductor layer in a desired shape using the resist pattern as a mask, and forming a resistor pattern;
After removing the first resist pattern, a second resist pattern is formed,
And a step of implanting an impurity using the second resist pattern as a mask to form a second conductivity type region at a corner edge portion of the resistor pattern. A method of manufacturing a semiconductor device according to claim 6,
The step of forming the resistor pattern includes:
Forming a semiconductor layer;
Forming a first resist pattern on the semiconductor layer, patterning the semiconductor layer in a desired shape using the resist pattern as a mask, and forming a resistor pattern;
Heat-treating and shrinking the first resist pattern;
And a step of implanting impurities using the shrunk first resist pattern as a mask to form a second conductivity type region at the periphery of the resistor pattern.

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