JP4577462B2 - Semiconductor heat treatment method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
Various heat treatments are performed in the semiconductor device manufacturing process. One of them is an activation annealing process after ion implantation. The present invention proposes an improved method of annealing after ion implantation. For example, annealing is required when fabricating a GaAs FET. The electron mobility of GaAs is considerably larger than that of Si. A GaAs-FET utilizing the high speed of electron mobility is used. Since GaAs has high electron mobility but low hole mobility, n-channel type FETs using electrons as carriers are mainly used.
[0002]
Unlike Si, genuine semiconductor GaAs is semi-insulating. This is an advantageous property for fabricating an FET. Semi-insulating GaAs is used as the GaAs FET substrate. An n-channel is formed on a part of the surface of the substrate, a drain region and a source region are formed at both ends of the channel, a drain electrode and a source electrode are provided, and a gate electrode is formed in the middle to form an FET element. Alternatively, an AlGaAs layer and a GaAs layer may be epitaxially grown on a GaAs substrate, a two-dimensional electron gas localized in a thin layer may be created using a difference in band gap, and the HEMT may be used as a carrier.
[0003]
In order to directly form an n-channel portion in a strip shape on a semi-insulating GaAs substrate, an n-type dopant may be thermally diffused and ion-implanted through a mask. Thermal diffusion increases the dopant concentration on the surface and is difficult to penetrate inside. Ion implantation is more suitable for forming a constant concentration n-type region. Therefore, an n-type dopant is ion-implanted in a strip shape to form an n-channel near the GaAs surface. For this purpose, Si ions are used. When Si ions are accelerated and implanted into GaAs and Ga in GaAs is replaced by Si ions, this becomes an n-type impurity and forms an n channel. However, only by ion implantation, the position of Si ions is still random and does not enter the Ga site. In addition, the GaAs lattice is also disturbed by ion implantation. Therefore, the lattice is repaired and Si is annealed to replace the Ga site. By applying heat, Si is an n-type impurity and the Si implantation region is an n-channel. The channel depth can be controlled by the ion implantation acceleration energy. The dopant density is determined by the current density of the ion beam and the implantation time.
[0004]
[Prior art]
Conventionally, a thin n-channel is formed by implanting Si ions at a low current density with an acceleration energy of about 100 keV or higher. However, higher speed GaAs-FETs have been demanded. In order to meet the demand for higher speed, a thinner n-channel is required. The FET principle is to control the current by forming a depletion layer in the n-channel with the voltage applied to the gate electrode and changing the size of the depletion layer. Therefore, the thinner channel is more suitable for higher speed. To make a thin channel, ions must be implanted with low acceleration energy. A Si layer having a steep density profile can be formed by low energy implantation. But don't just be thin. In order to obtain a sufficient current density at the time of ON, it is desirable that a high concentration carrier exists in the n channel. That is, it is necessary to implant an ion beam having a low energy and a high current density.
[0005]
In addition, it is necessary to suppress diffusion of ions by annealing.
Since annealing is a heat treatment, ions easily move and cause a diffusion motion that lowers the concentration difference. There is a possibility that the density distribution is averaged by diffusion and the steep concentration profile is lost. This is a problem. Annealing is an indispensable process for repairing the disorder of the GaAs lattice and fitting Si into the Ga site, but this always involves diffusion. Even if a thin Si injection layer is formed, if Si diffuses, it becomes a thick n-channel. If the channel is thicker than the design value, the speed cannot be increased and a leakage current is generated, which is disadvantageous.
[0006]
(1) Japanese Patent Application Laid-Open No. 62-114218 “Method of annealing compound semiconductor” (inventor: Toshio Nonaka, Seiichi Takahashi, Kenichi Kimura, Masahiro Ike, applicant; Oki Electric Industry Co., Ltd.) When annealing is performed by ion implantation, the problem is that crystal distortion occurs due to thermal strain. In particular, the generation of defects due to annealing is remarkable in a large-diameter GaAs wafer. In the conventional annealing, the temperature rise rate U and the temperature fall rate W are not controlled at all by simply specifying the annealing temperature Ta and the time t, so that crystal defects occur. In order to solve this problem, the GaAs substrate is heated in a temperature range in which arsenic is not dissociated at 400 ° C. to 600 ° C., the temperature is increased at a rate of U = 5 ° C./min to 15 ° C./min, and the annealing temperature Ta (800 C. to 900.degree. C.), for example, the temperature is kept for 20 minutes for annealing, and the temperature is lowered at a rate of W = -5.degree. C./minute to -15.degree. Si ions accelerated from 60 keV to 100 keV 10 ¹² -10 ¹³ cm ^-2 This is a dose amount of about.
[0007]
This is significant in that the range of the heating rate U and the cooling rate W is clearly defined. The rate of temperature change is clarified as 5 ° C./min to 15 ° C./min. The ion implantation energy is high and the implantation depth is deep. The thickness of the n channel is also large. Temperature change rate is slow. The rate of temperature change is uniform. dW / dt = 0, dU / dt = 0.
[0008]
(2) Japanese Patent Application Laid-Open No. 9-129570 “Semiconductor Device Manufacturing Method” (inventor: Akiyoshi Yoshida, applicant: Murata Manufacturing Co., Ltd.) describes that a slip is generated during annealing of a Si-implanted GaAs substrate. Try to prevent it. The Si ion-implanted GaAs is covered with a SiN film, placed in an infrared lamp annealing furnace, the substrate temperature is raised to 825 ° C. (850 ° C. in the figure) and held for 15 minutes, and 100 ° C./min or less, preferably 50 ° C./min The temperature is lowered to 300 ° C. at a temperature lowering rate of minutes. When the temperature was lowered at 200 ° C./min, many slip lines were generated, but at 100 ° C./min or less, there were few slip lines. The ion implantation energy is 150 keV and the dose is 5 × 10. ¹² cm ^-2 It is. This also means that the temperature drop rate after annealing is only 100 ° C./min or less, and the temperature drop rate is uniform and does not change the speed temporarily. Since the implantation energy is high, the implantation is deep and the n-channel thickness is large.
[0009]
(3) Japanese Patent Laid-Open No. 10-172777 “Method and apparatus for heat treatment of compound semiconductor substrate” (inventor: Yoshihiro Saito, applicant; Sumitomo Electric Industries, Ltd.) horizontally arranged six 3 inch GaAs wafers vertically Heat treatment is performed in an electric furnace, but helium gas is introduced to increase heat conduction and reduce the temperature difference between the central part and peripheral part of the wafer. The temperature difference between the inside and outside of the wafer is eliminated by the excellent heat conduction of helium so that no slip line is generated. Since six wafers are processed at a time, the relationship with the furnace is not necessarily uniform for each wafer. Therefore, He having excellent heat conduction is used. GaAs is annealed at 800 ° C. for 25 minutes, but the heating rate U is 30 ° C./min. The temperature decreasing rate is 100 ° C./min, and all are uniform. He also recommends the use of He in the case of lamp heating furnaces in addition to electric furnaces.
[0010]
In an electric furnace, a heater wire such as a Kanthal wire is wound around the furnace material to generate Joule heat, and the object is heated by infrared radiation from the furnace wall. Temperature change is slow due to the large heat capacity of the furnace material. In the case of lamp heating, a large number of lamps are arranged side by side on the upper, lower, left, and right sides of the furnace and optically heated by applying lamp light to the object. The heat capacity of the furnace material is irrelevant. Only the heat capacity of the object and the susceptor is relevant. So it is suitable for rapid heating. RTA (Rapid Thermal Annealing) is designed to enable rapid heating and rapid cooling by lamp heating. RTA is a known technique, for example
[0011]
▲ 4 ▼ H. Kohzu et al., “Infrared rapid thermal annealing for GaAs device fabrication”, J. Appl. Phys., Vol. 54 (9), p4998-5003 (1983) is Si-doped for GaAs-MESFET. We propose lamp annealing using halogen lamps for GaAs annealing. The Si-implanted GaAs wafer is heated by infrared by attaching 17 halogen lamps, 8 in the upper part and 9 in the lower part. The Si implantation energy is 100 keV and 150 keV. Until then, electric furnace annealing was performed over time, so it was necessary to prevent As from being lost. To prevent this, the wafer surface has SiO ₂ In other words, it was annealed with a SiN film. In the case of lamp annealing, heating is performed at a rate of 100 ° C./s, annealing is performed at 950 ° C. for 2 seconds, and then allowed to cool naturally. If lamp heating is started from 150 ° C., the temperature reaches 950 ° C. in about 7.5 seconds, is held for 2 seconds, and then is allowed to cool.
[0012]
The time from starting heating at 150 ° C., annealing, and returning to 150 ° C. by natural cooling is about 80 seconds and is extremely short. When the annealing time is 2 seconds, the optimum annealing temperature is about 900 ° C. In the case of 850 ° C., it should be kept for 10 seconds. The purpose of annealing is to replace the Ga site by the implanted Si and to recover the crystallinity. The results of annealing should be measured by the substitution of Si at the Ga site and the improvement in crystallinity. Here, the carrier concentration (electron concentration) is measured. When Si replaces the Ga site, one electron is generated. When Si replaces the As site, one electron disappears. A high electron concentration suggests that Si has replaced Ga. A value obtained by dividing the number of electrons by the amount of implanted Si is called an activation rate. This paper measures the effect of annealing by the activation rate (electrons / Si). Comparison is made between the case of annealing for 15 minutes in an electric furnace at 850 ° C. and the case of RTA at 950 ° C. for 2 seconds.
[0013]
When implanting at 150 keV, the RTA has a larger carrier concentration in the depth direction than the electric furnace annealing. The electron mobility also seems to be higher in the electric furnace annealing than in the RTA. When the implantation energy is 100 keV, RTA has a shallower carrier depth distribution than electric furnace annealing (FA).
[0014]
Thus, RTA is a general annealing technique. Regarding the annealing of GaAs, in addition to the above (1) to (3), there are the following documents by the present applicant.
[0015]
(5) Japanese Patent Application No. 9-42351 (Japanese Patent Laid-Open No. 9-321105) “Semiconductor Wafer Evaluation Method, Heat Treatment Method, and Heat Treatment Apparatus” (Inventor: Makoto Kiyama, Applicant: Sumitomo Electric Industries, Ltd.) Slip defects generated when epitaxial growth (600 ° C. to 700 ° C.), ion implantation, and activation annealing (800 ° C.) are performed on GaAs are a problem. When a GaAs wafer is heated during epitaxial growth and annealing, the temperature is not uniform inside and outside, and slip occurs in the peripheral portion. The slip surface is the (111) plane and the direction of deviation is [−110]. A 4-inch wafer is supported by a susceptor, and three concentric heaters are provided below the susceptor so that an arbitrary temperature distribution can be given in the radial direction of the GaAs wafer. An in-plane temperature distribution can be measured by a radiation thermometer that is provided with an opening above the furnace and can move two-dimensionally.
[0016]
It was examined whether slip occurred by giving various temperature differences Δ = T (0) −T (R) between the inside and outside of a 4-inch wafer. Slip is more likely to occur as the temperature difference Δ between the inside and outside increases, and as the temperature T (R) increases. Slip is likely to occur around the wafer. It may also occur in the center. Slip is unlikely to occur in the middle part. Slip at the periphery occurs when the stress σθ in the angular direction increases. Slip occurs even when Δ is positive (convex temperature distribution) or negative (concave temperature distribution). For example, when Δ is positive, tensile stress acts on the peripheral portion, and the occurrence of slip relaxes the tensile stress. The critical temperature difference at which slip occurs is a function of temperature Δ _c Obtained as (T). This is a function that decreases as temperature increases.
[0017]
The present invention clarifies when slip occurs in annealing of GaAs. However, this cannot be used for actual manufacturing. It is difficult to always monitor the temperature inside and outside the wafer in actual annealing. The apparatus is complicated and the operation becomes complicated. A furnace equipped with three internal and external resistance heating heaters is special for experiments. It is difficult to use such a furnace capable of precise control at the manufacturing site. When a lamp is used for this purpose, the lamp is outside the vacuum chamber, so it cannot be provided on the inside / outside of the wafer. The significance of the present invention is that slip occurs when annealing a Si-implanted GaAs wafer because of the temperature difference Δ between the wafer center and the periphery, and the critical temperature difference Δ _c Changes with temperature T, critical temperature change Δ _c (T) is given specifically.
[0018]
▲ 6 ▼ M. Kiyama, T. Takebe & K. Fujita, "Quantitative analysis of slip defect generation during thermal processes in GaAs wafers", Inst. Phys. Conf. Ser. No155, Chapter 12 presented at 23 rd Int. Symp. Compound Semiconductors, St Petersburg, Russia, 23-27 September 1996, p945-948 (1996)
This is a condition for determining the condition for occurrence of slip defects when a non-doped 4-inch GaAs wafer is heated. It is not doped with Si but non-doped SI (semi-insulating) -GaAs. Si ions are implanted into a 4-inch GaAs wafer for activation annealing, but triple concentric heaters (center heater, intermediate heater, and peripheral heater) are provided under the susceptor. The temperature distribution {T (r)} can be given freely in the radial direction. The actual temperature of the wafer is measured from above with a radiation thermometer. Since the radiation thermometer can move two-dimensionally, the temperature at an arbitrary part (r, θ) can be measured in a non-contact manner. The heater power is adjusted to give a convex temperature distribution or a concave temperature distribution. The temperature ranges from 400 ° C to 750 ° C. When the absolute value of Δ = T (0) −T (R) is large in both the convex temperature distribution and the concave temperature distribution, slip occurs in the peripheral portion. When Δ is positive (convex), the thermal stress in the angular direction of the peripheral portion is tensile stress σθ> 0. When Δ is negative (concave), the thermal stress in the angular direction of the peripheral portion is a compressive stress. While the absolute value of Δ is small, slip does not occur, but when this becomes large, slip occurs in the peripheral part. The allowable range in which slip does not occur is narrower as the temperature is higher.
Yield thermal stress σθ as a function of temperature _c (T), critical shear stress τ _c (T), critical slip temperature difference Δ _c Seeking. The outline will be described below.
In the experiment, it was found that the temperature distribution in the wafer surface can be approximated by a parabolic distribution in which the central part is hotter than the peripheral part. Therefore, assuming a parabolic temperature distribution, the thermal stress σθ in the angular direction around the wafer is a function of the temperature in the wafer surface.
[0019]
σθ (R) = αE (T (0) −T (R)) / 2 (1)
[0020]
Is given as follows. Where α is the coefficient of thermal expansion and E is the Young's modulus.
Since GaAs has anisotropy, slip occurs in the <110> / {111} sliding system (sliding in the <110> direction on the {111} plane). It is generally known that the relationship between the decomposition shear stress τ and σθ at this time is the relationship of τ = 0.493σθ, and using the equation (1),
[0021]
τ = 0.493 × αE (T (0) −T (R)) / 2 (2)
[0022]
It is indicated.
On the other hand, the critical shear stress τ at which slip is generated using the equation (2) from the experimental results of obtaining the slip generation conditions by changing T (0) and T (R). _c Is
[0023]
τ _c (T) = 2.3 × 10 ^-2 exp (0.38 eV / kT) MPa (3)
[0024]
I found out that Therefore, by calculating backward from the relationship of τ = 0.493 × σθ, the yield thermal stress when slip occurs (= σθ _c )
[0025]
σθ _c (T) = 4.6 × 10 ^-2 exp (0.38 eV / kT) MPa (4)
[0026]
It can be seen that The temperature difference Δ = T (0) −T (R) between the wafer central portion and the peripheral portion where slip occurs using the formula (1) again is the slip generation critical internal / external temperature difference Δ. _c It is. From equations (1) and (4),
[0027]
Δ _c (T) = 9.2 × 10 ^-2 exp (0.38eV / kT) / αE (5)
[0028]
Given in. Slip generation yield thermal stress (= σθ _c ) Is about 20 MPa at 450 ° C., about 7 MPa at 600 ° C., and about 3 MPa at 800 ° C.
Here, it is meaningful that the yield thermal stress of slip generation is obtained from an experiment as a function of temperature, and further clarified how much temperature difference in the wafer surface causes slip. However, the object is non-doped GaAs.
[0029]
[Problems to be solved by the invention]
In semiconductor devices such as Si and GaAs, it is often necessary to form a thin and steep doping layer. In particular, in a GaAs MESFET or HEMT, formation of a shallow, high-concentration and steep active layer has become indispensable for improving device performance. In the case of FET, an n-channel is formed in SI-GaAs, a source electrode and a drain electrode are attached to both ends thereof, and a gate electrode is provided in the middle through an insulating film. The n channel is formed by ion implantation of n-type impurities through a mask. A depletion layer is generated in the channel by the voltage applied to the gate electrode, and the current is controlled by changing the thickness of the depletion layer according to the magnitude of the gate voltage. In order to change the depletion layer rapidly in response to a change in voltage applied to the gate electrode, it is preferable that the channel thickness is small. The current cannot be taken only by being thin. To increase the current, it is necessary to increase the carrier density. In other words, a FET operating at high speed requires a thin channel with a high carrier concentration. As speed increases, the demand for channel thinning becomes increasingly severe.
[0030]
The channel thickness increases as the ion implantation energy increases. The carrier density of the channel is proportional to the ion beam current. In order to form a thin channel, the ion implantation energy must be lowered. In the conventional examples described so far, Si is implanted into GaAs with energy exceeding 100 keV, such as 100 keV or 150 keV. Of course, the implantation depth is deep. For example, in the case of (4) above, 150 keV, 5 × 10 ¹³ cm ^-2 When Si is implanted, the depth having the Si concentration peak is about 100 nm, and the Si-doped layer has a thickness of about 300 nm. 100 keV, 5 × 10 ¹² cm ^-2 When Si is implanted at a Si concentration of 10 ¹⁶ cm ^-3 If the above portion is regarded as the thickness, the thickness is about 300 nm. Both are channels with a thickness of several hundred nm.
[0031]
It is no longer such a thick channel that the present invention is directed to. A thin channel of 100 nm or less such as 50 nm or 70 nm is strongly required. Then the injection energy must be reduced by an order of magnitude. For example, low energy ion implantation such as 10 keV or 15 keV is performed. When implantation is performed with such a small energy, Si does not enter deep inside and is localized near the surface of GaAs. A Si concentration profile having a very steep gradient in the depth direction is formed.
[0032]
In the case of a process including ion implantation, a heat treatment called activation annealing is performed after the implantation. Since Si disturbs the GaAs lattice by ion implantation, it has the purpose of restoring crystallinity and the purpose of putting Si into the Ga site. This is a heat treatment at a high temperature of 800 ° C. or higher. During such high-temperature and long-time heat treatment, atoms implanted into the substrate (here, Si) and atoms in the epilayer (Si) diffuse. Even an implanted layer formed to a sharply bent concentration profile will be deviated by atomic diffusion during annealing. Anyone in the profile will result in degraded device performance. In the case of an FET, the desired thin channel is not obtained. It will be thicker. When the channel is thick, the time that the fluctuation of the gate voltage causes increase / decrease in the depletion layer is delayed. The operation speed as an FET decreases. Inward diffusion of impurities during annealing has been a problem even with the conventional one, but it becomes a more serious problem because the channel depth is shallow.
[0033]
Conventionally, Si was implanted into GaAs with an acceleration energy of 100 keV to 200 keV to form a channel of about 200 nm to 300 nm. For example, even if the Si concentration profile is expanded by 30 nm due to diffusion during annealing, the channel width is only increased by 10%. However, the channels required by current GaAs-FETs and HEMTs are extremely thin, such as 20 nm to 50 nm. For example, if the Si distribution is expanded by 30 nm inward due to diffusion, the channel width is increased about twice. This is a serious problem. Since the injection layer is originally thin, the influence is different even with the same diffusion amount.
[0034]
That is not all. In addition to being thin, the n-channel of the GaAs-FET must contain high concentration carriers. The diffusion length at time τ is (Dτ) ^1/2 Which does not include concentration. However, the speed of diffusion itself is proportional to the concentration. This is because the diffusion flow is j = −DδN / δz (N is the Si concentration, and z is the depth direction). Since a high concentration channel is formed, the amount of diffusion increases in proportion to the concentration N even if the diffusion coefficient D is the same. The effect of diffusion becomes more serious because it is a thin layer and has a high concentration. It is important to suppress diffusion during annealing.
[0035]
In order to maintain a steep concentration profile of implanted ions, atomic diffusion must be kept small during annealing. In order to suppress the atomic diffusion during the heat treatment, it is necessary to shorten the time during which the semiconductor wafer is exposed to a high temperature as much as possible. To that end, do not spend a long time for annealing. In that case, it is known that RTA, which is a short-time annealing capable of rapid temperature increase and decrease, is effective. It is heated by a lamp that emits infrared rays and has a small heat capacity, so it is suitable for rapid heating and rapid cooling. Therefore, RTA that can perform rapid temperature increase / decrease is often used for annealing Si-implanted GaAs.
[0036]
However, when the temperature is rapidly increased or decreased, a temperature difference is likely to occur between the central portion and the peripheral portion, particularly on a large-diameter substrate. Since heating and cooling are performed from the peripheral part, the temperature change in the central part tends to be delayed. That is, at the time of heating, the peripheral portion tends to be hotter than the central portion of the wafer. In the case of cooling, the central part tends to be hotter than the peripheral part of the wafer. As a result, a temperature difference occurs in the wafer surface. If the temperature difference within the wafer is excessive, wafer warpage or slip defects may occur.
[0037]
Due to warpage and slip, misalignment occurs during exposure. In particular, there has been a problem that the yield of device manufacturing is reduced in the peripheral area.
[0038]
In the case of increasing the temperature, there is a means for relaxing the temperature difference in the wafer. By optimizing the intensity distribution of the infrared lamp, the temperature difference between the center and the periphery of the wafer can be made more uniform. This is possible because of the positive heating.
[0039]
However, when the temperature is lowered, it is not allowed to be controlled by the lamp power because it is naturally cooled. Because of natural cooling, heat radiation from the wafer periphery is dominant. On the other hand, the loss due to heat conduction and radiation from the center cannot keep up. The greater the rate of temperature drop, the greater the temperature difference between the center and the periphery. It becomes difficult to make the temperature distribution uniform in the wafer plane. As a result, stress is generated in the wafer surface and the wafer is warped. In addition, slip transition occurs when stress exceeding the critical shear stress occurs. During exposure, a pattern shift occurs at the periphery of the substrate, and the yield of device manufacturing is reduced.
[0040]
Such a phenomenon appears particularly remarkably in GaAs. This is because the critical shear stress is smaller than that of Si and the thermal conductivity is low.
[0041]
Up to now, it has been explained that GaAs must be annealed after ion implantation in order to produce a GaAs FET by ion implantation of Si. It was stated that it is necessary to rapidly anneal so that Si does not diffuse during annealing. It was also explained that when a temperature change is applied rapidly, slip defects occur in the wafer and distortion occurs. Next, the results of actual investigation of residual strain and slip by RTA and electric furnace annealing of the Si-doped GaAs by the present inventor will be specifically described.
[0042]
[Si ion implantation into GaAs performed by the present inventors]
Si ions are applied to the entire surface of a 4-inch GaAs wafer at 10 keV, 1.5 × 10 ¹³ cm ^-2 Ion implantation at a density of When manufacturing an FET, ions are selectively implanted only into the channel portion using a mask, but here the ion implantation is performed on the entire surface because the purpose is to investigate residual strain and slip defects on the entire surface of the wafer. 10 keV is energy of 1/10 or less of the acceleration energy (100 keV to 150 keV) described as the conventional example. The Si ion concentration distribution is as thin as 20 nm to 30 nm from the surface. This was annealed by two methods of RTA (870 ° C., 2 seconds) and electric furnace annealing (800 ° C., 20 minutes).
[0043]
[1. Annealing by RTA (lamp heating)]
This Si-implanted GaAs wafer was subjected to activation annealing under the condition that it was held at a maximum temperature of 870 ° C. for 2 seconds using an RTA apparatus. The temperature was raised at a constant rate. The temperature was lowered by turning off the lamp and letting it cool naturally.
Wafer in-plane distortion before and after (here, | S _r -S _t (Only | was shown) was measured by the photoelastic method. This is to measure strain optically by utilizing the fact that the strain and birefringence of the crystal are proportional. Strain is the elongation divided by the original length. Multiplying the strain by the elastic modulus (Young's modulus, etc.) gives the force per unit area. Since the wafer is thin and rotationally symmetric, the radial strain S _r And tangential strain S _t (Thickness direction need not be considered). In the photoelastic method, the absolute value of the difference between the two strains | S _r -S _t I only know.
[0044]
FIG. 1 shows a residual strain before RTA treatment (left), a residual strain after RTA treatment (center), and a slip pattern (right) observed with a microscope. Residual distortion was expressed by a tone that continuously changed from white to black. The white background has no distortion. The surplus is 2 × 10 ^-5 Indicates. Residual strain is a dimensionless number because it is the elongation divided by the original length. When this is multiplied by the elastic modulus, it becomes a unit of pressure (MPa), but it is stress and not strain. Sometimes strain is expressed by stress, but both should be distinguished.
[0045]
Before RTA (left in FIG. 1), the residual strain is small at the center and the periphery. Residual strain is high in the middle part. This is a (100) wafer, which has an orientation flat (OF) on the hand side of the figure, which is the (011) plane. A portion having a large residual strain is formed in the [0 ± 10] and [00 ± 1] directions of the intermediate portion. The average in-plane residual strain is 4.75 × 10 ^-6 It is. Since no slip occurs before the heat treatment, the slip pattern is not shown.
[0046]
The residual strain (intermediate in FIG. 1) after performing RTA at 870 ° C. for 2 seconds increases as a whole.
Naturally, the distortion increases because of the heat. The center is darker. That is, the residual strain increases at the center. A much more significant difference is the increase in residual strain at the periphery. The largest residual strain is in the middle part. Since the residual strain increases as a whole, the average residual strain value is 6.47 × 10. ^-6 Has increased. The right end of FIG. 1 shows the slip pattern seen with a microscope. Several slips occur around the periphery. In any case, the surface where slip occurs is the {111} surface. The slip direction is a <110> direction orthogonal to the slip surface. Residual strain is 6.47 × 10 ^-6 Therefore, slip occurs and distortion occurs.
[0047]
[2. Electric furnace annealing (FA)]
The same Si-implanted GaAs wafer was subjected to activation annealing in an electric furnace under the condition of holding at a maximum temperature of 800 ° C. for 20 minutes. The temperature is raised at a constant speed, and cooling is performed by natural cooling.
[0048]
FIG. 2 shows the residual strain before the electric furnace annealing (left), the residual strain after the electric furnace annealing (center), and the slip pattern (right) observed with a microscope. Similar to FIG. 1, the residual strain was expressed by a tone that continuously changed from white to black.
[0049]
Before annealing (left of FIG. 2), the same characteristics as those before RTA in FIG. 1 are obtained because the same ion implantation is performed. The residual strain is small at the center and the periphery. Residual strain is high in the [0 ± 10] and [00 ± 1] directions at the intermediate portion ◇. The average in-plane residual strain is 4.75 × 10 ^-6 It is. Since no slip occurs before heat treatment, no slip pattern is shown.
[0050]
The residual strain (middle of FIG. 2) after performing FA (electric furnace annealing) at 800 ° C. for 20 minutes greatly increases as a whole. Naturally, distortion increases due to the application of heat, but the distribution is different from that before treatment. The center is whiter. That is, the residual strain is reduced at the center. The residual strain at the middle ◇ portion where the residual strain was large before annealing decreased. Near the center, there is a new portion where the residual strain is remarkably concentrated. Residual strain is greatly increased at the periphery. There is a feeling that the residual strain distribution is inverted before and after annealing. The average residual strain after annealing is 1.03 × 10 ^-5 It is. By annealing, it is increased more than twice. Even compared with the residual strain after RTA, it becomes 1.6 times. is increasing. A much more significant difference is the increase in residual strain at the periphery. The right end of FIG. 2 shows the slip pattern seen with a microscope. Despite the large residual strain at the periphery, no slip occurred. In the case of RTA, many slips are generated, but in the case of FA, there is almost no slip.
[0051]
In the case of electric furnace annealing, it is an advantage that slip does not occur despite prolonged heating. However, electric furnace annealing has other disadvantages. Since it heats for a long time, it means that Si ions diffuse and penetrate deep inside. When Si penetrates into the inside due to diffusion, a channel thicker than the designed value is formed. If the channel is thick, leakage current may occur. Moreover, the response speed as FET becomes low. That is, slip and distortion are not the only problems.
[0052]
[Distribution of Si atoms in the depth direction]
Therefore, the Si ion distribution profile in the depth direction of the wafer was examined by SIMS (Secondary Ion Mass Spectrography). This measures the amount of secondary ions that are ejected by implanting argon ions or the like onto the sample surface. When the amount of Si ions popping out as secondary ions is measured while etching the wafer surface, the Si concentration in the depth direction is obtained.
[0053]
FIG. 3 shows the profile in the depth direction of implanted Si ions obtained by SIMS for the wafer after RTA and the GaAs wafer after FA. The horizontal axis is depth (nm), and the vertical axis is Si ion concentration (cm ^-3 ).
Si concentration after RTA is 1.5 × 10 at the surface ¹⁸ cm ^-3 It is. 5x10 peak at 5nm depth ¹⁸ cm ^-3 To reach. Thereafter, the concentration decreases with depth. 1 × 10 at about 30 nm ¹⁸ cm ^-3 2 × 10 at 50 nm depth ¹⁷ cm ^-3 become. 1 × 10 at 61nm depth ¹⁷ cm ^-3 It becomes.
[0054]
Si concentration after electric furnace annealing (FA) is 1.5 × 10 at the surface ¹⁸ cm ^-3 It is. It becomes a peak at a depth of 4 nm, 3 × 10 ¹⁸ cm ^-3 To reach. Thereafter, the concentration decreases with depth. 1 × 10 at about 45 nm ¹⁸ cm ^-3 8 × 10 at 50 nm depth ¹⁷ cm ^-3 become. 1 × 10 at 70 nm ¹⁷ cm ^-3 It becomes.
[0055]
Comparing the two Si concentration distributions, it can be seen that Si atoms are diffused inward by electric furnace annealing. The definition of the channel width varies slightly depending on the carrier concentration of the non-doped GaAs substrate. Unlike Si-FETs, pn junctions are not possible, but the channel has a much higher carrier concentration than the substrate GaAs.
[0056]
For example, n ≧ 5 × 10 ¹⁷ cm ^-3 If n channel is defined, the RTA is about 40 nm, which is almost the same as the width in ion implantation. The result of FA is about 57 nm, which is 1.4 times larger than the distribution by ion implantation.
[0057]
Or, for example, n ≧ 2 × 10 ¹⁷ cm ^-3 If n channel is defined, the thickness by RTA is about 50 nm, which is almost the same as the width in ion implantation. The result of FA is about 63 nm, which is 1.3 times wider than the distribution by ion implantation. In other words, in this range, Si diffused 13 to 17 nm inward by electric furnace annealing (800 ° C., 20 minutes).
[0058]
If the ion implantation energy is as large as 150 keV and the Si concentration distribution is spread to about 300 nm, the channel width increase is only about 1.05 times even if it is diffused by about 15 nm. However, according to the present invention, Si is implanted at an extremely low energy to make an extremely thin channel, so even if the width is increased by slight thermal diffusion, the ratio increases.
[0059]
From these results, it can be seen that activation annealing by RTA can suppress the diffusion of implanted Si ions to a smaller extent than electric furnace annealing. This is because the annealing time is short. RTA is suitable for suppressing the Si diffusion and creating a shallow channel as designed. That is true, but as mentioned above, RTA also has drawbacks. The drawback can be seen by comparing the rightmost diagram in FIG. 1 (RTA) with the rightmost diagram in FIG. 2 (FA). RTA is more susceptible to distortion in the wafer surface during annealing than in electric furnace annealing. Therefore, RTA is more prone to slip and distortion than electric furnace annealing. RTA is suitable for preventing shallow Si diffusion, but electric furnace annealing is preferable for preventing slip and distortion.
[0060]
It is an object of the present invention to provide an improved annealing method that does not cause slip or distortion even by rapid annealing by RTA.
[0061]
[Means for Solving the Problems]
The present invention is characterized in that in the heat treatment including RTA in the semiconductor device manufacturing process, a standby step for temporarily stopping or decelerating the temperature change at the time of temperature decrease or temperature increase is provided. A standby step is provided when the temperature is lowered or raised, and the temperatures of the peripheral part and the central part are brought close to each other. The step may be inserted only once, but may be inserted twice or three times. In particular, it is effective to provide a standby step when the temperature falls. This is because the temperature difference between the inside and outside is more apparent when the temperature falls. Of course, a standby step may be provided even when the temperature rises.
[0062]
Here, the standby step is to temporarily stop or decelerate the temperature change of the wafer. Although it is possible to distinguish what completely stops the temperature change as a standby step and what decelerates it as a deceleration step, in the present invention, both are referred to as a standby step. This is because it is difficult to distinguish between the two. Since the lamp and heater power can be adjusted, they can be fixed at a fixed value. Such a case is called a standby step, and what reduces the power change can be called a deceleration step. However, it differs only in the mode of control variable change. The temperature change of the wafer cannot be fixed at a constant value. The stand-by step and the decelerating step do not change much in that the temperature change becomes slow. So there is no benefit in distinguishing both from the results. In the following, the standby step and the deceleration step may be distinguished, but there are places where both are referred to as the standby step.
[0063]
The wafer temperature is determined after the fact and cannot be directly controlled. The lamp output W is a variable that can be determined directly. The change in the wafer temperature is stopped by changing the lamp output, but it is necessary to determine the relationship. Therefore, it is necessary to determine the lamp output for giving the standby step by calculation or experiment in advance. The standby step during the temperature drop and the temperature rise correspond to a temperature sequence that is opposite to each other.
[0064]
It will be easier to understand when the temperature drops. Providing a standby step when the lamp is turned off and allowed to cool naturally (δT / δt <0) means that the lamp is temporarily turned on to heat the wafer. The temperature fluctuation is temporarily stopped (δT / δt = 0) or temporarily decreased (δT / δt ≧ 0) due to the balance between the heat supply from the lamp to the wafer and the heat radiation from the wafer to the surroundings. The lamp lighting time is t _n And turn off time t _f And Suppose this is repeated several times. Lighting time t _n ~ T _f Is equal to the length of the waiting step. This is simple, but how much lamp output will you make? This must be determined by experiment or calculation.
[0065]
When a standby step is inserted when the temperature rises, the lamp output is set such that the temperature rise is temporarily stopped or decelerated. Turn off the lamp or weaken the lamp output. The lamp cannot be weaker than turning it off. Therefore, depending on the temperature, it may be impossible to provide a standby step when the temperature is raised. Even in this case, it is possible to insert a deceleration step.
[0066]
The temperature difference in the substrate surface during RTA varies depending on the RTA furnace used and heat treatment conditions. It is necessary to design the conditions of the standby step at the time of raising and lowering the temperature according to the furnace and RTA conditions. Even if it is not a complete standby step in which δT / δt = 0 completely, a similar effect can be expected even in a temperature sequence (deceleration step) in which the temperature increase / decrease rate is temporarily reduced. The deceleration step must also be designed according to the furnace and RTA conditions.
[0067]
By applying the temperature sequence of the present invention including the standby step and the deceleration step, it is possible to suppress the occurrence of substrate distortion and slip even in heat treatment involving rapid temperature decrease and temperature increase. The rapid thermal treatment such as RTA can suppress the diffusion of various atoms forming the injection layer and the epi layer. Since the present invention provides a rapid heat treatment method free from slip and distortion, it can be expected to improve device manufacturing characteristics and yield.
[0068]
DETAILED DESCRIPTION OF THE INVENTION
Why do many slip defects occur in the periphery of the GaAs wafer after RTA (right column in FIG. 1)? This is a problem. In order to clarify the cause, thermocouples were embedded in the center and periphery of a 4-inch Si wafer. Center temperature T ₁ And ambient temperature T ₂ To know. This Si wafer is neither GaAs nor Si implanted. It is just a Si wafer. It is not the wafer itself in question. However, this is also useful for knowing the fluctuation of the temperature distribution in the wafer in RTA. Since Si has higher thermal conductivity than GaAs, GaAs should have a larger temperature difference than this result.
[0069]
This Si wafer was heat-treated by RTA. Lamp output W and wafer center temperature T ₁ And ambient temperature T ₂ FIG. 4 shows the result of measuring the change in time (t). The horizontal axis represents annealing time (seconds), and the vertical axis represents power and temperature. The alternate long and short dash line is the lamp power W, and the solid line is the center temperature T ₁ The broken line shows the ambient temperature T ₂ It is.
[0070]
The lamp output is a constant output in Iro and the wafer is heated to about 520 ° C. The temperature rise starts from about 520 ° C. (A). This is the temperature at which no diffusion occurs. When t = 5.7 seconds, the lamp power W is increased instantaneously as loha. The lamp power is increased at a constant rate from c to d (t = 21.4 seconds). Here, the lamp power is kept at a constant maximum value Niho for 2 seconds. Up to the point E (t = 23.4 seconds). The power is instantaneously dropped at the point of the ho. The same power is maintained from the point (t = 23.4 seconds) to the point (t = 26.8 seconds) for about 3 seconds. The power is reduced to the minimum value at the point. The same minimum power from the H point (t = 26.8 seconds) to the W point. The maximum power niho and the minimum power wrinkle are the maximum and minimum in this temperature sequence, not the maximum and minimum of the device performance.
Since it is a lamp output, it is easy to realize a rapid increase and decrease in power. Further, since the lamp is heated, the heat capacity is small, and the lamp power fluctuation is reflected in the wafer temperature change in a short time.
[0071]
From 520 ° C., A, B, and C, the wafer temperature rises rapidly and continuously. The maximum rate of temperature increase is + 21 ° C./second. The maximum temperature reaches 870 ° C. at point C (t = 25 seconds). This is the annealing temperature. The delay from the midpoint of the Niho point (t = 22.4 seconds) is only 2.5 seconds. The advantage of RTA is that the power fluctuation immediately leads to the wafer temperature fluctuation. Thereafter, the temperature decreases like CHJ. The average cooling rate is −6 ° C./second. There is a difference in speed between heating and cooling. Since the temperature is forcibly heated by a lamp, the temperature can rise rapidly. The temperature drop takes time because it is naturally allowed to cool and cannot forcibly remove the heat. The reason for slowing down the temperature is that it takes time to cool down.
[0072]
During temperature increase (ABC), the center temperature T ₁ And the ambient temperature T ₂ There is not much difference. The maximum temperature reaches 870 ° C. in about 25 seconds from the start. Thereafter (CHJ) the temperature decreases. When the temperature falls, a difference in temperature between the central part and the peripheral part appears. Since cooling is mainly performed by radiation from the periphery of the wafer or heat conduction, the temperature of the peripheral portion (shown by a broken line) first falls. A temperature difference clearly appears after 5 seconds from the start of temperature drop. There is an internal / external temperature difference of 17 ° C. at t = 45 seconds 20 seconds after the temperature starts to drop. In 60 seconds, there is a temperature difference of 23 ° C. At 75 seconds, there is still a temperature difference between 23 ° C and 23 ° C. Since it is naturally cooled, heat is released by radiation from the surroundings. Therefore, the temperature drop at the center tends to be delayed from the surroundings.
[0073]
When the temperature is raised, the peripheral portion of the wafer is heated before the central portion, but the temperature difference is small. However, there can be a difference in temperature between the inside and outside even when the temperature rises. In order to prevent this, the lamp is optimized, and a standby step (Iro) is provided in which the temperature rise is stopped at around 500 ° C. for 5.7 seconds. As a result, the temperature difference between the inside and outside at the time of temperature rise is kept small.
[0074]
However, when the temperature is lowered, the heat naturally escapes from the peripheral part because it is naturally cooled, and the peripheral temperature is lower (T ₁ > T ₂ ). When the temperature falls suddenly as in this case, the center T ₁ And peripheral part T ₂ The temperature difference increases. When the temperature is suddenly lowered, the temperature difference between the center and the periphery of the wafer is large, causing the wafer to warp or slip. Slip occurs when the decomposition shear stress at the sliding surface of the crystal caused by thermal stress exceeds the critical shear stress. Critical shear stress τ _c Is a function of temperature. The greater the temperature difference between the wafer center and the periphery, the greater the decomposition shear stress and the more likely slip occurs.
[0075]
In FIG. 4, it can be seen that there is a temperature difference between the central part and the peripheral part, but the temperature difference itself is difficult to understand. Therefore, the annealing time t and the internal / external temperature difference (Δ = T ₁ -T ₂ ) Is shown in FIG. 5 by a solid line.
[0076]
FIG. 5 shows a slip generation critical temperature difference Δ expected by a broken line. _c Is written as a function of t. It must be noted that it is a special expression. Since it is difficult to understand, I will describe it in detail. Original slip critical temperature difference Δ _c Is the wafer ambient temperature T ₂ Function Δ _c (T ₂ ) But here a function Δ of time t _c It is drawn as (t). Time t and wafer ambient temperature T ₂ Relationship T ₂ Since (t) is known in advance and has a relationship as shown in FIG. _c The function of time Δ _c (T ₂ (T)) can be written. It is a temperature profile T ₂ This is possible because (t) is determined, and the temperature profile T ₂ When (t) is different, the function is no longer as shown in FIG.
[0077]
Time t-slip generation temperature difference Δ as shown in FIG. _c To give this relationship: Time t and temperature T ₁ , T ₂ Is given by FIG. That is, T ₁ (T), T ₂ (T) is given. This is a different relationship depending on the temperature rise / fall profile. Temperature T ₁ And T ₂ By the critical shear stress τ _c Is decided. This is also described in the conventional examples (5) and (6). Equation (3) described in (6) is the critical shear stress τ _c It is itself. However, the value cannot be used in the present invention. Critical shear stress τ _c Depends on the crystal. There is a possibility that it may vary depending on the dopant and dose. (6) is specific to non-doped GaAs. _c Is given. Since the present invention targets Si-implanted GaAs, τ _c Is different. Τ as a function of temperature for the target Si-GaAs _c Must be obtained in advance.
[0078]
The values of the decomposition shear stress τ and the thermal stress σ are determined only after the surface on which the stress acts is determined. The thermal stress σ in any orientation is proportional to the decomposition shear stress τ in any orientation. The proportionality constant is only an angle, and the decomposition shear stress τ can be calculated from the thermal stress σ. The slip occurs on the {111} plane, and the direction of deviation is <011>. The resolving shear stress in that direction through the surface is important. Here, it will be discussed in terms of decomposition shear stress τ. Here, the decomposition shear stress is a force in the <110> direction acting on both sides of the {111} plane. Only the shear stresses in the other directions of the other surfaces are not important, so only this is considered. Since the plane and orientation are known, the tensor symbol to be attached to τ is omitted here.
[0079]
When the wafer is cylindrically symmetric and there is no internal strain, the decomposition shear stress τ is generally a function of only the internal and external temperature difference Δ. So τ (T ₁ -T ₂ ).
The decomposition shear stress will increase as the internal / external temperature difference Δ increases. On the other hand, critical shear stress τ _c Is larger as the temperature T is lower and smaller as the temperature is higher. Decomposition shear stress τ is critical shear stress τ _c Is equal to τ _c (T) = τ (T ₁ -T ₂ ), Critical shear stress τ _c Critical temperature difference Δ _c = (T ₁ -T ₂ ) _c Is a function of temperature T (T ₁ -T ₂ ) _c Obtained as (T). τ increases as Δ increases, and τ _c Decreases at higher temperatures, so τ = τ _c As shown in FIG. _c Should decrease with increasing temperature T. That's a little confusing, but that's it. This is the conventional example (5). (5) is the critical temperature difference Δ _c The temperature function Δ _c (T). The present invention also takes such a concept, but since the object is different, the function (5) cannot be adopted as it is. Since the present invention is a Si ion-implanted GaAs substrate, the temperature dependence Δ of the critical temperature difference is experimentally determined. _c (T) is obtained. With this alone, it is not possible to draw a graph as shown in FIG. This is because it is necessary to pull back to the time axis.
[0080]
When the annealing mode is determined (as shown in FIG. 4), the time t and the temperature T ₁ , T ₂ Relationship T ₁ (T), T ₂ (T) is determined. So critical temperature difference Δ that gives critical shear stress _c = (T ₁ -T ₂ ) _c Is obtained as a function of time t. Critical temperature difference Δ _c Is the temperature T ₂ Is low and the temperature T ₂ Is high and small. If you pull back to the time axis, the temperature will rise until t is 25 seconds. _c | Decreases. Since the temperature drops after 25 seconds, | Δ _c | Increases. This is the upper and lower critical temperature difference curve Δ shown by the broken line in FIG. _c ±. The upper and lower halves exist because Δ is positive (T ₁ > T ₂ ) Is also negative (T ₁ <T ₂ This is because a slip can occur in the same manner. Upper limb is Δ _c +, Lower leg is Δ _c -.
[0081]
Upper limb Δ of the critical temperature difference curve _c + Is high at the beginning (f) of annealing, decreases, and becomes the lowest at the highest temperature (T = 870 ° C., t = 25 seconds) (Y point). When the temperature falls thereafter (Yotareso), the temperature decreases and the critical temperature difference increases. Since the critical shear stress largely depends on the absolute value of the temperature difference between inside and outside, the upper limb Δ _c +, Baseline T ₁ -T ₂ = Lower limbs Δ folded back with respect to 0 _c -(Tsunenara) exists. The lower limb is initially a negative number with a large absolute value, but becomes a negative number (ne) with a small absolute value at the maximum temperature (T = 870 ° C., t = 25 seconds). When the temperature falls (Nenara), it becomes a negative number with a larger absolute value. Upper limb Δ _c + And lower limb Δ _c -The region between-is the thermal shear stress τ is the critical shear stress τ _c Is a smaller range. When the temperature at the time of temperature rise is low (T ₁ -T ₂ ) _c The distance between the upper and lower limbs is wide. When the temperature rises, the interval between the upper and lower limbs becomes narrower. It becomes the narrowest (between Yone) at the maximum temperature (T = 870 ° C., t = 25 seconds). After this, the critical temperature difference (T ₁ -T ₂ ) _c Will open.
[0082]
What has been described above is the critical temperature difference Δ _c Is a time change. Black dots and solid lines indicate temperature difference between inside and outside Δ = T ₁ -T ₂ The time change of is shown. At the beginning of heating (K; t = 0), the temperature at the periphery is high and the center is low, so Δ = T ₁ -T ₂ Is negative. The difference is about Δ = −4.2 ° C. until 13 seconds. As the temperature rises, the temperature difference between the inside and outside rises and falls below 0 at the point L (t = 21 seconds). The temperature difference becomes positive. When the maximum temperature of 870 ° C. is reached (M point; t = 25 seconds), the temperature difference at that time is as small as 2 ° C. Since natural cooling is started from now on, the temperature difference of the peripheral part opens and the temperature difference opens. It becomes 6 degreeC in t = 30 second.
[0083]
What is important is that the temperature difference Δ at the N point (t = 32 seconds) becomes the critical temperature difference Δ. _c It means crossing +. Δ = Δ at point N _c + = 7 ° C. Temperature T = 825 ° C. The internal / external temperature difference is 7 ° C., and the critical internal / external temperature difference is 7 ° C. at this temperature. Here, slip generation is allowed. After that, Δ is Δ _c Since it becomes larger, slip defects grow until thermal stress is relieved by the occurrence of slip. Δ = 17 ° C. in 45 seconds, Δ = 23 ° C. in 60 seconds (P point), and does not change much until the final point Q (t = 78 seconds, T = 570 ° C.). A state in which a slip can occur from point N (32 seconds) to point Q (78 seconds) continues for a long time. From these considerations, it is presumed that slip defects started to occur in the vicinity of 850 ° C. to 750 ° C. at the time of temperature drop.
[0084]
How can I suppress the occurrence of slips? Wafer center temperature T ₁ And ambient temperature T ₂ The difference between the two should not be too large. Especially when the temperature is high, the temperature difference (T ₁ -T ₂ ) Must not be large. In particular, it is sufficient if the temperature difference between the inside and outside can be reduced when the temperature falls. This is the presentation of the problem to be solved by the present invention. It has been quantitatively understood that the temperature difference between the inside and outside should be reduced and how much it should be reduced. Here is a break. Although (5) and (6) described as conventional examples are both in the hands of the applicant, a truly direct method is adopted in order to reduce the temperature difference between the inside and outside of the wafer. (5) and (6) are a radiation thermometer that two-dimensionally measures the temperature distribution in the plane of the wafer, and a heater H that has a triple concentric circle inside and outside. ₁ , H ₂ , H ₃ Is provided. The temperature T (x, y) throughout the wafer is repeatedly obtained with a radiation thermometer, and when a temperature difference between the inside and outside of the wafer occurs, the heater power close to the low temperature region is increased, and the heat at the higher temperature portion is increased. Lower the power. A combination of temperature measurement and heater power adjustment is intended to strictly control the temperature change. However, to do so, it is necessary to provide three types of heaters concentrically. In addition, the temperature must always be measured from above with a radiation thermometer. Providing heaters in the inner and outer triples is not applicable to lamp heating. Above all, the structure becomes too complicated. You can't measure with just one thermocouple.
[0085]
[Control method of the present invention]
Simpler equipment and simpler control are desirable. The present inventor has come up with the idea that the temperature decrease is temporarily stopped (standby step) or the temperature decrease rate is decreased when the temperature is decreased (or when the temperature is increased).
(A) At the time of temperature rise; Temporarily stop the temperature rise at the time of the temperature rise or decrease the temperature rise rate. Center temperature T ₁ Is the ambient temperature T ₂ It will be averaged from catching up to. The temperature rise can be stopped and the temperature rise can be reduced by reducing the lamp power. It may be effective to turn off the lamp. In the standby step at the time of temperature increase, how many times (T _s ? ) Is one of the problems. Length of time to stop temperature rise (t _s ? ) Is another problem.
(B) When the temperature is lowered; Temporarily stop the temperature drop or lower the temperature drop rate when the temperature is lowered. Center temperature T ₁ Is the ambient temperature T ₂ It will be averaged from catching up to. When it is allowed to cool naturally, the lamps and heaters are temporarily turned on and heated. As the heating and cooling are balanced, the snow can pause the temperature drop (standby step). Even if heating is not exactly balanced, the temperature lowering rate can be temporarily reduced (deceleration step). The standby step and the deceleration step can be provided not only in the case of natural cooling but also in the case of cooling while heating the lamp. Also in the case of temperature drop (T _s ) Do you stop cooling? How many seconds to stop (t _s ) Problem.
[0086]
Slip generation can be prevented by inserting a standby step and a deceleration step into the temperature sequence regardless of whether the temperature is lowered or raised. The following two points are noted in the design of the temperature sequence of the present invention.
(1) A standby step is provided in the vicinity of a temperature range where slip occurs.
(2) The waiting step time is made as short as possible.
[0087]
In order to suppress the diffusion of the implanted Si ions, it is necessary to shorten the time during which the wafer is exposed to a high temperature as much as possible. When Si diffuses, the channel width increases and a leakage current of the FET is generated. If a waiting step is provided, the diffusion time increases accordingly, and diffusion increases. Therefore, it is better that the waiting step is short. This is where condition (2) requires. It's not just a short one. There is no point in providing a standby step at a temperature at which slip occurs. This is what Condition (1) says. The temperature at which slip occurs is τ _c It is a temperature at which (T) is particularly lowered. The temperature range where slip is likely to occur is simply τ _c This is a time when not only (T) but also the temperature difference between the inside and outside is accumulated and increased when the temperature is lowered and when the temperature is raised. The problem (2) will be further described. The diffusion distance of Si ions in GaAs is given by the following equation.
[0088]
Δd = (Dτ) ^1/2 (6)
[0089]
Here, D is a diffusion coefficient and is a function of temperature. The higher the temperature, the greater D. τ is the time exposed to the temperature. The diffusion coefficient has the following form.
[0090]
D = D ₀ exp (-E / kT) (7)
[0091]
For diffusion of Si in GaAs, D ₀ = 0.7cm ² / S, E = 3.2 eV. this is
[0092]
▲ 7 ▼ Ddandandandy, Satoshi Matsumoto “Effect of melt stoichiometry on Si diffusion in LEC semi-insulating GaAs” (1988, Spring Society of Applied Physics, 28p-ZE-10, p943)
It is the value published in. In other words, the diffusion coefficient of Si in GaAs is
[0093]
D = 0.7exp (−3.2 / kT) (8)
[0094]
That's what it means. k is the Boltzmann constant and T is the absolute temperature. The annealing that is now a problem is a heat treatment that is held at 870 ° C. for 2 seconds. Ion travel distance Δd occurring at maximum temperature ₀ Can be obtained from (6) and (8). This is Δd ₀ = 1 nm. The size of the standby step that is given when the temperature is lowered is the diffusion length Δd of Si ions that occur in the meantime. _s Can be evaluated by. It is better not to spread as much as possible in the waiting step. Diffusion length Δd at standby step _s Is the diffusion length Δd at the maximum temperature ₀ About 20% or less (Δd _s ≦ 0.2Δd ₀ ).
[0095]
For example, assume that a standby step is provided at 750 ° C. That time t _s Is the diffusion length Δd in equation (6) _s = 0.2Δd ₁ Can be calculated as τ such that = 0.2 nm. Then the waiting step time is t _s = 4 seconds or less.
[0096]
【Example】
Same conditions (10 keV, 1.5 × 10 2 for 2 GaAs 4 inch wafers) ¹³ cm ^-2 ) Was implanted with Si ions. One was annealed with normal RTA, and the other was RTA annealed with a standby step, and an experiment was conducted to compare the two.
[0097]
[RTA] RTA annealing is performed at 870 ° C. for 2 seconds.
[0098]
[Standby Step] The standby step is to hold at 750 ° C. for 4 seconds.
[0099]
A. For samples that do not perform a waiting step
The strain before RTA, the strain after RTA, and the slip pattern were as shown in FIG. The residual strain before RTA is small at the center and the periphery and large at the middle ◇. The average residual strain is 4.75 × 10 ^-6 It is. Residual strain after RTA increases at the periphery, and the average is 6.47 × 10 ^-6 Met. There are many slips around the periphery.
[0100]
B. Samples with a waiting step
Wafer center temperature T when RTA including standby step is performed ₁ , Peripheral temperature T ₂ FIG. 8 shows the time change of the lamp power W. Start at around 520 ° C. The lamp output is constant and constant. At t = 5.7 seconds, the power is instantaneously increased to a high level. The power is increased uniformly from 2 to 21.4 seconds. Keep the same power up to the point of 23.4 seconds. Reduce the lamp power to point F (26.8 seconds) at point E. A constant power is used between the guts. At the point (26.8 seconds), the power is further reduced to a constant value (Tochi). The power is constant from the point H to the point (41.4 seconds). At the point, the power suddenly increases like Rinu. This is maintained for 3 seconds until the point (44.5 seconds). The power is instantly reduced from the point to the point. After that, keep the minimum power until wow. Rinulwo is the waiting step. The lowest power can be completely extinguished. The waiting step includes Iro and Heto, but what is newly added here is the portion of Rinulwo. Here, the lamp power temporarily increases. This reduces the temperature difference between the inside and outside of the wafer. No slip occurs because the temperature difference decreases. The decrease in temperature difference is the center temperature T ₁ , Ambient temperature T in broken line ₂ You can see by looking at It can be seen from the temperature variation between the EFs that there is no benefit in distinguishing between the standby step and the deceleration step. Since the power is constant between nulls, it will be called a standby step. However, the wafer temperature is not constant at EF. In other words, this is a deceleration step. It does not matter whether the power is a step (δW / δt = 0) in terms of influence on the wafer.
[0101]
From 520 ° C., A, B, and C, the wafer temperature rises rapidly and continuously. The maximum rate of temperature increase is + 21 ° C./second. The maximum temperature reaches 870 ° C. at point C (t = 25 seconds). This is the annealing temperature. The delay from the midpoint of the Niho point (t = 22.4 seconds) is 2.6 seconds. Since the lamp power is kept constant for 2 seconds when the wafer reaches 870 ° C., annealing at 870 ° C. for 2 seconds is called. Thereafter, the CD and wafer temperatures decrease. The descending speed is faster in the peripheral part (broken line) than in the central part (solid line).
[0102]
The effect of increasing the lamp power such as “Rinulwo” appears immediately in the portion of the wafer temperature curve EF. The rate of wafer cooling is decreasing. It can be seen that the temperature decreasing rate is not 0 but is decreasing. The important thing is that in the EF part, the temperature drop in the central part has come closer to the temperature drop in the peripheral part. Temperature difference Δ at E _E Temperature difference at F _F Is small (Δ _E > Δ _F ). At point F, the temperature starts decreasing from the reduced temperature difference. This is equivalent to reducing Δ like OR at point O of the Δ curve in FIG. Δ is the critical temperature difference Δ _c Pulled downward (point R). Thereafter, the temperature difference Δ increases, but Δ _c The final point S is reached without exceeding. That is, Δ (RS) <Δ _c Can be maintained. There is a slight risk of slippage from the maximum temperature N to O. However, slip does not always occur during that time. Rather, there is a high probability that slip will occur between the subsequent OQs. The possibility of slippage between OQs can be eliminated by the waiting step. Therefore, almost no slip occurs on the wafer after the RTA process. This is the effect of the waiting step.
[0103]
Of course there are disadvantages. Since the standby step is provided, it takes extra time to cool down. The average cooling rate at DEFG is −4.7 ° C./second. The time for the temperature to drop from 870 ° C. to 600 ° C. is 6 seconds longer. The increase in the temperature lowering time is not the same as the waiting step time (here, 4 seconds).
[0104]
FIG. 6 shows a strain before RTA and a strain slip pattern after RTA for the same sample subjected to RTA in a temperature sequence including a standby step. Before RTA, the residual strain is small at the center and the periphery and large at the middle ◇. The average residual strain is 4.69 × 10 ^-6 Met. The residual strain distribution after RTA is similar to that before RTA. Distribution that there is little residual strain is maintained in the central part and the peripheral part. The average residual strain is 4.53 × 10 ^-6 It is. The residual strain did not increase due to the waiting step. The effect is even more pronounced if you look at the slip pattern. No slip defects have occurred at the periphery of the wafer. There was no wafer warp.
[0105]
If the diffusion progresses by the waiting step, the effect is reduced. Therefore, the Si concentrations of Sample A (without standby step) and Sample B (with standby step) after RTA were measured by SIMS. FIG. 7 shows the result. The sample B with the waiting step seems to be slightly shifted to the right in the distribution, but it is not so, and since the total amount of Si is large, the distribution is in the upward direction as a whole. Therefore, it can be seen that the diffusion of Si into the back by the standby step is slight.
[0106]
C. When there is a faster standby step
Since the sample of B starts the standby step from 41 seconds, there is a possibility that slip occurs between NO in FIG. 5 a little later. In FIG. 5, Δ is Δ _c Is t = 32 seconds, so if a standby step is provided between 870 ° C. and 2 seconds hold t = 26 seconds and 32 seconds, Δ <Δ _c It can be. For example, a shorter standby step may be provided in 29 seconds to 32 seconds (850 ° C. to 830 ° C.). Then, as shown in FIG. 9, always Δ <Δ _c You can do that. In FIG. 9, 30 to 45 seconds, Δ is Δ _c It is approaching, but this is not exceeded. In this case, the possibility of occurrence of slip becomes zero. Naturally, the residual strain is also reduced and the wafer is not warped.
[0107]
【The invention's effect】
The present invention provides a standby step for temporarily stopping or decelerating the temperature change in the heat treatment including rapid temperature rise / fall of the semiconductor. Ambient temperature T ₂ And center temperature T ₁ , The thermal stress inside the wafer is reduced. Therefore, the wafer is not warped and the occurrence of slip is reduced. The yield at the time of device manufacture can be raised.
The device performance can still be improved.
[Brief description of the drawings]
FIG. 1 shows 1.5 × 10 at 10 keV on a 4 inch (100) GaAs wafer. ¹³ cm ^-2 FIG. 6 is a diagram of residual strain in a wafer immediately after implantation of Si ions, a distribution diagram of residual strain after RTA at 870 ° C. for 2 seconds, and a diagram of a slip pattern in the wafer surface. Residual strain is 0 for white, 2 × 10 ^-5 Is represented in black. Slip occurs on the {111} plane at the periphery of the wafer and slides in the <110> direction.
FIG. 2 shows 1.5 × 10 at 10 keV on a 4 inch (100) GaAs wafer. ¹³ cm ^-2 FIG. 5 is a diagram of residual strain in a wafer surface immediately after implantation of Si ions, a distribution diagram of residual strain after annealing at 800 ° C. for 20 minutes, and a slip pattern in the wafer surface. Residual strain is 0 for white and 2 × 10 ^-5 Is represented in black. Slip occurs on the {111} plane at the periphery of the wafer and slides in the <110> direction.
FIG. 3 shows 1.5 × 10 at 10 keV on a 4-inch GaAs wafer. ¹³ cm ^-2 FIG. 7 is a measurement diagram of Si atom concentration distribution in the depth direction for a wafer subjected to RTA at 870 ° C. for 2 seconds and a wafer subjected to electric furnace annealing at 800 ° C. for 20 minutes after implantation of Si ions. The horizontal axis is the depth from the surface (nm), and the vertical axis is the Si atom concentration (cm ^-3 ).
FIG. 4 shows 1.5 × 10 at 10 keV on a 4-inch GaAs wafer. ¹³ cm ^-2 After implantation of Si ions, the temperature T at the wafer center when RTA is performed at 870 ° C. for 2 seconds. ₁ (Solid line) and surrounding temperature T ₂ The graph which shows the time change of (dashed line). The horizontal axis represents annealing time (seconds), and the vertical axis represents temperature (° C.).
FIG. 5 shows 1.5 × 10 at 10 keV on a 4-inch GaAs wafer. ¹³ cm ^-2 After implantation of Si ions, the wafer center temperature T when RTA is performed at 870 ° C. for 2 seconds. ₁ And ambient temperature T ₂ Difference (T ₁ -T ₂ ) Over time and slip critical temperature difference (T ₁ -T ₂ ) _c The graph which shows the time change of. The horizontal axis represents the annealing time (seconds), and the vertical axis represents the temperature difference (° C.).
FIG. 6 shows 1.5 × 10 at 10 keV on a 4-inch GaAs wafer. ¹³ cm ^-2 Of residual strain immediately after implantation of Si ions, distribution diagram of residual strain of wafer when RTA is performed at 870 ° C. for 2 seconds and a waiting step of 4 seconds is provided at 750 ° C., and in-plane slip Pattern illustration. Residual strain is 0 for white, 2 × 10 ^-5 Is represented in black.
FIG. 7 shows 1.5 × 10 at 10 keV on a 4-inch GaAs wafer. ¹³ cm ^-2 After the implantation of Si ions, a wafer subjected to RTA at 870 ° C. for 2 seconds (no standby step) and a wafer provided with a standby step of 4 seconds at 750 ° C. in the post-cooling process at 870 ° C. for 2 seconds FIG. 6 is a measurement diagram of Si atom concentration distribution in the depth direction. The horizontal axis is the depth from the surface (nm), and the vertical axis is the Si atom concentration (cm ^-3 ).
FIG. 8 shows 1.5 × 10 at 10 keV on a 4-inch GaAs wafer. ¹³ cm ^-2 After the Si ions are implanted, RTA is performed at 870 ° C. for 2 seconds, and the temperature T at the wafer center when a waiting step of 4 seconds is provided at 750 ° C. during the temperature lowering process is performed. ₁ (Solid line) and surrounding temperature T ₂ The graph which shows the time change of (dashed line). The horizontal axis represents annealing time (seconds), and the vertical axis represents temperature (° C.).
FIG. 9 shows 1.5 × 10 at 10 keV on a 4-inch GaAs wafer. ¹³ cm ^-2 After the Si ions are implanted, RTA is performed at 870 ° C. for 2 seconds, and the wafer center temperature T when a standby step of about 2 seconds is provided between 850 ° C. and 830 ° C. during temperature reduction ₁ And ambient temperature T ₂ Difference (T ₁ -T ₂ ) Over time and slip critical temperature difference (T ₁ -T ₂ ) _c The graph which shows the time change of. The horizontal axis represents the annealing time (seconds), and the vertical axis represents the temperature difference (° C.).

Claims (3)

Lamp annealing (RTA) is used for activation annealing after ion implantation for accelerating and implanting impurity ions into a semiconductor substrate, and before the temperature difference Δ inside and outside the wafer reaches the slip generation critical temperature difference Δc during the temperature drop after annealing , a ramp is used. A semiconductor heat treatment method, characterized in that a standby step is provided in which the power is temporarily increased to decrease the temperature drop rate temporarily to reduce the temperature difference Δ between the inside and outside of the wafer . Lamp annealing (RTA) is used for activation annealing after ion implantation for accelerating and injecting impurity ions into a semiconductor substrate, and after the temperature difference Δ between the inside and outside of the wafer reaches the slip generation critical temperature difference Δc when the temperature decreases after annealing, A semiconductor heat treatment method, characterized in that a standby step is provided in which the power is temporarily increased and the temperature drop rate is temporarily decreased to make the wafer internal / external temperature difference Δ smaller than the slip generation critical temperature difference Δc . The time for temporarily increasing the lamp power in the standby step is such that the ion diffusion length at the standby step temperature is 20% or less of the ion diffusion length at the maximum temperature. The semiconductor heat treatment apparatus as described.

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