WO2003063218A2 - Method for forming shallow junctions by ion implantation in silicon wafers - Google Patents

Method for forming shallow junctions by ion implantation in silicon wafers Download PDF

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WO2003063218A2
WO2003063218A2 PCT/GB2003/000136 GB0300136W WO03063218A2 WO 2003063218 A2 WO2003063218 A2 WO 2003063218A2 GB 0300136 W GB0300136 W GB 0300136W WO 03063218 A2 WO03063218 A2 WO 03063218A2
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silicon
implanted
substrate
ion implantation
depth
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WO2003063218A3 (en
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Ahmed Nejim
Brian Sealy
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The University Of Surrey
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates

Definitions

  • This invention relates to ion implanted junctions in silicon wafers for use in microelectronic devices. Its particular concern is the fabrication of ultra-shallow junctions.
  • Ion implantation has become an industrial standard method in the manufacture of electrical junctions and integrated circuits.
  • small amounts of dopants such as boron or arsenic are implanted into a semiconductor substrate lattice to modify its electronic properties.
  • the substrate is typically a thin wafer (of about 0.5 mm thickness) of a material such as single crystal silicon, typically (100) silicon.
  • Ion implantation provides the ability to control in a reproducible manner the purity of the dopant isotope and the position and depth at which a layer of the dopant is created. Both the controllability and reproducibility are of great benefit in improving production yields.
  • the purity of the implanted atomic species and their depth profile are controlled by the mass/charge combination under a specific acceleration setting.
  • a silicon wafer incorporating such a junction can be provided by modifying the method to reduce the implant energy to values below 10 keV. This modification however produces damage in the structure of the substrate and thus hampers the electrical performance of the device. Annealing of the implanted substrate is therefore undertaken, using a high temperature "rapid thermal anneal” (RTA) , both to repair the ion implant damage and also to activate the dopants by placing them in atomic substitutional sites.
  • RTA rapid thermal anneal
  • the dopants diffuse away from high to lower concentration regions by a mechanism governed in part by the thermodynamic laws of diffusion.
  • TED transient enhanced diffusion
  • point defects take the form of vacancies and interstitials in the lattice.
  • This second diffusion mechanism appears only at the early stages of the rapid thermal annealing but is much more significant than the first diffusion mechanism. Since defect production is an inherent part of the ion implantation process, rapid thermal annealing is always accompanied by some transient enhanced diffusion.
  • barrier layer for example of an oxide, carbide or nitride, in the silicon wafer beneath the shallow doped layer.
  • specific materials for the barrier layer include aluminium oxide (Al 2 O 3 ), silicon oxide (SiO 2 ), suicides, silicon carbide (SiC), silicon nitride, silicon on insulator (SOI) or salicide silicon on insulator (SSOI) materials.
  • the barrier layer inhibits diffusion of point defects.
  • Boron which represents the main p-type dopant for silicon, can be successfully implanted using energies of 5 keN and less. This produces implanted junction depths of less than 100 nm.
  • the silicon initially has a substantially perfectly formed crystalline structure, the implantation process leads to the creation of point defects and in particular excess silicon interstitials within the structure. This interstitial supersaturation represents the vehicle for subsequent anomalous and unwanted diffusion of boron in the early stages of the annealing.
  • CMOS complementary metal oxide semiconductor
  • the key parameter in such implants is the concentration of vacancies created in the near-surface region which is required to annihilate the excess silicon interstitials and hence prevent transient enhanced diffusion.
  • Positron annihilation spectroscopy provides a direct method for measuring vacancy concentrations following MeV ion implantation of silicon but prior to annealing.
  • the measurement is non-destructive (allowing further processing of the samples to be performed) , requires no specific sample preparation, has a comparatively high throughput, and is sensitive to vacancy concentrations in the range 1 x 10 15 - 5 x 10 l9 cm 3 from samples of any doping type and concentration [Asoka-Kumar et al, Journal of Applied Physics, Vol. 76 (1994) 4935].
  • Previous studies [P J Simpson et al, Physical Review B, Vol. 44 (1991) 12 180; B Neilsen et al, Journal of Applied Physics, Vol.
  • the present invention relates to a method using high energy co-implantation to form low-energy ion-implanted ultra-shallow junctions in silicon wafers with buried barrier layers.
  • a method for ion implantation into a silicon semiconducting wafer with a buried barrier layer characterised in that dopant ions are implanted at a low energy level into the wafer substrate to a depth close to the surface, other ions are implanted at a high energy level into the substrate to form a network of extended defects at a depth beneath the barrier layer, and the so- implanted substrate is subjected to rapid thermal annealing to activate the dopants to form a shallow conducting layer close to the wafer surface.
  • the present invention further provides an ion-implanted silicon semiconducting wafer with a buried barrier layer in its substrate, characterised by a shallow conducting layer of dopant close to the wafer surface, and a network of extended defects beyond the barrier layer.
  • the invention is especially suitable for providing silicon semiconducting substrates with conductivity modified by controlled amounts of dopants in shallow layers of well-controlled depths. Such layers are an important requirement in complementary metal oxide semiconductor (CMOS) devices.
  • CMOS complementary metal oxide semiconductor
  • the barrier layer is useful not only in inhibiting dopant ions close to the surface from diffusing away from the surface but also in inhibiting the deep lying point defects, formed by the high energy implants, from diffusing back towards the surface and thus from facilitating transient enhanced diffusion of the said dopant ions.
  • the defects of the extended defect network are in Category I as defined by K S Jones et al (Applied Physics, A45, 1988, pp 1-34) , namely defects formed when the high energy implant dose is below the threshold level at which amorphisation of the silicon structure would occur.
  • the formation of the extended defect network is a secondary effect of the high energy implantation it does produce the advantage of providing gettering sites for any metallic contaminants within the silicon structure.
  • the network of extended defects exists at a substantial depth (typically about 1 ⁇ m) beneath the wafer surface. It is thus well away from the shallow conducting layer and electrically isolated from it by the barrier layer and accordingly has no harmful effect upon the electrical properties of the wafer.
  • a further useful effect of the barrier layer is that the interface it provides close to the doping region presents an additional sink for fast diffusing interstitials. This effect plays a significant role in reducing the concentration of interstitials and hence in further reducing transient enhanced diffusion of the dopant ions close to the surface.
  • the sequence in which the low energy implantation and the high energy implantion are conducted is not critical, although they must both follow the introduction of the barrier layer and precede the rapid thermal annealing.
  • the low energy ion implantation preferably employs an energy of less than 10 keV. Suitable ion species for this implantation include most elements of groups III and V of the periodic table, notably arsenic and boron. Boron is generally preferred as the p " type dopant.
  • the doped layer created by the implantation preferably extends from the substrate surface to a depth beneath the surface of not more than about 100 nm at lxlO'Vcm 3 atomic concentration. Following the rapid thermal annealing the layer typically diffuses into the substrate by not more than about 10 nm at an atomic concentration of lxl0 18 /cm 3 . This post-annealing depth represents a considerable and beneficial reduction over prior proposals and provides for the ultra-shallow junctions sought by the invention.
  • the high energy ion implantation preferably employs an energy in the range 500keV-2MeV.
  • Suitable ion species for this implantation include hydrogen, fluorine, phosphorus, silicon and larger mass ions such as germanium. It is important that the projected range of this implantation should be into a region deeper than the barrier layer so that damage caused by the implantation to the substrate structure in this region is at a deeper level than the top interface of the barrier layer, thereby enabling the barrier layer to isolate this region from the low energy dopant implant layer.
  • the depth at which the high energy implantation is effected is preferably in a region at a depth of at least 500 nm beneath the substrate surface.
  • Figure 1 is a graphical illustration of analysis by high resolution secondary ion mass spectroscopy of 5keV boron implanted into (100) silicon.
  • Figure 2 shows the defect profile in the silicon following lxlO 6 Si/cm 2 implant at 1 MeV.
  • the profile was obtained from RBS-c data (Rutherford backscattering spectroscopy-channelling) analysed using the DICADA code ["Dechannelling In Crystals And Defect Analysis” K Gartner and A Uguzzoni, , Nuclear Instruments and Methods in Physics Research B, Vol. 67 (1992) 189] .
  • the line without symbols is the as-implanted profile.
  • the line with squares is the annealed profile showing the effect of transient enhanced diffusion.
  • the line with diamonds shows similar data from the SOI (silicon on insulator) material where the silicon top layer is 190nm thick.
  • the line with triangles is the profile from the co- implanted material showing the influence of the high energy (lMeV) implantation on reducing transient enhanced diffusion by about 60% at lxlO 17 B/cm 3 concentration level.
  • the line with circles shows the boron profile from similar implant process in SOI material.
  • (100) n-type 100 mm Czochralski (CZ) silicon wafers were implanted with 2xlO u cm 2 5keV boron at 7° tilt and 22° rotation. These wafers were then implanted with lMeV silicon using similar wafer geometry to the boron implant and one of three doses of lx0 12 cm 2 , l ⁇ 0 1 cnr 2 or lxl0 16 c ⁇ v 2 , and then annealed at 1000°C for 13 seconds.
  • the boron profile was monitored using high resolution secondary ion mass spectroscopy analysis before and after annealing and also as a function of the substrate type. Point defect profiles from the high energy implants were also obtained using accurate Rutherford backscattering channelling analysis (RBS-c) and the DICADA code mentioned above.
  • RBS-c Rutherford backscattering channelling analysis
  • Figure lb further shows that a higher dose of lxO 16 Si/cm 2 produced a substantial retardation of the boron diffusion for concentrations between 2 ⁇ l0 18 cm 3 and 2 ⁇ l0 I6 cnv 3 .
  • l ⁇ l0 17 cm 3 boron concentration appeared at a depth of 133 nm while the boron-only material shows the same concentration at 158 nm.
  • the peak concentration for the co- implanted material drops to 2.6xl0 19 B/cm 3
  • the peak of the profile (above a concentration of lxlO 19 B/cm 3 ) is wider followed by a steeper gradient when compared with the boron only material. In fact this gradient is even steeper than the profile of the boron in the non-annealed material.
  • FIG. 2 shows the defect profile for material implanted with lxlO 16 Si/cm 2 and displays a substantial peak at a depth of 1.1 ⁇ m, reaching a concentration of 2xl0 0 cm 3 and extending from a depth of 750 nm up to 1500 nm. This peak is significantly deeper than barrier layer placed at a depth of 190- 560 nm in this particular example. The data from the top 190 nm region lies within the detection limit of the technique.
  • the retardation of the boron diffusion following the high dose high energy implant indicates that during this implant some of the silicon interstitials created during the boron implant which normally cause the transient enhanced diffusion are removed. This takes place via recombination and annihilation with excess vacancies generated in the near surface region from the high energy implant.
  • Positron annihilation analysis (PAS) of material implanted with lxlO 16 Si/cm 2 by the present inventors has shown that a vacancy concentration in the top 40 nm layer of 3.75 ⁇ l0 19 cm 3 , reducing to 1.5xl0 19 cm 3 at a depth of 120 nm. It was also revealed from this analysis that the diffusion length of these vacancies was of the order of 25-40 nm. Wafers implanted with lower silicon doses of lxlO 12 Si/cm 2 and lxlO 14 Si/cm 2 did not produce enough vacancies to perturb the Frenklel Pair concentration sufficiently in the near surface region to play an effective role in retarding the transient enhanced diffusion. The high dose high energy silicon implant also generated a large concentration of point defects deep in the material which act as gettering centres for metallic impurities.
  • the Si/SiO at a depth of 190 nm did not seem to play a role in retarding transient enhanced diffusion (see Figure la) . This is different when the top interface is positioned closer to the boron profile.
  • SIMS data from material with a top layer thickness of 100 nm showed that the boron peak concentration following similar RTA anneals was higher by lxlO 19 B/cm 3 .
  • the data from the material with a barrier layer between 190 nm-560 nm shows that all the quenching seen in this example was due to the combined effect of the high energy implant and the presence of the buried barrier layer (SiO 2 in this case) .

Abstract

A method for ion implantation into a silicon semiconducting wafer with a buried barrier layer includes the implantation of dopant ions at a low energy level into the substrate to a depth close to the surface. Other ions are implanted at a high energy level into the substrate to form a network of extended defects at a depth beyond the barrier layer. The implanted substrate is subjected to rapid thermal annealing to activate the dopants to form a shallow conducting layer close to the wafer surface.

Description

ION IMPLANTED JUNCTIONS IN SILICON WAFERS
This invention relates to ion implanted junctions in silicon wafers for use in microelectronic devices. Its particular concern is the fabrication of ultra-shallow junctions.
Ion implantation has become an industrial standard method in the manufacture of electrical junctions and integrated circuits. In this method small amounts of dopants such as boron or arsenic are implanted into a semiconductor substrate lattice to modify its electronic properties. The substrate is typically a thin wafer (of about 0.5 mm thickness) of a material such as single crystal silicon, typically (100) silicon.
Ion implantation provides the ability to control in a reproducible manner the purity of the dopant isotope and the position and depth at which a layer of the dopant is created. Both the controllability and reproducibility are of great benefit in improving production yields. The purity of the implanted atomic species and their depth profile are controlled by the mass/charge combination under a specific acceleration setting.
As integrated circuits become ever smaller a corresponding need arises for shallower doped layers with higher doping concentrations to produce ultra-shallow junctions close to the wafer surface. Since short channel effects are becoming a critical limitation to new generations of deep submicron devices which require high doping concentrations in thin layers, strict doping implant protocols have to be implemented.
The term "ultra-shallow" is used herein to indicate a junction depth of not more than 50 nm,) . Using ion implantation, a silicon wafer incorporating such a junction can be provided by modifying the method to reduce the implant energy to values below 10 keV. This modification however produces damage in the structure of the substrate and thus hampers the electrical performance of the device. Annealing of the implanted substrate is therefore undertaken, using a high temperature "rapid thermal anneal" (RTA) , both to repair the ion implant damage and also to activate the dopants by placing them in atomic substitutional sites.
During the high temperature annealing the dopants diffuse away from high to lower concentration regions by a mechanism governed in part by the thermodynamic laws of diffusion. There is also a second diffusion mechanism, known as "transient enhanced diffusion" (TED), which in turn is governed by the concentration of point defects available in the substrate lattice. These "point defects" take the form of vacancies and interstitials in the lattice. This second diffusion mechanism appears only at the early stages of the rapid thermal annealing but is much more significant than the first diffusion mechanism. Since defect production is an inherent part of the ion implantation process, rapid thermal annealing is always accompanied by some transient enhanced diffusion.
It is known to provide a buried barrier layer, for example of an oxide, carbide or nitride, in the silicon wafer beneath the shallow doped layer. Specific materials for the barrier layer include aluminium oxide (Al2O3), silicon oxide (SiO2), suicides, silicon carbide (SiC), silicon nitride, silicon on insulator (SOI) or salicide silicon on insulator (SSOI) materials. The barrier layer inhibits diffusion of point defects.
Boron, which represents the main p-type dopant for silicon, can be successfully implanted using energies of 5 keN and less. This produces implanted junction depths of less than 100 nm. Although the silicon initially has a substantially perfectly formed crystalline structure, the implantation process leads to the creation of point defects and in particular excess silicon interstitials within the structure. This interstitial supersaturation represents the vehicle for subsequent anomalous and unwanted diffusion of boron in the early stages of the annealing.
Because diffusion of boron (and other dopants) under transient enhanced diffusion conditions is orders of magnitude greater than under thermal equilibrium conditions the control and limitation of the broadening of the implanted boron profile, following the activation anneal, represents a significant challenge to device fabrication strategies. Transient enhanced diffusion has thus become a major issue for shallow doping profiles needed for very large scale integration (VLSI) of silicon devices.
A number of implantation-based, defect engineering solutions have been investigated by various research groups to counteract the effects of transient enhanced diffusion. These centre on co-implanting a second ion species with the dopant. Such approaches include:
(1) Co-implantation of an ion species, such as carbon or fluorine, whose presence retards the diffusion of silicon interstitials [S Nishikawa et al, Applied Physics Letters, Vol. 60 (1991) 2270-2272, and J P Crrok et al, Nuclear Instruments and Methods in Physics Research B, Vol. 55 (1991) 593] . It is however found that the required concentration of impurities such as carbon strongly reduces the activation of boron [V Privitera et al, Proceedings of IIT'98, Kyoto, Japan, paper P2-136 (1998)] . This is explained by the formation of complexes of boron with carbon. The formation of these complexes is enhanced as ion energies are lowered, as a result of vacancy sinking to the silicon surface.
(2) Low energy argon implantation utilising plasma immersion implantation to create shallow defects to pin excess interstitials generated from subsequent boron implantation during anneal activation [V Privitera et al, Proceedings of IIT'98, Kyoto, Japan, paper TH12 (1998)] . This technique produces dislocations close to the surface which contribute to the anomalous diffusion of boron [X Bao et al, Journal of Applied Physics, Vol. 66 (1989) 1475] .
(3) High energy implants to produce deep amorphous layers prior to boron implants. Such methods have the advantages of minimising channelling effects as well as limiting transient enhanced diffusion diffusion. The end-of-range (EOR) defects resulting from the annealing of the high energy implants are positioned deep and far away from the boron distribution and hence will not play a role in transient enhanced diffusion [S Salomi et al, Applied Physics Letters, Vol. 51 (1987) 331] . Unfortunately, amorphisation implants through limited area windows cause the formation of edge defects following solid phase epitaxial regrowth anneals. Such defects can act as recombination centres if they penetrate into the device active regions.
(4) Sub-amorphisation, high energy (MeN) implants to produce near surface supersaturation of vacancies which annihilate a substantial fraction of the excess interstitials induced by the boron implants [N Raineri et al, Applied Physics Letters, Vol. 58 (1991) 922] . This approach has several advantages such as the absence of solid phase epitaxy anneals; the requirement for small doses (and hence no restriction on implanted dose-rate) ; and the ability for inducing disassociation of complex boron clusters which are thermally stable and electrically inactive, in turn improving the activation of the implanted boron.
Increasingly, high energy implants are being incorporated into device processing for deep well formation. It is therefore anticipated that the sub-amorphisation MeN implantation approach will play a significant role in eliminating the transient-enhanced-diffusion of boron in source-drain contacts of complementary metal oxide semiconductor (CMOS) structures.
US patent No. 6,037,640 describes a technique for retarding boron diffusion and mentions a reference by Saito et al [Applied Physics Letters, Nol. 63 (1993) 197-199] to the achievement of a reduction of 50% in the depth of p-n junctions made by lOkeN boron implants. This junction, which was taken at a concentration of lxl017cπr3 boron was measured by secondary ion mass spectroscopy (SIMS) and spreading resistance profiling (SRP) . The reduction was achieved with the use of three step implant process. A fluorine pre-implant preceded a boron doping implant which was followed by a high energy fluorine or silicon implant. A junction shallower than 100 nm was achieved following an RTA step at 1000-1100°C for 10 seconds.
The key parameter in such implants is the concentration of vacancies created in the near-surface region which is required to annihilate the excess silicon interstitials and hence prevent transient enhanced diffusion.
To date there has been a limited number of measurements of vacancy concentrations associated with MeV implantation. For instance, initial data from studies involving the use of vacancy-diffusing marker layers indicate that a large burst of vacancies is released in the early stages of annealing [V C Venezia et al, Materials Research Society Symposium Proceedings, Vol. 568] . Other approaches using deep-level-transient spectroscopy (DLTS) have yielded information on the identification and concentration of vacancy-related levels [J L Benton et al, Materials Research Society Symposium Proceedings, Vol. 568] .
Positron annihilation spectroscopy (PAS) provides a direct method for measuring vacancy concentrations following MeV ion implantation of silicon but prior to annealing. The measurement is non-destructive (allowing further processing of the samples to be performed) , requires no specific sample preparation, has a comparatively high throughput, and is sensitive to vacancy concentrations in the range 1 x 1015 - 5 x 10l9cm 3 from samples of any doping type and concentration [Asoka-Kumar et al, Journal of Applied Physics, Vol. 76 (1994) 4935]. Previous studies [P J Simpson et al, Physical Review B, Vol. 44 (1991) 12 180; B Neilsen et al, Journal of Applied Physics, Vol. 74 (1993) 1636; , accepted for publication have indicated that high energy, low dose implants yield vacancy concentrations which are 10 times smaller than those predicted by the Transmission of Ions in Matter (TRIM) simulation code, indicating that a significant amount of dynamic annealing takes place during room temperature ion implantation.
Rutherford backscattering spectroscopy-channelling (RBS-c) has been successfully used to measure excess interstitials in material implanted with germanium at high and low dose rates [A P Knights, A Nejim, et al, Materials Research Society Symposium Proceedings, Vol. 532: Silicon Front-End Technology - Materials Processing and Modelling (1998)]. A similar approach has been used to obtain the interstitial defects concentration depth profiles for material implanted with MeV silicon. By combining RBS-c with positron annihilation spectroscopy data a comprehensive picture of the influence of MeV implants on the point defect populations in the vicinity of the boron profile, together with critical data on vacancy concentrations required to limit transient enhanced diffusion in boron shallow junctions has been obtained.
The present invention relates to a method using high energy co-implantation to form low-energy ion-implanted ultra-shallow junctions in silicon wafers with buried barrier layers.
According to the present invention there is provided a method for ion implantation into a silicon semiconducting wafer with a buried barrier layer, characterised in that dopant ions are implanted at a low energy level into the wafer substrate to a depth close to the surface, other ions are implanted at a high energy level into the substrate to form a network of extended defects at a depth beneath the barrier layer, and the so- implanted substrate is subjected to rapid thermal annealing to activate the dopants to form a shallow conducting layer close to the wafer surface.
The present invention further provides an ion-implanted silicon semiconducting wafer with a buried barrier layer in its substrate, characterised by a shallow conducting layer of dopant close to the wafer surface, and a network of extended defects beyond the barrier layer.
The invention is especially suitable for providing silicon semiconducting substrates with conductivity modified by controlled amounts of dopants in shallow layers of well-controlled depths. Such layers are an important requirement in complementary metal oxide semiconductor (CMOS) devices. During the rapid thermal annealing the barrier layer is useful not only in inhibiting dopant ions close to the surface from diffusing away from the surface but also in inhibiting the deep lying point defects, formed by the high energy implants, from diffusing back towards the surface and thus from facilitating transient enhanced diffusion of the said dopant ions.
The defects of the extended defect network are in Category I as defined by K S Jones et al (Applied Physics, A45, 1988, pp 1-34) , namely defects formed when the high energy implant dose is below the threshold level at which amorphisation of the silicon structure would occur.
Although the formation of the extended defect network is a secondary effect of the high energy implantation it does produce the advantage of providing gettering sites for any metallic contaminants within the silicon structure.
Moreover, the network of extended defects exists at a substantial depth (typically about 1 μm) beneath the wafer surface. It is thus well away from the shallow conducting layer and electrically isolated from it by the barrier layer and accordingly has no harmful effect upon the electrical properties of the wafer. A further useful effect of the barrier layer is that the interface it provides close to the doping region presents an additional sink for fast diffusing interstitials. This effect plays a significant role in reducing the concentration of interstitials and hence in further reducing transient enhanced diffusion of the dopant ions close to the surface.
The sequence in which the low energy implantation and the high energy implantion are conducted is not critical, although they must both follow the introduction of the barrier layer and precede the rapid thermal annealing.
The low energy ion implantation preferably employs an energy of less than 10 keV. Suitable ion species for this implantation include most elements of groups III and V of the periodic table, notably arsenic and boron. Boron is generally preferred as the p" type dopant. The doped layer created by the implantation preferably extends from the substrate surface to a depth beneath the surface of not more than about 100 nm at lxlO'Vcm3 atomic concentration. Following the rapid thermal annealing the layer typically diffuses into the substrate by not more than about 10 nm at an atomic concentration of lxl018/cm3. This post-annealing depth represents a considerable and beneficial reduction over prior proposals and provides for the ultra-shallow junctions sought by the invention.
The high energy ion implantation preferably employs an energy in the range 500keV-2MeV. Suitable ion species for this implantation include hydrogen, fluorine, phosphorus, silicon and larger mass ions such as germanium. It is important that the projected range of this implantation should be into a region deeper than the barrier layer so that damage caused by the implantation to the substrate structure in this region is at a deeper level than the top interface of the barrier layer, thereby enabling the barrier layer to isolate this region from the low energy dopant implant layer. In general it is preferred that the depth at which the high energy implantation is effected is preferably in a region at a depth of at least 500 nm beneath the substrate surface.
It is also important to avoid energy dose thresholds whereby total amorphisation is produced in the silicon top layers and the seed for subsequent epitaxial regrowth is lost. This can be done by controlling the total ion fluence and substrate temperature during implantation.
For low energy dopant layers with a pre-annealing depth of less than 50 nm and high concentrations of dopants (greater than 5χl019cm 3) rapid thermal annealing at 900°C-1100°C for a few seconds is required to activate substantially all (near to 100%) of the introduced dopants. It is also desirable to employ fast heating and cooling rates ("Ramp Up" and "Ramp Down") of 100°C/second or more for this annealing. Controlled dwell times are needed to adhere to the total thermal budget of the process.
The invention is further illustrated with reference to the accompanying figures and the following non-limiting example. It is emphasized that the invention is not limited to the specific material and parameters discussed therein.
Figure 1 is a graphical illustration of analysis by high resolution secondary ion mass spectroscopy of 5keV boron implanted into (100) silicon.
Figure 2 shows the defect profile in the silicon following lxlO6 Si/cm2 implant at 1 MeV. The profile was obtained from RBS-c data (Rutherford backscattering spectroscopy-channelling) analysed using the DICADA code ["Dechannelling In Crystals And Defect Analysis" K Gartner and A Uguzzoni, , Nuclear Instruments and Methods in Physics Research B, Vol. 67 (1992) 189] . In Figure la the line without symbols is the as-implanted profile. The line with squares is the annealed profile showing the effect of transient enhanced diffusion. The line with diamonds shows similar data from the SOI (silicon on insulator) material where the silicon top layer is 190nm thick. In Figure lb the line with triangles is the profile from the co- implanted material showing the influence of the high energy (lMeV) implantation on reducing transient enhanced diffusion by about 60% at lxlO17 B/cm3 concentration level. In Figure lc the line with circles shows the boron profile from similar implant process in SOI material.
In the example, (100) n-type 100 mm Czochralski (CZ) silicon wafers were implanted with 2xlOucm 2 5keV boron at 7° tilt and 22° rotation. These wafers were then implanted with lMeV silicon using similar wafer geometry to the boron implant and one of three doses of lx012cm 2, l χ01 cnr2 or lxl016cπv2, and then annealed at 1000°C for 13 seconds. The boron profile was monitored using high resolution secondary ion mass spectroscopy analysis before and after annealing and also as a function of the substrate type. Point defect profiles from the high energy implants were also obtained using accurate Rutherford backscattering channelling analysis (RBS-c) and the DICADA code mentioned above.
The boron exhibited the expected substantial diffusion in the silicon substrate following the rapid thermal anneal at 1000 °C. Figure la clearly shows transient enhanced diffusion for boron concentrations between 2χl019cm 3 and 2xl016cnr3 for a sample implanted with boron only. This figure also shows a substantial drop in the peak boron concentration at a depth of 12 nm, from 6.3xl019 B/cm3 to 2.9χl019 B/cm3. When compared with boron-only material, no significant change in the boron profile was seen when the material was co-implanted with lxO12 Si/cm2 or lxO14 Si/cm2 at lMeV (data not shown) . However, Figure lb further shows that a higher dose of lxO16 Si/cm2 produced a substantial retardation of the boron diffusion for concentrations between 2χl018cm 3 and 2χl0I6cnv3. For the co-implanted material, lχl017cm 3 boron concentration appeared at a depth of 133 nm while the boron-only material shows the same concentration at 158 nm. Although the peak concentration for the co- implanted material drops to 2.6xl019 B/cm3, the peak of the profile (above a concentration of lxlO19 B/cm3) is wider followed by a steeper gradient when compared with the boron only material. In fact this gradient is even steeper than the profile of the boron in the non-annealed material.
Silicon wafers implanted with high energy silicon were examined by Rutherford backscattering channelling analysis, which showed that prior to the high temperature anneal the near surface region of 300 nm was defect-free and comparable with virgin reference silicon. Figure 2 shows the defect profile for material implanted with lxlO16 Si/cm2 and displays a substantial peak at a depth of 1.1 μm, reaching a concentration of 2xl0 0cm 3 and extending from a depth of 750 nm up to 1500 nm. This peak is significantly deeper than barrier layer placed at a depth of 190- 560 nm in this particular example. The data from the top 190 nm region lies within the detection limit of the technique.
The retardation of the boron diffusion following the high dose high energy implant indicates that during this implant some of the silicon interstitials created during the boron implant which normally cause the transient enhanced diffusion are removed. This takes place via recombination and annihilation with excess vacancies generated in the near surface region from the high energy implant.
Positron annihilation analysis (PAS) of material implanted with lxlO16 Si/cm2 by the present inventors has shown that a vacancy concentration in the top 40 nm layer of 3.75χl019 cm 3, reducing to 1.5xl019 cm 3 at a depth of 120 nm. It was also revealed from this analysis that the diffusion length of these vacancies was of the order of 25-40 nm. Wafers implanted with lower silicon doses of lxlO12 Si/cm2 and lxlO14 Si/cm2 did not produce enough vacancies to perturb the Frenklel Pair concentration sufficiently in the near surface region to play an effective role in retarding the transient enhanced diffusion. The high dose high energy silicon implant also generated a large concentration of point defects deep in the material which act as gettering centres for metallic impurities.
In the present example the Si/SiO at a depth of 190 nm did not seem to play a role in retarding transient enhanced diffusion (see Figure la) . This is different when the top interface is positioned closer to the boron profile. SIMS data from material with a top layer thickness of 100 nm showed that the boron peak concentration following similar RTA anneals was higher by lxlO19 B/cm3.
The data from the material with a barrier layer between 190 nm-560 nm shows that all the quenching seen in this example was due to the combined effect of the high energy implant and the presence of the buried barrier layer (SiO2 in this case) .

Claims

Claims
1. A method for ion implantation into a silicon semiconducting wafer with a buried barrier layer, characterised in that dopant ions are implanted at a low energy level into the substrate to a depth close to the surface, other ions are implanted at a high energy level into the substrate to form a network of extended defects at a depth beyond the barrier layer, and the so-implanted substrate is subjected to rapid thermal annealing to activate the dopants to form a shallow conducting layer close to the wafer surface.
2. A method as claimed in claim 1 , in which the low energy ion implantation employs an energy of not more 15 keV.
3. A method as claimed in claim 1 or claim 2, in which the ion species for the low energy ion implantation is selected from arsenic, boron and other elements of groups III and V of the periodic table.
4. A method as claimed in any preceding claim, in which the high energy ion implantation employs an energy in the range 500keV-2MeV.
5. A method as claimed in any preceding claim, in which ion species for the high energy ion implantation is selected from hydrogen, fluorine, phosphorus, silicon and larger mass ions such as germanium.
6. A method as claimed in any preceding claim, in which the high energy ion implantation is effected into a region at a depth of at least 500 nm beneath the substrate surface.
7. A method as claimed in any preceding claim, in which the rapid thermal annealing is effected at a temperature in the range 900-1100°C.
8. A method as claimed in any preceding claim, in which the rapid thermal annealing includes fast heating and cooling rates of 100°C/second or more.
9. An ion-implanted silicon semiconducting wafer with a buried barrier layer in its substrate, characterised by a shallow conducting layer of dopant close to the wafer surface and a network of extended defects beyond the barrier layer.
10. A silicon wafer as claimed inClaim 9, in which the ion species of the dopant in the shallow conducting layer is selected from arsenic, boron and other elements of groups III and V of the periodic table.
11. A silicon wafer as claimed in claim 9 or claim 10, in which the shallow conducting layer extends from the substrate surface to a depth of not more than about 100 nm.
12. A silicon wafer as claimed in any of claims 9 to 11 , in which the network of extended defects is at a depth greater than 500 nm beneath the wafer surface.
PCT/GB2003/000136 2002-01-16 2003-01-15 Method for forming shallow junctions by ion implantation in silicon wafers WO2003063218A2 (en)

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US7846822B2 (en) 2004-07-30 2010-12-07 The Board Of Trustees Of The University Of Illinois Methods for controlling dopant concentration and activation in semiconductor structures
WO2006117238A1 (en) * 2005-05-05 2006-11-09 Infineon Technologies Ag Implantation process in semiconductor fabrication
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US7358167B2 (en) 2005-05-05 2008-04-15 Infineon Technologies Ag Implantation process in semiconductor fabrication
WO2006125993A1 (en) * 2005-05-27 2006-11-30 University Of Surrey Semiconductor device and method of manufacture
US7968440B2 (en) 2008-03-19 2011-06-28 The Board Of Trustees Of The University Of Illinois Preparation of ultra-shallow semiconductor junctions using intermediate temperature ramp rates and solid interfaces for defect engineering
US8871670B2 (en) 2011-01-05 2014-10-28 The Board Of Trustees Of The University Of Illinois Defect engineering in metal oxides via surfaces
EP2637008A3 (en) * 2012-03-05 2015-07-01 Honeywell International Inc. Apparatus and processes for silicon on insulator mems pressure sensors

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