WO2006125993A1 - Semiconductor device and method of manufacture - Google Patents

Semiconductor device and method of manufacture Download PDF

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Publication number
WO2006125993A1
WO2006125993A1 PCT/GB2006/001921 GB2006001921W WO2006125993A1 WO 2006125993 A1 WO2006125993 A1 WO 2006125993A1 GB 2006001921 W GB2006001921 W GB 2006001921W WO 2006125993 A1 WO2006125993 A1 WO 2006125993A1
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Prior art keywords
wafer
ions
implanted
dopant
layer
Prior art date
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PCT/GB2006/001921
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French (fr)
Inventor
Nicholas Edward Benedict Cowern
Andrew James Smith
Brian John Sealy
Benjamin Colombeau
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University Of Surrey
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Priority claimed from GB0510923A external-priority patent/GB0510923D0/en
Application filed by University Of Surrey filed Critical University Of Surrey
Publication of WO2006125993A1 publication Critical patent/WO2006125993A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates

Definitions

  • This invention relates to a semiconductor device and method of manufacture. More specifically, the invention relates to implanting vacancy generating ions to increase dopant electrical activation.
  • a dopant atom In order to become electrically active, a dopant atom must replace an atom of a semiconductor crystal in the crystal lattice. Dopant ions are usually implanted in the semiconductor crystal. The implantation process can cause some dopant ions to knock atoms of the semiconductor crystal out of the crystal lattice and replace them. However, most of the implanted dopant ions tend to settle at positions between the atoms of the crystal, e.g. to form so-called interstitials. The dopant implanted crystal can be annealed to cause these interstitial dopant ions to replace atoms of the semiconductor crystal.
  • pre-amorphisation and SPER can provide concentrations of electrically active dopant atoms above the solid solubility limit of the dopant atoms in the crystal.
  • the maximum achievable dopant electrical activation remains limited to just a small fraction above the solid solubility limit of the dopant atoms in the crystal. This is insufficient for upcoming requirements of semiconductor manufacture, e.g. as set out in the International Technology Roadmap for Semiconductors (ITRS) for Complementary Metal-Oxide Semiconductor (CMOS) technology and such like.
  • IRS International Technology Roadmap for Semiconductors
  • CMOS Complementary Metal-Oxide Semiconductor
  • pre-amorphisation and SPER techniques tend to produce dopant layers that have significant so-called End Of Range (EOR) defects at the bottom of the dopant layer.
  • vacancy engineering This involves implanting vacancy generating ions, which are usually, but not necessarily, electrically neutral, in the semiconductor crystal to generate vacancies in the crystal lattice. The vacancies encourage implanted dopant ions to enter the crystal lattice and become electrically active during annealing.
  • US 6632728 describes a method of vacancy engineering. This publication recognises that generated vacancies can be effective in increasing electrical activation of a dopant in certain circumstances.
  • vacancy generating Silicon (Si) ions into a single crystal Si substrate at an energy of 2 MeV to a dose of about 10 16 cm '2 ; and to implant dopant Boron (B) ions into the substrate at an energy of 40 keV to a dose of about 2 x 10 14 cm “2 ; and then to anneal the substrate for about 1 hr at temperatures ranging from about 400 0 C to 800 0 C.
  • the vacancy generating ions might be implanted at energies between 12 keV and 25 MeV to a dose between 10 12 and 10 17 .
  • the dopant ions might be implanted at an energy of the order of 10 keV. However, no clear guidance is given on how to select from these energies and doses to obtain increased electrical activation of the dopant. It is mentioned that the dose to which the vacancy generating ions is implanted should be higher than the dose to which the dopant ions are implanted. It is also mentioned that, in a preferred embodiment, the depth profile of the generated vacancies and the depth profile of the implanted dopant ions should overlap one anther, although no indication of how to achieve this is provided. Indeed, the mechanisms of vacancy generation and electrical activation are at best only partially understood and US 6632728 does not elaborate in any significant detail how to control these mechanisms to obtain increased dopant electrical activation. The present invention seeks to overcome this problem.
  • a method of manufacturing a semiconductor device comprising: implanting vacancy generating ions into a semiconductor wafer via a surface of the wafer to generate vacancies in the wafer; and providing dopant ions in the wafer to form a dopant layer very shallow under the surface, wherein the dopant layer remains substantially crystalline.
  • the applicants have recognised that the vacancies generated by the vacancy generating ions in the semiconductor wafer typically have a maximum concentration at the surface of the wafer via which the vacancy generating ions are implanted.
  • the concentration typically declines with increasing depth. So, providing the dopant ions in the semiconductor wafer just under the surface can make most effective use of the generated vacancies. This is extremely useful, as it is generally desired to manufacture semiconductor devices with increasingly shallow dopant layers.
  • significantly higher electrical activation can be attained than demonstrated either by pre-amorphisation and Solid Phase Epitaxial Re-growth (SPER) or by previously reported vacancy engineering techniques.
  • SPER Solid Phase Epitaxial Re-growth
  • the dopant layer may extend to less than around 50 nm below the surface.
  • the dopant layer may extend to less than 30 nm below the surface or even to less than 20 nm or 10 nm below the surface.
  • the dopant layer might preferably be called an ultra-shallow dopant layer.
  • the dopant ions are usually implanted in the semiconductor wafer, e.g. using ion beam or plasma implantation techniques.
  • the method may therefore comprise selecting an energy at which the dopant ions are implanted in the wafer to be less than around 5 keV.
  • the method may comprise selecting an/the energy at which the dopant ions are implanted in the wafer to be less than around 1 keV. This can provide a dopant layer that is suitably shallow.
  • the wafer can be any of a variety of suitable semiconductor materials.
  • the wafer may comprise a Silicon (Si) crystal, a Germanium (Ge) crystal, a Silicon Germanium (SiGe) alloy crystal, a Silicon Germanium Carbon (SiGeC) alloy crystal, a Silicon Carbon (SiC) alloy crystal, or various group Nl-V alloy crystals etc., whether produced by epitaxial growth or as bulk crystals, as desired.
  • the crystal may be strained or unstrained.
  • the wafer incorporates a layer that acts as a barrier to diffusion of interstitials (or more generally defects including vacancies and interstitials) in the wafer.
  • This barrier layer might be electrically insulating or electrically conducting or even a composite of insulating and conducting layers.
  • the barrier layer is a layer of electrically insulating material.
  • the barrier layer may be a layer of aluminium oxide (AI 2 O 3 ), aluminium nitride (AIN) or silicon oxide (SiO 2 ).
  • the wafer can be a so-called Silicon On Insulator (SOI) wafer.
  • the insulating layer may be an air gap or an air gap which has been back-filled with an insulating material.
  • the wafer might be a so-called Silicon On Nothing (SON) wafer or such like.
  • the wafer may be a strained SOI wafer, a Germanium On Insulator (GeOI) wafer or comprise any other material suitable for a desired application.
  • the wafer has a barrier layer
  • a method of manufacturing a semiconductor device comprising: implanting vacancy generating ions into a semiconductor wafer incorporating a layer that acts as a barrier to diffusion of interstitials, the vacancy generating ions being implanted via a surface of the wafer to generate vacancies in the wafer; providing dopant ions in the wafer primarily between the surface and the barrier layer; and selecting an energy at which the vacancy generating ions are implanted such that the implanted vacancy generating ions reside primarily in a layer on the other side of the barrier layer to the surface via which they are implanted.
  • the implanted vacancy generating ions tend to create interstitials that can diffuse through the wafer during anneal. However, these interstitials cannot diffuse through the barrier layer. So, implanting the vacancy generating ions primarily (or even substantially totally) on the other side of the barrier layer to the dopant ions prevents the interstitials generated by the vacancy generating ions diffusing to where the dopant ions are implanted. Furthermore, whilst the vacancy generating ions are typically electrically neutral, they can nevertheless cause defects in the semiconductor wafer that contribute to leakage currents and such like. Indeed, in the vacancy generating ions may not even be electrically neutral. So, implanting them behind the barrier layer can avoid the vacancy generating ions directly influencing the electrical characteristics of the semiconductor device, e.g. causing leakage currents and such like.
  • the method can distinguish from the pre- amorphisation and Solid Phase Epitaxial Re-growth (SPER) technique described in the introduction to this document by requiring that the dopant layer remains substantially crystalline (e.g. throughout manufacture or at least during ion implantation and/or provision).
  • the method may comprise selecting an/the energy at which and/or a dose to which the vacancy generating ions are implanted such that the vacancy generating ions do not amorphise the dopant layer.
  • the threshold between amorphous material and crystalline material is well understood in the art. Completely crystalline material comprises a single crystal lattice. Moving away from this, the lattice might be broken or have some imperfections, but still remain substantially crystalline.
  • polycrystalline material might be considered substantially crystalline in this context.
  • the material might also contain a number of pockets of amorphous material whilst the crystal lattice remains intact over distances long relative to the size of the pockets and be considered substantially crystalline.
  • the lattice is sufficiently interrupted by pockets or regions of amorphous material that the crystal lattice is no longer a connected structure over long distances, it is no longer substantially crystalline and becomes amorphous.
  • Amorphisation of the deeper parts of the wafer can be tolerated or even be useful.
  • the vacancy generating ions can amorphise a part of the wafer deeper from the surface than the barrier layer. Amorphisation of this part of the wafer can allow epitaxial re-growth to annihilate defects in this part of the wafer during annealling. Regardless, the structure of the wafer in this part of the wafer has little effect on the properties of the dopant layer or use of the dopant layer in the semiconductor device.
  • the applicants have also recognised that amorphisation of the wafer proximate to the barrier layer on the same side of the barrier layer as the surface can be useful.
  • the method comprises selecting an/the energy at which and/or a dose to which the vacancy generating ions are implanted such that the vacancy generating ions amorphise a layer of the wafer deeper in the wafer than the dopant layer.
  • This amorphised layer can be on the opposing side of the barrier layer or the same side of the barrier layer to the surface of the wafer via which the vacancy generating ions are implanted.
  • the method might comprise forming the mask on the wafer prior to implanting the vacancy generating ions and selecting the energy at which the vacancy generating ions are implanted such that substantially none of the vacancy generating ions penetrate directly through the mask.
  • the method may comprise forming the mask on the wafer prior to implanting the vacancy generating ions and selecting the energy at which the vacancy generating ions are implanted such that interstitials generated by the vacancy generating ions implanted through the mask and/or those ions themselves (also) reside primarily in a layer on the other side of a/the barrier layer (of the wafer) to the surface via which they are implanted.
  • the applicants have identified that selecting the energy at which the vacancy generating ions are implanted from a range between around 2 keV and 1 MeV is usually appropriate. Indeed, preferably the range is between around 5 keV and 100 keV (especially when the vacancy generating ions are Silicon (Si) ions and/or the mask or gate stack is relatively thin). This is significantly below the energy typically reported in the prior art and is achievable primarily due to utilisation of the peak vacancy concentration found at or just below the surface of the wafer through which the vacancy generating ions are implanted. These lower energies are also more readily and cheaply achievable during manufacture.
  • the vacancy generating ions for implementing the invention such as Carbon (C), or Fluorine (F) for example.
  • the implanted vacancy generating ions are most usually Silicon (Si) ions or Germanium (Ge) ions.
  • a variety of different ions are suitable for use as the dopant ions for implementing the invention, such as Indium (In), although the provided dopant ions are typically Boron (B) ions.
  • the applicants have recognised that good electrical activation is achievable at relatively low annealing temperatures and short annealing durations.
  • the method may comprise annealing the wafer at a temperature below around 85O 0 C.
  • the method may comprise annealing the wafer for duration less than around 10s. Both of these features have the advantage of reducing the cost of manufacture.
  • reference to the "surface of the wafer" is made loosely in this document rather than explicitly. More specifically, it is well known that the surface of a semiconductor wafer more often than not comprises a layer of oxide or such like in practice. Such a layer may be present or not and the term through the surface of the wafer can refer to through such a layer or not.
  • Figure 1 is a schematic sectional view of a first embodiment of a semiconductor device during manufacture
  • Figure 2 is a graphical representation of ion and vacancy concentration versus depth in a semiconductor wafer during manufacture of the semiconductor device illustrated in Figure 1 ;
  • Figure 3 is a graphical representation of vacancy concentration versus depth in the semiconductor wafer simulated using a Monte Carlo model for vacancy generating ions implanted at different energies and to different doses;
  • Figure 4 is a graphical representation of vacancy and interstitial concentration versus depth in the semiconductor wafer
  • Figure 5 is a graphical representation of crossover depth between vacancy generation and interstitial generation versus energy at which vacancy generating ions are implanted in the semiconductor wafer;
  • Figure 6 is a graphical representation of an ideal window of doses to which vacancy generating ions are implanted and energy at which the ions are implanted;
  • Figure 7 is a graphical illustration of energy at which vacancy generating ions penetrate gate stacks of different thicknesses
  • Figure 8 is a schematic sectional view of a second embodiment of a semiconductor device during manufacture
  • Figure 9 is a schematic sectional view of a third embodiment of a semiconductor device during manufacture
  • Figure 10 is a graphical illustration of atomic displacements per unit volume versus depth for different vacancy generating ion doses
  • Figure 11 is a graphical representation of the relation between windows of dose and energy for vacancy generating ions of different types
  • Figure 12 is a graphical representation of dopant electrical activation versus anneal temperature for three different vacancy generating ion implants
  • Figure 13 is a graphical representation of dopant atom concentration versus depth in the semiconductor wafer before and after annealing for vacancy generating ions implanted at 1 MeV; and Figure 14 is a graphical representation of dopant atom concentration versus depth in the semiconductor wafer before and after annealing for vacancy generating ions implanted at 300 keV;
  • a semiconductor device 10 is manufactured using a Silicon (Si) On Insulator (SOI) wafer 11.
  • SOI wafer 11 has an upper layer 12 and lower layer 13 of Si crystal separated by a barrier layer 14 Silicon Oxide (SiO 2 ).
  • the barrier layer 14 separates the two Si layers 12, 13, which can have a number of advantages, as elaborated below, and is often referred to as a Buried Oxide (BOX) layer.
  • BOX Buried Oxide
  • a gate stack 15 is formed on an upper surface 19 of the wafer 11.
  • the gate stack 15 and upper Si layer 12 of the wafer 11 are shown in contact with one another in Figure 1 , although in reality an oxide layer or such like may be present between the gate stack 15 and the wafer 11 , which is largely ignored in this description for simplicity.
  • the gate stack 15 has thickness of around 100 nm or less.
  • Source-drain extension regions are formed in the upper Si layer 12 of the wafer 11 on opposing sides of the gate stack 15 by implanting dopant Boron (B) ions in regions 18 shallow under the upper surface 19 of the wafer 11 , in the upper Si layer 12 of the wafer 11.
  • a region of the gate stack 15 between the source-drain extension regions forms a channel of the device 10.
  • the upper Si layer 12 can have thickness of around 50 nm or less. In this embodiment, the regions 18 formed by the dopant B ions have thickness less than around 20 nm.
  • a concentration profile of the dopant B ions with respect to depth in the wafer 11 is illustrated by a curve 20.
  • the concentration profile of the dopant B ions has a straggle that should ideally not extend deeper than around 20nm into the wafer 11 to achieve the required thickness of the dopant B ion regions 18. It is also intended that the dopant B ion regions 18 comprise "top" layers, e.g. that they extend from the upper surface 19 of the wafer 11 down into the wafer 11.
  • the dopant B ions are implanted at energy less than 5 keV, usually less than 1 keV and most usually between 100 eV and 1 keV.
  • the dopant B ions are also implanted to a dose between around 5 x 10 13 cm “2 and 2 x 10 15 cm “2 . This achieves a dopant B atom concentration having a peak concentration of around 10 21 cm "3 .
  • vacancies are generated in vacancy regions 17 in the upper Si layer 12 of the wafer 11, by implanting vacancy generating Si ions into the wafer 11.
  • the vacancy generating Si ions also generate interstitials in interstitial regions 16, primarily in the lower Si layer 13 of the wafer 11.
  • a concentration profile of vacancy generating Si ions with respect to depth in the wafer 11 is illustrated by a curve 21.
  • the concentration profile of the vacancy generating Si ions has a peak that is (significantly) deeper than the oxide layer 14.
  • the concentration profile of the vacancies generated by the vacancy generating Si ions is illustrated by a curve 22.
  • the vacancy concentration profile is maximum at the upper surface 19 of the wafer 11 and declines with increasing depth. So, the vacancy regions 17 can also be considered to comprise "top" layers, e.g. they extend from the upper surface 19 of the wafer 11 down into the wafer 11.
  • the vacancy concentration In order to maximise the electrical activation of the dopant B ions after annealing, it is desirable for the vacancy concentration to be similar to or greater than the dopant B ion concentration in the dopant B ion regions 18. This is broadly achieved by attaining a peak vacancy concentration around the same as the peak dopant B atom concentration, e.g. around 10 21 cm "3 .
  • Monte Carlo model simulations have been carried out for the generation of vacancies with vacancy generating Si ions implanted at an energy of 40 keV to a dose of 4.5 x 10 14 cm “2 (plot 30); vacancy generating Si ions implanted at an energy of 100 keV to a dose of 7.2 x 10 14 cm “2 (plot 31); vacancy generating Si ions implanted at an energy of 160 keV to a dose of 1.1 x 10 15 cm “2 (plot 32); and vacancy generating Si ions implanted at an energy of 500 keV to a dose of 1.55 x 10 15 cm “2 (plot 33).
  • the vacancy concentration decreases approximately linearly inversely proportionally with increasing depth, e.g. as 10 21 cm "3 / depth (nm).
  • other considerations should ideally be taken into account when selecting the energy at which and the dose to which the vacancy generating ions are implanted.
  • the vacancy generating Si ions primarily reside in the lower Si layer 13 following implantation. However, more accurately, it is the interstitials generated by these ions that should reside in the lower Si layer 13, on the opposing side of the oxide layer 14 to the implanted B ions.
  • the concentration of vacancies and interstitials generated by the vacancy generating Si ions e.g. defect concentration, varies with depth in the wafer 11 such that the vacancy concentration declines as depth increases with curve 40 to substantially zero at around a crossover depth 41; and such that the interstitial concentration is substantially zero at small depths and increases at around the crossover depth 41 as depth increases with curve 42.
  • the crossover depth 41 varies approximately linearly with the energy at which the vacancy generating Si ions are implanted. This is illustrated in figure 5, where it can be seen that the crossover depth 41 increases from around 50nm at vacancy generating Si ion implant energy of around 50 keV to around 400 nm at vacancy generating Si ion implant energy of around 500 keV. Ideally, the vacancy generating Si ion implant energy is selected using this relationship so that the crossover depth coincides with or is deeper in the wafer 11 than the shallowest side of the barrier layer 14. So the crossover 41 should be deeper than the depth X 3 illustrated in Figure 4 in this embodiment.
  • the energy value is shown as 12 keV in Figure 6, but might be as low as 2 keV in other embodiments.
  • At the right hand end of the window 60 there is another energy, illustrated by line 62, above which increases in the vacancy concentration attainable in the dopant regions 18 with increasing energy become small or negligible.
  • vacancy generating Si ions may also begin to penetrate the gate stack 15.
  • the gate stack 15 is intended to act as a mask, such that substantially no ions are implanted in the wafer 11 under the gate stack 15 (other than at the edges of the region due to edge effects) and the region can form a channel of the semiconductor device 10.
  • the energy at which the vacancy generating Si ions are implanted is limited to below the energy at which a significant number of the ions will pass through the gate stack.
  • This energy is illustrated as around 20 keV in Figure 6, but might be as high as 300 keV or even 1 MeV in other embodiments, depending on the thickness of the gate stack 15 and the material from which it is made.
  • An illustration of the energy of the vacancy generating Si ions at which the gate stack I penetrated for gate stacks 15 of different thicknesses is shown in Figure 7. Departing upwardly from the window 60 by increasing the dose to which the vacancy generating Si ions are implanted causes amorphisation of the wafer 11. Amorphisation at the upper surface of the wafer 11 or even in the dopant region 18 should be avoided.
  • amorphous regions 23 are provided elsewhere in the Si wafer 11. More specifically, in second and third embodiments of the invention, semiconductor devices 10 as shown in Figures 8 and 9 are provided, similar to that shown in Figure 1 , but with amorphous regions 23 in the Si wafer 11. It can be seen that amorphous regions 23 are provided in the semiconductor device shown in Figure 7 that extend from within the barrier layer 14 to the vacancy regions 17, but not into the dopant regions 18.
  • these amorphous regions cause defects in the wafer between the dopant regions 18 and the barrier layer 14 to be swept into the barrier layer by Solid Phase Epitaxial Regrowth (SPER).
  • SPER Solid Phase Epitaxial Regrowth
  • similar amorphous regions 23 are provided in the semiconductor device shown in Figure 9 within the barrier layer 14 and that the vacancy regions 17 extend into the barrier layer 14. In this case, any affect of the presence of the amorphous regions 23 is limited by their containment in the barrier layer 23. So, the upper dose value of the window 60 is illustrated in Figure 6 by line 63 at around 10 15 cm '2 , but this may vary according to whether or not it is desired to provide amorphous regions 23.
  • Figure 10 illustrates how the extent and depth of the amorphous regions 23 can be controlled. It can be seen that increasing doses increase the extent of the amorphous regions 23 though the depth of the wafer 11. The aim is to select a dose such that the extent of the amorphous region is bounded at the required depth in the wafer.
  • Departing downwardly from the window 60 by decreasing the dose to which the vacancy generating Si ions are implanted reduces the attained vacancy concentration below the peak dopant B atom concentration and therefore reduces electrical activation of the dopant after anneal once doses below a given value (illustrated by line 64 at a value of around 5 x 10 14 in Figure 6) are reached.
  • the dose of the vacancy generating Si ions implanted at energy of 1 MeV is 4 x 10 15 cm “2 .
  • the dopant B ions are implanted at energy of 2 keV to a dose of 10 15 cm "2 .
  • the upper Si layer 12 is 110nm deep and the vacancy generating Si ions implanted at energy of 300 keV reside in the wafer 11 with a peak concentration around 500 nm deep in the wafer 11. Hall effect measurements can be used to determine the concentration Ns of electrically active dopant B atoms after anneal. Referring to figure 12, this concentration Ns is plotted against anneal temperature, where the annealing process is an isochronal regime over a duration of 10 s.
  • the concentration of dopant B atoms before and after annealing are plotted against depth in the wafer 11 when vacancy generating Si ions have been implanted at energy of 1 MeV and vacancy generating Si ions have been implanted at energy of 300 keV in figures 13 and 14 respectively.
  • the annealing was at 700 0 C.
  • a similar plot when no vacancy generating Si ions have been implanted shows no change in the concentration of implanted dopant B atoms.
  • a kink K is present in the profile of the concentration of dopant B atoms after annealing, but not before, when vacancy generating Si ions have been implanted at energy of 1 MeV.
  • This kink K represents a point at which an electrically active region of the profile of the concentration of dopant B atoms meets a region of clustered, electrically inactive dopant B atoms.
  • the position of the kink K suggests a concentration of electrically active dopant B atoms of around 5 x 10 19 cm "3 .
  • the kink K is also present in the profile of the concentration of dopant B atoms after annealing, but not before, when vacancy generating Si ions have been implanted at energy of 300 MeV.
  • the position of the kink K in this profile suggests a concentration of electrically active dopant B atoms of around 7 x 10 19 cm "3 , which is higher than when the vacancy generating Si ions have been implanted at energy of 1 MeV.
  • the described embodiments of the invention are only examples of how the invention may be implemented. For example, it is generally expected that the dimensions of semiconductor devices will gradually shrink as semiconductor manufacturing technology advances and consequently many of the dimensions, energies, doses and such like with decrease.
  • the invention might also be applied to other semiconductor devices, such as non-planar devices or bi-polar devices.
  • the ion implantation can be perpendicular to the wafer or at an angle, as desired.
  • Other modifications, variations and changes to the described embodiments will also occur to those having appropriate skills and knowledge. These modifications, variations and changes may be made without departure from the spirit and scope of the invention defined in the claims and its equivalents.

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Abstract

A semiconductor device 10 is manufactured using a Silicon (Si) On Insulator (SOI) wafer 11. The SOI wafer 11 has an upper layer 12 and lower layer 13 of Si crystal separated by a barrier layer 14 Silicon Oxide (SiO2). A gate stack 15 is formed on an upper surface 19 of the wafer 11. Source- drain extension regions are formed in the upper Si layer 12 of the wafer 11 on opposing sides of the gate stack 15 by implanting dopant Boron (B) ions in regions 18 shallow under the upper surface 19 of the wafer 11 , in the upper Si layer 12 of the wafer 11. The dopant B ions are implanted at energy less than around 5 keV and to a dose between around 5 x 1013 cm'2 and 2 x 1015 cm'2. This achieves a dopant B atom concentration having a peak concentration of around 1021 cm'3. Either before or after the dopant B ions are implanted, vacancies are generated in vacancy regions 17 in the upper Si layer 12 of the wafer 11 by implanting vacancy generating Si ions into the wafer 11. This can maximise the electrical activation of the dopant B ions after annealing.

Description

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
Field of the Invention
This invention relates to a semiconductor device and method of manufacture. More specifically, the invention relates to implanting vacancy generating ions to increase dopant electrical activation.
Background to the Invention
Increasing dopant electrical activation is a significant present concern in the field of semiconductor device manufacture. In order to become electrically active, a dopant atom must replace an atom of a semiconductor crystal in the crystal lattice. Dopant ions are usually implanted in the semiconductor crystal. The implantation process can cause some dopant ions to knock atoms of the semiconductor crystal out of the crystal lattice and replace them. However, most of the implanted dopant ions tend to settle at positions between the atoms of the crystal, e.g. to form so-called interstitials. The dopant implanted crystal can be annealed to cause these interstitial dopant ions to replace atoms of the semiconductor crystal. However, despite this, the attainable concentration of electrically active dopant atoms in the crystal tends to be limited to well below the solid solubility limit of the dopant atoms in the crystal, largely because the implanted dopant ions tend to cluster as their concentration increases and this clustering is promoted by the presence of excess interstitials. One suggested approach to improving dopant electrical activation has been to implant dopant ions in a region of the semiconductor crystal that has been amorphised. An annealing process can then be used to re-grow the semiconductor crystal in the dopant implanted amorphised region. This technique is commonly referred to as pre-amorphisation and the re-growth process known as Solid Phase Epitaxial Re-growth (SPER). It has been shown that pre-amorphisation and SPER can provide concentrations of electrically active dopant atoms above the solid solubility limit of the dopant atoms in the crystal. However, the maximum achievable dopant electrical activation remains limited to just a small fraction above the solid solubility limit of the dopant atoms in the crystal. This is insufficient for upcoming requirements of semiconductor manufacture, e.g. as set out in the International Technology Roadmap for Semiconductors (ITRS) for Complementary Metal-Oxide Semiconductor (CMOS) technology and such like. Furthermore, pre-amorphisation and SPER techniques tend to produce dopant layers that have significant so-called End Of Range (EOR) defects at the bottom of the dopant layer. These can influence the electrical characteristics of the semiconductor device, causing leakage currents and such like. Another, perhaps more promising, approach that has been suggested is commonly referred to as vacancy engineering. This involves implanting vacancy generating ions, which are usually, but not necessarily, electrically neutral, in the semiconductor crystal to generate vacancies in the crystal lattice. The vacancies encourage implanted dopant ions to enter the crystal lattice and become electrically active during annealing. US 6632728 describes a method of vacancy engineering. This publication recognises that generated vacancies can be effective in increasing electrical activation of a dopant in certain circumstances. In a specific example, it is suggested to implant vacancy generating Silicon (Si) ions into a single crystal Si substrate at an energy of 2 MeV to a dose of about 1016 cm'2; and to implant dopant Boron (B) ions into the substrate at an energy of 40 keV to a dose of about 2 x 1014 cm"2; and then to anneal the substrate for about 1 hr at temperatures ranging from about 400 0C to 800 0C. Elsewhere, it is suggested that the vacancy generating ions might be implanted at energies between 12 keV and 25 MeV to a dose between 1012 and 1017. It is also mentioned that the dopant ions might be implanted at an energy of the order of 10 keV. However, no clear guidance is given on how to select from these energies and doses to obtain increased electrical activation of the dopant. It is mentioned that the dose to which the vacancy generating ions is implanted should be higher than the dose to which the dopant ions are implanted. It is also mentioned that, in a preferred embodiment, the depth profile of the generated vacancies and the depth profile of the implanted dopant ions should overlap one anther, although no indication of how to achieve this is provided. Indeed, the mechanisms of vacancy generation and electrical activation are at best only partially understood and US 6632728 does not elaborate in any significant detail how to control these mechanisms to obtain increased dopant electrical activation. The present invention seeks to overcome this problem.
Summary of the Invention According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method comprising: implanting vacancy generating ions into a semiconductor wafer via a surface of the wafer to generate vacancies in the wafer; and providing dopant ions in the wafer to form a dopant layer very shallow under the surface, wherein the dopant layer remains substantially crystalline.
Importantly, the applicants have recognised that the vacancies generated by the vacancy generating ions in the semiconductor wafer typically have a maximum concentration at the surface of the wafer via which the vacancy generating ions are implanted. The concentration typically declines with increasing depth. So, providing the dopant ions in the semiconductor wafer just under the surface can make most effective use of the generated vacancies. This is extremely useful, as it is generally desired to manufacture semiconductor devices with increasingly shallow dopant layers. Furthermore, using this method, significantly higher electrical activation can be attained than demonstrated either by pre-amorphisation and Solid Phase Epitaxial Re-growth (SPER) or by previously reported vacancy engineering techniques. The reference to a "very shallow" dopant layer used above is well understood in the art. It typically refers to layers that extend to less than around 50 nm below the surface. However, the dopant layer may extend to less than 30 nm below the surface or even to less than 20 nm or 10 nm below the surface. This means that the dopant layer might preferably be called an ultra-shallow dopant layer. Whilst techniques such as ion diffusion can be used to provide the dopant ions in the semiconductor wafer, the dopant ions are usually implanted in the semiconductor wafer, e.g. using ion beam or plasma implantation techniques. The method may therefore comprise selecting an energy at which the dopant ions are implanted in the wafer to be less than around 5 keV. Indeed, the method may comprise selecting an/the energy at which the dopant ions are implanted in the wafer to be less than around 1 keV. This can provide a dopant layer that is suitably shallow.
The wafer can be any of a variety of suitable semiconductor materials. For example, the wafer may comprise a Silicon (Si) crystal, a Germanium (Ge) crystal, a Silicon Germanium (SiGe) alloy crystal, a Silicon Germanium Carbon (SiGeC) alloy crystal, a Silicon Carbon (SiC) alloy crystal, or various group Nl-V alloy crystals etc., whether produced by epitaxial growth or as bulk crystals, as desired. The crystal may be strained or unstrained.
It is preferred that the wafer incorporates a layer that acts as a barrier to diffusion of interstitials (or more generally defects including vacancies and interstitials) in the wafer. This barrier layer might be electrically insulating or electrically conducting or even a composite of insulating and conducting layers. Most frequently, the barrier layer is a layer of electrically insulating material. For example, the barrier layer may be a layer of aluminium oxide (AI2O3), aluminium nitride (AIN) or silicon oxide (SiO2). In particular, the wafer can be a so-called Silicon On Insulator (SOI) wafer. Alternatively, the insulating layer may be an air gap or an air gap which has been back-filled with an insulating material. In other words, the wafer might be a so-called Silicon On Nothing (SON) wafer or such like. In other examples, the wafer may be a strained SOI wafer, a Germanium On Insulator (GeOI) wafer or comprise any other material suitable for a desired application.
When the wafer has a barrier layer, it can be useful for method to comprise selecting an/the energy at which the vacancy generating ions are implanted in the wafer to be sufficient that the implanted vacancy generating ions reside primarily on the other side of the barrier layer to the surface via which they are implanted. Indeed, this is considered to be new in itself and, according to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method comprising: implanting vacancy generating ions into a semiconductor wafer incorporating a layer that acts as a barrier to diffusion of interstitials, the vacancy generating ions being implanted via a surface of the wafer to generate vacancies in the wafer; providing dopant ions in the wafer primarily between the surface and the barrier layer; and selecting an energy at which the vacancy generating ions are implanted such that the implanted vacancy generating ions reside primarily in a layer on the other side of the barrier layer to the surface via which they are implanted.
The implanted vacancy generating ions tend to create interstitials that can diffuse through the wafer during anneal. However, these interstitials cannot diffuse through the barrier layer. So, implanting the vacancy generating ions primarily (or even substantially totally) on the other side of the barrier layer to the dopant ions prevents the interstitials generated by the vacancy generating ions diffusing to where the dopant ions are implanted. Furthermore, whilst the vacancy generating ions are typically electrically neutral, they can nevertheless cause defects in the semiconductor wafer that contribute to leakage currents and such like. Indeed, in the vacancy generating ions may not even be electrically neutral. So, implanting them behind the barrier layer can avoid the vacancy generating ions directly influencing the electrical characteristics of the semiconductor device, e.g. causing leakage currents and such like.
It can be appreciated that the method can distinguish from the pre- amorphisation and Solid Phase Epitaxial Re-growth (SPER) technique described in the introduction to this document by requiring that the dopant layer remains substantially crystalline (e.g. throughout manufacture or at least during ion implantation and/or provision). In other words, the method may comprise selecting an/the energy at which and/or a dose to which the vacancy generating ions are implanted such that the vacancy generating ions do not amorphise the dopant layer. The threshold between amorphous material and crystalline material is well understood in the art. Completely crystalline material comprises a single crystal lattice. Moving away from this, the lattice might be broken or have some imperfections, but still remain substantially crystalline. Even polycrystalline material might be considered substantially crystalline in this context. The material might also contain a number of pockets of amorphous material whilst the crystal lattice remains intact over distances long relative to the size of the pockets and be considered substantially crystalline. However, once the lattice is sufficiently interrupted by pockets or regions of amorphous material that the crystal lattice is no longer a connected structure over long distances, it is no longer substantially crystalline and becomes amorphous.
Amorphisation of the deeper parts of the wafer can be tolerated or even be useful. In particular, the vacancy generating ions can amorphise a part of the wafer deeper from the surface than the barrier layer. Amorphisation of this part of the wafer can allow epitaxial re-growth to annihilate defects in this part of the wafer during annealling. Regardless, the structure of the wafer in this part of the wafer has little effect on the properties of the dopant layer or use of the dopant layer in the semiconductor device. The applicants have also recognised that amorphisation of the wafer proximate to the barrier layer on the same side of the barrier layer as the surface can be useful. More specifically, when this part of the wafer is amorphised, during annealing epitaxial re-growth can annihilate defects in this part of the wafer and/or sweep them down into the barrier layer away from the dopant layer. So, it can be preferred for the method to comprise selecting an/the energy at which and/or a dose to which the vacancy generating ions are implanted such that the vacancy generating ions amorphise a layer of the wafer deeper in the wafer than the dopant layer. This amorphised layer can be on the opposing side of the barrier layer or the same side of the barrier layer to the surface of the wafer via which the vacancy generating ions are implanted.
It is common to apply a mask to a semiconductor wafer before implanting the dopant ions, so that the dopant ions are only implanted through areas of the surface below which it is desired to form dopant layers, e.g. at the source and drain regions of semiconductor device. The mask might be a gate stack or such like. The applicants have recognised that it is useful to consider the influence of the mask on the vacancy generation ions. So, the method might comprise forming the mask on the wafer prior to implanting the vacancy generating ions and selecting the energy at which the vacancy generating ions are implanted such that substantially none of the vacancy generating ions penetrate directly through the mask. This can prevent either vacancies or interstitials generated by the vacancy generating ions or the vacancy generating ions themselves residing in the wafer under the mask. This, in turn, can prevent unwanted electrically active atoms residing under the mask after anneal. In another example, the method may comprise forming the mask on the wafer prior to implanting the vacancy generating ions and selecting the energy at which the vacancy generating ions are implanted such that interstitials generated by the vacancy generating ions implanted through the mask and/or those ions themselves (also) reside primarily in a layer on the other side of a/the barrier layer (of the wafer) to the surface via which they are implanted. This at least ensures that the most of the interstitials and vacancy generating ions reside under the barrier layer and do not affect electrical activation in the wafer between the barrier layer and the mask. It can also help to avoid the interstitials and/or vacancy generating ions directly influencing the electrical characteristics of the semiconductor device, e.g. causing leakage currents and such like.
The applicants have identified that selecting the energy at which the vacancy generating ions are implanted from a range between around 2 keV and 1 MeV is usually appropriate. Indeed, preferably the range is between around 5 keV and 100 keV (especially when the vacancy generating ions are Silicon (Si) ions and/or the mask or gate stack is relatively thin). This is significantly below the energy typically reported in the prior art and is achievable primarily due to utilisation of the peak vacancy concentration found at or just below the surface of the wafer through which the vacancy generating ions are implanted. These lower energies are also more readily and cheaply achievable during manufacture.
A variety of different ions are suitable for use and the vacancy generating ions for implementing the invention, such as Carbon (C), or Fluorine (F) for example. However, the implanted vacancy generating ions are most usually Silicon (Si) ions or Germanium (Ge) ions. Similarly, a variety of different ions are suitable for use as the dopant ions for implementing the invention, such as Indium (In), although the provided dopant ions are typically Boron (B) ions.
Conveniently, the applicants have recognised that good electrical activation is achievable at relatively low annealing temperatures and short annealing durations. Indeed, the method may comprise annealing the wafer at a temperature below around 85O0C. Similarly, the method may comprise annealing the wafer for duration less than around 10s. Both of these features have the advantage of reducing the cost of manufacture. It should be noted that reference to the "surface of the wafer" is made loosely in this document rather than explicitly. More specifically, it is well known that the surface of a semiconductor wafer more often than not comprises a layer of oxide or such like in practice. Such a layer may be present or not and the term through the surface of the wafer can refer to through such a layer or not. However, it may be necessary to select appropriate energies or doses that take into account the presence or not of such a layer. It might also be preferred for the method to include removing any such layer before or after ion implantation and/or provision, e.g. by thermal desorption or such like. Preferred embodiments of the invention are now described, by way of example only, with reference to the accompanying drawings.
Brief Description of the Drawings
Figure 1 is a schematic sectional view of a first embodiment of a semiconductor device during manufacture;
Figure 2 is a graphical representation of ion and vacancy concentration versus depth in a semiconductor wafer during manufacture of the semiconductor device illustrated in Figure 1 ; Figure 3 is a graphical representation of vacancy concentration versus depth in the semiconductor wafer simulated using a Monte Carlo model for vacancy generating ions implanted at different energies and to different doses;
Figure 4 is a graphical representation of vacancy and interstitial concentration versus depth in the semiconductor wafer;
Figure 5 is a graphical representation of crossover depth between vacancy generation and interstitial generation versus energy at which vacancy generating ions are implanted in the semiconductor wafer; Figure 6 is a graphical representation of an ideal window of doses to which vacancy generating ions are implanted and energy at which the ions are implanted;
Figure 7 is a graphical illustration of energy at which vacancy generating ions penetrate gate stacks of different thicknesses;
Figure 8 is a schematic sectional view of a second embodiment of a semiconductor device during manufacture
Figure 9 is a schematic sectional view of a third embodiment of a semiconductor device during manufacture; Figure 10 is a graphical illustration of atomic displacements per unit volume versus depth for different vacancy generating ion doses;
Figure 11 is a graphical representation of the relation between windows of dose and energy for vacancy generating ions of different types;
Figure 12 is a graphical representation of dopant electrical activation versus anneal temperature for three different vacancy generating ion implants;
Figure 13 is a graphical representation of dopant atom concentration versus depth in the semiconductor wafer before and after annealing for vacancy generating ions implanted at 1 MeV; and Figure 14 is a graphical representation of dopant atom concentration versus depth in the semiconductor wafer before and after annealing for vacancy generating ions implanted at 300 keV;
Detailed Description of the Preferred Embodiments Referring to figure 1 , in a first embodiment of the invention, a semiconductor device 10 is manufactured using a Silicon (Si) On Insulator (SOI) wafer 11. The SOI wafer 11 has an upper layer 12 and lower layer 13 of Si crystal separated by a barrier layer 14 Silicon Oxide (SiO2). The barrier layer 14 separates the two Si layers 12, 13, which can have a number of advantages, as elaborated below, and is often referred to as a Buried Oxide (BOX) layer.
A gate stack 15 is formed on an upper surface 19 of the wafer 11. The gate stack 15 and upper Si layer 12 of the wafer 11 are shown in contact with one another in Figure 1 , although in reality an oxide layer or such like may be present between the gate stack 15 and the wafer 11 , which is largely ignored in this description for simplicity. The gate stack 15 has thickness of around 100 nm or less. Source-drain extension regions are formed in the upper Si layer 12 of the wafer 11 on opposing sides of the gate stack 15 by implanting dopant Boron (B) ions in regions 18 shallow under the upper surface 19 of the wafer 11 , in the upper Si layer 12 of the wafer 11. A region of the gate stack 15 between the source-drain extension regions forms a channel of the device 10. The upper Si layer 12 can have thickness of around 50 nm or less. In this embodiment, the regions 18 formed by the dopant B ions have thickness less than around 20 nm.
Referring to figure 2, a concentration profile of the dopant B ions with respect to depth in the wafer 11 is illustrated by a curve 20. The concentration profile of the dopant B ions has a straggle that should ideally not extend deeper than around 20nm into the wafer 11 to achieve the required thickness of the dopant B ion regions 18. It is also intended that the dopant B ion regions 18 comprise "top" layers, e.g. that they extend from the upper surface 19 of the wafer 11 down into the wafer 11. In order to achieve this, the dopant B ions are implanted at energy less than 5 keV, usually less than 1 keV and most usually between 100 eV and 1 keV. The dopant B ions are also implanted to a dose between around 5 x 1013 cm"2 and 2 x 1015 cm"2. This achieves a dopant B atom concentration having a peak concentration of around 1021 cm"3.
Either before or after the dopant B ions are implanted, vacancies are generated in vacancy regions 17 in the upper Si layer 12 of the wafer 11, by implanting vacancy generating Si ions into the wafer 11. The vacancy generating Si ions also generate interstitials in interstitial regions 16, primarily in the lower Si layer 13 of the wafer 11. Referring again to Figure 2, a concentration profile of vacancy generating Si ions with respect to depth in the wafer 11 is illustrated by a curve 21. In this embodiment, the concentration profile of the vacancy generating Si ions has a peak that is (significantly) deeper than the oxide layer 14. The concentration profile of the vacancies generated by the vacancy generating Si ions is illustrated by a curve 22. It can be seen that the vacancy concentration profile is maximum at the upper surface 19 of the wafer 11 and declines with increasing depth. So, the vacancy regions 17 can also be considered to comprise "top" layers, e.g. they extend from the upper surface 19 of the wafer 11 down into the wafer 11.
In order to maximise the electrical activation of the dopant B ions after annealing, it is desirable for the vacancy concentration to be similar to or greater than the dopant B ion concentration in the dopant B ion regions 18. This is broadly achieved by attaining a peak vacancy concentration around the same as the peak dopant B atom concentration, e.g. around 1021 cm"3. Referring to figure 3, Monte Carlo model simulations have been carried out for the generation of vacancies with vacancy generating Si ions implanted at an energy of 40 keV to a dose of 4.5 x 1014 cm"2 (plot 30); vacancy generating Si ions implanted at an energy of 100 keV to a dose of 7.2 x 1014 cm"2 (plot 31); vacancy generating Si ions implanted at an energy of 160 keV to a dose of 1.1 x 1015 cm"2 (plot 32); and vacancy generating Si ions implanted at an energy of 500 keV to a dose of 1.55 x 1015 cm"2 (plot 33). It can be seen that, between depths in the wafer 11 below the upper surface 19 of around 1 nm to around 10 nm, the vacancy concentration decreases approximately linearly inversely proportionally with increasing depth, e.g. as 1021 cm"3/ depth (nm). However, other considerations should ideally be taken into account when selecting the energy at which and the dose to which the vacancy generating ions are implanted.
It has been mentioned above that the vacancy generating Si ions primarily reside in the lower Si layer 13 following implantation. However, more accurately, it is the interstitials generated by these ions that should reside in the lower Si layer 13, on the opposing side of the oxide layer 14 to the implanted B ions. As illustrated in Figure 4, the concentration of vacancies and interstitials generated by the vacancy generating Si ions, e.g. defect concentration, varies with depth in the wafer 11 such that the vacancy concentration declines as depth increases with curve 40 to substantially zero at around a crossover depth 41; and such that the interstitial concentration is substantially zero at small depths and increases at around the crossover depth 41 as depth increases with curve 42. Importantly, the crossover depth 41 varies approximately linearly with the energy at which the vacancy generating Si ions are implanted. This is illustrated in figure 5, where it can be seen that the crossover depth 41 increases from around 50nm at vacancy generating Si ion implant energy of around 50 keV to around 400 nm at vacancy generating Si ion implant energy of around 500 keV. Ideally, the vacancy generating Si ion implant energy is selected using this relationship so that the crossover depth coincides with or is deeper in the wafer 11 than the shallowest side of the barrier layer 14. So the crossover 41 should be deeper than the depth X3 illustrated in Figure 4 in this embodiment.
It is useful to consider the extent to which the selection of the energy at which and dose to which the vacancy generating Si ions can be varied. The extent of the possible variation is illustrated in Figure 6 by a window 60 of possible energy/dose combinations. At the left hand end of the window 60 is an energy value illustrated by line 61 , below which the crossover depth 41 referred to above is likely to reside too shallow in the wafer 11. In the embodiment described above with reference to Figure 1 , this energy value is that at which the crossover depth 41 shallower than the shallowest side of the barrier layer 14. In other embodiments, it is the energy at which a significant number of interstitials or implanted vacancy generating Si ions begin to reside in the dopant regions 18. The energy value is shown as 12 keV in Figure 6, but might be as low as 2 keV in other embodiments. At the right hand end of the window 60 there is another energy, illustrated by line 62, above which increases in the vacancy concentration attainable in the dopant regions 18 with increasing energy become small or negligible. Importantly, above this energy value, vacancy generating Si ions may also begin to penetrate the gate stack 15. The gate stack 15 is intended to act as a mask, such that substantially no ions are implanted in the wafer 11 under the gate stack 15 (other than at the edges of the region due to edge effects) and the region can form a channel of the semiconductor device 10. So the energy at which the vacancy generating Si ions are implanted is limited to below the energy at which a significant number of the ions will pass through the gate stack. This energy is illustrated as around 20 keV in Figure 6, but might be as high as 300 keV or even 1 MeV in other embodiments, depending on the thickness of the gate stack 15 and the material from which it is made. An illustration of the energy of the vacancy generating Si ions at which the gate stack I penetrated for gate stacks 15 of different thicknesses is shown in Figure 7. Departing upwardly from the window 60 by increasing the dose to which the vacancy generating Si ions are implanted causes amorphisation of the wafer 11. Amorphisation at the upper surface of the wafer 11 or even in the dopant region 18 should be avoided. Indeed, in the embodiment of the invention shown in Figure 1, amorphisation anywhere in the wafer 11 is avoided. However, referring to Figures 8 and 9, in other embodiments of the invention, amorphous regions 23 are provided elsewhere in the Si wafer 11. More specifically, in second and third embodiments of the invention, semiconductor devices 10 as shown in Figures 8 and 9 are provided, similar to that shown in Figure 1 , but with amorphous regions 23 in the Si wafer 11. It can be seen that amorphous regions 23 are provided in the semiconductor device shown in Figure 7 that extend from within the barrier layer 14 to the vacancy regions 17, but not into the dopant regions 18. During annealing, these amorphous regions cause defects in the wafer between the dopant regions 18 and the barrier layer 14 to be swept into the barrier layer by Solid Phase Epitaxial Regrowth (SPER). Similarly, it can be seen that similar amorphous regions 23 are provided in the semiconductor device shown in Figure 9 within the barrier layer 14 and that the vacancy regions 17 extend into the barrier layer 14. In this case, any affect of the presence of the amorphous regions 23 is limited by their containment in the barrier layer 23. So, the upper dose value of the window 60 is illustrated in Figure 6 by line 63 at around 1015 cm'2, but this may vary according to whether or not it is desired to provide amorphous regions 23.
Figure 10 illustrates how the extent and depth of the amorphous regions 23 can be controlled. It can be seen that increasing doses increase the extent of the amorphous regions 23 though the depth of the wafer 11. The aim is to select a dose such that the extent of the amorphous region is bounded at the required depth in the wafer.
Departing downwardly from the window 60 by decreasing the dose to which the vacancy generating Si ions are implanted reduces the attained vacancy concentration below the peak dopant B atom concentration and therefore reduces electrical activation of the dopant after anneal once doses below a given value (illustrated by line 64 at a value of around 5 x 1014 in Figure 6) are reached.
Similar windows exist for other types of vacancy generating ions and the relationship between these windows is illustrated in Figure 11. It can be appreciated that Germanium (Ge) can be implanted with lower doses than Si, as it has a higher atomic mass and therefore generates more vacancies per unit dose. In contrast, higher doses of Carbon (C) or Fluorine (F) are required. It is interesting to compare experimentally the effects of not implanting vacancy generating ions; implanting vacancy generating Si ions at energy of 300 keV; and implanting vacancy generating Si ions at energy of 1 MeV. The dose of the vacancy generating Si ions implanted at energy of 300 keV is 1.5 x 1015 cm'2. The dose of the vacancy generating Si ions implanted at energy of 1 MeV is 4 x 1015 cm"2. The dopant B ions are implanted at energy of 2 keV to a dose of 1015 cm"2. The upper Si layer 12 is 110nm deep and the vacancy generating Si ions implanted at energy of 300 keV reside in the wafer 11 with a peak concentration around 500 nm deep in the wafer 11. Hall effect measurements can be used to determine the concentration Ns of electrically active dopant B atoms after anneal. Referring to figure 12, this concentration Ns is plotted against anneal temperature, where the annealing process is an isochronal regime over a duration of 10 s. It can be seen that there is a significantly greater concentration of electrically active dopant B atoms for anneal temperatures below around 850 0C when vacancy generating Si ions are implanted at energy of 300 keV (plot 70) than when vacancy generating Si ions are implanted at energy of 1 MeV (plot 71) and, in turn, when no vacancy generating Si ions are implanted (plot 70). This suggests that annealing the wafer at temperature below around 850 0C is effective to increase electrical activation and the cost of higher temperature annealing can be avoided.
Looking at this in more detail, the concentration of dopant B atoms before and after annealing are plotted against depth in the wafer 11 when vacancy generating Si ions have been implanted at energy of 1 MeV and vacancy generating Si ions have been implanted at energy of 300 keV in figures 13 and 14 respectively. Here, the annealing was at 700 0C. A similar plot when no vacancy generating Si ions have been implanted shows no change in the concentration of implanted dopant B atoms. Referring to figure 13, a kink K is present in the profile of the concentration of dopant B atoms after annealing, but not before, when vacancy generating Si ions have been implanted at energy of 1 MeV. This kink K represents a point at which an electrically active region of the profile of the concentration of dopant B atoms meets a region of clustered, electrically inactive dopant B atoms. The position of the kink K suggests a concentration of electrically active dopant B atoms of around 5 x 1019 cm"3. Referring to figure 14, the kink K is also present in the profile of the concentration of dopant B atoms after annealing, but not before, when vacancy generating Si ions have been implanted at energy of 300 MeV. However, the position of the kink K in this profile suggests a concentration of electrically active dopant B atoms of around 7 x 1019 cm"3, which is higher than when the vacancy generating Si ions have been implanted at energy of 1 MeV.
The described embodiments of the invention are only examples of how the invention may be implemented. For example, it is generally expected that the dimensions of semiconductor devices will gradually shrink as semiconductor manufacturing technology advances and consequently many of the dimensions, energies, doses and such like with decrease. The invention might also be applied to other semiconductor devices, such as non-planar devices or bi-polar devices. The ion implantation can be perpendicular to the wafer or at an angle, as desired. Other modifications, variations and changes to the described embodiments will also occur to those having appropriate skills and knowledge. These modifications, variations and changes may be made without departure from the spirit and scope of the invention defined in the claims and its equivalents.

Claims

Claims
1. A method of manufacturing a semiconductor device, the method comprising: implanting vacancy generating ions into a semiconductor wafer via a surface of the wafer to generate vacancies in the wafer; and providing dopant ions in the wafer to form a dopant layer very shallow under the surface, wherein the dopant layer remains substantially crystalline.
2. The method of claim 1 , wherein the dopant layer extends to less than around 50 nm below the surface.
3. The method of claim 1 or claim 2, comprising implanting the dopant ions in the semiconductor wafer.
4. The method of claim 2, comprising selecting an energy at which the dopant ions are implanted in the wafer to be less than around 5 keV.
5. The method of claim 3 or claim 4, comprising selecting an/the energy at which the dopant ions are implanted in the wafer to be less than around 1 keV.
6. The method of any one of the preceding claims, wherein the wafer incorporates a layer that acts as a barrier to diffusion of interstitials.
7. The method of claim 6, wherein the wafer comprises a silicon crystal and the barrier layer is a layer of silicon oxide.
8. The method of claim 6 or claim 7, comprising selecting an/the energy at which the vacancy generating ions are implanted in the wafer to be sufficient that the implanted vacancy generating ions reside primarily on the other side of the barrier layer to the surface via which they are implanted.
9. A method of manufacturing a semiconductor device, the method comprising: implanting vacancy generating ions into a semiconductor wafer incorporating a layer that acts as a barrier to diffusion of interstitials, the vacancy generating ions being implanted via a surface of the wafer to generate vacancies in the wafer; providing dopant ions in the wafer primarily between the surface and the barrier layer; and selecting the energy at which and/or a dose to which the vacancy generating ions are implanted such that the vacancy generating ions amorphise a layer of the wafer deeper in the wafer than the dopant layer.
10. The method of any one of the preceding claims, comprising selecting the energy at which and/or a dose to which the vacancy generating ions are implanted such that the vacancy generating ions amorphise a layer of the wafer deeper in the wafer than the dopant layer.
11. The method of any one claims 6 to 9, comprising selecting the energy at which and/or a dose to which the vacancy generating ions are implanted such that the vacancy generating ions amorphise a layer of the wafer deeper in the wafer than the dopant layer but with at least a portion of the layer being shallower in the wafer than the barrier layer.
12. The method of any one claims 6 to 9, comprising selecting the energy at which and/or a dose to which the vacancy generating ions are implanted such that the vacancy generating ions amorphise a layer of the wafer within the barrier layer.
13. The method of any one of the preceding claims, comprising forming a mask on the wafer prior to implanting the vacancy generating ions and selecting the energy at which the vacancy generating ions are implanted such that substantially none of the vacancy generating ions penetrate directly through the mask.
14. The method of any one of claims 1 to 12, comprising forming a mask on the wafer prior to implanting the vacancy generating ions and selecting the energy at which the vacancy generating ions are implanted such that the vacancy generating ions implanted through the mask also reside primarily in a layer on the other side of the barrier layer to the surface via which they are implanted.
15. The method of claim 13 or claim 14, wherein the mask forms a gate stack of the device.
16. The method of any one of the preceding claims, comprising selecting the energy at which the vacancy generating ions are implanted from a range between around 2 keV and 1 MeV.
17. The method of any one of the preceding claims, comprising selecting the energy at which the vacancy generating ions are implanted from a range between around 5 keV and 100 keV.
18. The method of any one of the preceding claims, wherein the implanted vacancy generating ions are Silicon ions.
19. The method of any one of the preceding claims, wherein the implanted vacancy generating ions are Germanium ions.
20. The method of any one of the preceding claims, wherein the provided dopant ions are Boron ions.
21. The method of any one of the preceding claims, comprising annealing the wafer at a temperature less than around 8500C.
22. A semiconductor device manufactured using the method of any one of the preceding claims.
23. A method of manufacturing a semiconductor device, substantially as described with reference to the accompanying drawings.
24. A semiconductor device, substantially as described with reference to the accompanying drawings.
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