AU2003201676A1 - Method for forming shallow junctions by ion implantation in silicon wafers - Google Patents

Method for forming shallow junctions by ion implantation in silicon wafers

Info

Publication number
AU2003201676A1
AU2003201676A1 AU2003201676A AU2003201676A AU2003201676A1 AU 2003201676 A1 AU2003201676 A1 AU 2003201676A1 AU 2003201676 A AU2003201676 A AU 2003201676A AU 2003201676 A AU2003201676 A AU 2003201676A AU 2003201676 A1 AU2003201676 A1 AU 2003201676A1
Authority
AU
Australia
Prior art keywords
ion implantation
silicon wafers
shallow junctions
forming shallow
junctions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003201676A
Inventor
Ahmed Nejim
Brian Sealy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Surrey
Original Assignee
University of Surrey
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Surrey filed Critical University of Surrey
Publication of AU2003201676A1 publication Critical patent/AU2003201676A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/66772Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Physical Vapour Deposition (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
AU2003201676A 2002-01-16 2003-01-15 Method for forming shallow junctions by ion implantation in silicon wafers Abandoned AU2003201676A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GBGB0200879.5A GB0200879D0 (en) 2002-01-16 2002-01-16 Ion implanted junctions in silicon wafers
GB0200879.5 2002-01-16
PCT/GB2003/000136 WO2003063218A2 (en) 2002-01-16 2003-01-15 Method for forming shallow junctions by ion implantation in silicon wafers

Publications (1)

Publication Number Publication Date
AU2003201676A1 true AU2003201676A1 (en) 2003-09-02

Family

ID=9929131

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003201676A Abandoned AU2003201676A1 (en) 2002-01-16 2003-01-15 Method for forming shallow junctions by ion implantation in silicon wafers

Country Status (3)

Country Link
AU (1) AU2003201676A1 (en)
GB (1) GB0200879D0 (en)
WO (1) WO2003063218A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7846822B2 (en) 2004-07-30 2010-12-07 The Board Of Trustees Of The University Of Illinois Methods for controlling dopant concentration and activation in semiconductor structures
US7172954B2 (en) 2005-05-05 2007-02-06 Infineon Technologies Ag Implantation process in semiconductor fabrication
WO2006125993A1 (en) * 2005-05-27 2006-11-30 University Of Surrey Semiconductor device and method of manufacture
US7968440B2 (en) 2008-03-19 2011-06-28 The Board Of Trustees Of The University Of Illinois Preparation of ultra-shallow semiconductor junctions using intermediate temperature ramp rates and solid interfaces for defect engineering
US8871670B2 (en) 2011-01-05 2014-10-28 The Board Of Trustees Of The University Of Illinois Defect engineering in metal oxides via surfaces
US8813580B2 (en) * 2012-03-05 2014-08-26 Honeywell International Inc. Apparatus and processes for silicon on insulator MEMS pressure sensors

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05129536A (en) * 1991-11-01 1993-05-25 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
JP3070420B2 (en) * 1994-12-21 2000-07-31 日本電気株式会社 Method for manufacturing semiconductor device
KR970072066A (en) * 1996-04-29 1997-11-07 윌리엄 비. 켐플러 How to optimize the sub-amorphous threshold amount implantation energy used prior to dopant implantation to achieve shallower junctions
US6037640A (en) * 1997-11-12 2000-03-14 International Business Machines Corporation Ultra-shallow semiconductor junction formation

Also Published As

Publication number Publication date
WO2003063218A3 (en) 2003-11-06
WO2003063218A2 (en) 2003-07-31
GB0200879D0 (en) 2002-03-06

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase