JP4573544B2 - Display device - Google Patents

Description

  The present invention relates to a display device using an insulated gate field effect transistor, and more particularly to a circuit that converts a serially input display signal into a parallel signal. More specifically, the present invention relates to a configuration of a level conversion unit that performs level conversion on a digital display signal having a small amplitude and latches the digital display signal.

  In a display device such as liquid crystal or organic EL (electroluminescence), pixel data signals for driving display pixels are supplied from an IC (integrated circuit chip) provided outside the display device. In this case, the external IC transfers, for example, a TTL level small amplitude signal as the display data signal. The pixel display signal applied to the pixel element is given as a multi-bit digital signal. After a display data signal from the outside is level-converted inside the display device to a voltage level required by the display device, a multi-bit digital signal is converted into an analog signal, a corresponding gradation voltage is selected, and a pixel element Written in.

  The display data for each pixel is composed of a plurality of bits, and the display data for each pixel is transferred serially, and then the pixels in one row are output in parallel and converted into analog signals. Accordingly, as a signal line for transmitting display data, in the case of the full color specification, 3 · M signals are used to transmit data of a plurality of bits for each of R (red), G (green), and B (blue). A line is provided. Here, M indicates the number of bits of display data.

  In the display device, only circuit portions required for display operation are integrated, and other circuit portions are provided outside the display device. As a result, the number of circuits used in the display device is reduced, and accordingly the cost and size of the display device are reduced.

  These display signals are supplied from a driving LSI provided outside. The drive LSI is being miniaturized to reduce the manufacturing cost, and accordingly, the breakdown voltage of the transistor is lowered. In order to compensate the breakdown voltage characteristics of the transistor and reduce power consumption, the power supply voltage level is reduced. As a result, the amplitude of the pixel display data signal supplied from the driving LSI is also reduced, and for example, the logic high level (H level) voltage level may be 1.8V.

  In addition, since the reduction of the amplitude of the image data signal is preferable from the viewpoint of reducing EMI (electromagnetic radiation noise) and / or power consumption due to the signals of a large number of input pixel data lines, the signal amplitude is further reduced in the future. Be in the direction to be.

  On the other hand, in this display device, a polysilicon TFT (thin film transistor) is used as a transistor. In a display device, it is difficult to perform high-temperature heat treatment from the viewpoint of the reliability of display pixels. Therefore, the crystallinity of polysilicon TFT is worse than that of a transistor using single crystal silicon, and the threshold voltage is reduced. It is difficult to reduce the manufacturing technology.

  At present, the threshold voltage of this polysilicon TFT is as high as 2V to 4V, and it is difficult to operate this polysilicon TFT using a signal of 1.8V. Therefore, at present, in a display device incorporating a serial / parallel conversion circuit for a pixel display data signal, 3V to 5V is generally used as the H level of the pixel display data signal. This serial / parallel conversion circuit converts a multi-bit pixel data signal given serially in pixel units from the outside into a display data signal for one row of pixels. A display signal supplied to each pixel is generated by converting a display data signal of a plurality of bits for each pixel into an analog signal.

  In this converter, in order to convert a display data signal with a small amplitude from the outside into a signal corresponding to the operating power supply voltage inside the display device, the voltage level of the input pixel display data signal (digital signal) A level conversion circuit for converting the level into a signal having a voltage amplitude necessary for driving the circuit is provided.

  An example of a circuit configuration for driving a data line of a display device having such a level conversion circuit is shown in Patent Document 1 (Japanese Patent Laid-Open No. 2000-122623). In Patent Document 1, pixel data is sampled in a sampling memory according to a shift register. After sampling the data corresponding to the display pixels of one row (one scanning line), the sampling data is transferred to the hold memory. The output signal of the hold memory is level-converted by a level shifter, then digital / analog converted and output. In this patent document 1, in a color liquid crystal display device, an operation mode for simultaneously capturing three basic data of RGB and an operation mode for capturing these RGB in three times for each system are switched. Yes. However, no consideration is given to the specific configuration of the level shifter, and no consideration is given to the amplitude of the input pixel data signal.

  In addition, a configuration in which a level conversion circuit is provided in a serial / parallel conversion unit of a TFT type liquid crystal display device is shown in Patent Document 2 (Japanese Patent Laid-Open No. 11-95729). In the configuration disclosed in Patent Document 2, an input data signal is sequentially latched by a data latch circuit in accordance with the output of the shift register, the level of the latch signal of the data latch circuit is converted, and then a digital / analog conversion is performed to display a display signal. The configuration to generate is shown. In Patent Document 2, an adjacent data line is temporarily short-circuited at the time of polarity reversal during AC operation, the amplitude at the time of data line driving at the time of polarity change of gradation voltage is reduced, and a common constant driving method with low power consumption. The dot inversion drive is performed according to the above. Here, the common constant drive method is a method in which a voltage having a positive polarity and a voltage having a negative polarity are alternately applied to the pixel electrode while the voltage of the counter electrode is fixed at a constant level. .

Further, Patent Document 3 (Japanese Patent Laid-Open No. 2002-358055) discloses a configuration in which a differential amplifier is used for a level conversion unit of a level conversion circuit in a display device. In Patent Document 3, for example, the level conversion circuit is operated only for a predetermined period in accordance with the pixel start signal of the frame to compare the input signal with the reference voltage, and the comparison result is latched by the latch circuit at the next stage. By operating the differential amplifier of the level conversion circuit only for a necessary period, current consumption is reduced compared to the case where this differential amplifier is always operated.
JP 2000-122623 A Japanese Patent Laid-Open No. 11-95729 Japanese Patent Laid-Open No. 2002-358055 JP-A-5-129848

  The level conversion circuit disclosed in Patent Document 3 described above has a configuration in which a TTL level DC signal given from the outside is converted into a DC signal at a power supply voltage level used inside the display device and used in the internal circuit. When the level conversion circuit shown in Patent Document 3 is used for a circuit for converting the level of an input pixel data signal supplied from an external drive LSI, a differential amplifier circuit is arranged corresponding to each pixel data line. There is a need. Therefore, the same number of differential amplifier circuits as the pixels aligned in the horizontal direction of the pixel matrix are connected to the pixel data signal line, and the load on the input pixel data signal line is large, and the pixel data signal is Therefore, there is a problem that the power consumption of the driving LSI increases.

  In the differential amplifier, an offset voltage is generated due to variations in threshold voltages of transistors constituting the differential stage. In particular, when a polysilicon TFT generally used in a display device is used, the threshold voltage variation of the transistor is large as described above, and the offset voltage of the differential amplifier is also large. If the offset voltage is not compensated, the comparison between the reference voltage and the input signal cannot be performed accurately. In Patent Document 3, the existence of the offset voltage of such a differential amplifier and its influence are not taken into consideration.

  A general configuration of a differential amplifier that compensates for this offset voltage is disclosed in the aforementioned Patent Document 4. In the configuration disclosed in Patent Document 4, the output node is driven according to the output voltage of the differential amplifier while the differential input of the differential amplifier is short-circuited. The output node voltage is compared with the reference voltage, and the output voltage level of the differential amplifier is adjusted based on the comparison result so that the output voltage of the differential amplifier matches the reference voltage. The reference voltage is made to correspond to the input logic threshold value of the next stage circuit. In the configuration shown in this Patent Document 4, in order to adjust the output voltage level of the differential amplifier, the drive current of the current mirror stage of the differential amplifier is adjusted using the charging voltage of the capacitive element to output the differential amplifier. The voltage level of the voltage and the reference voltage are matched. As a result, the number of circuit elements increases and the circuit occupation area increases. Further, the offset of the comparison circuit that compares the output voltage and the reference voltage is not taken into consideration.

  In the configuration disclosed in Patent Document 4, a control circuit is required for each differential amplifier to control the charge / discharge operation of the capacitive element based on the match / mismatch of the reference voltage and the output voltage. Therefore, it is difficult to use the offset voltage compensation configuration of the differential amplifier circuit disclosed in Patent Document 4 for level conversion of pixel data signals in a display device that requires small size and low power consumption. .

  SUMMARY OF THE INVENTION An object of the present invention is to provide a display device that can operate accurately even when a pixel data signal having a voltage level lower than the threshold voltage of a TFT is input.

  Another object of the present invention is to provide a display device capable of reducing EMI and power consumption by reducing the amplitude of an input pixel data signal.

Display device according to the inventions has a plurality of pixel elements arranged in rows and columns, it is arranged corresponding to each pixel column, each being connected to a corresponding pixel element, the display for the selected pixel elements in the corresponding column A plurality of data lines for transferring signals and a voltage having a potential difference larger than the amplitude of the input data signal are received as operation power supply voltages and activated in response to a data line selection signal for selecting a data line. A differential amplifier circuit that differentially amplifies and outputs the potentials of the first and second inputs, a capacitive element having one electrode connected to the second input of the differential amplifier circuit, and a data line Conducting according to the activation of the selection signal, and when conducting, the first switching element for transmitting the input data signal to the first input of the differential amplifier circuit and the first switching selectively according to the activation of the data line selection signal Complementary to the element And, a second switching element for transmitting the reference voltage to the first input of the differential amplifier circuit conducts the second switching element and phase in accordance with the data line selection signal, when conductive, the output of the differential amplifier circuit A third switching element coupled to one electrode of the capacitive element, a latch circuit for latching an output signal of the differential amplifier circuit, and a display for generating a display signal for a corresponding data line based on at least the output signal of the latch circuit A signal generation circuit.

In the display device according to the invention is carried out level conversion of the input data signal using a differential amplifier circuit, even when the differential amplifier circuit is formed of polysilicon TFT, than its threshold voltage It is possible to perform level conversion of an input data signal having a low voltage level. Thereby, the power consumption of the driving LSI can be reduced, and a display device with reduced EMI can be realized.

  In the differential amplifier circuit, the differential amplifier circuit is operated by a voltage follower, the output voltage with respect to the reference voltage is stored in the capacitive element, and the stored voltage of the capacitive element is compared with the input pixel data signal. Therefore, even when the threshold voltage variation of the TFT of the differential amplifier circuit is large, the offset of the differential amplifier circuit can be accurately canceled to generate the output voltage, and the input pixel data can be accurately generated. Level conversion can be performed by determining the logic level of the signal. In addition, the reference voltage compensated for offset is stored in the capacitor element, the circuit configuration is simplified, the number of elements can be reduced, and a display device with reduced power consumption with a small occupation area can be realized. it can.

[Embodiment 1]
FIG. 1 schematically shows an overall configuration of the display device according to the first embodiment of the present invention. In FIG. 1, a configuration of a liquid crystal display device 10 in which a liquid crystal element is used as a pixel element is shown as an example of the display device.

  In FIG. 1, the liquid crystal display device 10 includes a pixel matrix 20 including a plurality of pixels 25 arranged in a matrix, and gate lines GL (GL1,...) Provided corresponding to the rows of the pixels of the pixel matrix 20. A gate line driving circuit 30 for driving and a data line driving circuit 40 for transmitting a pixel display signal to the data lines DL (DL1, DL2,...) Provided corresponding to the pixel columns of the pixel matrix 20 are included.

  In the pixel matrix 20, data lines are arranged corresponding to the respective pixel columns, and gate lines are arranged corresponding to the respective pixel rows. However, in FIG. 1, the data lines DL1 and DL2 are typically shown. A gate line GL1 is shown.

  In the following description, the direction in which the gate line GL1 extends is referred to as the row direction, and the direction in which the data lines DL1 and DL2 extend is referred to as the column direction.

  In addition, the symbol GL is used when generically indicating the gate line, and the symbol DL is used when generically showing the data line.

  The pixel 25 is provided between the corresponding data line DL and the internal pixel node NX1, and is turned on in response to the signal potential on the corresponding gate line GL, and the pixel node NX1 and the common electrode. A capacitive element 27 and a liquid crystal display element 28 provided in parallel with each other between the nodes NX2 are included.

  The orientation of the liquid crystal in the liquid crystal display element 28 changes according to the voltage difference between the pixel node NX1 and the common electrode node NX2, and the display brightness of the liquid crystal display element 28 changes accordingly. The display signal is transferred through the data line DL, and the display signal is transmitted to the pixel node NX1 through the pixel selection switch 26. Thereby, the luminance of the pixel 25 can be controlled. The pixel switch 26 is typically composed of an N-type polysilicon TFT. Further, the capacitor element 27 holds the written display signal and holds the display state (luminance) of the display element 28.

  The gate line driving circuit 30 sequentially drives the gate lines GL1,... To a selected state based on a predetermined scanning cycle. During the period when the gate line GL is selected, the data line DL is connected to the pixel node NX1 of the corresponding pixel 25, and the display signal (gray scale voltage) output on the data line DL by the data line driving circuit 40 is selected. The data is written in the pixel connected to the gate line and held by the capacitor 27.

  The data line driving circuit 40 outputs a display signal set in a stepwise manner to the data line DL according to the pixel display data signal SIG which is an N-bit digital signal. In FIG. 1, as an example, a case where the pixel display data signal SIG given from the outside is composed of 6 bits D0 to D5 is shown as an example. As a display specification in the display device, a full color display and a display of 260,000 colors are generally used. In this case, it is necessary to perform gradation display of 64 levels for each of the three primary colors of red (R), green (G), and blue (B), and therefore 6-bit pixel data is required for each primary color. The Therefore, the pixel display data signal SIG composed of 6 bits D0 to D5 is transmitted for each of R, G, and B, and 18 signals are used as signal lines for transmitting the pixel display data signal (digital signal) SIG. A line is needed.

  The data line driving circuit 40 generates data line selection signals SH1, SH2,... According to a shift clock signal (not shown), and input pixel display data according to the data line selection signals SH (SH1, SH2...) From the shift register 50. Level conversion circuit 52 that takes in signal SIG and performs level conversion of the pixel data signal, data latch circuit 54 that latches the output signal of level conversion circuit 52, and latch signal of data latch circuit 54 in accordance with latch instruction signal LT A data latch circuit 56 that latches, a gradation voltage supply circuit 60 that supplies gradation voltages V1 to V64, a decode circuit 70 that selects a gradation voltage for each pixel in accordance with the level-converted pixel data signal from the data latch circuit 56, According to the output voltage of the decoding circuit 70, the data And an output buffer circuit 80 for driving the line DL.

  The input pixel display data signal SIG is serially input as pixel data corresponding to a display signal transmitted to each of the data lines DL in a predetermined cycle in units of pixels (units of data lines). The shift register 50 sequentially switches the data line selection signals SH (SH1, SH2,...) To the selected state in synchronization with the cycle in which the pixel display data signal SIG is applied.

  Level conversion circuit 52 includes a level conversion unit (level shifter) provided for each data line DL, and the level conversion unit provided for the data line designated by data line selection signal SH from shift register 50 is activated. Then, level conversion is performed on the input pixel display data signal SIG.

  The data latch circuit 54 latches the output signal of the level conversion unit of the level conversion circuit 52 according to the data line selection signal from the shift register 50.

  The data latch circuit 56 latches the latch signal of the data latch circuit 54 in accordance with the latch instruction signal LT when the latch of the pixel display data signal for the pixels in one row is completed in the data latch circuit 54.

  The gradation voltage supply circuit 60 is constituted by, for example, a voltage dividing resistor connected in series between the high voltage VDH and the low voltage VDL, and the high voltage VDH and the low voltage VDL are divided by resistance to obtain 64 gradation voltages V1. -V64 is generated.

  The decode circuit 70 decodes the 6-bit signal for each data line DL latched by the data latch circuit 56 and, based on the decoding result, the corresponding gradation among the gradation voltages V1 to V64 from the gradation voltage supply circuit 60. Select the voltage.

  A display signal for each data line is generated by the decode circuit 70 and then transmitted to the corresponding data line DL via the output buffer circuit 80. As a method of transmitting a display signal from the output buffer circuit 80 to the data line DL, a line sequential driving method in which display voltages of one row are output in parallel may be used, and a display signal is sequentially applied to each data line. A dot sequential method may be used. The output buffer circuit 80 is an analog circuit, receives the gradation voltage from the decoding circuit 70, drives each data line DL, and writes a display signal (gradation voltage) for the selected pixel.

  In the configuration of the display device shown in FIG. 1, gradation voltage supply circuit 60 and decode circuit 70 may be configured by a digital / analog conversion circuit that performs digital / analog conversion on the output signal of data latch circuit 56. . Further, the gate line driving circuit 30 and the data line driving circuit 40 may be provided as an external device (as a separate chip) of the display panel (liquid crystal matrix).

  The input pixel display data signal SIG is converted into a power supply voltage level signal in the display device using the level conversion circuit 52 and transferred through the data latch circuits 54 and 56 to generate a gradation voltage. Compared with the configuration in which the level of the signal latched in the data latch circuit 56 is converted, a display signal corresponding to the input pixel display data signal is output from the output buffer circuit 80 without causing a gate delay in the level conversion circuit 52. be able to.

  FIG. 2 is a diagram specifically showing the configuration of level conversion circuit 52 and data latch circuits 54 and 56 shown in FIG. FIG. 2 representatively shows a configuration of a portion corresponding to two data lines for a 1-bit signal of input pixel display data signal SIG. Level conversion circuit 52 is activated in accordance with each of data line selection signals SH1 and SH2 from shift register 50. When activated, level conversion circuit 52 makes a difference between reference voltage VREF and an input display data signal (hereinafter simply referred to as a data signal) DI. Level shifters LCK1 and LCK2 which amplify and perform level conversion automatically. The data signal DI is, for example, a binary signal whose logic low level (L level) and logic high level (H level) are 0V and 1.8V, respectively, and the reference voltage VREF is an intermediate 0.9V. The level shifters LCK1 and LCK2 constitute a level conversion unit in the level conversion circuit 52. When activated, the level shifters LCK1 and LCK2 respectively determine the logic level of the data signal DI with reference to the reference voltage VREF, and the H level voltage of the input display data signal DI. The level is converted to a higher power supply voltage VDD level of the display device or a voltage level close thereto.

  First data latch circuit 54 includes first data latches FDK1 and FDK2 provided for level shifters LCK1 and LCK2, respectively. First data latches FDK1 and FDK2 are activated complementary to corresponding level shifters LCK1 and LCK2 in accordance with data line selection signals SH1 and SH2, respectively, and latch the output signals of corresponding level shifters LCK1 and LCK2 when activated. . Since first data latches FDK1 and FDK2 operate in accordance with complementary data line selection signals, inverters IV1 and IV2 for inverting data line selection signals SH1 and SH2 are provided correspondingly.

  Second data latch circuit 56 is provided corresponding to each of first data latches FDK1 and FDK2, and latches the output signals of corresponding first data latches FDK1 and FDK2 in accordance with complementary latch signals LAT and / LAT. 2 data latches SDK1 and SDK2. Complementary latch signals LAT and / LAT correspond to latch instruction signal LT shown in FIG. Using the complementary latch signals LAT and / LAT, the second data latches SDK1 and SDK2 included in the second data latch circuit 55 perform a latch operation in parallel, and the decode circuit 70 causes the second data latch SDK (SDK1 , SDK2...), Display signals for the data lines are generated in parallel.

  In the configuration shown in FIG. 2, shift register 50 sequentially drives data line selection signals SH1, SH2,. The level shifters LCK1 and LCK2 are selectively activated by the data line selection signals SH1 and SH2, and the level conversion of the input data signal DI is performed. The data signals level-converted by the level shifters LCK1, LCK2,... Are latched by the first data latches FDK1, FDK2 by deactivating the data line selection signals SH1 and SH2, respectively. As a result, the serially input data signal DI is converted into a parallel signal. When the latch operation in the first data latch FDK (FDK1, FDK2,...) For the pixels in one row is completed, the complementary latch signals LAT and / LAT are activated, and the level is set by the second data latch SDK (SDK1, SDK2,...). The converted data signal (pixel display data signal) is transferred and latched. Subsequently, the decoding circuit 70 performs a decoding operation, and selects a gradation voltage for each data line according to the decoding result.

  FIG. 3 is a diagram showing a specific configuration of the level shifter LCK (LCK1, LCK2...) And the first data latch FDK (FDK1, FDK2...) Shown in FIG. FIG. 3 representatively shows configurations of level shifter LCKi and first data latch FDKi arranged corresponding to data line selection signal SHi (i = 1−n; n is the number of data lines). The structures of the level shifter LCK and the first data latch FDK provided for each data line are the same.

  The second data latch SDK has the same configuration as the first data latch FDK. Instead of the data line selection signal SHi, latch signals LAT and / LAT are given as latch operation control signals.

  In FIG. 3, the level shifter LCKi is connected between the high-side power supply node AN1 and the internal node AN7, is connected between the constant current source 100 for supplying the constant current I, the internal node AN7 and the internal node AN8, and its gate. Is connected to data signal input node AN3, P channel MOS transistor 102 connected between internal node AN7 and internal node AN9 and receiving reference voltage VREF at its gate, internal node AN8 and internal node AN8 N channel MOS transistor 103 connected between node AN10 and having its gate connected to internal node AN8, and N channel having its gate connected to internal node AN8 and connected between internal node AN9 and internal node AN10 MOS transistor 104 and internal node Including de AN10 and the high-side N-channel MOS transistor 105 which receives the data line selection signal SHi via the node AN5 connected to and having a gate between the power supply node AN2.

  MOS transistors 101 and 102 constitute a comparison stage for comparing input data signal DI with reference voltage VREF. MOS transistors 103 and 104 constitute a current mirror circuit and act as a load circuit for driving the same current to MOS transistors 101 and 102. The power supply voltage VDD supplied to the high-side power supply node AN1 is higher than the H level voltage level of the data signal DI. The constant current source 100 is constituted by a current mirror circuit, for example.

  First data latch FDKi is activated in accordance with activation of complementary data line selection signals SHi and / SHi, and inverts the signal on output node AN9 of level shifter LCKi, and the output signal of clocked inverter 120 Is inverted complementary to clocked inverter 120 in accordance with complementary data line selection signals SHi and / SHi, and when activated, the signal on internal node AN14 is inverted to output node of clocked inverter 120 A clocked inverter 111 that transmits to the AN 12 is included.

  Clocked inverter 120 is connected between high-side power supply node AN1 and internal node AN11, and has its gate receiving P channel MOS transistor 106 receiving complementary data line selection signal / SHi via node AN6, node AN11 and internal node P-channel MOS transistor 107 connected between output node AN12 and its gate connected to output node AN9 of level shifter LCKi, and connected between internal output node AN12 and internal node AN13 and its gate connected to output node AN13 of level shifter LCKi N-channel MOS transistor 108 connected to output node AN9, N-channel MOS transistor 10 connected between internal node AN13 and low-side power supply node AN2 and receiving at its gate data line selection signal SHi via node AN5 Including the.

  Clocked inverter 120 is activated when data line selection signals SHi and / SHi are at the H level and the L level, respectively, and inverts the output signal of level shifter LCKi. When data line selection signals SHi and / SHi attain an L level and an H level, respectively, in clocked inverter 120, MOS transistors 106 and 109 are turned off and an output high impedance state is obtained.

  FIG. 4 is a diagram showing an example of the configuration of clocked inverter 111 shown in FIG. In FIG. 4, clocked inverter 111 includes P-channel MOS transistors PQ1 and PQ2 connected in series between high-side power supply node AN1 and internal output node AN12, and between internal output node AN12 and low-side power supply node AN2. N channel MOS transistors NQ1 and NQ2 connected in series are included. Data line connection signals SHi and / SHi are applied to the gates of MOS transistors PQ1 and NQ2, respectively. MOS transistors PQ2 and NQ1 have their gates connected to internal node AN14 shown in FIG.

  Clocked inverter 111 is in an output high impedance state when data line selection signals SHi and / SHi are at the H level and L level, respectively, while data line selection signals SHi and / SHi are at the L level and H level, respectively. When activated, the signal on internal node AN14 is inverted and transmitted to internal output node AN12.

  Here, in the configuration shown in FIG. 3, the high-side power supply voltage VDD is commonly applied to the level shifter LCKi and the first data latch FDKi. However, the high-side power supply voltage having a different voltage level may be supplied to the level shifter LCKi and the first data latch FDKi. The high-side power supply voltage VDD for the level conversion circuit LCKi may be set to a voltage level higher than the high-side power supply voltage of the first data latch FDKi. In this case, in the level shifter LCKi, the voltage difference between the high-side power supply voltage VDD and the input data signal DI and the reference voltage VREF is increased, the operation margin can be expanded, and the level conversion operation can be performed accurately.

  FIG. 5 is a timing chart showing the operation of the circuit shown in FIG. Hereinafter, operations of the level shifter LCKi and the first data latch FDKi shown in FIG. 3 will be described with reference to FIG.

  The input data signal DI is serially input for each display pixel at a predetermined cycle. The shift register 50 shown in FIG. 2 shifts the data line selection signal SHi (SH1, SH2,...) By half a cycle from the input cycle of the data signal DI in accordance with the input clock signal that defines the transfer cycle of the input data signal DI. Change. That is, the input data signal DI changes at the central point of the activation period of the data line selection signal SH. Thereby, the operation timing margin for the level determination operation (differential amplification operation) of the input data signal is expanded.

  FIG. 5 is a timing chart showing the operation of the circuit shown in FIG. Hereinafter, the level conversion operation of the display device according to the first embodiment of the present invention will be described with reference to FIG.

  At time t0, data line selection signal SH1 rises to H level, and complementary data line selection signal / SH1 falls to L level. In response, level shifter 1 shown in FIG. 2 is activated, and comparison is made between reference voltage VREF and input data signal DI applied to input node AN3. The level shifter LCKi is composed of a differential amplifier circuit, and does not determine the logic level according to the voltage level with respect to the reference potential (ground voltage) of the input data signal DI, but the voltage between the reference voltage VREF and the input data signal DI. Operates according to the difference. Therefore, the level shifter LCKi can normally perform an amplification operation if a voltage difference of about 0.1 V exists between the reference voltage VREF and the input data signal DI. Reference voltage VREF is 0.9V, while H level and L level of input data signal DI are 1.8V and 0V, respectively. Therefore, a voltage difference of 0.9 V exists between the differential nodes AN3 and AN4 of the level shifter LCKi, and a sufficient amplification operation can be performed.

  Due to the differential amplification operation of the level shifter LCKi, the L level of the output node AN9 of the level shifter LCKi is substantially the ground voltage level, the H level is lower than the high-side power supply voltage VDD, and the input logic of the clocked inverter 120 The voltage level is higher than the threshold voltage level, and the voltage level causes the clocked inverter 120 to accurately perform the binary operation. The H level of the output signal of the level shifter LCKi depends on the magnitude of the driving current I of the constant current source 100. By increasing the magnitude of the current I, the H level of the output signal of the level shifter LCKi is increased to the high side. The voltage level is close to the power supply voltage VDD.

  When the input data signal DI changes at time t0a and the display data for the pixel changes, a signal having a logic level corresponding to the logic level of the input data signal DI is output from the level shifter LCKi. Here, when the input data signal DI is lower than the reference voltage VREF, the drive current amount of the P-channel MOS transistor 101 is larger than the drive current amount of the MOS transistor 102. The drive current of the MOS transistor 101 is supplied to the MOS transistor 103. MOS transistors 103 and 104 form a current mirror circuit, and currents of the same magnitude flow through these MOS transistors 103 and 104. Therefore, MOS transistor 104 discharges a current larger than the drive current of MOS transistor 102, and the voltage level of output node AN9 decreases.

  Conversely, when the voltage level of the input data signal DI is higher than the reference voltage VREF, the amount of drive current of the MOS transistor 101 becomes smaller than the amount of drive current of the MOS transistor 102. Therefore, in this case, MOS transistor 104 cannot discharge the current from MOS transistor 102, and the voltage level of output node AN9 rises to H level. In first data latch FDKi, clocked inverter 120 is in an active state, and the output signal of level shifter LCKi is inverted and transmitted to internal output node AN12 after the gate delay time of clocked inverter 120. Clocked inverter 120 receives power supply voltage VDD as an operating power supply voltage, and converts an L level output signal of level shifter LCKi to a power supply voltage level signal. Therefore, even if the output signal of the level shifter LCKi is at a voltage level lower than the power supply voltage level, a signal at the power supply voltage VDD level is reliably generated.

  When the data line selection signal SHi becomes L level at time t1, the MOS transistor 105 is turned off in the level shifter LCKi, the operating current path in the level shifter LCKi is cut off, and the differential amplification operation is deactivated. By turning off the MOS transistor 105, power consumption by the level shifter LCKi is stopped. By operating only the level shifter that performs level conversion, the power consumption in the level conversion circuit 52 shown in FIG. 2 is reduced.

  At time t1, when data line selection signals SHi and / SHi become L level and H level, respectively, in first data latch FDKi, MOS transistors 106 and 109 of clocked inverter 120 are turned off, and clocked inverter 120 is turned on. Output high impedance state. On the other hand, as shown in FIG. 4, in the clocked inverter 111, the internal MOS transistors PQ1 and NQ2 are turned on and activated, and the voltage of the output node AN12 of the clocked inverter 120 is activated by the inverter 110 and the clocked inverter 111. The level is held in a low impedance state. By maintaining the voltage of the output node AN12 in a low impedance state, it is possible to hold a signal whose level has been stably converted without being affected by noise.

  At time t1, data line selection signals SH2 and / SH2 for next data line DL2 attain H level and L level, respectively, and level shifter LCK2 is activated to perform differential amplification operation. At this time, the input data signal DI is a display data bit for the data line DL1.

  At time t1a, the input data signal DI from the outside changes to pixel data for the data line DL2, and the same operation as that in the previous level shifter LCK1 and the first data latch FDK1 is performed, and the voltage of the input data signal DI Level conversion is selectively performed and latched in the corresponding first data latch FDK2.

  At time t2, the data line selection signals SH2 and / SH2 become L level and H level, respectively, and the level conversion operation for the second input data signal DI is completed, and is latched by the first data latch FDK2 at the next stage. At time t2, next data line selection signals SH3 and / SH3 (not shown) become H level and L level, respectively, and the level conversion operation is performed in the level shifter (LCK3) of the next stage of the level conversion circuit. At time t3, The level conversion operation for the third input data signal DI is completed. Thereafter, the same operation as that from time t0 is executed for all data lines.

  In this level conversion operation, DC power consumption occurs in the level shifter LCK during the differential amplification operation. However, the power consumption in the level shifter occurs only when the corresponding data line is selected, and the power consumption can be sufficiently reduced. For example, let T be the time required to latch the input to all the data lines by setting the power supply current I flowing through the differential amplifier circuit constituting one level shifter LCKi to a maximum of about 1 μA with a margin. The power consumption per one input pixel display data line is expressed by the following equation.

Idd = 1 (μA) · 18 / T = 18 / T (μA)
PW = 18 (μA) · 5 (V) / T = 90 / T (μW)
Here, Idd indicates a power supply current in one level shifter, PW indicates power consumption per one input pixel display data signal line, and the power supply voltage VDD is 5V.

  Therefore, the power consumption required to write the display pixel data bits for all the data lines is PW · T = 90 (μW), which can be set to a sufficiently small value.

  Further, inactivation of the level shifter turns off the current source transistor 105, and the internal output node AN9 is precharged to the power supply voltage level. However, in this case, the level-converted signal is already latched in the next stage circuit, and no particular problem occurs.

[Example of change]
In the process in which the differential amplifier circuit constituting the level shifter LCKi and the clocked inverter 120 at the next stage are deactivated, the level shifter LCKi is deactivated before the clocked inverter, and the voltage of the output node AN9 The level becomes a voltage level different from the normal correct voltage level, and the clocked inverter 120 in the next stage transfers this inaccurate voltage level, so that erroneous data may be latched. Therefore, as shown in FIG. 6, the fall delay signal SHDi of the data line selection signal SHi is given to the level shifter LCKi as an activation control signal. The configuration shown in FIG. 6 is the same as the configuration shown in FIG. 3 except that the data line selection signal SHDi is supplied to the gate of the MOS transistor 105 for activating the level shifter LCKi instead of the data line selection signal SHi. Corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  Therefore, as shown in FIG. 7, at time t1, data line selection signals SH1 and / SH1 attain an L level and an H level, respectively, and clocked inverter 120 becomes inactive and becomes an output high impedance state. At this time, the delayed data line selection signal SHD1 is at the H level, and the level shifter LCKi is in the active state. By driving the level shifter LCK1 to the inactive state after the clocked inverter 120 becomes inactive, it is possible to prevent the clocked inverter 120 in the next stage from transferring erroneous data, and the circuit operation margin. Can be increased.

  FIG. 8 is a diagram illustrating an example of a configuration of a portion that generates the delayed data line selection signal SHDi. As shown in FIG. 8, the delayed data line selection signal SHDi is generated by a falling delay circuit 121 that delays the falling of the data line selection signal SHi from the shift register 50 for a predetermined time. As a result, the deactivation timing of the level shifter LCKi can be delayed for a necessary period, and the transfer and latching of the level-converted pixel data signal can be accurately performed by the first data latch FDKi.

  As described above, according to the first embodiment of the present invention, the pixel display data signal input from the outside is compared with the reference voltage by the differential amplifier circuit, and level conversion is performed. Therefore, even when the amplitude of the input pixel display data signal is lower than the threshold voltage of the MOS transistor of the display device, it is possible to accurately determine the logic level and perform level conversion. Accordingly, a display device that can reduce the amplitude of the input display data signal, reduce power consumption, and reduce EMI can be realized.

  Further, the level shifter is deactivated after the latch operation of the first data latch in the next stage is activated, so that the display data signal whose level has been converted can be accurately latched in the first data latch circuit. In addition, the margin of the operation timing for the activation and deactivation of the level conversion circuit and the first data latch circuit can be expanded.

[Embodiment 2]
FIG. 9 shows a structure of a main part of the display device according to the second embodiment of the present invention. The display device shown in FIG. 9 differs from the display device shown in FIG. 3 in the following points. That is, in level shifter LCKi, electrical connection is selectively made between node AN3 receiving input data signal DI and gate node AN15 of P-channel MOS transistor 101 constituting differential amplifier circuit 130 in response to data line selection signal SHi. A switching element 132 is provided. The differential amplifier circuit 130 corresponds to the configuration of the level shifter LCKi shown in FIG. In the configuration shown in FIG. 9, switching element 132 is formed of an N-channel MOS transistor as an example. The other configuration of the display device shown in FIG. 9 is the same as the configuration of the display device shown in FIG. 3, and the corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  In the display device shown in FIG. 9, the differential amplifier circuit 130 of the level shifter LCKi is coupled to the pixel input node AN3 only when the data line selection signal SHi is activated. When the level shifter LCKi is inactivated, the switching element 132 is non-conductive. Therefore, this data signal DI is always required to drive internal node AN15 of differential amplifier circuit 130 of the selected level shifter, and the load is reduced. Accordingly, the load on the circuit that drives the data signal DI is reduced, and the power consumption can be reduced.

  In FIG. 9, switching element 132 is formed of an N-channel MOS transistor. However, switching element 132 may be formed of a CMOS transmission gate in which a P-channel MOS transistor and an N-channel MOS transistor are connected in parallel. In that case, conduction / non-conduction of the SMOS transmission gate is controlled by complementary data line selection signals SHi and / SHi. If a negative voltage can be used, a P-channel MOS transistor may be used as switching element 132. Negative voltage level data line selection signal / SHi is supplied to the control node (gate electrode) of switching element 132 formed of this P-channel MOS transistor.

  The switching element 132 may be supplied with the data line selection signal SHi, and the delay data line selection signal SHDi may be supplied to the gate of the activation MOS transistor 105 of the differential amplifier circuit 130.

  As described above, according to the second embodiment of the present invention, the differential amplifier circuit of the level shifter is coupled to the signal line for transmitting pixels only when selected. Therefore, the capacity of the signal line for transmitting the pixel display data signal is reduced, the data signal (pixel display data signal) can be transferred at high speed, and the power consumption of the circuit driving the pixel display data signal is reduced. be able to. In particular, the pixel display data signal is a multi-bit signal, and by reducing the load on each data signal line, the power consumption of the driving LSI that drives the pixel display data line can be greatly reduced.

[Embodiment 3]
FIG. 10 shows a structure of level shifter LCKi according to the third embodiment of the present invention. The configuration of the first data latch FDKi arranged at the next stage of the level shifter LCKi is the same as the configuration shown in FIGS. The configuration of the level shifter LCKi shown in FIG. 10 is different from the configuration of the level shifter LCKi shown in FIG. 3 in the following points.

  That is, in level shifter LCKi, switching elements 135 and 136 are provided in parallel to gate node AN15 of P channel MOS transistor 101 constituting differential amplifier circuit 130. Switching element 135 is rendered conductive when select signal S1 is activated, and transmits data signal DI applied to data signal input node AN3 to gate node AN15. Switching element 136 is rendered conductive when select signal S2 is activated, and transmits reference voltage VREF on internal node AN4 to gate node AN15. These selection signals S1 and S2 are selectively activated sequentially when the data line selection signal SHi is activated.

  Further, in this level shifter LCKi, a storage capacitor element CH is provided between the gate node AN16 and the low-side power supply node AN2 of the P-channel MOS transistor 102 in the differential stage. One electrode node (internal node) AN16 of storage capacitor element CH is coupled to internal output node AN9 of differential amplifier circuit 130 via switching element 137. The selection signal S3 is activated in the same phase as the selection signal S2. When switching element 137 is conductive, differential amplifier circuit 130 operates as a voltage follower, with gate node AN16 of P channel MOS transistor 102 and internal output node AN9 being interconnected.

  The other configuration of the level shifter LCKi shown in FIG. 10 is the same as that of the level shifter LCKi shown in FIG. 3, and the corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 11 is a timing chart showing the operation of the level shifter LCKi shown in FIG. Hereinafter, the operation of the level shifter LCKi shown in FIG. 10 will be described with reference to FIG. FIG. 11 shows a signal waveform when data line selection signal SH1 is driven to the selected state. In the following description, the operation of level shifter LCK1 will be described as level shifter LCKi.

  At time t10, data line selection signal SH1 rises to H level, and differential amplifier circuit 130 of level shifter LCK1 designated by data line selection signal SH1 is activated. At this time, the selection signals S2 and S3 are in the active state at the H level for a predetermined period in accordance with the activation of the data line selection signal SH1. In response, switching elements 136 and 137 conduct, while switching element 135 remains off. In this state, differential amplifier circuit 130 operates in the voltage follower mode, and transmits reference voltage VREF to internal output node AN9. In this case, internal output node AN9 and gate node AN16 are driven to the voltage level of voltage VREF + VOF. Here, the voltage VOF indicates an output offset voltage of the differential amplifier circuit 130.

  That is, when the threshold voltages of MOS transistors 101 and 102 are the same in differential amplifier circuit 130, when operating in the voltage follower mode, when the gain is 1, the voltage levels of nodes AN9 and AN16 are set to gate node AN15. Is equal to the voltage level of the reference voltage VREF applied to the signal. However, the MOS transistors 101 and 102 have a variation in threshold voltage, and even if the source-gate voltages of the MOS transistors 101 and 102 are the same, the difference between the threshold voltages is different between these MOS transistors. The drive current of 101 and 102 is affected. As a result, offset voltage VOF corresponding to the difference between the threshold voltages of MOS transistors 101 and 102 is generated at output node AN9. This offset voltage VOF can be either positive or negative.

  At time t11, selection signals S2 and S3 are inactive at L level, and switching elements S2 and S3 are in non-conduction state. At this time, the selection signal S1 is also in the active state at the H level. At time t11, input data signal DI is applied, switching element 135 is turned on, and data signal DI for the data line selected by data line selection signal SH1 is passed through switching element 135 to the gate node of MOS transistor 101. Given.

  The gate node AN16 of the MOS transistor 102 holds the voltage VREF + VOF by the storage capacitor element CH. Differential amplifier circuit 130 differentially amplifies input data signal DI and voltage VREF + VOF of gate node AN16. Accordingly, during this comparison operation, the offset voltage VOF of the differential amplifier circuit 130 is canceled, and the voltage level of the input data signal DI is accurately compared with the reference voltage VREF. That is, in differential amplifier circuit 130, the voltage level of the input signal applied to gate node AN15 is regarded as a voltage level that is higher by the offset voltage VOF, and the comparison operation is performed. Therefore, by setting the voltage level of gate node AN16 that provides the reference voltage to a voltage level that is higher than offset voltage VOF than reference voltage VREF, the offset of differential amplifier circuit 130 with respect to the voltage level of the input signal applied to gate node AN15. The voltage can be canceled out. Thus, the level conversion can be performed by accurately performing the comparison operation to determine the level of the input data signal DI.

  At time t12, the selection signal S1 is deactivated together with the deactivation of the data line selection signal SH1, and the switching element 135 is turned off. Switching element 137 is in the off state, and internal output node AN9 is maintained at the voltage level corresponding to input data signal DI (1) by storage capacitor element CH.

  In the signal waveform diagram shown in FIG. 11, in order to explain the offset cancel operation, internal output node AN9 is shown to maintain the logic level of input data signal DI. However, the differential amplifier circuit 130 is deactivated in response to the deactivation of the data line selection signal SH1, and its operating current path is cut off, so that the internal output node AN9 is connected via the MOS transistor 102. Although the voltage level increases in the direction of the power supply voltage VDD due to the current from the constant current source 100, the waveform of the precharge operation due to the leakage current at the time of non-selection is not shown. In this case, the clocked inverter in the first data latch FDKi at the next stage is already in the output high impedance state, and the level-converted data signal is accurately latched by the first data latch at the next stage. be able to.

  In the differential amplifier circuit 130 shown in FIG. 10, the constant current source 100 is set to a non-conductive state when the data line selection signal SHi (SH1) is inactive, and the high-side power supply node AN1 and the low-side power supply node In each of AN2, the current supply path may be cut off. In this case, the internal node AN9 is in a state of maintaining the signal resulting from the differential amplification.

  Also in the differential amplifier circuit 130 shown in FIG. 10, the delayed data line selection signal SHDi may be applied to the gate of the activating MOS transistor 105.

  Switching elements 135 to 137 may be formed of CMOS transmission gates, may be formed of N-channel MOS transistors, or may be formed of P-channel MOS transistors when a negative voltage can be used. It may be configured. The voltage level of the selection signals S1-S3 is higher than the voltage level of the reference voltage VREF by a voltage level higher than the threshold voltage of the MOS transistor. Even if the MOS transistor alone is used as a switching element, the threshold voltage The input data signal DI and the reference voltage VREF can be transmitted without any loss.

  FIG. 12 is a diagram showing an example of a configuration of a part that generates selection signals S1-S3 shown in FIG. In FIG. 12, a selection signal generator receives a clock signal CLK and a data line selection signal SHi, generates a selection signal S2 and S3, and receives a clock signal CLK and a data line selection signal SHi. An AND gate 142 for generating S1 is included. Clock signal CLK defines a transfer cycle of data signal DI, and data signal DI is transferred in accordance with clock signal CLK.

  Gate circuit 140 drives selection signals S2 and S3 to H level when clock signal CLK is at L level and data line selection signal SHi is at H level. AND gate 142 drives selection signal S1 to H level when both clock signal CLK and data line selection signal SHi are at H level.

  FIG. 13 is a timing chart showing the operation of the selection signal generator shown in FIG. Hereinafter, the operation of the selection signal generator shown in FIG. 12 will be described with reference to FIG.

  At time ta, the (i−1) th data signal DI (i−1) is input in synchronization with the rise of the clock signal CLK.

  At time tb, when clock signal CLK falls to L level, data line selection signal SHi rises to H level. According to the rise of data line selection signal SHi and the fall of clock signal CLK, selection signals S2 and S3 are both driven to the H level. Since the clock signal CLK is at the L level, the selection signal S1 maintains the L level. In this state, the offset voltage of the differential amplifier circuit is detected and the reference voltage is set.

  When the clock signal CLK rises at time tc, the i-th DI (i) is input. In response to the rise of clock signal CLK, selection signals S2 and S3 from gate circuit 140 both attain an L level. On the other hand, since the data line selection signal SHi is at the H level at this time, the selection signal S1 from the AND gate 142 becomes the H level as the clock signal CLK rises, and the i-th DI (i) goes to the differential amplifier circuit. Transferred.

  In the configuration of the selection signal generator shown in FIG. 12, by providing gate circuits 140 and 142 for each level shifter, selection signals S1-S3 for the corresponding level shifter can be generated.

  FIG. 14 is a diagram schematically showing another configuration of the selection signal generator. In FIG. 14, a selection signal generation unit includes a one-shot pulse generation circuit 144 that generates a one-shot pulse signal that is in an active state (H level) for a predetermined period in response to a fall of the data line selection signal SHi. A gate circuit 146 that receives the output signal of the one-shot pulse generation circuit 144 and the data line selection signal SHi and generates the selection signal S1 is included.

  Selection signals S2 and S3 are generated from one-shot pulse generation circuit 144. Gate circuit 146 maintains selection signal S1 at H level when the output signal of one-shot pulse generation circuit 144 is at L level and data line selection signal SHi is at H level. Therefore, when data line selection signal SHi rises to H level, selection signals S2 and S3 are first driven to an active state of H level. Thereby, the offset voltage detecting operation for offset cancellation and the offset compensation for the reference voltage are performed in the level shifter. When the selection signals S2 and S3 are at the L level, the selection signal S1 from the gate circuit 146 is maintained at the H level while the data line selection signal SHi is at the H level, and the input data signal DI and the offset compensated reference voltage are Are compared.

  In the configuration of the selection signal generation unit shown in FIG. 14, it is only required to arrange one-shot pulse generation circuit 144 and gate circuit 146 corresponding to the level shifter (LCKi). The clock signal CLK for data input does not need to drive the selection signal generator provided in all level shifters, and the load of the clock signal CLK is reduced.

  As described above, according to the third embodiment of the present invention, the function for canceling the offset voltage is provided in the differential amplifier circuit of the level shifter that performs level conversion, and the logical level of the input data signal is accurately determined. Thus, the level conversion can be performed. In particular, when a polysilicon TFT is used as the configuration of this differential amplifier circuit, the variation in the threshold voltage becomes large. In such a case, the offset voltage of the differential amplifier circuit can be canceled out even if the threshold voltage variation of about 100 mV occurs, for example, and the margin for the voltage comparison operation of the differential amplifier circuit of the level shifter Can be suppressed.

[Embodiment 4]
FIG. 15 is a timing diagram representing an operation of the level shifter according to the fourth embodiment of the present invention. As the configuration of the level shifter, the configuration of the differential amplifier circuit with an offset cancel function shown in FIG. 10 used in the third embodiment is used. Hereinafter, the operation of level shifter LCKi according to the fourth embodiment of the present invention will be described with reference to FIGS. The selection signals S1, S2 and S3 in the level shifter LCKi are shown as signals S1i, S2i and S3i.

  At time t00, data line selection signal SH1 becomes H level, and selection signals S21 (S2) and S31 (S3) rise to H level accordingly. Accordingly, switching elements 136 and 137 shown in FIG. 10 are turned on, differential amplifier circuit 130 performs a voltage follower operation, and a voltage obtained by adding reference voltage VREF and offset voltage VOF is stored in storage capacitor element CH.

  At time t0, the selection signals S21 and S31 are at the L level, and the selection signal S11 is at the H level. As a result, switching element 135 shown in FIG. 10 is turned on, and switching elements 136 and 137 are turned off, and the comparison operation for the input data bit is started. At this time, the data line selection signal SH2 for the adjacent data line is also at the H level. In response to the rise of data line selection signal SH2, selection signals S22 (S2) and S32 (S3) attain an H level. In level shifter LCK2 provided for data line selection signal SH2, switching elements 136 and 137 The ON state is entered, and the offset voltage detection / compensation operation is performed. At this time, in the level shifter LCK2, the switching element 135 for the input data signal is in an OFF state, and the input data signal DI is input to the level shifter LCK1 designated by the data line selection signal SH1 to perform a comparison operation.

  The input pixel data changes at time t0a, and the level conversion operation of the corresponding pixel data signal is performed in the level shifter LCK1.

  At time t1, the data line selection signal SH1 becomes L level, and accordingly the selection signal S11 becomes L level. As a result, the level shifter LCK1 is deactivated.

  At this time, in the level shifter LCK2, the selection signals S22 and S32 become L level and the selection signal S12 becomes H level, the offset voltage detection / compensation operation period ends, and the comparison operation for the next input pixel data signal is started. The

  At time t1a, the pixel for the next level shifter LCK2 is input, and the level conversion operation for this input pixel data bit is executed.

  At time t2, the data line selection signal SH2 becomes L level. In response, the selection signal S12 falls to L level, and the level shifter LCK2 is deactivated.

  Therefore, the level shifter performs an offset voltage detection operation before inputting the corresponding pixel data signal, completes the offset voltage detection / accumulation operation in a cycle in which the pixel data signal is input, and executes the comparison / level conversion operation. . In level shifter LCKi, conduction period T of switching elements 135-137 is the same as input cycle T of input data signal DI, and a sufficient margin for the offset voltage detection operation and comparison / level conversion operation in level shifter LCKi can be secured. .

  FIG. 16 is a diagram schematically showing an example of the configuration of the selection signal generator in the fourth embodiment of the present invention. In FIG. 16, the selection signal generation unit includes OR gates OG1-OGn provided corresponding to main data line selection signals MSH0-MSHn generated from shift register 50 in synchronization with clock signal CLK. Each of the OR gates OG1-OGn receives the corresponding main data line selection signal MSHi and the main data line selection signal MSH (i-1) one stage before in the selection sequence, and selects the data line for the corresponding level conversion circuit LCKi. A signal SHi is generated. For example, OR gate OG2 receives main data line selection signal MSH1 for data line DL1 and main data line selection signal MSH2 for corresponding data line DL2, and generates data line selection signal SH2 for corresponding level conversion circuit LCK2. .

  Further, a frequency divider 150 is provided that generates a divided signal BCLK by dividing the clock signal CLK by two. Based on the divided clock signal BCLK and the data line selection signals SH1-SHn, selection signals S1-S3 are generated in the level shifters. A circuit shown in FIG. 12 is assumed as a circuit for generating the selection signals S1-S3. In the circuit configuration shown in FIG. 12, a divided clock signal BCLK is used instead of the clock signal CLK.

  FIG. 17 is a timing chart showing a configuration of the data line selection signal generation unit shown in FIG. Hereinafter, the operation of the data line selection signal generator shown in FIG. 16 will be briefly described with reference to FIG.

  When clock signal CLK falls to L level at time t30, main data line selection signal MSH0 is driven to H level in synchronization with the fall of clock signal CLK from shift register 50. This is because the main data line selection signals MSH0 to MSH2 are maintained at the H level for the same period as the input cycle of the input data signal DI, and the main data line selection signal MSH0 is kept at the H level from time t30 to time t31. Then, the main data line selection signal MSH1 is at the H level from time t31 to time t33, and the main data line selection signal MSH2 is at the H level from time t33 to time t35.

  On the other hand, the frequency divider 150 is composed of, for example, a D flip-flop whose output signal changes with the falling edge of the clock signal CLK as a trigger, and divides the clock signal CLK by 2 to generate a divided clock signal BCLK. Therefore, using the circuit shown in FIG. 12 as a circuit for generating selection signals S1 to S3, selection signals S1i, S2i and S3i are generated in accordance with frequency-divided clock signal BCLK and data line selection signal SHi.

  Therefore, data line selection signals SH1-SHn output from OR gates OG1-OGn maintain the H level for a period twice as long as input cycle time T of input data signal DI. For example, the data line selection signal SH1 is at the H level from time t30 to time t33, while the data line selection signal SH2 is at the H level from time t31 to t35.

  For example, in the level shifter LCK1, the selection signals S21 and S31 are at the H level during the period in which the divided clock signal BCLK is at the L level and the data line selection signal SH1 is at the H level. The selection signal S11 becomes H level in synchronization with the rising of the divided clock signal BCLK at time t31, and becomes L level when the main data line selection signal MSH1 becomes L level at time t33.

  By using this divided clock signal BCLK as a clock signal for activating the selection signal, the data line selection signals SH1-SHn are maintained at the H level for a period twice as long as the data input cycle. S3 can be maintained at the H level for one cycle period of the input data signal.

  In the shift register 50, it is required to drive the main data line selection signal MSH0 to the selected state one cycle before the data signal DI is input. Therefore, the data signal DI is input 1 according to the clock signal CLK. The shift operation starts before the clock cycle.

[Example of change]
FIG. 18 is a diagram showing a modification of the level shifter LCKi according to the fourth embodiment of the present invention. The level shifter LCKi has the same configuration as the level shifter LCKi shown in FIG. 10 and has an offset cancel function. Level shifter LCKi generates selection signal S1 according to the signal applied to input S1, and also generates selection signals S2 and S3 according to the signals applied to inputs S2 and S3, respectively. In FIG. 18, the selection signal and the input node are denoted by the same reference numerals. Further, the level shifter LCKi is activated according to a signal applied to its activation input EN, and performs a differential amplification operation. This activation input EN corresponds to node AN5 in level shifter LCKi shown in FIG. 10 and is connected to the gate of activation transistor 105.

  A data line selection signal SHi shown in FIG. 16 is applied to the activation input EN of the level shifter LCKi. Main data line selection signal MSHi from shift register circuit 50 shown in FIG. 16 is applied to input S1. Main data line selection signal MSH (i-1) for level shifter LCK (i-1) at the previous stage is applied to inputs S2 and S3.

  Therefore, in the level shifter LCKi shown in FIG. 18, the internal differential amplifier circuit is activated during the activation period of the data line selection signal SHi. When the input data bit comparison / level conversion operation is performed in the previous level shifter (LCK (i-1)), similarly, the selection signals S2 and S3 are activated in this level shifter LCKi, and the offset voltage detection and holding capacitor are activated. An offset voltage compensation operation for voltage accumulation in the element is performed. When the level conversion operation is completed in the previous level shifter LCK (i−1), the main data line selection signal MSHi is activated, the offset voltage detection / compensation operation is completed, and the comparison / level conversion operation for the corresponding input data signal is performed. Done. This main data line selection signal MSHi is applied to inputs S2 and S3 of the next level shifter (LCK (i + 1)). In the next level shifter LCK (i + 1), in parallel with the level conversion operation of the level shifter LCKi, Offset voltage detection and compensation operations are performed.

  Therefore, even when the configuration shown in FIG. 18 is used, the offset voltage detection / compensation period and the comparison / level conversion period for the input signal can each be set to one cycle period of input data signal DI.

  As described above, according to the fourth embodiment of the present invention, the level shifter is set to one cycle period of the input data bits of the offset voltage detection / accumulation period and the input signal comparison / level conversion period. The offset voltage detection and the input signal comparison / level conversion can be performed with a sufficient margin.

[Embodiment 5]
FIG. 19 shows a structure of differential amplifier circuit 130 according to the fifth embodiment of the present invention. The differential amplifier circuit 130 shown in FIG. 19 differs from the differential amplifier circuit included in the level shifter LCKi shown in FIG. 3 in the following points. That is, in differential amplifier circuit 130 (level shifter LCKi) shown in FIG. 19, instead of constant current source 100, data line selection signal / SHi is received between high-side power supply node AN1 and internal node AN7 at its gate. A P channel MOS transistor 155 is provided. Common source node AN10 of MOS transistors 103 and 104 constituting the current mirror circuit is coupled to low-side power supply node AN2. The other configuration of the differential amplifier circuit 130 (level shifter LCKi) shown in FIG. 19 is the same as the configuration of the differential amplifier circuit included in the level shifter LCKi shown in FIG. 3, and corresponding portions are denoted by the same reference numerals. Detailed description thereof will be omitted.

  In the differential amplifier circuit 130 shown in FIG. 19, the MOS transistor 155 realizes the functions of both a current supply source and an activation / deactivation control transistor. Therefore, in this differential amplifier circuit 130, it is not necessary to use a constant current source, the number of circuit elements can be reduced, and the circuit occupation area can be reduced.

  In the configuration of differential amplifier circuit 130 shown in FIG. 19, input data signal DI is supplied to the gate node of P channel MOS transistor 101 only when level shifter LCKi is selected, as shown in the second embodiment. A configuration may be used. Complementary delayed data line selection signal / SHDi is applied to the gate of P channel MOS transistor 155 so that this inactivation of differential amplifier circuit 130 is after the shift of the latch operation of the first data latch of the next stage. May be.

  Further, as shown in the previous third or fourth embodiment, an offset cancel function may be provided.

  As described above, according to the fifth embodiment of the present invention, the active / inactive control transistor is also used as the current supply transistor in the differential amplifier circuit 130 included in the level shifter, and the number of circuit elements can be reduced. Accordingly, the circuit occupation area can be reduced.

[Embodiment 6]
FIG. 20 schematically shows a structure of a main part of the display device according to the sixth embodiment. In the configuration shown in FIG. 20, the configuration of first data latch FDKi that latches the signal of output node AN9 of level shifter LCKi is different from the configuration shown in the first embodiment. That is, first data latch FDKi is selectively turned on in response to data line selection signals SHi and / SHi instead of clocked inverter 120, and when turned on, output node AN9 of level shifter LCKi is connected to internal node AN12. A CMOS transmission gate 160 is provided for electrical connection. In first data latch FDKi, similarly to the configuration of the first embodiment (see FIG. 3), inverter 110 and clocked inverter 111 that constitute a latch circuit are provided.

  Any of the configurations of the first to fifth embodiments may be used for the level shifter LCKi. In the first data latch FDKi shown in FIG. 20, when the level shifter LCKi is activated by the data line selection signal SHi and performing the level conversion operation, the CMOS transmission gate 160 becomes conductive, and the output of the level shifter LCKi The signal is transmitted to the internal node AN12. Clocked inverter 111 is in an inactive state in this state, and is therefore in an output high impedance state.

  When level shifter LCKi is deactivated, CMOS transmission gate 160 is rendered non-conductive, and nodes AN12 and AN9 are electrically isolated. On the other hand, clocked inverter 111 is activated and operates as an inverter, and the signal at node AN12 is latched by inverter 110 and clocked inverter 111.

  In the configuration shown in FIG. 20, the logic level of the signal on internal node AN12 is inverted from that in the first embodiment shown in FIG. In order to maintain the same logic level, an inverter is arranged in the next stage so as to invert the signal of internal output node AN9.

  By using the CMOS transmission gate 160 instead of the clocked inverter 120 (see FIG. 3) in the first input stage of the first data latch FDKi, the number of circuit elements can be reduced, and the circuit occupation area can be reduced. be able to.

  The level conversion circuit according to the present invention can be generally applied to a purpose of level-converting and latching a small amplitude signal. In particular, the present invention can be applied to a configuration in which a digital signal input serially is converted into a parallel digital signal and level conversion is performed. In particular, by using it in a circuit that converts an input pixel data signal into a parallel data signal in a display device using a polysilicon TFT in which the variation in threshold voltages of the constituent transistors is large, low power consumption and low EMI are achieved. A display device can be realized.

It is a figure which shows roughly the structure of the display apparatus according to this invention. FIG. 2 is a diagram illustrating specific configurations of a level conversion circuit and a data latch circuit illustrated in FIG. 1. FIG. 3 is a diagram more specifically showing configurations of a level shifter and a first data latch shown in FIG. 2. FIG. 4 is a diagram illustrating an example of a configuration of an inverter of a first data latch illustrated in FIG. 3. FIG. 4 is a timing chart showing an operation of the circuit shown in FIG. 3. It is a figure which shows the structure of the example of a change of this Embodiment 1. FIG. FIG. 7 is a signal waveform diagram illustrating an operation of the level shifter illustrated in FIG. 6. FIG. 7 is a diagram showing an example of a configuration of a portion that generates a delayed data line selection signal shown in FIG. 6. It is a figure which shows the structure of the level shifter according to Embodiment 2 of this invention. It is a figure which shows the structure of the level shifter according to Embodiment 3 of this invention. FIG. 11 is a timing diagram illustrating an operation of the level shifter illustrated in FIG. 10. It is a figure which shows an example of a structure of the part which generate | occur | produces the selection signal shown in FIG. FIG. 13 is a timing chart showing an operation of the circuit shown in FIG. 12. It is a figure which shows the example of a change of the part which generate | occur | produces the selection signal shown in FIG. It is a timing diagram which shows the operation | movement of the level shifter according to Embodiment 4 of this invention. FIG. 16 is a diagram illustrating an example of a configuration of a portion that generates a data line selection signal illustrated in FIG. 15. FIG. 17 is a timing diagram illustrating an operation of the circuit illustrated in FIG. 16. It is a figure which shows schematically the structure of the example of a change of Embodiment 4 of this invention. It is a figure which shows the structure of the level shifter according to Embodiment 5 of this invention. It is a figure which shows the structure of the 1st data latch according to Embodiment 6 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Display apparatus, 20 pixel matrix, 52 level conversion circuit, 54,56 data latch circuit, LCK1, LCK2, LCKi level shifter, FDK1, FDK2, FDKi 1st data latch, SDK1, SDK2 2nd data latch, 101, 102 P channel MOS transistor, 100 constant current source, 46 inverter, 111, 120 clocked inverter, 132 switching element, 135, 137 switching element, 160 CMOS transmission gate.

Claims (6)

A plurality of pixel elements arranged in a matrix,
A plurality of data lines arranged corresponding to each pixel column, each having a corresponding pixel element connected thereto, and transferring a display signal to a selected pixel element in the corresponding column;
A voltage having a potential difference larger than the amplitude of the input data signal is received as an operation power supply voltage, activated in response to a data line selection signal for selecting the data line, and when activated, the first and second inputs A differential amplifier circuit that differentially amplifies and outputs the potential of the input data signal and performs level conversion of the input data signal
A capacitive element having one electrode connected to the second input;
A first switching element that conducts according to the activation of the data line selection signal and transmits an input data signal to the first input when conducting;
A second switching element that selectively conducts complementarily with the first switching element in accordance with the activation of the data line selection signal and transmits a reference voltage to a first input of the differential amplifier circuit;
A third switching element that conducts in phase with the second switching element according to the data line selection signal, and couples the output of the differential amplifier circuit to one electrode of the capacitive element when conducting;
A display device comprising: a latch circuit that latches an output signal of the differential amplifier circuit; and a display signal generation circuit that generates a display signal for a corresponding data line based on at least the output signal of the latch circuit. The differential amplifier circuit is:
A constant current source coupled to the first power supply node;
A first transistor of a first conductivity type connected between the constant current source and a first internal node and having a gate connected to the first input;
A second transistor of a first conductivity type connected between the constant current source and a second internal node and having its gate connected to the second input;
A third transistor of the second conductivity type connected between the first internal node and the third internal node and having its gate connected to the first internal node;
A second conductive fourth transistor connected between the second internal node and the third internal node and having a gate connected to the first internal node;
Connected between said third internal node and a second power supply node, and and a fifth transistor of the second conductivity type for receiving said data line selection signal to the gate, display of claim 1 Symbol placement apparatus. The latch circuit is
In accordance with the data line selection signal, it is activated in parallel with the differential amplifier circuit, and when activated, takes in and transfers the output signal of the differential amplifier circuit and is earlier than the deactivation of the differential amplifier circuit. A transfer circuit which is deactivated at a timing and becomes a cut-off state;
Wherein according to the data line selection signal, the are complementarily activated the transfer circuit, when activated, and a latch for latching the output signal of the transfer circuit, according to claim 1 Symbol placement of the display device. The data line selection signal is generated such that data line selection signals that are continuously activated overlap activation periods, and the first switching element is rendered conductive during the overlap of the activation periods. that, according to claim 1 Symbol placement of the display device. The data line selection signal has an activation period twice as long as the input cycle of the input data signal, and the conduction period of the first switching element and the conduction period of the second and third switching elements are substantially equal. 5. The display device according to claim 4 , wherein the display device is the same. The differential amplifier circuit is:
A first conductivity type first transistor connected between a first power supply node and a first internal node and receiving the data line selection signal at its gate;
A second transistor of the first conductivity type connected between the first internal node and the second internal node and having its gate connected to the first input;
A fourth transistor of a second conductivity type connected between the second internal node and a second power supply node and having its gate connected to the second internal node;
Connected between said third internal node and said second power supply node, and and a fifth transistor of the second conductivity type having a gate connected to said second internal node, claim 1 serial mounting of the display device.

Images