JP2006033794A - Level converting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a level converting circuit which performs level conversion at high speed and saves the area to be occupied. <P>SOLUTION: An MOS capacitor (6) is provided in an internal node (ND7) for sampling an input signal (IN) of a small amplitude, and signal voltage of the internal node is selectively boosted by a charge pump operation of the MOS capacitor. Latch circuits (IV1, IV2, 7) each of which is selectively turned into latch state to latch the voltage of the internal node, are provided for the internal node. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a level conversion circuit using an insulated gate field effect transistor (MOS transistor), and more particularly, to a level shift circuit having a latch function used in a display device using a liquid crystal element, an organic electroluminescence (EL) element, and the like. About. More specifically, the present invention relates to a circuit configuration for latching and level shifting a pixel data signal supplied to a display pixel.

  In a display device using a liquid crystal element or an organic EL element (electroluminescence element) as a display pixel element, a pixel data signal for driving the display pixel is an IC (integrated circuit chip; LSI) provided outside the display device. Given by. In this case, the external IC transfers, for example, a TTL level small amplitude signal as the display pixel data signal. The pixel display signal applied to the pixel element is given as a multi-bit digital signal. These external display data signals are level-converted inside the display device to a voltage level required by the display device, and then a multi-bit digital signal is converted into an analog signal to generate a corresponding gradation voltage. Written in the pixel element.

  In the display device, only circuit portions required for display operation are integrated, and other circuit portions are provided outside the display device. Accordingly, the number of circuits used in the display device is reduced, and the cost and size of the display device are reduced.

  As described above, the pixel data signal supplied to the display device is supplied from the driving LSI constituted by an IC provided outside. In this driving LSI, miniaturization of transistor elements is being promoted in order to reduce manufacturing costs, and accordingly, the breakdown voltage of the transistors is lowered. In order to guarantee the breakdown voltage characteristics of the transistor and to reduce power consumption, the power supply voltage level of the driving LSI is reduced. As a result, the amplitude of the display pixel data signal supplied from the driving LSI is also reduced, and for example, the logic high level (H level) voltage level may be 1.8V. This reduction in the amplitude of the display pixel data signal is preferable from the viewpoint of reducing EMI (electromagnetic radiation noise) and / or power consumption due to the signals of a large number of input pixel data lines, and hence the signal amplitude will be further reduced in the future. In the direction.

  On the other hand, in a display device, a polysilicon TFT (thin film transistor) is used as a transistor element. In a display device, it is difficult to perform high-temperature heat treatment from the viewpoint of display pixel reliability. Therefore, the crystallinity of polysilicon TFT is worse than that of a transistor using single crystal silicon, and its threshold voltage is low. It is difficult in terms of manufacturing technology to reduce the absolute value of.

  At present, the threshold voltage of this polysilicon TFT is as high as 2V to 4V, and it is difficult to operate such a polysilicon TFT using a signal of 1.8V. Therefore, at present, in a display device incorporating a serial / parallel conversion circuit for a display pixel data signal, a voltage of 3 V to 5 V is generally used as the H level of the display pixel data signal. In order to convert a small amplitude signal supplied from an external driving LSI into a large amplitude display pixel data signal inside the display device, the display pixel data signal is generated by expanding the amplitude of the external pixel data signal. Thus, a level conversion circuit that supplies the pixel element is used.

  In such display devices, it is generally required to reduce power consumption in order to prevent heat generation, and when used in applications using a battery such as a portable device, power consumption is further reduced. It is required to do. A configuration of a level conversion circuit intended to reduce such power consumption is disclosed in Japanese Patent Application Laid-Open No. 2003-115758.

In the configuration disclosed in Patent Document 1, an input signal is held in a first capacitor element according to a sampling pulse, and after completion of this sampling, a MOS drive having a level conversion function according to a voltage held in the first capacitor element Drive the stage. In accordance with the output signal of the MOS drive stage, the second capacitive element is charged to generate a level-converted signal. This Patent Document 1 also aims to perform level conversion of an input signal with a small number of elements in addition to reduction of current consumption.
JP 2003-115758 A

  As described above, the low-temperature polysilicon TFT used as the MOS transistor in the display device has a low crystal quality due to the heat treatment at a low temperature as compared with the MOS transistor using single crystal polysilicon. The variation is large, and the channel resistance (ON resistance) during conduction is also large.

  In the configuration disclosed in Patent Document 1 described above, during the level conversion operation, the transistor in the output drive stage is driven in accordance with the small amplitude input signal held in the first capacitor element, and is held in the second capacitor element. Discharge the recorded voltage. When this output drive stage transistor is composed of a low-temperature polysilicon TFT, its current driving capability is small, and an H level signal applied to the control electrode of the output drive stage transistor is applied from an external driving LSI. The small amplitude signal is at the H level, and the difference from the threshold voltage of the output drive stage transistor is not sufficient. As a result, the large-amplitude level-converted signal held in the second capacitive element cannot be discharged at high speed, resulting in a problem that high-speed operability is not guaranteed.

  In applications such as portable devices, it is preferable from the viewpoint of miniaturization of the device that the area occupied by the portion other than the display panel on which the display pixels are arranged be as small as possible. However, in the above-mentioned Patent Document 1, no consideration is given to the configuration for reducing the layout area of the level conversion circuit.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a level conversion circuit having a small occupation area capable of converting a small voltage amplitude signal into a high voltage amplitude signal at high speed and with low power consumption.

  Another object of the present invention is to provide a level shift circuit capable of converting the level of a display pixel data signal of a low high level inputted from an external LSI at high speed.

  A level conversion circuit according to the present invention includes a first transfer gate for transferring an input signal applied to an input to an internal node in response to a latch signal, and a signal holding circuit for holding a logic state of a signal of the internal node Is provided. This signal holding circuit includes a MOS type capacitive element coupled to the internal node and selectively boosting the voltage level of the internal node.

  In the present invention, the input signal is coupled to the MOS type capacitive element. Therefore, when the input signal is sampled, the MOS type capacitive element selectively operates as a capacitive element according to the logic level of the input signal, so that the operation of the MOS type capacitive element as the capacitive element is stopped during the sampling. By doing so, it is possible to change the voltage held by the MOS capacitor according to the input signal at high speed. Further, by performing a boosting operation using this MOS type capacitive element, a level conversion operation can be performed at a high speed. Further, the boosting operation of the MOS type capacitive element can be realized by capacitive coupling (charge pump operation), and the power consumption for level conversion can be reduced.

[Embodiment 1]
FIG. 1 shows a structure of a level conversion circuit according to the first embodiment of the present invention. In FIG. 1, the level conversion circuit N-channel MOS transistor (insulated gate field effect transistor) 5 for transmitting an input signal IN applied to input node ND5 to internal node ND7 in accordance with a latch signal SL applied via node ND4. A MOS capacitor (MOS type capacitive element) 6 that selectively boosts the voltage level of internal node ND7 in accordance with boost signal BS, and two-stage CMOS inverter IV1 cascaded between internal node ND7 and output node ND6, and It includes an N channel MOS transistor 7 which is selectively turned on according to IV2 and holding signal HD and electrically connects output node ND6 and internal node ND7 when turned on.

  The input signal IN is a small amplitude signal (low voltage level signal) supplied from an external LSI. MOS capacitor 6 is formed of an N-channel MOS transistor, and has its gate connected to internal node ND7, and its source and drain interconnected and connected to node ND3. Boost signal BS is applied to node ND3.

  Inverters IV1 and IV2 each include a P channel MOS transistor PQ and an N channel MOS transistor NQ connected in series between high side power supply node NDH and low side power supply node NDL, as shown in an example of the configuration in FIG. Including.

  The high-side power supply node NDH is supplied with the power supply voltage VDD of the display device using this level conversion circuit, and the low-side power supply node NDL is supplied with the ground voltage VSS which is the reference potential of the display device. Inverters IV1 and IV2 and MOS transistor 7 constitute a flip-flop circuit.

  Holding signal HD applied to node ND9 prevents the threshold voltage loss in MOS transistor 7 from occurring, and when activated (at the H level), the high level of the signal after level conversion output from node ND6 It is set to a voltage level higher than the threshold voltage (VTN) of MOS transistor 7 than the level (VDD level).

  The level conversion circuit shown in FIG. 1 latches an input signal IN of a low voltage level (small amplitude) input from an external LSI, and changes the high level voltage VIH of the input signal IN to a higher power supply voltage VDD level. Has the function to convert. However, when the level-converted output is generated from the node ND8 between the inverters IV1 and IV2, this level conversion circuit is provided with the low level voltage VIL (ground voltage level) of the input signal IN of the low voltage level signal. Is converted into the power supply voltage VDD level and output.

  FIG. 3 is a signal waveform diagram showing an operation of the level conversion circuit shown in FIG. The operation of the level conversion circuit shown in FIG. 1 will be described below with reference to FIG.

  In the following description, the input signal IN has an H level (logic high level) of 3V, an L level (logic low level) of 0V, and the signal after level conversion has an H level of 5V. The low level power supply potential VSS is 0V, and the threshold voltage of the MOS transistors constituting this level conversion circuit is N channel MOS transistors 5, 6, 7 and NQ are 2V, P channel MOS transistor PQ Is assumed to be -2V.

  At time t0, the latch signal SL becomes H level while the input signal IN is at H level. Accordingly, MOS transistor 5 is turned on, input signal IN is transmitted to internal node ND7, and the voltage level of internal node ND7 becomes H level voltage VIH (3 V) of input signal IN.

  At this time, boost signal BS is at the L level of the ground voltage level, and the voltage difference between internal node ND7 and node ND3 is 3V. Since this voltage difference is larger than the threshold voltage of 2V of the MOS transistor constituting the MOS capacitor 6, a channel is formed in the MOS capacitor 6 and corresponds to the gate area of the transistor constituting the MOS capacitor 6. A gate capacitance is formed and the voltage of internal node ND7 is held.

  The voltage level of the internal node ND7 is 3V, which is a voltage level higher than the input logic threshold value of the inverter IV1, that is, (VDD−VSS) /2=2.5V, and the voltage level of the internal node ND7 is Although it is recognized as the H level, the margin is small. That is, when the voltage level of the input signal of the inverter IV1 is lowered by several hundred mV due to fluctuations in the power supply voltage VDD or noise of the input signal IN, the voltage level is erroneously recognized as the L level by the inverter IV1. It may be in an unstable state.

  At time t1, latch signal SL becomes L level, MOS transistor 5 is turned off, and internal node ND7 is isolated from input node ND5. At this time, since the holding signal HD is at the L level, the MOS transistor 7 is in the off state, the internal node ND7 is in the floating state, and the input signal IN is held in the internal node ND7 in a high impedance state. .

  When the boost signal BS rises from the L level to the H level at time t2, the voltage change (5 V) of the boost signal BS is transmitted to the internal node ND7 via the MOS capacitor 6, and the voltage of the internal node ND7 is Increase by ΔVH. This voltage increase amount ΔVH is expressed by the following equation (1).

ΔVH = (VBH−VBL) · C6H / (C6H + CST) (1)
In the above equation (1), VBH−VBL indicates the voltage amplitude (voltage difference between the H level and the L level) of the boost signal BS, C6H indicates the capacitance value of the MOS capacitor at the time of channel formation, and CST indicates the internal A capacitance value of a parasitic capacitance (not shown) existing in the node ND7 is shown.

  For example, assuming that C6H = CST is set, the above equation (1) is transformed into the following equation (2).

ΔVH = (VBH−VBL) · (1/2) (2)
In the state represented by the expression (2), the voltage increase amount ΔVH is ½ times (= 2.5 V) the voltage amplitude of the boost signal BS. In this state, the voltage level of internal node ND7 is 5.5V, and similarly to the internal circuit operating at power supply voltage VDD, P channel MOS transistor PQ (see FIG. 2) of inverter IV1 is sufficiently turned off, Further, the voltage level is such that N channel MOS transistor NQ can be sufficiently set to an on state. Therefore, inverter IV1 can perform an inverting operation with a sufficient margin, and inverter IV2 accordingly provides a signal after level conversion to output node ND6 in accordance with the signal on node ND8 output from inverter IV1. Can be generated.

  At time t3, the holding signal HD becomes H level, the MOS transistor 7 is turned on, the output node ND6 and the internal node ND7 are electrically connected, a flip-flop circuit is configured, and the voltage level of the internal node ND7 is held. The At this time, the internal node ND7 has been in a high impedance state so far, and the voltage level of the internal node ND7 is determined by the voltage level of the node ND6 in the low impedance state due to the conduction of the MOS transistor 7, and the output signal of the inverter I2 The power supply voltage VDD level is set according to the voltage level.

  Here, holding signal HD is at a voltage level higher than voltage VDD + VTN, and a signal at power supply voltage VDD level can be transmitted to internal node ND7 without causing a threshold voltage loss of MOS transistor 7. .

  At time t4, the input signal IN changes from H level to L level. Since MOS transistor 5 is off, the change in input signal IN does not affect the voltage level of internal node ND7.

  At time t5, the boost signal BS decreases from the H level to the L level. At this time, an operation opposite to the step-up operation at time t2 is performed, and the voltage level of internal node ND7 tends to decrease by ΔVH by MOS capacitor 6. However, MOS transistor 7 is on, and internal node ND7 is coupled to the output of inverter IV2. The voltage level of internal node ND7 is maintained at the power supply voltage VDD level with low impedance.

  At time t6, when holding signal HD becomes L level, MOS transistor 7 is turned off, internal node ND7 is isolated from output node ND6, and internal node ND7 is maintained at the high impedance VDD level.

  At time t7, the latch signal SL changes from the L level to the H level, the MOS transistor 5 becomes conductive, and the L level input signal IN is transmitted to the internal node ND7. In response, inverters IV1 and IV2 also cause the voltage level of output node ND6 to be L level of ground voltage VSS level in accordance with the voltage level of input signal IN.

  At time t8, the latch signal SL becomes L level, the MOS transistor 5 is turned off, the node ND7 is separated from the input node ND5, and becomes the high impedance ground voltage VSS level. In this state, the boost signal BS is at L level, the node ND3 is at the ground voltage VSS level, the potential difference between the electrodes of the MOS capacitor 6 is 0 V, and no channel is formed. The capacitance between the internal node ND7 and the node ND3 is only a slight capacitance formed by the overlapping portion of the gate and drain / source portion of the transistor constituting the MOS capacitor 6.

  At time t9, the boost signal BS becomes H level. However, even if this boost signal BS rises to the H level, no capacitance is formed in the MOS capacitor 6 except for the parasitic capacitance. Therefore, the change in the voltage level of the internal node ND7 due to the change in the boost signal BS does not occur. , A slight amount ΔVL. This variation ΔVL is caused by the capacitance formed by the overlap between the gate and the source / drain existing in the MOS capacitor 6. The voltage ΔVL is determined with a sufficient margin in the inverter IV1 with the L level, the output signal of the inverter IV1 is not inverted, and the output node ND6 is maintained at the ground voltage VSS level.

  At time t10, when the holding signal HD becomes H level, the MOS transistor 7 becomes conductive, the internal node ND7 is driven by the inverter IV2, and the voltage level becomes the ground voltage VSS level.

  Thereafter, the sampling of the input signal IN by the latch signal SL and the selective boosting operation by the boosting signal BS are repeated, and the level conversion operation of the input signal IN is performed.

  When the input signal IN is at the H level, a capacitor is formed in the MOS capacitor 6 and the input signal IN is stably held. On the other hand, when this input signal IN becomes L level, no capacitance is formed in MOS capacitor 6, so that internal node ND7 can be driven to L level of the ground voltage level at high speed, and accordingly high-speed level conversion is performed. Can be realized.

  Further, a flip-flop circuit is configured by using cascaded inverters and MOS transistors, and the voltage level of this internal node can be stably maintained at the power supply voltage level even when the boost signal BS is lowered. When the boost signal BS changes, it is possible to prevent a change in the voltage level of the output signal after level conversion.

  Further, the level conversion operation only uses the charge pump operation of the MOS capacitor 6, and the current consumption can be reduced.

[Modification 1]
FIG. 4 shows a structure of a main portion of the level conversion circuit according to the first modification of the first embodiment of the present invention. FIG. 4 shows a configuration of inverters IV1 and IV2 constituting a signal holding circuit in the level conversion circuit. In FIG. 4, inverter IV1 is connected between P channel MOS transistor PQ1 and N channel MOS transistor NQ1, whose gates are connected to internal node ND7, and between P channel MOS transistor PQ1 and high side power supply node NDH and P channel MOS transistor PQ3 receiving latch signal SL via node ND4 is included at the gate. The source of the MOS transistor NQ1 is connected to the low-side power supply node NDL. MOS transistors PQ1 and NQ1 have their drain nodes coupled in common to form an output node of inverter IV1.

  Inverter IV2, similarly to inverter IV1, is connected between P channel MOS transistors PQ2 and NQ2 receiving the output signal of inverter IV1 at their gates, between MOS transistor PQ2 and high-side power supply node NDH, and has node ND4 at its gate. P channel MOS transistor PQ4 receiving latch signal SL through the same. The source of the MOS transistor NQ2 is connected to the low-side power supply node NDL.

  In the configuration of inverters IV1 and IV2 shown in FIG. 4, MOS transistors PQ3 and PQ4 are turned on in accordance with deactivation of latch signal SL, and supply current from high-side power supply node NDH receiving power supply voltage VDD. On the other hand, when latch signal SL attains an active H level, MOS transistors PQ3 and PQ4 are turned off, and a path for supplying current from high-side power supply node NDH is cut off. When latch signal SL is at H level, in the level conversion circuit, MOS transistor 5 in the input stage shown in FIG. 1 is turned on, and input signal IN is transmitted to internal node ND7. As shown in FIG. 3, when this input signal IN is at H level and the voltage level of internal node ND7 becomes VIH, both MOS transistors PQ1 and NQ1 are turned on. However, in this state, the high-side power supply node NDH and the MOS transistor PQ1 are separated from each other by maintaining the MOS transistor PQ3 in the off state, and a through current is passed from the high-side power supply node NDH to the low-side power supply node NDL. It can be prevented from flowing and current consumption can be reduced.

  The absolute value of the threshold voltage of MOS transistors PQ1 and NQ1 is about 2V. When the voltage VIH of the input signal IN is about 2.5V, in the MO and the transistor NQ1, the difference between the gate-source voltage and the threshold voltage is 0.5V. Considering the fluctuation of the voltage level due to the influence of noise or the like of the input signal IN, the output signal may become unstable when the input signal IN when the latch signal SL becomes H level is sampled or when the inverter IV1 is not operating. There is. In this state, in order to prevent the output signal of the inverter IV2 from becoming similarly unstable, the MOS transistor PQ4 is also turned off during the activation period of the latch signal SL, and similarly prevents a through current from flowing through the inverter IV2. .

  When the sampling operation of input signal IN is completed and the holding mode is entered, latch signal SL becomes L level, MOS transistors PQ3 and PQ4 are both turned on, and inverters IV1 and IV2 realize the function as an inverter. After the deactivation of the latch signal SL, as shown in FIG. 3, the boost signal BS is activated to boost the voltage VIH of the input signal IN, and a signal corresponding to the input signal IN is accurately generated at the output node ND6. Is done.

  Therefore, in inverters IV1 and IV2 shown in FIG. 4, high-side current source transistors PQ3 and PQ4 are selectively activated according to latch signal SL, so that a period from time t1 to time t2 shown in FIG. There is only a possibility that a through current flows, and current consumption can be reduced.

[Modification 2]
FIG. 5 shows a structure of a second modification of the level conversion circuit according to the first embodiment of the present invention. FIG. 5 also shows the configuration of inverters IV1 and IV2 constituting the signal holding circuit. In the configuration of inverters IV1 and IV2 shown in FIG. 5, N-channel MOS transistors NQ3 and NQ4 receiving boosted signal BS at their gates are connected between MOS transistors NQ1 and NQ2 and low-side power supply node NDL, respectively. MOS transistors PQ1 and PQ2 are directly connected to high-side power supply node NDH, respectively.

  In the configuration of inverters IV1 and IV2 shown in FIG. 5, while boosted signal BS is at the L level, MOS transistors NQ3 and NQ4 are turned off, and the path through which the through current flows in inverters IV1 and IV2 is blocked. Therefore, even when internal node ND7 is maintained at voltage VIH level lower than power supply voltage VDD, it is possible to reliably prevent the occurrence of a through current and reduce the current consumption.

  In the case of the configuration of inverters IV1 and IV2 shown in FIG. 5, inverters IV1 and IV2 are inactivated (inverter operation is stopped) until internal node ND7 is boosted, and the internal operation current flows therethrough. Is cut off. Therefore, when internal node ND7 is driven to the boosted voltage level, inverters IV1 and IV2 are also activated and operate as an inverter, so that the period during which the through current flows can be shortened and the current consumption can be reduced. can do.

  As described above, according to the first embodiment of the present invention, the internal node to which the input signal is transmitted is boosted by the charge pump operation according to the boost signal using the MOS capacitor, and the input signal IN is L Even at the level, the capacitance is sufficiently small for the internal node, and the L-level input signal IN can be transmitted to the internal node at high speed. Accordingly, it is possible to generate a large amplitude signal (high voltage level signal) by converting the level of a small amplitude signal (low voltage level signal) at high speed.

[Embodiment 2]
FIG. 6 shows a structure of a level conversion circuit according to the second embodiment of the present invention. The level conversion circuit shown in FIG. 6 differs from the level conversion circuit shown in FIG. 1 in the following points. More specifically, N channel MOS transistor 9 is provided between internal node ND7 and input node (latch input node) ND10 of inverter IV1, and N channel MOS transistor 10 is initialized to initialize latch input node ND10 to a predetermined potential. Is provided. MOS transistor 9 has its gate connected to internal node ND7, and conducts when internal node ND7 is at the H level, and transmits boosted signal BS on node ND3 to latch input node ND10.

  MOS transistor 10 receives latch signal SL at its gate, and conducts when latch signal SL is at the active H level, and applies reference voltage (hereinafter referred to as ground voltage) VSS of low-side power supply node NDL to latch input node ND10. To communicate.

  Inverters IV1 and IV2 are cascaded between latch input node ND10 and output node ND6. These inverters IV1 and IV2 form a buffer / transfer circuit BF. Inverters IV1 and IV2 may each be constituted by a CMOS inverter, or may be constituted by a clocked inverter shown in FIG. 4 or FIG. The other configuration of the level conversion circuit shown in FIG. 6 is the same as that of the level conversion circuit shown in FIG. 1, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 7 is a signal waveform diagram showing an operation of the level conversion circuit shown in FIG. The operation of the level conversion circuit shown in FIG. 6 will be described below with reference to FIG. The conditions such as the voltage amplitude of latch signal SL and boost signal BS and the threshold voltage of the MOS transistor are the same as in the first embodiment.

  At time t0, the latch signal SL becomes the H level of the power supply voltage VDD level, the MOS transistor 5 is turned on, and the input signal IN is transmitted to the internal node ND7. Assume that the input signal IN is at a voltage VIH level and at an H level. According to this input signal IN, the voltage level of internal node ND7 becomes VIH level. Boost signal BS is at the level of ground voltage VSS, a channel is formed in MOS capacitor 6, and the voltage level of internal node ND 7 is held by MOS capacitor 6.

  On the other hand, when the latch signal SL is activated, the MOS transistor 10 is in the on state, the ground voltage VSS of the low-side power supply node NDL is transmitted to the latch input node ND10, and the latch input node ND10 is at the level of the ground voltage VSS. Accordingly, output node ND6 is also maintained at the level of ground voltage VSS.

  At time t1, the latch signal SL becomes L level, and the sampling of the input signal IN is completed. At this time, the boosted signal BS is at the ground voltage VSS level and the MOS transistor 9 is turned on, and the boosted signal BS at the ground voltage level is transmitted to the latch input node ND10. Further, MOS transistor 10 is turned off in accordance with deactivation of latch signal SL, and internal latch input node ND10 is isolated from low-side power supply node ND6. However, in this state, boost signal BS is transmitted to latch input node ND10, and latch input node ND10 is stably maintained at the L level.

  At time t2, boost signal BS is activated and rises from L level to H level (power supply voltage VDD level). Accordingly, as in the first embodiment, the voltage level of internal node ND7 increases by the voltage ΔVH by the charge pump operation of MOS capacitor 6. This voltage ΔVH + VIH is a voltage level sufficiently higher than the sum of threshold voltage VTN of MOS transistor 9 and power supply voltage VDD, and H-level boost signal BS is transmitted to latch input node HD10, and latch input node ND10 is The power supply voltage VDD level (the H level of the boost signal BS) is charged. Accordingly, the voltage level of output node ND6 also becomes power supply voltage VDD level by the amplification operation of buffer / transfer circuit BF.

  At time t3, the hold signal HD is activated (becomes H level), the MOS transistor 7 is turned on, the output node ND6 is electrically connected to the latch input node ND10, and the latch input node ND10 has an H level (VDD) Level) is maintained at a low impedance.

  Here, the holding signal HD is at a voltage level higher than the voltage VDD + VTN as in the first embodiment, and the MOS transistor 7 latches the signal at the power supply voltage VDD level without latch voltage loss. It can be transmitted to the node ND10.

  At time t4, the input signal IN changes from the H level to the L level (voltage VIL level: VIL = VSS). However, MOS transistor 5 is in an off state, and the change in input signal IN is not transmitted to internal node ND7.

  At time t5, the boost signal BS is deactivated and falls from the H level to the L level. In accordance with the fall of boosted signal BS, MOS capacitor 6 performs an operation opposite to the operation at time t2, and the voltage level of internal node ND7 is lowered by this increased voltage ΔVH to become voltage VIH level. When internal node ND7 falls to VIH level, MOS transistor 9 is in the on state, and latch input node ND10 attains L level (ground voltage VSS level) in accordance with the fall of boost signal BS (generation of boost signal BS). The driving force of the circuit is sufficiently larger than the output driving force of the inverter IV2.) Accordingly, the voltage level of internal node ND6 also becomes L level (voltage VSS level) after the propagation delay time of buffer / transfer circuit BF has elapsed.

  When holding signal HD is deactivated at time t6 and MOS transistor 7 is turned off, input node ND10 is reliably maintained at ground voltage VSS level according to boosted signal BS.

  At time t7, the latch signal SL becomes H level again, the MOS transistor 5 is turned on, and the internal node ND7 becomes the ground voltage VSS level corresponding to the voltage level of the input signal IN. When the L level input signal IN is transmitted to the internal node ND7, a channel is not formed in the MOS capacitor 6 as the voltage level of the internal node ND7 decreases as in the first embodiment, so that the capacity of the internal node ND7 is sufficient. The internal node ND7 at VIH level can be discharged to the ground voltage VSS level according to the input signal IN at a high speed. That is, if the voltage VIH is 2.5V and the threshold voltage of the MOS transistor constituting the MOS capacitor 6 is 2V, the MOS transistor constituting the MOS capacitor 6 is in a weak ON state and the gate voltage is lowered. Accordingly, the inversion layer of the channel becomes a non-inversion layer, the capacity operation is stopped, and the capacity value can be reduced at a high speed as the voltage level of the internal node ND7 decreases.

  At time t8, the latch signal SL becomes L level, the MOS transistor 5 is turned off, and the internal node ND7 is maintained at L level with high impedance. In this state, the MOS transistor 9 is off. However, when the latch signal SL is activated, the MOS transistor 10 is in the on state, and the latch input node ND10 is surely initialized to the ground voltage VSS level.

  At time t9, boost signal BS is activated and rises from L level to H level. However, in this case, the MOS capacitor 6 is merely boosted by the capacitance due to the overlapping portion of its gate and source / drain regions, and the voltage level of the node ND7 increases by the voltage ΔVL. The voltage ΔVL is a voltage level sufficiently lower than the threshold voltage VTN of the MOS transistor 9, the MOS transistor 9 maintains the off state, and the latch input node ND10 has a high impedance and is precharged to the L level. Maintained. At this time, even when the voltage ΔVL is higher than the threshold voltage VTN of the MOS transistor 9, when the boost signal BS is activated, the MOS transistor 9 operates in the source follower mode. Only the voltage ΔVL−VTN can be transmitted to the latch input node ND10, and the voltage rise of the latch input node ND10 can be reliably prevented.

  At time t10, when holding signal HD becomes H level, MOS transistor 7 is turned on, and latch input node ND10 is electrically coupled to output node ND6, and is maintained at ground voltage VSS level with low impedance.

  In the configuration of the level conversion circuit shown in FIG. 6, internal node ND 7 is coupled to latch input node ND 10 through MOS transistor 9. Therefore, the parasitic capacitance of internal node ND7 is only the gate capacitance and wiring capacitance of MOS transistor 9, and is more parasitic than the configuration in which both gates of the P and N-channel MOS transistors of inverter IV1 are connected to internal node ND7. The capacity can be reduced, and internal node ND7 can be charged and discharged at high speed and efficiently. Particularly during the boosting operation, the voltage level of the internal node ND7 can be sufficiently increased because the parasitic capacitance is small, and the voltage rise amount ΔVH can be sufficiently increased via the MOS transistor 9 to the latch input node ND10 at high speed. A signal can be transmitted.

  Further, by raising the boosting operation BS to the H level while the boosting signal BS is transmitted to the latch input node ND10 through the MOS transistor 9, the latch input node ND10 is driven to the H level according to the boosting signal BS at a high speed. And a faster level conversion operation can be realized.

  In the configuration of the level conversion circuit shown in FIG. 6, boosted signal BS may be transmitted to the source node of MOS transistor 10 instead of ground voltage VSS. When the latch input node ND10 is initialized according to the latch signal SL, the boost signal BS is at the L level. Therefore, the latch input node ND10 can be surely initialized to the L level of the ground voltage level according to the boost signal BS. it can.

  FIG. 8 is a diagram schematically showing an example of a configuration of a part that generates a control signal used in the level conversion circuit in the first and second embodiments. The control signal generator shown in FIG. 8 generates a latch signal SL, a boost signal BS, and a holding signal HD in accordance with a clock signal CLK that defines an application cycle of the input signal IN.

  In FIG. 8, the control signal generation unit includes a delay circuit 20 that delays the clock signal CLK for a predetermined time, a gate circuit 22 that passes the output signal of the delay circuit 20 when the hold signal HD is inactivated, and an output of the gate circuit 22. A one-shot pulse generation circuit 24 that generates a one-shot pulse signal in response to the rise of the signal, and a one-shot pulse generation circuit 26 that generates a one-shot pulse signal according to the fall of the output signal of the one-shot pulse generation circuit 24 And a delay circuit 28 for delaying the output signal of the one-shot pulse generation circuit 26 for a predetermined time.

  The latch signal SL is generated from the one-shot pulse generation circuit 24 in the form of a one-shot pulse signal, and the boost signal BS is generated from the one-shot pulse generation circuit 26 in the form of a one-shot pulse signal. A hold signal HD is generated from the delay circuit 28 in a form in which the boost signal BS is delayed for a predetermined time. The delay circuit 28 has a level conversion function, and sets the holding signal HD at the H level to a voltage level equal to or higher than the power supply voltage VDD + VTN.

  FIG. 9 is a signal waveform diagram showing an operation of the control signal generator shown in FIG. Hereinafter, the operation of the control signal generator shown in FIG. 8 will be briefly described with reference to FIG.

  The input signal IN is transferred (changed) in synchronization with the rise of the clock signal CLK. That is, when the input signal IN is a display pixel data signal, the input signal IN is transferred from an external driving LSI in synchronization with the clock signal CLK. The delay circuit 20 delays the clock signal CLK for a predetermined time. When holding signal HD is at L level and the output signal of delay circuit 20 is at H level, the output signal of gate circuit 22 is at H level. Accordingly, the latch signal SL from the one-shot pulse generation circuit 24 is activated and maintained in an active state for a predetermined period.

  When the latch signal SL is deactivated, the one-shot pulse generation circuit 26 activates the boost signal BS in response to the deactivation. The delay circuit 28 delays the boost signal BS for a predetermined time to generate a hold signal HD. The hold signal HD is activated and deactivated with a delay of a predetermined time with respect to the boost signal BS. Yes.

  When the hold signal HD from the delay circuit 28 is deactivated, the gate circuit 22 is enabled, and the input signal IN can be sampled according to the next clock signal CLK. When the holding signal HD is in the active state, the gate circuit 22 is in a disabled state, and even if the output signal of the delay circuit 20 becomes H level, the output signal of the gate circuit 22 is fixed at L level, and the latch signal SL is Not generated. Therefore, after the latch function is canceled in the level conversion circuit, the input signal IN is sampled, and the state of the output signal can be changed according to the sampled input signal IN.

  The hold signal HD may be deactivated at a time before the latch signal SL is activated. For example, a configuration in which the boost signal BS is deactivated in synchronization with the rise of the clock signal CLK is used. May be.

  The configuration of the control signal generator shown in FIG. 8 can also be applied to the level conversion circuit in the first embodiment.

  As described above, according to the second embodiment of the present invention, the internal node to which input signal IN is transmitted is connected to the gate of the transfer MOS transistor, and input to the latch input node via this transfer MOS transistor. A large amplitude signal having a logic level corresponding to the signal is transmitted. Therefore, the load capacity of the internal node can be reduced, and level conversion can be performed by charging / discharging the internal node at high speed.

[Embodiment 3]
FIG. 10 shows a structure of the level conversion circuit according to the third embodiment of the present invention. The level conversion circuit shown in FIG. 10 differs from the level conversion circuit shown in FIG. 6 in the following points. That is, MOS capacitor 6 has its source / drain node connected to latch input node ND10, not to node ND3 that receives boosted signal BS. The other configuration of the level conversion circuit shown in FIG. 10 is the same as the configuration of the level conversion circuit shown in FIG. 6, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  The operation waveform of the level conversion circuit shown in FIG. 10 is the same as the operation waveform shown in FIG. In accordance with the latch signal SL, the input signal IN is sampled and confined in the internal node ND7, and then the boost signal BS is activated. Boost signal BS is transmitted to latch input node ND10 through MOS transistor 9 when internal node ND7 is at the H level. Therefore, as the voltage level of latch input node ND10 increases according to boosted signal BS, MOS capacitor 6 increases the voltage level of internal node ND7 by charge pump operation or capacitive coupling. Therefore, the MOS capacitor 6 substantially boosts the internal node ND7 according to the boost signal BS, and the MOS transistor 9 reliably transmits the boost signal BS to the latch input node ND10 as the potential of the internal node ND7 rises. To do. That is, the positive feedback operation of increasing the voltage level of the latch input node ND10 and the internal node ND7 by the MOS transistor 9 and the MOS capacitor 6 causes the voltage level of the internal node ND7 to rise at a high speed, and accordingly, the latch input node ND10 The voltage level rises at high speed, and level conversion is performed at high speed.

  When the voltage level of internal node ND7 is L level, MOS transistor 9 is off, MOS transistor 9 remains off, and boost signal BS is not transferred. Although the potential of the internal node ND11 slightly rises due to the parasitic capacitance between the gate and drain of the MOS transistor 9, the parasitic capacitance is sufficiently small, and the latch input node ND10 is maintained at the L level. When the holding signal HD is activated, the latch input node ND10 is reliably maintained at the ground voltage VSS level by the buffer / transfer circuit BF.

  In the configuration of the level conversion circuit shown in FIG. 10, it is not necessary to use the boost signal BS for controlling the operation of the MOS capacitor, and the source / drain region of the MOS capacitor 6 can be simply connected to the latch input node ND10. It is only required. Therefore, circuit layout design is facilitated.

  In the level conversion circuit shown in FIG. 10, boosting signal BS may be supplied to node NDL. This is the same as in the second embodiment.

[Embodiment 4]
FIG. 11 shows a structure of the level conversion circuit according to the fourth embodiment of the present invention. The level conversion circuit shown in FIG. 11 differs from the level conversion circuit shown in FIG. 10 in the following points. That is, in the level conversion circuit shown in FIG. 11, the MOS capacitor 6 is not provided. N channel MOS transistor 39 transmitting boosted signal BS to latch input node ND10 in accordance with the voltage level of internal node ND7 has its channel width W sufficiently large. The other configuration of the level conversion circuit shown in FIG. 11 is the same as that of the level conversion circuit shown in FIG. 10, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  The MOS transistor 39 also functions as a MOS capacitor when conducting. In other words, when a channel is formed in the channel region in MOS transistor 39, the voltage level of the channel rises according to the voltage level of boosted signal BS, and internal node ND7 is caused by capacitive coupling through the gate insulating film. The voltage level increases. That is, when internal node ND7 is at the H level in the high impedance state, MOS transistor 39 raises the voltage level of internal node ND7 by the self-bootstrap action as the voltage level of boosted signal BS rises, and latches boosted signal BS. This is transmitted to the input node ND10.

  The operation waveform of the level conversion circuit shown in FIG. 11 is the same as the operation waveform shown in FIG. By increasing the channel width W of the MOS transistor 39 sufficiently to increase the current driving capability, the voltage level of the latch input node ND10 can be increased at high speed.

  The channel width W of the MOS transistor 39 only needs to be large enough to realize the capacitance value of the MOS capacitor 6.

  In the configuration of the level conversion circuit shown in FIG. 11, the MOS capacitor 6 is not required, the degree of freedom in circuit layout design is increased, and the layout design is facilitated.

  As described above, according to the fourth embodiment of the present invention, the MOS transistor for transferring the boost signal to the latch input node is also operated as a MOS capacitor, so that the circuit layout area can be reduced and the number of circuit elements can be reduced. Therefore, the layout design is facilitated, the current driving capability of the transfer transistor is large, and the latch input node can be driven at high speed to perform level conversion.

[Embodiment 5]
FIG. 12 shows a structure of the level conversion circuit according to the fifth embodiment of the present invention. The level conversion circuit shown in FIG. 12 differs from the level conversion circuit shown in FIG. 11 in the following points. That is, in the structure of the level conversion circuit shown in FIG. 12, a latch circuit is provided for reliably maintaining the latch input node ND10 at the L level when an L level signal is transmitted to the latch input node ND10. It is done. This latch circuit includes a P channel MOS transistor 41 and an N channel MOS transistor 42 connected in series between a high side power supply node NDH and a low side power supply node NDL. P-channel MOS transistor 41 receives boost signal BS at its gate, and drain node ND11 is connected to the gate of MOS transistor 10. N channel MOS transistor 42 has its gate connected to latch input node ND10, its drain connected to node ND11, and its source connected to low-side power supply node NDL.

  The other configuration of the level conversion circuit shown in FIG. 12 is the same as the configuration of the level conversion circuit shown in FIG. 11, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 13 is a signal waveform diagram representing an operation of the level conversion circuit shown in FIG. The operation of the level conversion circuit shown in FIG. 12 will be described below with reference to FIG.

  Before time t2, boost signal BS is at L level, MOS transistor 41 is on, and node ND11 is maintained at power supply voltage VDD level. MOS transistor 10 is on, and ground voltage VSS of low-side power supply node NDL is transmitted to latch input node ND10. According to the voltage level of latch input node ND10, MOS transistor 42 is off.

  In accordance with activation of latch signal SL, input signal IN at H level (voltage VIH level) is transmitted to internal node ND7. MOS transistor 39 is rendered conductive as the voltage level of internal node ND7 increases. In this state, boosted signal BS is at L level and MOS transistor 10 is on, so that latch input node ND10 is maintained at ground voltage level VSS level.

  When boosted signal BS rises to H level at time t2, MOS transistor 41 is turned off. When boosted signal BS is transmitted to latch input node ND10 via MOS transistor 39 and its voltage level rises, MOS transistor 42 is turned on, lowering the voltage level at node ND11, and the conductance of MOS transistor 10 being reduced. The latch input node ND10 is driven to the power supply voltage VDD level at high speed according to the boost signal BS. In response, node ND11 is discharged to ground voltage VSS level by MOS transistor. Accordingly, MOS transistor 10 is turned off, and latch input node ND10 is reliably set to power supply voltage VDD level according to boosted signal BS. When the boost signal BS is transmitted to the latch input node ND10, the voltage level of the internal node ND7 rises to the voltage level of VIH + ΔVH due to the self bootstrap action of the MOS transistor 39.

  At time t3, the holding signal HD becomes H level, and the latch input node ND10 is maintained at H level with low impedance.

  At time t4, the input signal IN decreases to the L level, and at time t5, the boost signal BS decreases to the L level. Latch signal SL is at L level, and the change in input signal IN is not transmitted to internal node ND7. On the other hand, in response to the fall of boost signal BS, MOS transistor 41 is turned on, node ND11 is charged, and its voltage level rises. As the voltage level of node ND11 increases, MOS transistor 10 becomes conductive, latch input node ND10 is driven in the direction of ground voltage VSS, and latch input node ND10 goes to the ground voltage level at a higher speed as boost signal BS decreases. Driven. The potential level drop of latch input node ND10 is transmitted through buffer / transfer circuit BF and MOS transistor 7, and latch input node ND10 is discharged to the ground voltage level.

  In the discharging operation of the latch node ND11, if the current driving capability of the MOS transistor 10 and the current driving capability of the boost signal BS are set to be larger than the current driving capability of the inverter IV2, the latch input node ND10 is set at a high speed. Can be driven to ground voltage level.

  On the other hand, as the potential level of boosted signal BS decreases, the voltage level of internal node ND7 is decreased by ΔVH by MOS transistor 39 to voltage VIH level.

  At time t6, the holding signal HD becomes L level, and the MOS transistor 7 is turned off. In this state, MOS transistor 10 is on, and latch input node ND10 is maintained at the L level with low impedance.

  At time t7, the latch signal SL becomes H level, the L level input signal IN is transmitted to the internal node ND7, the internal node ND11 has little charge and its parasitic capacitance is small. It becomes VSS level.

  At time t8, latch signal SL becomes L level, and at time t9, boost signal BS rises to H level. As the boost signal BS rises, the voltage level of the internal node ND7 increases by the voltage ΔVL due to capacitive coupling of the parasitic capacitance of the MOS transistor 39. However, voltage ΔVL is at a voltage level sufficiently lower than threshold voltage VTN of MOS transistor 39, MOS transistor 39 maintains a non-conductive state, and boost signal BS is not transmitted to latch input node ND10. At this time, the node ND11 is at the H level, the MOS transistor 10 is in the ON state, and the latch input node ND10 is maintained at the ground voltage VS level. Responsively, MOS transistor 42 remains off, and node ND11 is maintained at the precharged power supply voltage VDD level.

  When holding signal HD is activated at time t10, MOS transistor 7 is rendered conductive, and latch input node ND10 is reliably maintained at the L level. While boosting signal BS is at the H level, the voltage level of internal node ND7 is maintained at the voltage ΔVL level due to capacitive coupling. The level of the voltage ΔVL of the internal node ND7 is driven to the ground voltage VSS level by the capacitive coupling of the MOS transistor 39 when the boost signal BS is lowered.

  Therefore, when input signal IN is at L level, latch input node ND10 can be reliably maintained at ground voltage VSS level until holding signal HD is activated. Thereby, even if the voltage level of internal node ND7 rises as boost signal BS rises, latch input node ND10 can be reliably maintained at a low impedance L level, and malfunction and through current in inverter IV1 can be maintained. Can be prevented.

  In the level conversion circuit shown in FIG. 12, the MOS capacitor 6 is not used. However, a configuration in which MOS capacitor 6 is connected to internal node ND7 may be used as in the configurations shown in the second and third embodiments. Even in this case, the latch input node ND10 can be reliably maintained at the L level with low impedance when the L level signal is transmitted, and can be reliably maintained at the ground voltage VSS level.

  As described above, according to the fifth embodiment of the present invention, when an L level signal is transmitted to the latch input node, the L level is maintained at a low impedance, and the potential level of the latch input node is maintained. The rise (lift) can be prevented, and the malfunction and the through current can be suppressed in the next-stage inverter.

[Embodiment 6]
FIG. 14 shows a structure of the level conversion circuit according to the sixth embodiment of the present invention. The level conversion circuit shown in FIG. 14 differs from the level conversion circuit shown in FIG. 1 in the following points. That is, the latch signal SLBT having an amplitude larger than the power supply voltage VDD is applied to the gate of the MOS transistor 5 in the input stage. The other configuration of the level conversion circuit shown in FIG. 14 is the same as the configuration of the level conversion circuit shown in FIG. 1, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 15 is a signal waveform diagram representing an operation of the level conversion circuit shown in FIG. The operation of the level conversion circuit shown in FIG. 14 will be briefly described below with reference to FIG.

  The operation waveform diagram of the level conversion circuit shown in FIG. 15 is the same as the operation waveform diagram shown in FIG. 3 except that the H level voltage level of latch signal SLBT is different. That is, the latch signal SLBT is set to a voltage level whose H level is higher than the voltage VDD + VTN. VTN represents the threshold voltage of the MOS transistor.

  If threshold voltage VTN of MOS transistor 5 becomes high due to, for example, manufacturing parameter variations, H level voltage VIH of input signal IN may not be transmitted to internal node ND7. However, by utilizing the boosted latch signal SLBT, the MOS transistor 5 is reliably set to a voltage level higher than its threshold voltage to the internal node ND7. The VIH level input signal IN can be reliably transmitted.

  The H level of the boosted latch signal SBLT is substantially the same voltage level as the H level of the holding signal HD. For example, the operation power supply voltage of the one-shot pulse generation circuits 24 and 28 in the control signal generation unit shown in FIG. By setting the voltage level higher than the voltage VDD + VTN, it is possible to realize a configuration in which the latch signal SLBT and the holding signal HD having an easily boosted H level are generated.

  As described above, according to the sixth embodiment of the present invention, the transfer control signal (latch signal) having an enlarged amplitude is used as the transfer control signal of the input signal of the input unit. The input signal IN can be reliably transmitted to the internal node ND7 without any loss of threshold voltage.

  When a CMOS transmission gate is used in place of MOS transistor 5, it is not particularly required to use boosted latch signal SLBT.

  In the first to sixth embodiments, a CMOS transmission gate may be used for these transfer transistors 5 and 7, or an analog buffer may be used.

[Embodiment 7]
FIG. 16 shows a structure of the level conversion circuit according to the seventh embodiment of the present invention. The level conversion circuit shown in FIG. 16 differs from the level conversion circuit according to the fourth embodiment shown in FIG. 11 in the following points. That is, the internal node ND10 is connected to the output node ND6 via the wiring 50. Therefore, internal node ND10 is always connected to output node ND6. The MOS transistor (7) responding to the holding signal HD is not used.

  The other configuration of the level conversion circuit shown in FIG. 16 is the same as the configuration of the level conversion circuit shown in FIG. 11, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 17 is a timing chart showing the operation of the level conversion circuit shown in FIG. The operation of the level conversion circuit shown in FIG. 16 will be briefly described below with reference to FIG. In the signal waveform diagram shown in FIG. 17 as well, the H level voltage VIH (eg, 3.0 V) of the input signal IN is converted to the boosted voltage VDD (eg, 5 V), and the L level voltage VIL of the input signal IN is equal to the ground voltage VSS. The voltage level is not converted, and the L level voltage from the output node ND6 is maintained at the ground voltage VSS.

  Nodes ND6 and ND10 are at the H level or the L level according to the voltage level of input signal IN in the previous cycle.

  At time t0, the latch signal SL becomes the H level of the voltage VDD level. Responsively, MOS transistor 5 is turned on, and input signal IN applied to input node ND5 is transmitted to internal node ND7. Now, the voltage level of input signal IN is H level voltage VIH, and internal node ND7 is also driven to H level voltage VIH level accordingly.

  In response to the rise of latch signal SL, MOS transistor 10 is turned on, and nodes ND6 and ND10 are discharged to the level of ground voltage VSS. In this case, if the output signal of the inverter IV2 at the output stage of the buffer / transfer circuit BF is at the H level, the H level output of the inverter IV2 and the L level driving of the MOS transistor 10 are in a competitive state. However, by making the on resistance (source / drain resistance in the on state) Ron of the MOS transistor 10 sufficiently lower than the output impedance of the inverter IV2, the MOS transistor 10 causes the potential levels of the nodes ND6 and ND10 to be sufficiently low. Driven to level. Accordingly, in the buffer / transfer circuit BF, the inverter IV1 determines that the voltage level of the node ND10 is L level and outputs an H level signal, so that the output signal of the inverter IV2 is inverted to L level. Thereby, nodes ND6 and ND10 are maintained at the L level of the ground voltage VSS level.

  At time t1, latch signal SL becomes L level, MOS transistor 5 is turned off, and voltage VIH is maintained in a high impedance state at internal node ND7. At this time, the MOS transistor 10 is also turned off in response to the fall of the latch signal SL. Boost signal BS applied to node ND3 is at L level (ground voltage VSS level), MOS transistor 39 is turned on in accordance with voltage VIH at node ND7, and boost signal BS at L level is supplied to node ND10 (ND6). Also, nodes ND6 and ND10 are maintained at the L level by buffer / transfer circuit BF.

  When boosted signal BS rises to voltage VDD level at time t2, voltage levels of nodes ND10 and ND6 begin to rise from L level to H level via MOS transistor 39 in the on state. MOS transistor 39 has a larger channel width W, and the on-resistance of MOS transistor 39 is set sufficiently lower than the output impedance of inverter IV2 (the on-resistance of the discharging N-channel MOS transistor). Regardless, the voltage level of the nodes ND10 and ND6 rises due to the charging current from the MOS transistor 39.

  At this time, the internal node ND7 is in a high impedance state, and the voltage level rises by ΔVH due to the self bootstrap action of the MOS transistor 39 to become voltage VIH + ΔVH (> VDD), and the node ND10 rises to the H level at high speed. . Buffer / transfer circuit BF raises the potentials of nodes ND6 and ND10 in accordance with the rise in potential of node ND10, and nodes ND10 and ND6 rise to the voltage VDD level at high speed.

  When the voltage of each node is stabilized at time t3, node ND7 is at the level of voltage VIH + ΔVH, and nodes ND6 and ND10 are at the level of voltage VDD. When boosting signal BS is supplied (when voltage at node ND10 rises), latch signal SL is at L level, MOS transistor 10 is maintained in the off state, and the boosting operations of internal nodes ND10 and ND6 are not affected. Absent. That is, the node ND4 is maintained at the ground voltage VSS with a low impedance by the circuit that outputs the latch signal SL, and the potential of the node ND4 does not increase at all when the level of the boost signal BS increases.

  At time t4, the input signal IN changes from the H level to the L level, and the voltage level of the input signal IN becomes the VIL (= VSS) level. Even in this state, the latch signal SL is at the L level (VSS level), the MOS transistor 5 remains in the OFF state, and the voltage level of the internal node ND7 does not change, and the voltage level of the voltage VIH + ΔVH is maintained. Similarly, nodes ND6 and ND10 do not change their voltage levels and maintain the voltage VDD level.

  At time t5, boost signal BS falls from voltage VDD to ground voltage VSS level. The latch signal SL is at L level, and the MOS transistor 5 is in an off state. Therefore, since node ND7 is in a high impedance state (floating state), the voltage level of node ND7 decreases to the voltage VIH level as the boost signal BS falls.

  Boosted signal BS is transmitted to nodes ND10 and ND6 through MOS transistor 39 according to the voltage level of internal node ND7. In this case, depending on the relationship between the on-resistance of MOS transistor 39 and the output impedance of inverter IV2 (the on-resistance of the charging P-channel transistor of inverter IV2), the voltage levels at nodes ND10 and ND6 drop to the L level or H Maintain level. In FIG. 17, a signal waveform in which the voltage level of nodes ND6 and ND10 decreases to ground voltage level VSS is indicated by a solid line, and a state where the voltage level is held at H level is indicated by a one-dot chain line.

  That is, when the voltage level of node ND7 is voltage VIH + ΔVH level higher than power supply voltage VDD, MOS transistor 39 has its on-resistance sufficiently lower than the output impedance of inverter IV2, but the voltage level of node ND7 decreases to voltage VIH. Then, the on-resistance increases. Therefore, when the ON resistance of MOS transistor 39 is higher than the output impedance of inverter IV2, nodes ND10 and ND6 are maintained at the H level by inverter IV2, while the ON resistance of MOS transistor 39 is the output of inverter IV2. When the impedance is smaller than the impedance, nodes ND6 and ND10 have their voltage levels lowered according to boosted signal BS via MOS transistor 39, and this voltage drop is amplified by buffer / transfer circuit BF. The voltage drops to the ground voltage VSS level.

  At time t6, the voltage levels of nodes ND6, ND7, and ND10 are stabilized according to the change in boost signal BS.

  When the latch signal SL rises to H level at time t7, the MOS transistor 5 is turned on, the L level input signal IN is transmitted to the node ND7, and the node ND7 becomes the low level voltage VIL (= VSS) level. . As the voltage level of node ND7 decreases, MOS transistor 39 is turned off. On the other hand, MOS transistor 10 is turned on in accordance with latch signal SL, and nodes ND6 and ND10 are driven to the level of ground voltage VSS similarly to time t0.

  When latch signal SL falls to L level at time t8, internal node ND7 becomes L level in a high impedance state. At this time, the MOS transistor 10 is also turned off. Nodes ND6 and ND10 are maintained at the level of ground voltage VSS by inverter IV2 of buffer / transfer circuit BF.

  At time t9, boost signal BS rises to H level. At this time, the internal node ND7 is at the ground voltage level, and no channel is formed in the MOS transistor 39. Therefore, the self-bootstrap action of the MOS transistor 39 is small, and the potential of the node ND7 is equal to that of the nodes ND3 and ND7. The voltage ΔVL rises due to the capacitive coupling of the parasitic capacitance between them (the drain-gate capacitance of the MOS transistor 39). This voltage ΔVL is lower than the threshold voltage of MOS transistor 39, MOS transistor 39 is kept off, and nodes ND6 and ND10 are maintained at L level (voltage VSS level) by buffer / transfer circuit BF. The

  In the configuration of the level conversion circuit shown in FIG. 16, even if the output node ND6 and the latch input node ND10 of the buffer / transfer circuit BF are short-circuited by the wiring 50, the so-called half latch circuit configuration can be used accurately as a latch circuit. Then, level conversion of the H level voltage VHI of the input signal IN can be performed to generate a signal at the voltage VDD level at the output node ND6.

  Note that the output signal of the inverter (inversion buffer circuit) IV1 of the buffer / transfer circuit BF may be used as a level conversion signal. In that case, a level conversion signal in which the logic of the input signal IN is inverted is generated.

  In the level conversion circuit shown in FIG. 16, wiring 50 is used and nodes ND6 and ND10 are always connected. Therefore, the switching transistor (7) for connecting / cutting off the nodes ND6 and ND10, the circuit for generating the operation control signal (holding signal HD) and the holding signal transmission line are not required, and the layout area of the level conversion circuit and its surroundings are eliminated. The layout area of the circuit can be reduced, and it is not necessary to generate the holding signal HD, so that current consumption is reduced.

  As described above, according to the seventh embodiment of the present invention, the latch input node and the output node are short-circuited, and the boost signal is transmitted to the latch input node using the MOS transistor self-bootstrap circuit according to the input signal. Therefore, a level conversion circuit with a small occupation area and low power consumption can be realized.

[Embodiment 8]
FIG. 18 shows a structure of the level conversion circuit according to the eighth embodiment of the present invention. The configuration of the level conversion circuit shown in FIG. 18 is different from the configuration of the level conversion circuit shown in FIG. 16 in the following points. In other words, N channel MOS transistor 55 is provided between internal node ND7 and nodes ND10 and ND6 to electrically connect internal node ND7 and nodes ND10 and ND6 in accordance with boosted signal BS. The other configuration of the level conversion circuit shown in FIG. 18 is the same as the configuration of the level conversion circuit shown in FIG. 16, and the corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  In an image display device or the like, the drive period of a pixel is one field period or a frame period, for example, 16 ms (one field period), depending on the drive method, and the H level period of the boost signal BS is relatively long. long. The operation when the H level period of the boost signal BS is relatively long will be described with reference to FIG. The voltage relationship between the input signal IN and the output signal after level conversion is the same as that of the timing diagram shown in FIG.

  Prior to time t0, the input signal IN is at the H level voltage VIH. Nodes ND6 and ND10 attain an H level or an L level according to the voltage level in the previous cycle.

  At time t0, latch signal SL rises to H level, and MOS transistor ND4 is turned on. Accordingly, input signal IN is transmitted to internal node ND7, and node ND7 attains voltage VIH level. Since MOS transistor 10 is turned on or boosted signal BS is at L level, nodes ND10 and ND6 are set to L level. Since boosted signal BS is at the L level, MOS transistor 55 is in the off state, and node ND7 is reliably maintained at voltage VIH level.

  At time t1, the latch signal SL becomes L level, and the MOS transistor 5 is turned off. In response, node ND7 is maintained at the H level in the high impedance state. MOS transistor 10 is turned off, and nodes ND6 and ND10 are maintained at the L level by buffer / transfer circuit BF.

  At time t2, boost signal BS rises from ground voltage VSS to power supply voltage VDD level. Due to the rise of boosted signal BS, the voltage level of node ND7 rises through the self bootstrap action of MOS transistor 39, and accordingly, the voltage level of node ND10 rises according to boosted signal BS. At this time, the voltage levels of nodes ND6 and ND10 rise to the H level (voltage VDD level) at substantially the same speed as boosted signal BS. On the other hand, internal node ND7 is driven to a voltage level higher than voltage VDD. Therefore, in MOS transistor 55, the gate (node ND3) and source (node ND10) potentials rise while maintaining substantially the same potential, so that the off state is maintained, and internal node ND7 is at voltage VIH + ΔVH level. Will definitely rise up.

  At time t3, voltage levels of nodes ND7, ND6, and ND10 are stabilized at voltages VIH + ΔVH and VDD, respectively.

  Since the operation from time t4 to time t8 is the same as the operation shown in the timing chart of FIG. 17, the description thereof is omitted.

  When the boost signal BS rises to the voltage VDD level at time t9, the voltage level of the node ND7 tends to rise due to capacitive coupling via the gate-drain parasitic capacitance of the MOS transistor 39. At this time, the MOS transistor 55 is turned on by the rise of the boost signal BS. The nodes ND6 and ND10 are maintained at the ground voltage VSS level with low impedance by the buffer / transfer circuit BF, and the voltage level of the internal node ND7 in the high impedance state is buffer / transfer as shown by a solid line in FIG. It is maintained at the ground voltage level by inverter IV2 of circuit BF. Therefore, MOS transistor 39 is surely maintained in the off state, prevents boosted signal BS from being transmitted to nodes ND6 and ND10, and avoids problems of current consumption and malfunction as described later.

  At time t10, the voltage level of internal node ND7 is stabilized at a predetermined voltage level.

  At time t11, the input signal IN rises from the L level VIL to the high level voltage VIH. Latch signal SL applied to the gate of MOS transistor 5 via node ND4 is maintained at L level voltage VIL level. In this case, the gate voltage of the MOS transistor 5 is the ground voltage VSS level, and the subthreshold current (off-leakage current) flows through the MOS transistor 5 in accordance with the H level input signal IN. However, since MOS transistor 55 is in the on state, the subthreshold current flowing into internal node ND7 is discharged to the ground node via discharge N-channel MOS transistor (NQ) included in inverter IV2, and internal node ND7. The rise of the voltage level is suppressed, and the MOS transistor 39 reliably maintains the off state.

  FIG. 19 shows a state where the voltage level of node ND7 is maintained at the ground voltage level. However, the voltage level of internal node ND7 may be set to a voltage level higher than the ground voltage by the combined resistance of the ON resistance of MOS transistor 55 and the ON resistance of the discharging N-channel MOS transistor of inverter IV2. Even in this case, the MOS transistor 39 has a gate-source voltage sufficiently lower than the threshold voltage, and is reliably maintained in the off state. Even if a subthreshold current flows through MOS transistor 39, inverter IV2 discharges to the ground voltage level, and nodes ND6 and ND10 are maintained at the ground voltage level.

  When this MOS transistor 55 is not provided, the voltage level of the node ND7 rises due to the subthreshold current flowing through the MOS transistor 5, as shown by the dashed line in FIG. Is turned on. When MOS transistor 39 is turned on by the potential rise of node ND7 due to the subthreshold current from MOS transistor 5, from the circuit driving boost signal BS applied to node ND3, the inverter IV2 of buffer / transfer circuit BF A current flows to the ground node via the discharging MOS transistor, and the voltages of nodes ND6 and ND10 are maintained at the L level, but current is unnecessarily consumed and current consumption increases. By providing the MOS transistor 55, the potential rise of the internal node ND7 is prevented, and the MOS transistor 39 is reliably maintained in the OFF state, thereby preventing unnecessary current consumption. When the MOS transistor 55 is not provided, the voltage level of the internal node ND7 increases due to the subthreshold current (off-leakage current) from the MOS transistor 5 for the following reason.

  FIG. 20 schematically shows a cross-sectional structure when MOS transistor 5 has a bulk type transistor structure. 20, MOS transistor 5 includes a p-type semiconductor substrate region 60, n-type impurity regions 61a and 61b formed on the surface of p-type semiconductor substrate region 60, and impurity regions 61a and 61b. And a gate electrode 62 formed through a gate insulating film (not shown) on the surface of the substrate region therebetween.

  Impurity regions 61a and 61b are connected to input node ND5 and internal node ND7, respectively, and gate 62 is connected to node ND4. In the bulk transistor structure, when the latch signal SL of the node ND4 is at L level, the subthreshold current Il flows from the impurity region 61a to the impurity region 61b. Due to the current component Ila of the subthreshold current Il, the voltage level of the internal node ND7 in the high impedance state rises. Accordingly, in MOS transistor 5, the gate (gate electrode 62) and the source (impurity region 61b) are set in the reverse bias state, the deeper off state is set, the subthreshold current Il is reduced, and the voltage level of node ND7 is reduced. The rise of is suppressed. Further, a PN junction exists between the n-type impurity region 61b and the p-type semiconductor substrate region 62, and the subthreshold current Il is discharged by the PN junction reverse leakage current Ilb (normally, the p-type semiconductor substrate region is Maintained at ground voltage level). Therefore, an increase in the voltage level of internal node ND7 is suppressed by this PN junction leakage current, and when a bulk transistor is used, an increase in potential due to the subthreshold current of internal node ND7 is not particularly problematic.

  On the other hand, when this level conversion circuit is used in an image display device, MOS transistors 5, 39 and 55 are formed by TFTs such as low-temperature polysilicon TFTs (thin film transistors). A TFT has source and drain impurity regions formed on an insulating substrate, as schematically shown in FIG.

  That is, in FIG. 21, a MOS transistor 5 having a TFT structure includes impurity regions 66a and 66b formed on an insulating substrate 65 made of, for example, a glass substrate, and between these impurity regions 66a and 66b. A gate electrode 67 is formed on the surface of this region via a gate insulating film (not shown). Impurity regions 66a and 66b are formed by implanting impurities into polysilicon layer 68.

  Impurity regions 66a and 66b are connected to nodes ND5 and ND7, respectively, and gate electrode 67 is connected to node ND4.

  In the structure of MOS transistor 5 shown in FIG. 21, when input signal IN is at H level and latch signal SL is at L level, subthreshold current Il flows through substrate region 66c between impurity regions 66a and 66b. . Due to the subthreshold current Il, the voltage level of the node ND7 rises, the gate-source of the MOS transistor is brought into a reverse bias state, and the subthreshold current Il is suppressed. However, there is no PN junction between the insulating substrate 65 and the impurity region 66b, and no junction leakage current flows. Therefore, in MOS transistor 5, even if the gate-source is in a reverse bias state, a minute subthreshold current Il continues to flow and the voltage level of node ND7 continues to rise. Therefore, when the transistor of the level conversion circuit is formed of a TFT, a problem that the potential of the node in the high impedance state rises due to the subthreshold current is more likely to occur than when a bulk transistor is used.

  Although a top gate type TFT in which the gate electrode is formed in an upper layer than the polysilicon layer as a TFT structure is shown in FIG. 21, the gate electrode is formed on an insulating substrate, and the gate electrode is interposed through the gate insulating film. Even in a bottom gate TFT structure in which a polysilicon layer is formed as an upper layer, the polysilicon layer constituting the source / drain region is formed between the gate insulating film and the interlayer insulating film, and similarly, in the source / drain region. On the other hand, there is no path through which the PN junction leakage current flows, and the problem of voltage increase due to the leakage current occurs.

  As a countermeasure, even when the MOS transistor 55 shown in FIG. 18 is provided and the level conversion circuit is configured using TFTs, the potential of the internal node ND7 is reliably maintained at the L level, and the boost signal transfer MOS is provided. The malfunction of the transistor 39 is prevented and current consumption is reduced.

[Example of change]
FIG. 22 shows a structure of a modification of the eighth embodiment of the present invention. The level conversion circuit shown in FIG. 22 differs from the configuration of the level conversion circuit shown in FIG. 10 in the following points. That is, N channel MOS transistor 70 receiving latch signal BS at its gate is provided between nodes ND10 and ND7. The other configuration of the level conversion circuit shown in FIG. 22 is the same as the configuration of the level conversion circuit shown in FIG. 10, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  Also in the configuration of the level conversion circuit shown in FIG. 22, when the H level period of the boost signal BS is long, when the input signal IN is at the H level and the latch signal SL is at the L level, An increase in the voltage level of the node ND7 due to the threshold current is suppressed. In particular, when the MOS capacitor 6 is provided, when the voltage level of the node ND10 rises according to the boost signal BS due to the potential rise of the node ND7, the capacitive coupling (charge pump) by the MOS capacitor element 6 causes the internal node ND7 to There is a possibility that the voltage level is further increased and the current consumption is further increased. Therefore, MOS transistor 70 is provided, and when the latch signal BS is at the H level, the rise in the voltage level of the internal node ND7 is suppressed and the MOS transistor 9 is reliably maintained in the OFF state. Thereby, the problem of current consumption due to the subthreshold current can be avoided.

  Also in the level conversion circuit shown in FIG. 22, when the potential of node ND10 / ND6 rises according to boosted signal BS, the gate and source of MOS transistor 70 (nodes ND10 and ND6) rise at the same potential, so that MOS transistor 70 The off state is maintained and the potential rise of node ND7 is not affected, and node ND7 is surely boosted to the high voltage level by the self bootstrap action of MOS transistor 9 and the charge pump of MOS capacitor element 6. The

  Note that the configuration in which MOS transistor 70 receiving latch signal BS at the gate is provided between latch input node ND10 and internal node ND7 is different from the configuration of the level conversion circuit shown in FIGS. 6, 11 and 12. Can be applied.

  As described above, according to the eighth embodiment of the present invention, when the internal node is at the L level, even if the latch signal BS is at the H level, the latch is surely maintained at the L level. A transistor element is provided between the input node and the internal node, and the potential increase of the internal node due to the subthreshold current when the input signal changes can be suppressed, and accordingly, current can be prevented from flowing to the latch input node. Current consumption can be reduced.

[Embodiment 9]
FIG. 23 shows a structure of a level conversion circuit according to the ninth embodiment of the present invention. The level conversion circuit shown in FIG. 23 differs from the level conversion circuit shown in FIG. 16 in the following points. That is, an N-channel MOS transistor 75 receiving the power supply voltage VDD via the high-side power supply node NDH is provided between the MOS transistor 5 for transferring the input signal IN according to the latch signal SL and the internal node ND7. The other configuration of the level conversion circuit shown in FIG. 23 is the same as the configuration of the level conversion circuit shown in FIG. 16, and the corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  As shown in the timing chart of FIG. 17, when boosted signal BS rises to the H level (voltage VDD level) at time t2, the voltage level of internal node ND7 becomes the voltage level of voltage VIH + ΔVH. In the case where a TFT (thin film transistor) is used as the MOS transistor, when a high voltage (voltage VDD or higher) is applied between the drain and gate in the off state, charges are accumulated in the substrate region 66c shown in FIG. A phenomenon (body effect) is known in which the value voltage increases equivalently and the on-state current of the transistor gradually decreases. As described above, when the on-current is decreased, the drive current is decreased, and the transmission of the signal to the output node ND6 is delayed according to the input signal IN. When the pixel writing voltage is generated in accordance with the output signal of the level conversion circuit in the application of the image display device, it takes a long time to generate the pixel writing voltage, and the writing speed of the pixel data becomes slow.

  In the configuration shown in FIG. 23, MOS transistor 75 receives voltage VDD at its gate, and is on when transmitting input signal IN to internal node ND7 in accordance with latch signal SL. The H level of the input signal IN is a voltage level lower than the power supply voltage VDD (the latch signal SL is the same voltage level as the voltage VDD), and the H level voltage VIH of the input signal IN is transmitted to the node ND7 without voltage loss. Is done. In this case, the drain-gate voltage VDG (75) of the MOS transistor 75 is expressed by the following equation (3).

VDG (75) = VIH + ΔVH−VDD (3)
Assuming that this voltage increase ΔVH becomes the maximum power supply voltage VDD, the relationship represented by the following equation (4) is established.

VDD (75) = VIH + VDD−VDD = VIH <VDD (4)
Therefore, the drain-gate voltage of the MOS transistor 75 is smaller than the power supply voltage VDD, and the problem that the previous on-current gradually decreases can be avoided. Further, when the voltage of the internal node ND7 rises, the source node of the MOS transistor 75 is the node ND70, and the voltage level of the node ND70 is the voltage VDD−VTN. Here, VTN represents the threshold voltage of the MOS transistor 75. Therefore, in the MOS transistor 5 as well, the MOS transistor 75 functions as a decoupling transistor that prevents high voltage transmission, the drain-gate voltage is the maximum VDD-VTN, and the drain-gate voltage is equal to or lower than the voltage VDD. In the MOS transistor 5 as well, the problem of a decrease in on-current can be avoided.

[Example of change]
FIG. 24 shows a structure of a modification of the level conversion circuit according to the ninth embodiment of the present invention. The level conversion circuit shown in FIG. 24 differs from the level conversion circuit shown in FIG. 1 in the following points. That is, an N-channel MOS transistor 77 receiving the power supply voltage VDD via the high-side power supply node NDH is provided between the internal node ND7 and the MOS transistor 5 at its gate. The other configuration of the level conversion circuit shown in FIG. 24 is the same as the configuration of the level conversion circuit shown in FIG. 1, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  Also in the configuration of the level conversion circuit shown in FIG. 20, the internal node ND7 rises from the power supply voltage VDD by the voltage ΔVH shown by the equation (1) by the boosting operation of the MOS capacitor 6. The voltage level of the internal node ND7 is, for example, 1.5 · VDD level as shown as an example in the previous equation (2). Therefore, the drain-gate voltage in the MOS transistor 77 is lower than the voltage VDD, and the above-described problem of reduction in on-current can be avoided in the MOS transistor 77. Similarly, for MOS transistor 5, MOS transistor 77 has a drain voltage lower than the gate voltage and functions as a decoupled transistor, and applies voltage VDD-VTN to its source node (a node between MOS transistors 77 and 5). Just communicate. Therefore, also in the MOS transistor 5, only the maximum voltage VDD-VTN is applied between the drain and the gate, and the problem of a decrease in on-current can be avoided.

  Further, the high voltage transmission preventing transistor (decoupled transistor) for preventing the high voltage from being applied to the MOS transistor 5 on the input side is shown in FIG. 6, FIG. 10, FIG. 11, FIG. 12, and FIG. The same applies to the structure shown. By placing a decoupled transistor between the boosting node where the internal voltage level is boosted and the MOS transistor in the input section, and setting the gate voltage to the power supply voltage level, for example, the problem of reduced on-current can be avoided. Therefore, it is possible to prevent the operation speed of the level conversion circuit from being lowered. In particular, when applied to an image display device, it is possible to prevent the writing of pixel data from slowing down and to realize high-speed pixel writing.

  The voltage applied to the gates of the decouple transistors 75 and 77 is not the power supply voltage VDD, and when the input signal IN is transmitted to the internal node ND7, the input signal IN does not cause a voltage loss, and the internal voltage is not lost. Any voltage level that can transmit the input signal IN to the node ND7 may be used. That is, the voltage Vdcp satisfying the relationship of the following equation (5) may be applied to the gate node of the decoupled transistor 75 or 77.

VIH + VTN <Vdcp, VDD + VTN> Vdcp, and VIH + ΔVH−VDD <Vdcp (5)
The first relational expression is required to transmit the input signal IN to the internal node ND7 without causing a voltage loss, and the second relational expression applies a voltage equal to or lower than the voltage VDD to the drain of the input transistor 5. The third relational expression required for acting as a transmitting decoupled transistor is a relation required for the difference between the drain (internal node 7) of the decoupled transistor and the gate voltage Vdcp to be equal to or lower than the power supply voltage VDD.

  As described above, according to the ninth embodiment of the present invention, the decoupling transistor that suppresses application of a high voltage between the drain and gate is provided between the internal boosting node and the input MOS transistor. A decrease in current can be suppressed, and high-speed level conversion can be realized.

[Embodiment 10]
FIG. 25 schematically shows a whole structure of the display device according to the tenth embodiment of the invention. In FIG. 25, a configuration of a liquid crystal display device 100 in which a liquid crystal element is used as a pixel element is shown as an example of the display device. As this pixel element, an organic EL element may be used.

  In FIG. 25, the liquid crystal display device 100 includes a pixel matrix 120 including a plurality of pixels 125 arranged in a matrix, and gate lines GL (GL1,...) Provided corresponding to the respective rows of the pixels of the pixel matrix 120. A gate line driving circuit 130 for driving, and a data line driving circuit 140 for transmitting display pixel data signals to data lines DL (DL1, DL2,...) Provided corresponding to the pixel columns of the pixel matrix 120, respectively.

  In the pixel matrix 120, the data lines DL are arranged corresponding to the respective pixel columns, and the gate lines GL are arranged corresponding to the respective pixel rows. However, in FIG. 25, the data lines DL1 and DL2 are representatively shown. And the gate line GL1.

  In the following description, the symbol GL is used when the gate lines are generically shown, and the symbol DL is used when the data lines are generically shown.

  The pixel 125 is provided between the corresponding data line DL and the internal pixel node NX1, and is common to the pixel node NX1 and the pixel selection switch 126 that is turned on in response to the signal potential on the corresponding gate line GL. A capacitive element 127 and a liquid crystal display element 128 are provided in parallel between the electrode nodes NX2.

  The orientation of the liquid crystal in the liquid crystal display element 128 changes according to the voltage difference between the pixel node NX1 and the common electrode node NX2, and the display brightness of the liquid crystal display element 128 changes accordingly. The display pixel data signal is transferred via the data line DL, and the display pixel data signal is transmitted to the pixel node NX1 via the pixel selection switch 126. Thereby, the luminance of the pixel 125 can be controlled. The pixel selection switch 126 is typically composed of an N-type polysilicon TFT. In addition, the capacitor 127 holds the written display pixel data signal and holds the display state (luminance) of the display element 128.

  The gate line driving circuit 130 sequentially drives the gate lines GL1,... To a selected state based on a predetermined scanning cycle. During the period when the gate line GL is selected, the data line DL is connected to the pixel node NX1 of the corresponding pixel 125, and the display pixel data signal (grayscale voltage) output on the data line DL by the data line driving circuit 140. Is written to the pixel connected to the selected gate line and held by the capacitor 127.

  The data line driving circuit 140 outputs a display pixel data signal, which is set in a stepwise manner, to the data line DL based on the display pixel data signal SIG of an N-bit digital signal. In FIG. 16, as an example, a case where a display pixel data signal SIG given from the outside is configured by 6 bits D0 to D5 is shown as an example. As a display specification in the display device, a full color display and a display of 260,000 colors are generally used. In this case, it is necessary to perform gradation display in 64 steps for each of the three primary colors of red (R), green (G), and blue (B). Therefore, 6-bit pixel data is required for each primary color. Is done. Therefore, the display pixel data signal SIG composed of 6 bits D0 to D5 is transmitted for each of the three primary colors R, G, and B (SIGx3).

  Each bit D (D0-D5) of the display pixel data signal SIG corresponds to the input signal IN of the first to ninth embodiments, and is supplied from the external driving LSI, and the signal amplitude of each bit is small.

  The data line driving circuit 140 generates data line selection signals SH1, SH2,... According to a shift clock signal (not shown), and inputs according to the data line selection signals SH (SH1, SH2,...) From the shift register circuit 150. The level conversion unit 152 that takes in the display pixel data signal SIG and converts the level of the pixel data signal, the first data latch unit 154 that latches the output signal of the level conversion unit 152, and the first data latch unit 154 The second data latch unit 156 that latches the latch signal in accordance with the latch instruction signal LT, and selects one of the gradation voltages V1 to V64 based on the display pixel data signal output from the second data latch unit 156 DAC (digital / analog converter) 160 for generating gradation voltage, and this And an output buffer circuit 180 for driving the data line DL in accordance with the output signal of AC160.

  The input display pixel data signal SIG is serially input in a predetermined cycle for each pixel unit (data line unit) as pixel data corresponding to a display signal transmitted to each data line DL. The shift register circuit 150 sequentially switches the data line selection signals SH (SH1, SH2,...) To the selected state in synchronization with the cycle in which the display pixel data signal SIG is applied.

  Level conversion unit 152 includes a level conversion unit provided for each data line DL, and the level conversion unit provided for the data line specified by data line selection signal SH from shift register circuit 150 is activated, Level conversion is performed on the input display pixel data signal SIG. In level conversion unit 152, a control unit for generating latch signal SL and boost signal BS based on data line selection signal SH is arranged.

  The first data latch unit 154 holds the signal level-converted by the level conversion unit 152 in accordance with a holding signal generated based on the data line selection signal SH from the shift register circuit 150.

  When the first data latch unit 154 completes the latch of the display pixel data signal for the pixels in one row, the second data latch unit 156 latches the latch signal of the first data latch unit 154 according to the latch instruction signal LT.

  The DAC 160 includes a gradation voltage supply circuit 60 that supplies gradation voltages V 1 to V 64, and a decode circuit 170 that selects a gradation voltage for each pixel according to the pixel data signal subjected to level conversion from the second data latch unit 156. . As an example, the gradation voltage supply circuit 160 includes a voltage dividing resistor connected in series between the high voltage VDH and the low voltage VDL. The high voltage VDH and the low voltage VDL are divided into resistors and divided into 64 stages. The gradation voltages V1-V64 are generated.

  The decode circuit 170 decodes a 6-bit signal for each data line DL latched by the second data latch unit 156, and based on the result of the decoding, from the gradation voltages V1-V64 from the gradation voltage supply circuit 160. Are selected and output (for one color).

  The decode circuit 170 generates a display signal for each data line, and then transmits the generated display signal to the corresponding data line DL via the output buffer circuit 180. As a method for transmitting a display signal from the output buffer circuit 180 to the data line DL, a line sequential driving method in which display signals for pixels in one row are output in parallel may be used. A dot sequential method (dot sequential method) in which sequential display signals are transmitted may be used. The output buffer circuit 180 is an analog circuit, receives the gradation voltage from the decoding circuit 170, drives the corresponding data line DL, and writes a display signal (gradation voltage) for the selected pixel.

  Note that the DAC 160 shown in FIG. 25 may simply be configured by a digital / analog converter that directly converts a 6-bit display pixel data signal for each pixel provided from the second data latch unit 156 into an analog signal.

  FIG. 26 shows a specific configuration of level conversion unit 152, first data latch unit 154, and second data latch unit 156 shown in FIG. FIG. 26 representatively shows the configuration of a portion that performs level conversion of a 1-bit pixel signal for two columns of data lines.

  In FIG. 26, a shift register circuit 150 is provided for each of the data lines, and sequentially shifts the pixel data input start instruction signal START according to the shift clock signals C and / C to generate the data line selection signal SH. , SR1. The shift clock signals C and / C are two-phase complementary clock signals, and the shift register SR (SR0, SR1...) Divides these shift clock signals C and / C by two to obtain a data line selection signal. SH (SH0, SH1) is generated.

  Level conversion unit 152 includes level conversion units SF (SF0, SF1) provided for the respective data lines. In FIG. 26, reference numerals are assigned in detail to the components of level conversion unit SF0 provided for data line DL0. Level conversion unit SF0 selectively performs boost operation on internal node ND7 according to boost signal BS0 and N channel MOS transistor 5 for transferring display pixel data signal IN applied via input node ND5 to internal node ND7 according to latch signal SL0. Includes a MOS capacitor 6. The configuration of level conversion unit SF is the same as the configuration of the level conversion unit of the level conversion circuit according to the first embodiment shown in FIG. However, any of the level conversion circuits of the second to ninth embodiments may be used in this level conversion unit SF.

  MOS transistor 5 and MOS capacitor 6 perform level conversion of a 1-bit signal for one color for the corresponding data line. This level conversion unit SF is arranged for each data bit of the three primary colors R, G, and B. The same applies to the configuration of each part of the first data latch unit 154 and the second data latch unit 156.

  First data latch unit 154 includes first latches FLT (FLT0, FTL1,...) Provided corresponding to the data lines. In FIG. 26, reference numerals are assigned to the components of the first latch FLT0. First latch FLT0 includes inverters IV1 and IV2 connected in series between internal node ND7 and internal output node ND6 of level conversion unit SF0, and N-channel MOS for electrically connecting nodes ND6 and ND7 in accordance with holding signal HD0 A transistor 7 is included.

  Second data latch unit 156 is provided corresponding to each of first latches FLT (FLT0, FLT1,...), And takes a latch / output signal of corresponding first latch FLT according to latch instruction signal LT, and second latch SLT ( SLT0, SLT1). This second latch SLT (SLT0, SLT1) takes in and latches the pixel data signal after the level conversion of the corresponding first latch FLT in accordance with the latch instruction signal LT after the level conversion of the data signal for one row of pixels is completed.

  In order to control the operations of the level conversion unit 152 and the first data latch unit 154 in units of data lines, control units CTL (CTL0, CTL1) are provided corresponding to the data lines. In FIG. 26, reference numerals are assigned to the components of the control unit CTL0. Control unit CTL0 receives data line selection signal SH1 for the data line in the adjacent column and data line selection signal SH0 for the corresponding data line and generates latch signal SL0, and data line selection signals SH1 and SH0. It includes a NOR gate circuit G2 that receives the boost signal BS0 and a level conversion delay circuit DG that delays the output signal of the NOR gate circuit G2 for a predetermined time and converts the H level to a boosted voltage level.

  The shift register SR (SR0, SR1) divides the shift clock signals C and / C by two, and by using these gate circuits G1 and G2, a half cycle period of the shift clock signals C and / C, Latch signal SL and boost signal BS can be activated.

  FIG. 27 is a signal waveform diagram representing an operation of the circuit shown in FIG. The operation of the circuit shown in FIG. 26 will be described below with reference to FIG.

  At time t0, the pixel data input start instruction signal START becomes H level, which specifies that an effective pixel data signal for one row of pixels is input. The pixel data input start instruction signal START is generated based on, for example, a horizontal synchronization clock signal that defines a cycle for driving the gate lines of the pixel matrix.

  When the shift clock signal C becomes H level and the complementary shift clock signal / C becomes L level at time t1, the output data line selection signal SH0 is driven to H level by the shift operation of the shift register SR0. In response to the rise of the data line selection signal SH0, the boost signal BS0 output from the NOR gate circuit G2 becomes L level, and after a predetermined time elapses, the hold signal HD0 from the level conversion delay circuit DG becomes L level. However, the pixel data signal is invalid during this period, and the valid pixel data signal is not latched in the first latch FLT.

  When the shift clock signal C becomes L level and the complementary shift clock signal / C becomes H level at time t2, the shift register SR1 performs a shift operation, and the output data line selection signal SH1 is set to H in accordance with the data line selection signal SH0. Drive to level. Accordingly, also in the control unit CTL1, the boost signal BS1 becomes L level and the holding signal HD1 becomes L level.

  At time t3, the pixel data input start instruction signal START becomes L level, and the first valid pixel data signal IN0 is supplied accordingly. The input signal IN is sampled at every change of the shift clock signal C. Therefore, the pixel from the driving LSI is synchronized with the rising and falling edges of the clock signal in accordance with the clock signal that is 90 ° out of phase with the shift clock signal C. A data signal IN is supplied.

  In accordance with activation of data line selection signal SH1 at time t2, latch signal SL0 output from AND gate circuit G1 at control unit CTR0 attains H level, MOS transistor 5 is turned on, and input signal IN is transmitted to internal node ND7. The When the valid input pixel data signal IN0 is determined, the transfer clock signal C becomes H level and the complementary shift clock signal / C becomes L level. Accordingly, the data line selection signal SH0 is changed to L level by the shift operation of the shift register SR0. It becomes. Accordingly, the latch signal SL0 from the AND gate circuit G1 becomes L level, and the sampling of the first input signal IN0 is completed and latched.

  When data line selection signal SL0 attains L level, data line selection signal SH2 rises to H level in synchronization with the rise of shift clock signal C at time t4, and accordingly, latch signal SL1 attains H level in control unit CTL1. The input signal IN is captured (sampling), and the effective pixel data signal IN1 is captured and latched.

  In synchronization with the fall of the shift clock signal C at time t5, the shift operation of the shift register SR1 of the L-level data line selection signal SH0 causes the output data line selection signal SH1 to become L level, and accordingly the latch signal SL1. Becomes L level.

  On the other hand, when data line selection signals SH0 and SH1 both attain an L level, boosting signal BS0 output from NOR gate circuit G2 at control unit CTR0 attains an H level, and a selective boosting operation is performed by MOS capacitor 6 to input data. Boosting operation of the voltage level of signal IN0 at H level is performed.

  After the elapse of a predetermined period after the boost signal BS0 rises to the H level, the holding signal HD0 output from the level conversion delay circuit DG becomes the H level, and the level-converted signal is held by the first latch FLT0.

  When the shift clock signal C becomes H level at time t6, the data line selection signal SH2 becomes L level. Accordingly, in the control unit CTL1, the boost signal BS1 becomes H level and a selective boosting operation is performed. The later signal is latched in the first latch FLT1.

  At every half cycle of the shift clock signal C, the data line selection signals SH0, SH1, SH2 are sequentially set to the H level for one cycle period of the shift clock signal C, and after the activation of the data line selection signal for the adjacent column is completed, the MOS capacitor 6 The step-up operation is performed, and the step-up operation is sequentially executed for each column in the half cycle period of the shift clock signal C.

  Boost signal BS (BS0, BS1) and hold signal HD (HD0, HD1) are deactivated in the cycle before the pixel data input is taken in to the corresponding data line, and the pixel data signal for the corresponding data line is It is inactive during the period during which input is input and level conversion is performed. When the capture of the data signal in the adjacent column is completed, the captured pixel data signal is boosted and held. Therefore, the boost signal BS and the holding signal HD are maintained in the active state of the writing period H level for the pixels in one row, and the first latch FLT (FLT0, FLT1) is level-converted for one horizontal scanning period, respectively. Hold the pixel data signal.

  When the level conversion of the pixel data signal for the last row by the level conversion unit SFn and the latch operation by the first latch FLTn are completed, the latch instruction signal LT is activated, and the pixel data signal for the pixel of one row is the second data latch unit 156. The second latch SLT (SLT0 to SLTn) (not shown) is latched.

  When the latch instruction signal LT is deactivated, the second latch SLT (SLT0 to SLTn) is in a latched state. The DAC 160 generates display signals PX0, PX1,... PXn for the respective data lines based on the pixel data signals latched by the second latches SLT (SLT0 to SLTn) provided for the respective data lines.

  The data line selection signals SH0, SH1, SH2,... May be signals having a phase difference of one cycle period of the transfer cycle of the input signal IN, and the shift registers SR (SR0, SR1) inside the shift register circuit 150 are sufficient. It may be generated in a different manner from the generation by.

  As the second latch SLT (SLT0, SLT1), a configuration in which a given signal is taken in when the latch instruction signal LT is activated and is in a latch state when the latch instruction signal LT is inactive is used. The input stage is provided with a clocked buffer that operates when the latch instruction signal LT is activated and becomes an output high-impedance state when the latch instruction signal LT is inactive. The output of the clocked inverter is output to the inverter latch of the next stage. A circuit configuration for transferring a signal may be used.

  The present invention can also be applied to a display device in which an EL element is used as the display pixel element.

  In the above description, the output signals of the second latches SLT0, SLT1,... Of the second data latch unit 156 are transmitted in parallel to the DAC 160 of the display device. However, the present invention can be generally applied to a serial / parallel conversion circuit that performs level conversion of an input signal IN input serially and outputs the signal in parallel.

  As described above, according to the tenth embodiment of the present invention, the level conversion and latch circuit is provided for each data unit of the serially input signal, and the data signal is fetched according to the shift clock signal. Level conversion and latching are performed, and a circuit that performs level conversion and serial / parallel conversion at a high speed with a small occupation area can be realized.

  In general, the present invention can be applied to a circuit portion that converts a serial input signal of a display device into a parallel signal by performing level conversion and transfers the parallel signal to a DAC (digital / analog converter). Further, the present invention is not limited to this, and the level conversion circuit of the present invention can generally be applied to an interface unit that performs level conversion of a signal to be transferred in circuit portions having different power supply voltages.

It is a figure which shows the structure of the level conversion circuit according to Embodiment 1 of this invention. It is a figure which shows an example of a structure of the inverter shown in FIG. FIG. 2 is a signal waveform diagram showing an operation of the level conversion circuit shown in FIG. 1. It is a figure which shows the example of a change of the inverter shown in FIG. It is a figure which shows the 2nd modification of the inverter shown in FIG. It is a figure which shows the structure of the level conversion circuit according to Embodiment 2 of this invention. FIG. 7 is a signal waveform diagram showing an operation of the level conversion circuit shown in FIG. 6. FIG. 7 is a diagram schematically showing an example of a configuration of a portion that generates a control signal used in the level conversion circuit shown in FIGS. 1 and 6. It is a signal waveform diagram which shows the operation | movement of the control signal generation part shown in FIG. It is a figure which shows the structure of the level conversion circuit according to Embodiment 3 of this invention. It is a figure which shows the structure of the level conversion circuit according to Embodiment 4 of this invention. It is a figure which shows the structure of the level conversion circuit according to Embodiment 5 of this invention. FIG. 13 is a signal waveform diagram showing an operation of the level conversion circuit shown in FIG. 12. It is a figure which shows the structure of the level conversion circuit according to Embodiment 6 of this invention. FIG. 15 is a signal waveform diagram showing an operation of the level conversion circuit shown in FIG. 14. It is a figure which shows the structure of the level conversion circuit according to Embodiment 7 of this invention. FIG. 17 is a timing chart showing an operation of the level conversion circuit shown in FIG. 16. It is a figure which shows the structure of the level conversion circuit according to Embodiment 8 of this invention. FIG. 19 is a timing chart showing an operation of the level conversion circuit shown in FIG. 18. FIG. 19 is a diagram schematically showing a cross-sectional structure when the MOS transistor shown in FIG. 18 has a bulk type transistor structure. FIG. 19 is a diagram schematically showing a cross-sectional structure when the MOS transistor shown in FIG. 18 is a TFT. It is a figure which shows the structure of the level conversion circuit according to the modification of Embodiment 8 of this invention. It is a figure which shows the structure of the level conversion circuit according to Embodiment 9 of this invention. It is a figure which shows the structure of the level conversion circuit according to the modification of Embodiment 9 of this invention. It is a figure which shows roughly the structure of the display apparatus according to Embodiment 10 of this invention. It is a figure which shows the structure of the principal part of the display apparatus shown in FIG. FIG. 27 is a signal waveform diagram illustrating an operation of the configuration illustrated in FIG. 26.

Explanation of symbols

  5,7 MOS transistor, 6 MOS capacitor, IV1, IV2 inverter, 9,10 N channel MOS transistor, 41 P channel MOS transistor, 42 N channel MOS transistor, 50 wiring, 55, 70, 75, 77 MOS transistor, 150 shift Register circuit, 152 level conversion unit, 154 first data latch unit, 156 second data latch unit, 120 pixel matrix, 130 gate line drive circuit, 160 DAC, CTL0, CTL1 control unit, SF0, SF1 level conversion unit, SFT0, SFT1 first latch, SLT0, SLT1 second latch.

Claims (16)

A first transfer gate that transfers an input signal given to an input to an internal node in response to a latch signal; and a signal holding circuit that holds a logic state of the signal of the internal node, A level conversion circuit comprising a MOS type capacitive element coupled to the internal node and selectively boosting the voltage level of the internal node.   2. The level conversion circuit according to claim 1, wherein the MOS capacitance element includes a MOS capacitor having a first electrode coupled to the internal node and a second electrode receiving a boost signal. The signal holding circuit further includes:
A transfer transistor for selectively transferring a boost signal to a latch input node according to the voltage of the internal node;
The level conversion circuit according to claim 2, further comprising: a latch circuit that latches a signal of the latch input node according to a holding signal. The signal holding circuit is
A transfer transistor having a control electrode coupled to the internal node and selectively transmitting a boost signal to a latch input node according to a voltage of the internal node;
A latch circuit that holds the signal of the latch input node according to a holding signal;
2. The level conversion circuit according to claim 1, wherein the transfer transistor functions as the MOS-type capacitance element when the boost signal is applied and selectively boosts the voltage of the internal node by a self-bootstrap action. The signal holding circuit is
A transfer transistor having a control electrode coupled to the internal node and transmitting a boost signal to a latch input node;
A latch circuit that latches a signal of the latch input node according to a holding instruction signal;
The level conversion circuit according to claim 1, wherein the MOS capacitance element includes a MOS capacitor connected between the internal node and the latch input node. The signal holding circuit further includes:
6. The level conversion circuit according to claim 3, further comprising a precharge transistor that precharges the latch input node to a predetermined voltage level when the input signal is applied.   A precharge control circuit for forcibly turning on the precharge transistor upon application of the input signal and selectively holding the precharge transistor on in accordance with the voltage level of the latch input node after application of the input signal The level conversion circuit according to claim 6, further comprising: The first transfer gate includes a first conductivity type insulated gate field effect transistor,
The latch signal is set to a voltage level that prevents a loss corresponding to a threshold voltage of the insulated gate field effect transistor from occurring when the input signal is transferred to the internal node when activated. The level conversion circuit according to 1. The signal holding circuit is
2. The level conversion according to claim 1, further comprising: a latch circuit connected between a latch input node to which a boosted voltage is transmitted according to a boosted voltage of the internal node and an output node, and latching the voltage of the latch input node. circuit. The latch circuit includes an even number of cascaded inverting buffer circuits connected between the latch input node and the output node;
The level conversion circuit according to claim 9, further comprising a transmission gate that connects the latch input node and the output node according to a holding signal. The latch circuit is
An even number of cascaded inverting buffer circuits connected between the latch input node and the output node;
The level conversion circuit according to claim 9, further comprising a wiring that short-circuits the latch input node and the output node.   12. The level conversion circuit according to claim 10, wherein the inverting buffer circuit includes a clock-controlled inverting circuit whose own through current path is cut off when the input signal is applied. The signal holding circuit is
A second transfer gate for selectively transmitting a boost signal to the latch input node according to the voltage of the internal node;
The level conversion circuit according to claim 9, further comprising a transmission gate that selectively couples the latch input node and the internal node according to the boost signal.   The decoupling transistor is further connected between the first transfer gate and the internal node, and prevents a boosted voltage of the internal node from being transmitted to the first transfer gate. Level conversion circuit. The input signal includes a signal that is input serially and applied to a plurality of signal lines,
The first transfer gate is set to a conductive state based on a signal line designating signal designating the signal line,
The MOS capacitor includes a MOS capacitor having a first electrode connected to the internal node and a second electrode for receiving a signal generated based on the signal line designation signal. Level conversion circuit.   A digital / analog that receives the output signal of the signal holding circuit and latches the output signal of the signal holding circuit according to a latch instruction signal, and the output signal of the latch circuit drives the plurality of signal lines in parallel; The level conversion circuit according to claim 1, which is supplied to the conversion circuit.

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