JP4563253B2 - Liquid crystal display - Google Patents
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- JP4563253B2 JP4563253B2 JP2005154791A JP2005154791A JP4563253B2 JP 4563253 B2 JP4563253 B2 JP 4563253B2 JP 2005154791 A JP2005154791 A JP 2005154791A JP 2005154791 A JP2005154791 A JP 2005154791A JP 4563253 B2 JP4563253 B2 JP 4563253B2
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3622—Control of matrices with row and column drivers using a passive matrix
- G09G3/3629—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals
- G09G3/3637—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals with intermediate tones displayed by domain size control
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2203/00—Function characteristic
- G02F2203/30—Gray scale
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/02—Composition of display devices
- G09G2300/023—Display panel composed of stacked panels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/028—Improving the quality of display appearance by changing the viewing angle properties, e.g. widening the viewing angle, adapting the viewing angle to the view direction
Description
本発明は液晶表示装置（LCD）に関し、特に階調反転を改善できる液晶表示装置に関する。 The present invention relates to a liquid crystal display device (LCD), and more particularly to a liquid crystal display device that can improve gradation inversion.
従来のTN（Twisted Nematic）型LCD（以下TN-LCD）は下視野角方向に重大な階調反転現象が見られ、視野角特性が悪いという問題がある。図１は、操作モードがノーマリ・ホワイト(Normally White)方式である従来のTN-LCDの各下視野角角度における各階調の相対輝度差を示す。曲線１２は第１及び第２階調との間の輝度差を表わし、曲線２３は第２及び第３階調との間の輝度差を表わし、曲線３４は第３及び第４階調との間の輝度差を表わし、曲線４５は第４及び第５階調との間の輝度差を表わしている。図１から分かるように、従来のTN-LCDの下視野角は約２０度ぐらいで階調反転現象GSが生じる。 Conventional TN (Twisted Nematic) type LCD (hereinafter referred to as TN-LCD) has a problem that a serious gradation reversal phenomenon is seen in the lower viewing angle direction and the viewing angle characteristics are poor. FIG. 1 shows a relative luminance difference of each gradation at each lower viewing angle angle of a conventional TN-LCD in which the operation mode is a normally white method. Curve 12 represents the luminance difference between the first and second gradations, curve 23 represents the luminance difference between the second and third gradations, and curve 34 represents the difference between the third and fourth gradations. The curve 45 represents the luminance difference between the fourth and fifth gradations. As can be seen from FIG. 1, the gray scale inversion phenomenon GS occurs when the lower viewing angle of the conventional TN-LCD is about 20 degrees.
特許文献１において、Hirataが視野角特性を改善できるTN-LCDを開示している。該発明は画素電極上に誘電体層パターンを形成することで異なる液晶セルギャップを形成し、視野角特性を改善する。該方法によれば、視野角範囲は増大できるが、然し本願のLCD構造については教示していない。 In Patent Document 1, Hirata discloses a TN-LCD that can improve viewing angle characteristics. The present invention forms different liquid crystal cell gaps by forming a dielectric layer pattern on the pixel electrode and improves the viewing angle characteristics. The method can increase the viewing angle range, but does not teach the LCD structure of the present application.
特許文献２において、Nakayamaは視野角特性を改善できるTN-LCDを開示している。該発明は異なる平面にある二層の画素電極を形成して視野角特性を改善する。該方法によれば、視野角範囲は増大するが、然し、本願のLCD構造を教示していない。 In Patent Document 2, Nakayama discloses a TN-LCD that can improve viewing angle characteristics. The invention improves the viewing angle characteristics by forming two layers of pixel electrodes on different planes. The method increases the viewing angle range, but does not teach the LCD structure of the present application.
本発明は前述した従来のTN-LCDの欠点を鑑みてなされたものであり、階調反転現象（即ち、視野角特性）を改善する液晶表示装置を提供することを目的とする。 The present invention has been made in view of the above-described drawbacks of the conventional TN-LCD, and an object thereof is to provide a liquid crystal display device that improves the gradation inversion phenomenon (that is, viewing angle characteristics).
上記の目的を達成するために、本発明は、複数の画素領域を有する液晶表示装置であって、前記各画素領域が、第１基板と、第２基板と、前記第１及び第２基板との間に挟装された液晶層と、前記第１基板の一部の上に形成された第１画素電極と、前記第１基板の一部の上に形成され、前記第１画素電極と電気的に接続する第１画素駆動素子と、前記第１基板の一部の上に形成された第２画素電極と、前記第１基板の一部の上に形成され、前記第２画素電極と電気的に接続する第２画素駆動素子と、及び、前記第２基板の内側表面上に形成された共通電極と、を備え、前記第１及び第２画素電極の電圧が異なるように前記第１及び第２画素駆動素子が異なるオン電流（ION）を有することを特徴とする液晶表示装置を提供する。 In order to achieve the above object, the present invention provides a liquid crystal display device having a plurality of pixel regions, wherein each pixel region includes a first substrate, a second substrate, and the first and second substrates. A liquid crystal layer sandwiched between the first substrate, a first pixel electrode formed on a part of the first substrate, and a first pixel electrode formed on a part of the first substrate. Connected first pixel driving elements, a second pixel electrode formed on a part of the first substrate, and a second pixel electrode formed on a part of the first substrate. Second pixel driving elements connected to each other and a common electrode formed on the inner surface of the second substrate, and the first and second pixel electrodes have different voltages. A liquid crystal display device characterized in that the second pixel driving element has different on-currents (I ON ).
従来の液晶表示装置と比較して、本発明の液晶表示装置における各画素の第１及び第２画素電極が異なる電圧を有するので、階調反転角度を増大させて視野角特性を改善する効果が得られる。 Compared with the conventional liquid crystal display device, the first and second pixel electrodes of each pixel in the liquid crystal display device of the present invention have different voltages, so that the effect of improving the viewing angle characteristics by increasing the gradation inversion angle. can get.
以下で実施の形態を参照して、本発明の目的を達成するための技術手段と構造の特徴を詳細に説明する。 The technical means for achieving the object of the present invention and the features of the structure will be described in detail below with reference to the embodiments.
本発明の液晶表示装置は、各画素における薄膜トランジスタ素子TFT１とTFT２が異なるオン電流（ION）を有し、充電後の画素電極２６０と２６５の間に電圧差（ΔV）が生じて各画素における液晶層６４０内の液晶分子が二つの異なる配向を有するため、階調反転角度を増大させて視野角特性を改善する効果を挙げる。 In the liquid crystal display device of the present invention, the thin film transistor elements TFT1 and TFT2 in each pixel have different on-currents (I ON ), and a voltage difference (ΔV) is generated between the pixel electrodes 260 and 265 after charging. Since the liquid crystal molecules in the liquid crystal layer 640 have two different orientations, the effect of improving the viewing angle characteristics by increasing the gradation inversion angle is given.
以下で実施形態により本発明に係る階調反転現象（視野角特性）を改善する液晶表示装置を説明する。 Hereinafter, a liquid crystal display device that improves the gradation inversion phenomenon (viewing angle characteristic) according to the present invention will be described according to an embodiment.
（第１の実施形態）
図２は本発明による第１実施形態であるLCDにおける単一画素領域Pのアレイ基板の平面図である。図３は図２における３-３線に沿った断面図である。図６は、本発明の第１実施形態に係るLCDの部分構造断面図である。ここで特に強調したいのは、図２には単一の画素領域Pのみが示されているが、実際は本発明のLCDは複数の画素領域Pを備えている。これら画素領域Pは、交錯しているゲート線とソース線（又はデータ線という）により定義される。
(First embodiment)
FIG. 2 is a plan view of the array substrate of the single pixel region P in the LCD according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view taken along line 3-3 in FIG. FIG. 6 is a partial cross-sectional view of the LCD according to the first embodiment of the present invention. It should be particularly emphasized here that only a single pixel region P is shown in FIG. 2, but the LCD of the present invention actually includes a plurality of pixel regions P. These pixel regions P are defined by intersecting gate lines and source lines (or data lines).
図２及び図３に示すように、例えばガラス又は石英の第１基板２００上に、横方向に延伸するゲート線２１０と横方向に延伸する蓄積容量電極線２１２（storage capacitance electrode line, 以下Cs線と称する）とを形成し、上記ゲート線２１０が更にゲート２１５を備える。上記ゲート線２１０と上記Cs線２１２の材質は、例えばAl、Cr、Mo若しくはそれらの合金である。次に、例えばSiO２層であるゲート絶縁層２２０を形成して上記第１基板２００全体を被覆する。 2 and 3, for example, on a first substrate 200 made of glass or quartz, a gate line 210 extending in the lateral direction and a storage capacitance electrode line 212 (hereinafter referred to as Cs line) extending in the lateral direction. The gate line 210 further includes a gate 215. The material of the gate line 210 and the Cs line 212 is, for example, Al, Cr, Mo, or an alloy thereof. Next, a gate insulating layer 220 that is, for example, a SiO 2 layer is formed to cover the entire first substrate 200.
その後、シリコンなどの材質からなり、チャネル層２３０となる半導体層を上記ゲート絶縁層２２０の一部の上に形成する。 Thereafter, a semiconductor layer made of a material such as silicon and serving as the channel layer 230 is formed on a part of the gate insulating layer 220.
次に、上記ゲート絶縁層２２０上に縦方向に延伸し、チャネル層２３０の一部にまで延伸するソース２４２を含むソース線２４０を形成し、同時にチャネル層２３０の一部の上及びゲート絶縁層２２０上に第１ドレイン２４４及び第２ドレイン２４５を形成する。このうち、第１ドレイン２４４は第１延伸部２４４’を有してCs線２１２の一部と重なり、第２ドレイン２４５は第２延伸部２４５’を有してCs線２１２の一部と重なる。ソース線２４０、ソース２４２、ドレイン２４４及び２４５などの材質は、例えばAl、Cr、Mo若しくはそれらの合金である。このようにして、ゲート２１５、ゲート絶縁層２２０、チャネル層２３０、ソース２４２及び第１ドレイン２４４は、第１画素駆動素子である第１薄膜トランジスタ素子TFT１を構成し、且つゲート２１５、ゲート絶縁層２２０、チャネル層２３０、ソース２４２及び第２ドレイン２４５は第２画素駆動素子である第２薄膜トランジスタ素子TFT２を構成する。これら薄膜トランジスタ素子TFT１とTFT２の作用は、スイッチ素子として充放電の電荷の下記の画素電極への流動を制御する。 Next, a source line 240 including a source 242 extending in the vertical direction on the gate insulating layer 220 and extending to a part of the channel layer 230 is formed, and at the same time on a part of the channel layer 230 and the gate insulating layer. A first drain 244 and a second drain 245 are formed on 220. Among these, the first drain 244 has a first extending portion 244 ′ and overlaps with a part of the Cs line 212, and the second drain 245 has a second extending portion 245 ′ and overlaps with a part of the Cs line 212. . The materials of the source line 240, the source 242, the drains 244 and 245, etc. are, for example, Al, Cr, Mo or their alloys. Thus, the gate 215, the gate insulating layer 220, the channel layer 230, the source 242 and the first drain 244 constitute the first thin film transistor element TFT1 which is the first pixel driving element, and the gate 215 and the gate insulating layer 220. The channel layer 230, the source 242 and the second drain 245 constitute a second thin film transistor element TFT2 which is a second pixel driving element. The action of these thin film transistor elements TFT1 and TFT2 controls the flow of charge / discharge charges to the pixel electrodes described below as switching elements.
本実施形態におけるこれら薄膜トランジスタ素子TFT１及びTFT２は、同じゲート２１５、チャネル層２３０及びソース２４２を含むものを例として挙げているが、実際にはこれら薄膜トランジスタ素子TFT１及びTFT２はそれぞれ独立した素子であっても良い。重要な点は、上記第１薄膜トランジスタ素子TFT１と第２薄膜トランジスタ素子TFT２が異なるオン電流（ION）を有する必要がある。 The thin film transistor elements TFT1 and TFT2 in this embodiment are exemplified as those including the same gate 215, channel layer 230, and source 242, but actually, these thin film transistor elements TFT1 and TFT2 are independent elements. Also good. The important point is that the first thin film transistor element TFT1 and the second thin film transistor element TFT2 need to have different on-currents (I ON ).
その後、絶縁層２５０を形成して第１基板２００を被覆する。前記絶縁層２５０の材質は例えば有機材料若しくは無機材料である。その後、リソグラフィー工程により、上記第１延伸部２４４’を露出させる第１通り孔２５２と、上記第２延伸部２４５’を露出させる第２通り孔２５４とを形成する。その後、第１面積（A１）を有する第１画素電極２６０と第２面積（A２）を有する第２画素電極２６５を絶縁層２５０上に形成して、第１画素電極２６０を第１通り孔２５２に埋め込んで第１ドレイン２４４と電気的接続させ、かつ第２画素電極２６５を第２通り孔２５４に埋め込んで第２ドレイン２４５と電気的接続させる。これら画素電極２６０と２６５は、例えば蒸着法によって形成されたITO層(Indium Tin Oxide)若しくはIZO層(Indium Zinc Oxide)である。第１薄膜トランジスタ素子TFT１と第２薄膜トランジスタ素子TFT２が異なるオン電流（ION）を有するので、第１画素電極２６０が第１電圧（V１）を有し、第２画素電極２６５が第２電圧（V２）を有し、第１電圧（V１）と第２電圧（V２）との間に電圧差（△V）がある。 Thereafter, the insulating layer 250 is formed to cover the first substrate 200. The material of the insulating layer 250 is, for example, an organic material or an inorganic material. Thereafter, a first through hole 252 exposing the first extended portion 244 ′ and a second through hole 254 exposing the second extended portion 245 ′ are formed by a lithography process. Thereafter, the first pixel electrode 260 having the first area (A1) and the second pixel electrode 265 having the second area (A2) are formed on the insulating layer 250, and the first pixel electrode 260 is formed in the first through hole 252. The second pixel electrode 265 is buried in the second through hole 254 and is electrically connected to the second drain 245. The pixel electrodes 260 and 265 are, for example, an ITO layer (Indium Tin Oxide) or an IZO layer (Indium Zinc Oxide) formed by a vapor deposition method. Since the first thin film transistor element TFT1 and the second thin film transistor element TFT2 have different on-currents (I ON ), the first pixel electrode 260 has the first voltage (V1) and the second pixel electrode 265 has the second voltage (V2). ), And there is a voltage difference (ΔV) between the first voltage (V1) and the second voltage (V2).
図４及び図５は、本実施形態における画素電極２６０及び２６５が異なる電圧を有するような設計を説明する。図４は、本実施形態における薄膜トランジスタ素子TFT１及びTFT２の一部拡大図である。図５は薄膜トランジスタ素子TFT１及びTFT２の作動状況を示す。図４において、第１ドレイン２４４が第１幅（W１）を、第１ドレイン２４４とソース２４２との間に第１距離（L１）を、第２ドレイン２４５が第２幅（W２）を、第２ドレイン２４５とソース２４２との間に第２距離（L２）を有して、関係式W１/L１≠W２/L２を満たすので、薄膜トランジスタ素子TFT１及びTFT２が異なるオン電流（ION）を有する。図５に示すように、ソース線２４０が駆動電圧Vsを提供する時、及びゲート２１５のオンタイム（gate turn on time）をｔON（例えば１０〜３０μsec）に設定すると、薄膜トランジスタ素子TFT１及びTFT２は異なるオン電流（ION）を有するので、充電後の画素電極２６０及び２６５との間に電圧差（△V）が生じる。 4 and 5 illustrate a design in which the pixel electrodes 260 and 265 in this embodiment have different voltages. FIG. 4 is a partially enlarged view of the thin film transistor elements TFT1 and TFT2 in the present embodiment. FIG. 5 shows the operating state of the thin film transistor elements TFT1 and TFT2. In FIG. 4, the first drain 244 has the first width (W1), the first distance (L1) between the first drain 244 and the source 242, the second drain 245 has the second width (W2), Since there is a second distance (L2) between the two drains 245 and the source 242 and the relational expression W1 / L1 ≠ W2 / L2 is satisfied, the thin film transistor elements TFT1 and TFT2 have different on-currents (I ON ). As shown in FIG. 5, when the source line 240 provides the drive voltage Vs and when the gate turn on time of the gate 215 is set to t ON (for example, 10 to 30 μsec), the thin film transistor elements TFT1 and TFT2 are Since they have different on-currents (I ON ), a voltage difference (ΔV) occurs between the pixel electrodes 260 and 265 after charging.
次に、図６に示すように、上記画素電極２６０と２６５及び絶縁層２５０上に配向膜２７０を形成する。まず、例えばカラーフィルタ６１０を備えるガラス基板を準備して、第１基板２００と対向する第２基板６００とする。このカラーフィルタ６１０の内側表面上に、例えば蒸着法により形成されたITO層若しくはIZO層である共通電極６２０を形成する。そして、もう一つの配向膜６３０を共通電極６２０上に形成する。 Next, as shown in FIG. 6, an alignment film 270 is formed on the pixel electrodes 260 and 265 and the insulating layer 250. First, for example, a glass substrate provided with the color filter 610 is prepared and used as the second substrate 600 facing the first substrate 200. On the inner surface of the color filter 610, a common electrode 620 that is, for example, an ITO layer or an IZO layer formed by vapor deposition is formed. Then, another alignment film 630 is formed on the common electrode 620.
次に、TN型液晶分子６３５を第１基板２００及び第２基板６００との間に充填して、例えば厚さ２〜１０μmの、好ましくは５μmの液晶層６４０を形成する。 Next, TN liquid crystal molecules 635 are filled between the first substrate 200 and the second substrate 600 to form a liquid crystal layer 640 having a thickness of 2 to 10 μm, preferably 5 μm, for example.
図６に示すとおり、第１画素電極２６０の電圧（V１）は第２画素電極２６５の電圧（V２）と異なるので、第１画素電極２６０及び第２画素電極２６５の上方にある液晶分子６３５が異なる配向を有して、階調反転現象（視野角特性）を改善する。 As shown in FIG. 6, since the voltage (V1) of the first pixel electrode 260 is different from the voltage (V2) of the second pixel electrode 265, the liquid crystal molecules 635 above the first pixel electrode 260 and the second pixel electrode 265 It has different orientations and improves the gradation inversion phenomenon (viewing angle characteristics).
図７は、本発明による各種異なる電圧差（△V）条件のもとで、第１画素電極２６０の面積（A１）と、第１画素電極２６０と第２画素電極２６５の総面積（A１＋A２）との比率が、下視野角の階調反転角度に対する影響を示す。図７から分かるように、従来のTN-LCD（△V＝０）と比較すると、本発明のLCDは０＜電圧差(△V)＜０.６Vsの条件のもとでは、A１とA２が、０＜A１/（A１+A２）＜０.８、を満たす時に、その下視野角の階調反転の角度は従来の２０度より大きく、本発明により下視野角の階調反転を改善する効果を有することが証明された。一方、本発明のLCDは、電圧差（△V）＝０.６Vsの条件のもとでは、A１とA２は、０.４５＜A１/（A１+A２）＜０.８、を満たす時、下視野角の階調反転の角度も従来の２０度より大きく、本発明により下視野角の階調反転が改善された効果を有することが証明された。 FIG. 7 shows the area (A1) of the first pixel electrode 260 and the total area (A1 + A2) of the first pixel electrode 260 and the second pixel electrode 265 under various voltage difference (ΔV) conditions according to the present invention. The influence of the lower viewing angle on the gradation inversion angle is shown. As can be seen from FIG. 7, when compared with the conventional TN-LCD (ΔV = 0), the LCD of the present invention has A1 and A2 under the condition of 0 <voltage difference (ΔV) <0.6 Vs. , 0 <A1 / (A1 + A2) <0.8, the angle of inversion of the lower viewing angle is larger than the conventional 20 degrees, and the present invention improves the inversion of the lower viewing angle. Proven to have an effect. On the other hand, in the LCD of the present invention, when A1 and A2 satisfy 0.45 <A1 / (A1 + A2) <0.8 under the condition of voltage difference (ΔV) = 0.6 Vs, The angle of gradation inversion of the lower viewing angle is also larger than the conventional 20 degrees, and it has been proved that the present invention has an effect of improving the gradation inversion of the lower viewing angle by the present invention.
ここで、本発明に係るLCDの設計例を説明するために例を挙げる。例えば、走査周波数が７５Hz及び解析度が１０２４＊７６８であるLCDを例にすると、図４及び図５に示すとおり、まず第１薄膜トランジスタ素子TFT１のW１/L１を３に定義し、第２薄膜トランジスタ素子TFT２のW２/L２を０.８８９と定義し、又ゲート２１５のオンタイムｔONを１０μsec、及びソース線２４０が提供する駆動電圧（Vs）を５Vに設定する。このようにしてTFT１と電気的接続する第１画素電極２６０の充電率CR１が９９.３６％まで、TFT２と電気的接続する第２画素電極２６５の充電率CR２が７６.７１％に達する。その計算過程は下記のとおりである。まず、LCDの駆動操作を、図８のようなRC回路と見なす。RONはTFTがオンである時の等価抵抗を表わし、CLCは液晶容量を表わし、CCSは蓄積容量を表わす。ゲートのオンタイムｔON後の画素電極の電圧VPは、
１．液晶容量 CLC＝０.４２９８E-１２（F）
２．蓄積容量 CCS＝０.１８９６E-１２（F）
３．ソースとドレインの間の電圧差VSD＝１０（V）、ソースとドレインの間の極性反転電圧は±５（V）である。
４．電荷キャリアの移動度 μ＝０.３５E−４（ｍ２/V）
５．ゲート絶縁層の単位面積あたりの容量COX＝１.４９E-４（F/ｍ２）
６．ゲートは、TFTがオンである時の最高電圧 Vgh＝２２（V）
７．TFTの起動電圧 Vth＝２（V）
Here, an example will be given to explain a design example of the LCD according to the present invention. For example, in the case of an LCD having a scanning frequency of 75 Hz and an analysis level of 1024 * 768, as shown in FIGS. 4 and 5, first, W1 / L1 of the first thin film transistor element TFT1 is defined as 3, and the second thin film transistor element The W2 / L2 of the TFT 2 is defined as 0.889, the on-time t ON of the gate 215 is set to 10 μsec, and the drive voltage (Vs) provided by the source line 240 is set to 5V. In this way, the charging rate CR1 of the first pixel electrode 260 electrically connected to the TFT1 reaches 99.36%, and the charging rate CR2 of the second pixel electrode 265 electrically connected to the TFT2 reaches 76.71%. The calculation process is as follows. First, the driving operation of the LCD is regarded as an RC circuit as shown in FIG. R ON represents the equivalent resistance when the TFT is on, C LC represents the liquid crystal capacitance, and C CS represents the storage capacitance. The voltage V P of the pixel electrode after the gate on-time t ON is
1. Liquid crystal capacity C LC = 0.4298E-12 (F)
2. Storage capacity C CS = 0.1896E-12 (F)
3. The voltage difference V SD = 10 (V) between the source and the drain, and the polarity reversal voltage between the source and the drain is ± 5 (V).
4). Charge carrier mobility μ = 0.35E-4 (m 2 / V)
5). Capacitance per unit area of gate insulating layer C OX = 1.49E-4 (F / m 2 )
6). The gate has the highest voltage when the TFT is on Vgh = 22 (V)
7). TFT start-up voltage Vth = 2 (V)
第１薄膜トランジスタ素子TFT１については、W/L=３であるので、Ron=３.２E６（Ω）となり、その充電率はCR１=９９.３６％である。 For the first thin film transistor element TFT1, since W / L = 3, R on = 3.2E6 (Ω), and the charging rate is CR1 = 99.36%.
第２薄膜トランジスタ素子TFT２については、W/L=０.８８９であるので、Ron=１１.０８E６（Ω）となり、その充電率はCR２=７６.７１％である。 For the second thin film transistor element TFT2, since W / L = 0.889, R on = 11.08E6 (Ω), and the charging rate is CR2 = 76.71%.
従って、第１画素電極２６０と第２画素電極２６５の間の電圧差は（ΔV）＝（CR１-CR２）＊Vs＝２２.６５％＊５＝１.１（V）となる。 Therefore, the voltage difference between the first pixel electrode 260 and the second pixel electrode 265 is (ΔV) = (CR1−CR2) * Vs = 22.65% * 5 = 1.1 (V).
図７から分かるように、電圧差が（ΔV）＝０.２Vsであるとき、その下視野角の階調反転角度は、全て２５度以上である。 As can be seen from FIG. 7, when the voltage difference is (ΔV) = 0.2 Vs, the gradation inversion angles of the lower viewing angle are all 25 degrees or more.
（第２の実施形態）
図９は、本発明による第２実施形態のLCDにおける単一画素領域Pのアレイ基板の平面図である。第２実施形態と第１実施形態との差異は、第２実施形態では画素電極２６０、２６５の一部が、Cs線２１２に代わってゲート線２１０と重なることである。第２実施形態のその他の部分については、第１実施形態と類似するので、ここでは特に述べない。
(Second Embodiment)
FIG. 9 is a plan view of the array substrate of the single pixel region P in the LCD according to the second embodiment of the present invention. The difference between the second embodiment and the first embodiment is that part of the pixel electrodes 260 and 265 overlaps the gate line 210 instead of the Cs line 212 in the second embodiment. Other parts of the second embodiment are similar to those of the first embodiment, and are not specifically described here.
以上、本発明の実施例を図面を参照して詳述してきたが、具体的な構成は、この実施例に限られるものではなく、本発明の要旨を逸脱しない範囲の設計変更等があっても、本発明に含まれる。 The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and there are design changes and the like that do not depart from the gist of the present invention. Are also included in the present invention.
２００ 第１基板
２１０ ゲート線
２１０ 蓄積容量線（Cs線）
２１５ ゲート
２２０ ゲート絶縁層
２３０ チャネル層
２４０ ソース線
２４２ ソース
２４４ 第１ドレイン
２４４’第１延伸部
２４５ 第２ドレイン
２４５’第２延伸部
２５０ 絶縁層
２５１ 第１通り孔
２５４ 第２通り孔
２６０ 第１画素電極
２６５ 第２画素電極
２７０、６３０ 配向膜
６００ 第２基板
６１０ カラーフィルタ
P 画素領域
GS 階調反転現象が起きる箇所
200 First substrate 210 Gate line 210 Storage capacitor line (Cs line)
215 Gate 220 Gate insulating layer 230 Channel layer 240 Source line 242 Source 244 First drain 244 ′ First extended portion 245 Second drain 245 ′ Second extended portion 250 Insulating layer 251 First through hole 254 Second through hole 260 First Pixel electrode 265 Second pixel electrode 270, 630 Alignment film 600 Second substrate 610 Color filter
P pixel area
Where GS gradation inversion occurs
Claims (6)
第１基板上に形成された横方向に延伸するゲート線と縦方向に延伸するソース線と、
前記ゲート線と前記ソース線との交叉点に位置して、前記ゲート線から延伸された１つのゲートと、前記ソース線から延伸された１つのソースと、第１ドレイン及び第２ドレインとを有する薄膜トランジスタ素子と、
第１面積A１を有し、前記第１ドレインを通して前記ソースと電気的接続をし、よって第１電圧を有する第１画素電極と、
第２面積A２を有し、前記第２ドレインを通して前記ソースと電気的接続をし、よって前記第１電圧との間に電圧差（△V）がある第２電圧を有する第２画素電極と、
前記第１基板と対向する第２基板と、
前記第２基板の内側表面上に形成された共通電極と、
前記第１基板と前記第２基板との間に挟装され、ＴＮ型液晶分子を有し、厚さが２〜１０μｍである液晶層と、
を備え、
前記第１ドレインの幅をW1、前記ソースとの距離をL1、前記第２ドレインの幅をW2、前記ソースとの距離をL2、とした時、W1/L1≠W2/L2の関係式を有すると共に、前記ソース線が駆動電圧（Vs）を提供し、０＜前記電圧差（△V）＜０.６Vsであるとき、前記第１面積（A１）と前記第１及び第２面積の総和（A１＋A２）が関係式０＜A１/（A１+A２）＜０.８を満たし、
且つ、前記電圧差（△V）は、前記第１画素電極及び前記第２画素電極の上方に位置する液晶分子に異なる配向をもたせることを特徴とする液晶表示装置。 A liquid crystal display device comprising a plurality of pixel regions, wherein each pixel region is
A gate line extending in the horizontal direction and a source line extending in the vertical direction formed on the first substrate;
Located at the intersectional point between the source line and the gate line, having a single gate, which is extended from the gate line, and one source that is drawn from the source line, and a first drain and the second drain A thin film transistor element;
It has a first area A1, a first pixel electrode having the source to scan the electrical connection, thus the first voltage through the first drain,
A second area A2, and the source and electrically connected through said second drain, thus a second pixel electrode having a second voltage that is a voltage difference (△ V) between the first voltage ,
A second substrate facing the first substrate;
A common electrode formed on the inner surface of the second substrate;
A liquid crystal layer sandwiched between the first substrate and the second substrate, having TN type liquid crystal molecules and having a thickness of 2 to 10 μm;
With
When the width of the first drain is W1, the distance to the source is L1, the width of the second drain is W2, and the distance to the source is L2, the relational expression is W1 / L1 ≠ W2 / L2. In addition, when the source line provides a driving voltage (Vs) and 0 <the voltage difference (ΔV) <0.6 Vs, the first area (A1) and the sum of the first and second areas ( A1 + A2) satisfies the relational expression 0 <A1 / (A1 + A2) <0.8,
The voltage difference (ΔV) causes the liquid crystal molecules positioned above the first pixel electrode and the second pixel electrode to have different orientations.
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| JPH08201777A (en) * | 1995-01-30 | 1996-08-09 | Matsushita Electric Ind Co Ltd | Liquid crystal display device |
| JPH0943609A (en) * | 1995-07-31 | 1997-02-14 | Matsushita Electric Ind Co Ltd | Liquid crystal display panel |
| JPH10142629A (en) * | 1996-11-07 | 1998-05-29 | Sharp Corp | Active matrix liquid crystal display device |
| JPH10274783A (en) * | 1997-03-31 | 1998-10-13 | Sharp Corp | Liquid crystal display device |
| JPH10311989A (en) * | 1997-05-14 | 1998-11-24 | Seiko Epson Corp | Liquid crystal display element |
Also Published As
| Publication number | Publication date |
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| TWI240904B (en) | 2005-10-01 |
| JP2005338853A (en) | 2005-12-08 |
| TW200539082A (en) | 2005-12-01 |
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