KR101269005B1 - Array substrate of Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device for minimizing a difference in level shift voltage generated between pixels sharing a data line, comprising: a data line on a substrate; First and second pixels disposed left and right about the data line; First and second gate wirings disposed in upper and lower rows of the first pixel and the second pixel, respectively; A first thin film transistor including a first gate electrode connected to the first gate line between the first pixel and the data line, and connected to the second gate line between the second pixel and the data line A second thin film transceiver comprising a second gate electrode; A common electrode having one side disposed on the first pixel and the second pixel in proximity to the first thin film transistor and the second thin film transistor; A first capacitance compensator and a second capacitance compensator extending from the first thin film transistor and the second thin film transistor, respectively, and overlapping the common electrode; And a first pixel electrode and a second pixel electrode respectively disposed on the first pixel and the second pixel via a protective film.

LCD, data wiring, level shift voltage, parasitic capacitance

Description

Array substrate of liquid crystal display device

1 is a circuit diagram of a liquid crystal display device sharing the data wiring of the prior art.

2 is a plan view of a liquid crystal display device sharing data wiring of the related art.

3 is a diagram illustrating a change in voltage of a liquid crystal layer due to various signal waveforms and level shift voltages of a pixel;

4 is a plan view of a liquid crystal display device sharing data lines according to an exemplary embodiment of the present invention.

5 is a cross-sectional view taken along line AA 'of FIG.

6 is a cross-sectional view taken along line BB ′ of FIG. 4.

Explanation of symbols for main parts of drawings *

110 substrate 111 first pixel

112: second pixel 113: data wiring

114: first gate wiring 115: second gate wiring

116: first thin film transistor 117: second thin film transistor

160: first capacitance compensation unit 161: second capacitance compensation unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device which minimizes a difference in level shift voltages generated between adjacent pixels sharing data lines.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Recently, liquid crystal display (LCD), plasma display panel (PDP), electro luminescent display (ELD), and VFD (vacuum) Various flat panel displays such as fluorescent displays are used. Among flat panel displays, liquid crystal displays are widely used because they have advantages of miniaturization, light weight, thinness, and low power driving.

The liquid crystal display device includes two substrates facing each other and a liquid crystal interposed between the two substrates. In general, a liquid crystal display device is driven by displaying an image by changing a liquid crystal array by an electric field generated between a pixel electrode and a common electrode formed on two substrates.

Such liquid crystal display devices generally have thin film transistors arranged at the same position in the same column for one data line, but in order to reduce the number of source driving circuits, a liquid crystal display device which shares data lines with adjacent pixels to the left and right is commonly used. can do.

In the liquid crystal display device sharing the data wiring, the number of source driving circuits is reduced, but the number of gate driving circuits is increased. In the left and right pixels of the liquid crystal display device, the thin film transistors connected to the pixels are located on the upper and lower sides of the data wiring. Is placed.

In addition, during the manufacturing process of the thin film transistor, the level shift voltage is changed due to the parasitic capacitance difference between the gate electrode and the source electrode of the adjacent pixel due to misalignment of the source electrode and the drain electrode constituting the thin film transistor. The luminance difference occurs. Such a difference in the level shift voltage may cause a poor image quality in the form of a dim in the vertical direction. In a liquid crystal display device in which such adjacent left and right pixels share data wirings, a conventional technique of generating a difference in level shift voltage when a source electrode and a drain electrode are misaligned will be described as follows.

1 is a circuit diagram of a liquid crystal display device sharing the data wiring of the prior art, and FIG. 2 is a plan view of the liquid crystal display device sharing the data wiring of the prior art.

Generally, a liquid crystal display device is composed of two opposing substrates, but FIGS. 1 and 2 only show an array structure of a lower substrate on which main components of the liquid crystal display device are formed.

1 and 2, in the liquid crystal display device, the first pixel 11 and the second pixel 12 share the data line 13, and the first pixel 11 and the second pixel 12. The first gate wiring 14 and the second gate wiring 15 are disposed in the upper column and the lower column of the circuit. In addition, a common wiring 16 is provided on the first pixel 11 and the second pixel 12. The first source electrode 18 of the first thin film transistor 16 is connected to the first pixel 11, the first drain electrode 19 is connected to the data line 13, and the first gate electrode 20. Is connected to the first gate line 14 provided on the first pixel 11. The second source electrode 21 of the second thin film transistor 17 is connected to the second pixel 12, the second drain electrode 22 is connected to the data line 13, and the second gate electrode 23. ) Is connected to the second gate line 15 provided under the second pixel 12.

As illustrated in FIG. 2, a first gate electrode 20 protruding from the first thin film transistor 16 connected to the first gate line 14 is positioned, and the first gate electrode 20 is positioned on the first active 24. The first drain electrode 18 and the first source electrode 19 are formed on both sides of the first source electrode 19, the first source electrode 19 is connected to the data line 13, and the first source electrode 18 is the first pixel. It extends to the area of 11 and is connected. In the second thin film transistor 17, a second gate electrode 23 protruding from the second active line 25 is connected to the second gate line 15, and the second thin film transistor 17 is disposed on both sides of the second gate electrode 23. A drain electrode 21 and a second source electrode 22 are formed, the second source electrode 22 is connected to the data line 13, and the second drain electrode 21 is an area of the second pixel 12. Extends to connect.

1 and 2, in a liquid crystal display device in which left and right adjacent pixels share a data line, misalignment may occur in a vertical direction when forming a source electrode and a drain electrode during a manufacturing process.

However, thin film transistors of pixels sharing the data wirings are disposed on the upper left side and the lower right side of the data wiring, respectively. Therefore, when a misalignment occurs in which the source electrode and the drain electrode move downward with respect to the gate electrode, the first gate electrode 20 and the first source electrode 18 overlap each other in the first pixel 11. The first region 26 decreases, and the second region 27 overlapping the second gate electrode 23 and the second source electrode 21 increases in the second pixel 12. Between the first gate electrode 20 and the first source electrode 18 and between the second gate electrode 23 and the second source electrode 21 are formed via a gate insulating film (not shown). The parasitic capacitances Cgs between the gate electrode and the source electrode are different from each other.

When the left and right pixels do not share data wiring, the thin film transistors have the same wiring direction, so that the parasitic capacitance Cgs between the gate electrode and the source electrode does not occur in the left and right pixels. Such a difference in parasitic capacitance Cgs causes a difference in luminance due to different level shift voltages of two adjacent pixels, and deteriorates the image quality of the liquid crystal display.

If the level shift voltage is 100%, the voltage V _LC (t) of the liquid crystal layer immediately before the thin film transceiver is turned off is the voltage V _D applied to the data wiring. to be. As the gate voltage changes from Vgh to Vgl, the thin film transistor turns off, and at that moment, the parasitic capacitance Cgs causes the voltage V _LC (t) applied to the liquid crystal layer to change as follows.

V _LC (t) = VD-ΔVp

ΔVp = [Cgs / (Cgs + Cst + Clc)] (Vgh-Vgl)

Here, Vgh is a high voltage of the gate electrode, and Vgl is a low voltage of the gate electrode. Cgs is the parasitic capacitance between the gate electrode and the source electrode, Cst is the capacitance between the common electrode and the source electrode, and Clc is the capacitance of the liquid crystal layer.

The polarity of the voltage is applied to the liquid crystal layer alternately every frame. The level shift voltage ΔVp lowers the voltage applied to the liquid crystal layer in the (+) frame and increases the voltage applied to the liquid crystal layer in the (-) frame by ΔVp. .

3 is a diagram illustrating a change in voltage of a liquid crystal layer due to various signal waveforms and level shift voltages of a pixel.

If the voltage of the data line is Vp = 5 V and the level shift voltage ΔVp = 1 V, the voltage applied to the liquid crystal layer during the (+) frame due to the level shift voltage becomes Vp (+) = 4 V and during the (-) frame. Vp (-) = 6 V. The difference between the absolute voltage across the liquid crystal layer during the positive and negative frames is 2.ΔVp. The difference in brightness results in a difference in brightness, resulting in screen dim.

Referring to a case in which misalignment occurs in which the source electrode and the drain electrode move downward with respect to the gate electrode, the first region 26 is reduced in the first pixel 11, and the second pixel 12 in the second pixel 12 is reduced. The two areas 27 will increase. The reduction of the first region 26 and the increase of the second region 27 inevitably change the parasitic capacitances Cgs of the adjacent pixels on each side, resulting in different level shift voltages, resulting in a luminance difference. This results in poor image quality.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device which minimizes the difference in level shift voltage generated between pixels sharing data wiring.

In particular, the capacitance compensation unit extending from the source electrode is overlapped with the common electrode, and the parasitic capacitance between the gate electrode and the source electrode of each pixel caused by misalignment is compensated for, thereby minimizing the difference in the level shift voltage, thereby improving image quality. An object of the present invention is to provide an improved liquid crystal display device.

In order to achieve the above object, an array substrate of a liquid crystal display according to an exemplary embodiment of the present invention includes data wiring on a substrate; First and second pixels disposed left and right about the data line; First and second gate wirings disposed in upper and lower rows of the first pixel and the second pixel, respectively; A first thin film transistor including a first gate electrode connected to the first gate line between the first pixel and the data line, and connected to the second gate line between the second pixel and the data line A second thin film transceiver comprising a second gate electrode; A common electrode having one side disposed on the first pixel and the second pixel in proximity to the first thin film transistor and the second thin film transistor; A first capacitance compensator and a second capacitance compensator extending from the first thin film transistor and the second thin film transistor, respectively, and overlapping the common electrode; And a first pixel electrode and a second pixel electrode respectively disposed on the first pixel and the second pixel via a protective film.

In the array substrate of the liquid crystal display device, the first capacitance compensator extends from the first drain electrode of the first thin film transistor to be formed on the first pixel to overlap the common electrode, and the second capacitance The compensator extends from the second drain electrode of the second thin film transistor and is formed on the second pixel to overlap the common electrode.

In the array substrate of the liquid crystal display device, the common electrode has a first side at a position adjacent to the first thin film transistor and the second thin film transistor, and is adjacent to the first side, and the first pixel and the first Both sides of the second pixel 112 have second and third sides, respectively, and the horizontal center portion of the first side has a side toward the first drain electrode and the second capacitance compensation of the first capacitance compensation unit, respectively. A side surface of the negative portion facing the second drain electrode is positioned.

In the array substrate of the liquid crystal display device, the common electrode may have an opening at a side facing the first thin film transistor and the second thin film transistor.

The array substrate of the liquid crystal display device, wherein the first pixel electrode and the second pixel electrode are formed through the first source contact hole and the second source contact hole formed in the passivation layer, respectively. And a second capacitance compensator.

In the array substrate of the liquid crystal display device, the first thin film transistor includes: a first active on the first gate electrode and the first gate electrode connected to the first gate wiring; and the first and second gate electrodes on both sides of the first gate electrode. A first source electrode connected to the first pixel electrode and a first drain electrode connected to the data line, wherein the second thin film transistor is connected to the second gate line. A second active electrode on the second gate electrode and the second gate electrode, a second source electrode formed on the second active layer on both sides of the second gate electrode, and connected to the second pixel electrode; And a second drain electrode connected thereto.

In the array substrate of the liquid crystal display device, a gate insulating film is provided between the first gate electrode and the first active, and between the second gate electrode and the second active, and the gate insulating film includes silicon oxide and silicon nitride. The inorganic insulating material, or an organic insulating material containing benzocyclobutene (BCB), acrylic resin (resin) is selected and used.

In the array substrate of the liquid crystal display device, the protective film is characterized in that using the photoacryl.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

4 is a plan view of a liquid crystal display device sharing data lines according to an exemplary embodiment of the present invention.

Generally, a liquid crystal display device is composed of two facing substrates, but in the exemplary embodiment of the present invention, only an array structure of a lower substrate on which main components of the liquid crystal display device are formed will be described.

Referring to FIG. 4, in the liquid crystal display device of the present invention, the first pixel 111 and the second pixel 112 share the data line 113, and the first pixel 111 and the second pixel 112. The first gate wiring 114 and the second gate wiring 115 are disposed in the upper column and the lower column, respectively.

On the first active 124 of the first thin film transistor 116, the first gate electrode 120 protruding from the first thin film transistor 116 is protruded, and the first gate electrode 120 is disposed on both sides of the first gate electrode 120. The source electrode 118 and the first drain electrode 119 are formed, the first drain electrode 119 is connected to the data line 113, and the first source electrode 118 is an area of the first pixel 111. Extends to connect. In the second thin film transistor 117, the second gate electrode 123 protruding from the second active line 125 is connected to the second gate line 115, and the second thin film transistor 117 is provided on both sides of the second gate electrode 123. The source electrode 121 and the second drain electrode 122 are formed, the second drain electrode 122 is connected to the data line 113, and the second source electrode 121 is an area of the second pixel 112. Extends to connect.

The first source electrode 118 has a first capacitance compensator 160 that overlaps the common electrode 116 on the first pixel 111 to compensate for a difference in level shift voltage with an adjacent pixel. Similarly, a second capacitance compensator 161 is disposed on the second pixel 112 to overlap the common electrode 116 to compensate for the difference between the adjacent pixel and the level shift voltage.

A portion of the common electrode 116 may be formed of the first thin film transistor 116 and the first thin film transistor 116 so that the first capacitance compensator 160 and the second capacitance compensator 161 may compensate for the level shift voltage difference. The second thin film transistor 117 is designed to overlap the first source electrode 118 and the second source electrode 121.

Therefore, in FIG. 4, the common electrode 116 has a first side at an adjacent position of the first thin film transistor 116 and the second thin film transistor 117, is adjacent to the first side, and the first pixel 112 and the first pixel. Designed to have second side surfaces and third side surfaces on both sides of the two pixels 112, respectively, so as to have openings at positions facing the first side of the common electrode 116 in each pixel.

If the correct alignment is made, the side toward the first drain electrode 118 of the first capacitance compensator 160 is positioned at the horizontal center of the first side of the common electrode 116. Similarly, the side facing the second drain electrode 122 of the second capacitance compensator 161 is designed to be positioned at the horizontal center of the first side of the common electrode 116.

5 is a cross-sectional view taken along line AA ′ of FIG. 4, and FIG. 6 is a cross-sectional view taken along line B ′ B ′ of FIG. 4. 5 and 6 are cross-sectional views of the first pixel 111 and the first thin film transistor 116, but all pixels have the same cross section as the first pixel 111 and are simultaneously manufactured in the same manner.

5 and 6, the first metal film is deposited and patterned on the substrate 110 to form a first gate wiring (not shown), a common wiring 116, and a first gate electrode 120. A gate insulating layer 151 is formed on the substrate 110 including the gate wiring, the common wiring, and the gate electrode 120. The first metal layer may include copper (Cu), copper alloy (Cu alloy), aluminum (Al), aluminum alloy (Al alloy), chromium (Cr), molybdenum (Mo), tungsten (W), and tantalum (Ta). By using one or an alloy thereof, the gate insulating film 151 is selected from an inorganic insulating material containing silicon oxide and silicon nitride, or an organic insulating material containing benzocyclobutene (BCB) and acrylic resin. use.

The first active 124 is formed as a semiconductor layer on the gate insulating layer 151. The semiconductor layer is formed of an amorphous silicon layer containing impurities at an upper portion thereof and an amorphous silicon layer containing impurities at a lower portion thereof, and an amorphous silicon layer containing impurities of the first active 124 in which the channel is formed is removed.

The second metal film is deposited and patterned on the gate insulating layer 151 including the first active 124 to form the data line 116, the first source electrode 118, and the first drain electrode 119. The second metal film is formed of the same material as the first metal film.

The protective layer 152 is formed on the gate insulating layer 151 including the data line 116, the first source electrode 118, and the first drain electrode 119, and the protective layer 152 is patterned to form a first source. A first source contact hole 153 exposing the electrode 118 is formed. The protective layer 153 uses an organic insulating material having a low dielectric constant, for example, photoacryl. In addition, a transparent conductive metal layer is deposited and patterned on the protective layer 152 to form a first pixel electrode 154 connected to the first source electrode 118 through the source contact hole 153. Although not shown in the drawing, the second source contact hole and the second pixel electrode are formed in the cross-sectional view of the second pixel 112.

4 to 6, thin film transistors of pixels sharing the data wirings are disposed on the upper and lower left sides of the data wirings, respectively, so that misalignment may occur in the vertical direction when the source and drain electrodes are formed. have. Referring to a case in which misalignment occurs in which the source electrode and the drain electrode move upward with respect to the gate electrode, in the first pixel 111, the first capacitance compensation of the first gate electrode 120 and the first source electrode 118 is performed. The first region 126 in which the unit 160 and the common electrode 116 overlap with each other increases, and in the second pixel 112, the second capacitance of the second gate electrode 123 and the second source electrode 121 is increased. The second region 127 overlapping the compensator 161 and the common electrode 116 is reduced.

Therefore, in the first pixel 111, Cgs1 overlapping the first gate electrode 120 and the first source electrode 118 and Cst1 overlapping the first capacitance compensator 160 and the common electrode 116 increase. In the second pixel 112, Cgs2 overlapping the second gate electrode 123 and the second source electrode 121 and Cst2 overlapping the second capacitance compensator 160 and the common electrode 116 are reduced. Done.

Applying the result of this misalignment to the formula for determining the level shift voltage, ΔVp = [Cgs / (Cgs + Cst + Clc)] (Vgh-Vgl), the denominator Cgs + when the molecule Cgs changes By changing Cst, it is possible to reduce the difference between ΔVp of adjacent pixels left and right.

According to an embodiment of the present invention, in the left and right adjacent pixels sharing the data wiring, the capacitance compensation unit extending from the source electrode of the thin film transistor overlaps with the common electrode, and the gate electrode and the source of each pixel generated by misalignment. Compensation for the difference in parasitic capacitance between the electrodes minimizes the difference in the level shift voltage, thereby improving image quality.

Claims (8)

Data wiring on the substrate; First and second pixels disposed left and right about the data line; First and second gate wirings disposed in upper and lower rows of the first pixel and the second pixel, respectively; A first thin film transistor including a first gate electrode and a first source electrode connected to the first gate line between the first pixel and the data line, and between the second pixel and the data line; A second thin film transistor including a second gate electrode and a second source electrode connected to the second gate line; A common electrode on one side of the first pixel and the second pixel, the common electrode being adjacent to the first thin film transistor and the second thin film transistor; A first capacitance compensator and a second capacitance compensator extending from the first thin film transistor and the second thin film transistor, respectively, and overlapping the common electrode; First and second pixel electrodes respectively disposed on the first pixel and the second pixel via a protective film; / RTI > The first source electrode and the first gate electrode overlap to form a first parasitic capacitance, and the second source electrode and the second gate electrode overlap to form a second parasitic capacitance, and the overlapping first capacitance The compensator and the common electrode form a first capacitance, the overlapping second capacitance compensator and the common electrode form a second capacitance, and the first parasitic capacitance and the first capacitance may increase. And wherein the second parasitic capacitance and the second parasitic capacitance are reduced to reduce the level shift voltage difference between the first pixel and the second pixel. The method of claim 1, The first capacitance compensator extends from the first source electrode of the first thin film transistor, is formed on the first pixel to overlap the common electrode, and the second capacitance compensator is formed on the second of the second thin film transistor. An array substrate of a liquid crystal display device extending from a source electrode and formed on the second pixel to overlap the common electrode. The method of claim 2, The common electrode has a first side at a position adjacent to the first thin film transistor and the second thin film transistor, is adjacent to the first side surface, and has a second side surface at both sides of the first pixel and the second pixel, respectively. A liquid crystal having a third side surface and having a side toward the first source electrode of the first capacitance compensator and a side toward the second source electrode of the second capacitance compensator, respectively, in the horizontal center portion of the first side; Array board of display device. The method of claim 3, wherein And the common electrode has an opening at a side facing the first thin film transistor and the second thin film transistor. The method of claim 2, The first pixel electrode and the second pixel electrode are connected to the first capacitance compensator and the second capacitance compensator through a first source contact hole and a second source contact hole respectively formed in the passivation layer. Array board of display device. The method of claim 1, The first thin film transistor is formed on the first active layer on the first gate electrode and the first gate electrode connected to the first gate wiring, on the first active layer on both sides of the first gate electrode, And a first drain electrode connected to the first pixel electrode and a first drain electrode connected to the data wiring, wherein the second thin film transistor is connected to the second gate wiring and the second gate electrode. A second active layer formed on a second gate electrode, and a second active layer formed on both sides of the second gate electrode, and connected to the second source electrode and the data wiring connected to the second pixel electrode; An array substrate of a liquid crystal display device comprising drain electrodes. The method of claim 6, A gate insulating film is formed between the first gate electrode and the first active layer and between the second gate electrode and the second active layer, and the gate insulating film is an inorganic insulating material including silicon oxide and silicon nitride, or benzo An array substrate of a liquid crystal display device using one of an organic insulating material including cyclobutene (BCB) and acrylic resin. The method of claim 1, The protective layer is an array substrate of a liquid crystal display device using photoacryl.

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