KR102459724B1 - Liquid crystal display device - Google Patents

Abstract

The present invention provides a display device comprising: a substrate in which a display area including a plurality of divided areas in which pixels are arranged in horizontal and vertical directions and a non-display area around the display area are defined; a plurality of gate wirings extending in the horizontal direction to transmit a gate voltage to a corresponding pixel in the display area on the substrate; a common electrode formed in the display area on the substrate; a pixel electrode having a plurality of electrode patterns facing each other with the common electrode and an insulating layer interposed therebetween; display is provided.

Description

Liquid crystal display device

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of improving the uniformity of a common voltage by alleviating a variation in pixel voltage variation for each region within a display area of a liquid crystal panel.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms, and in recent years, a liquid crystal display device (LCD), a plasma display panel (PDP), and an organic Various flat display devices such as organic light emitting diode (OLED) display devices are being used.

Among these flat panel display devices, the liquid crystal display device is widely used because it has the advantages of miniaturization, weight reduction, thinness, and low power driving.

Recently, a GIP (gate-in panel) type gate driving circuit in which a gate driving circuit is directly formed on an array substrate of a liquid crystal panel has been used.

Such a GIP gate driving circuit is disposed in the non-display area outside the display area in the horizontal direction, and sequentially outputs the gate voltage to the gate wiring. The gate clock for generating such a gate voltage is transmitted along the vertical direction of the non-display area and is input to the gate driving circuit.

As the size of the liquid crystal panel on which the gate driving circuit is formed increases and the bezel becomes narrower, a load deviation occurs for each area within the display area, and as a result, gate signals such as gate clock and gate voltage The delay causes a deviation in the amount of attenuation for each area.

Accordingly, the variation of the pixel voltage variation ΔVp for each region is generated within the display region, and thus the optimal common voltage value is different for each region, thereby lowering the uniformity of the common voltage in the display region.

As a result, such a reduction in the uniformity of the common voltage causes flicker and the like, and thus the image quality is deteriorated.

An object of the present invention is to provide a method for improving the uniformity of the common voltage by alleviating the variation in the pixel voltage variation for each area within the display area of a liquid crystal panel.

In order to achieve the above object, the present invention provides a substrate including a display area including a plurality of divided areas in which pixels are arranged in horizontal and vertical directions and a non-display area around the display area are defined; a plurality of gate wirings extending in the horizontal direction to transmit a gate voltage to a corresponding pixel in the display area on the substrate; a common electrode formed in the display area on the substrate; a pixel electrode having a plurality of electrode patterns facing each other with the common electrode and an insulating layer interposed therebetween; display is provided.

Here, the width of the electrode pattern of the pixel electrode may be different between the divided regions adjacent in the horizontal direction or the vertical direction.

The pixel electrode may include a connecting portion connecting one end of the plurality of electrode patterns, and an outer edge extending outward of the connecting portion, and an area of the outer edge of the pixel electrode between the divided regions adjacent to each other in a horizontal or vertical direction. These may be different from each other.

A width of an outer edge of the pixel electrode may be different between the divided regions adjacent in the horizontal direction or the vertical direction.

a gate driving circuit connected to the plurality of gate lines on the substrate in the non-display area; A transfer line extending in the vertical direction to transmit the gate clock to the gate driving circuit may be further included on the substrate of the non-display area.

An area of the pixel electrode between the divided regions adjacent in the horizontal or vertical direction may be inversely proportional to the magnitude of a load for the gate voltage between the divided regions.

The maximum deviation of the common voltage between the plurality of division regions may be less than 10 mV.

A common voltage deviation between the divided regions adjacent in the horizontal or vertical direction may be 10 mV or more when the areas of the pixel electrodes are the same.

In the present invention, the display area is divided into a plurality of divided areas according to the load deviation for the gate signal, and the area of the pixel electrode is differentiated for each divided area to differentiate the storage capacitor capacity.

Accordingly, as the variation in the pixel voltage variation between the divided regions is alleviated, the optimum common voltage variation is improved and common voltage uniformity is secured, thereby improving image quality such as flicker.

1 is a block diagram schematically showing a liquid crystal display device according to a first embodiment of the present invention.
2 is a circuit diagram schematically showing the structure of a pixel according to a first embodiment of the present invention;
3 is a plan view illustrating a pixel according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. 3 ;
5 is a diagram schematically illustrating a pixel structure in divided regions arranged in a horizontal direction in a display region of a liquid crystal panel according to a first embodiment of the present invention;
6 is a diagram schematically illustrating a pixel structure in divided regions arranged in a vertical direction in a display region of a liquid crystal panel according to a first embodiment of the present invention;
7 is a block diagram schematically showing a liquid crystal display device according to a second embodiment of the present invention.
8 is a diagram schematically illustrating a pixel structure in divided regions arranged in a horizontal direction in a display region of a liquid crystal panel according to a second embodiment of the present invention;
9 is a diagram schematically illustrating a pixel structure in divided regions arranged in a vertical direction in a display region of a liquid crystal panel according to a second embodiment of the present invention;
10 is a diagram illustrating experimental results for an optimal common voltage for each region in a storage capacitor differential structure for each region according to embodiments of the present invention;

Hereinafter, embodiments of the present invention will be described with reference to the drawings. On the other hand, in the following embodiment, the same and similar reference numerals are given to the same and similar components, and duplicate descriptions may be omitted.

<First embodiment>

1 is a block diagram schematically showing a liquid crystal display according to a first embodiment of the present invention, and FIG. 2 is a circuit diagram schematically showing a structure of a pixel according to a first embodiment of the present invention.

Referring to FIG. 1 , a liquid crystal display 10 according to an embodiment of the present invention includes a liquid crystal panel 100 , a data driving circuit 310 , a gate driving circuit 320 , and a timing control circuit 330 . may include

The liquid crystal panel 100 is a display panel that displays an image, and may include a display area AA, which is an area for displaying an image, and a non-display area NA, which is located around and surrounds the display area AA. .

In the display area AA of the liquid crystal panel 100 , pixels P are arranged in a matrix form along a plurality of row lines and column lines.

Such a liquid crystal panel 100 may include a liquid crystal layer and a first substrate 101 and a second substrate, which are two substrates face to face bonded to each other with the liquid crystal layer therebetween.

The first substrate 101 corresponds to, for example, a lower substrate or an array substrate, and an array element for driving the pixels P may be formed on the first substrate.

The second substrate, which is a substrate opposite to the first substrate 101, corresponds to, for example, an upper substrate or a color filter substrate, and includes a color filter pattern corresponding to each pixel P, and an array element surrounding the color filter pattern. A black matrix may be formed to cover the

On the other hand, in the liquid crystal panel 100 of this embodiment, the pixel electrode and the common electrode for driving the liquid crystal are formed on the first substrate 101 which is an array substrate, and is formed by a fringe field generated between the pixel electrode and the common electrode. A so-called AH-IPS (advanced high performance-IPS) type liquid crystal panel that drives the liquid crystal may be used.

At this time, based on each pixel (P), the common electrode is substantially formed in a plate shape on the entire surface of the corresponding pixel (P), and the pixel electrode is formed in a plurality of finger-shaped (or bar-shaped) electrode patterns to form a fringe field. can be configured to form.

The liquid crystal panel 100 (or the first substrate 101 ) has first to fourth outer sides L1 to L4 that are four outer sides defining its shape.

Here, for convenience of explanation, the outer edges located at the left end, the right end, the lower end, and the upper end (or the left, right, lower, upper side) in the drawing are referred to as first, second, third, and fourth outer sides (L1 to L4), respectively. do.

Meanwhile, the display area AA may be divided (or divided) into a plurality of divided areas (or partial areas).

In this regard, for example, the central area Am may be positioned in the center of the display area AA.

In addition, the first to fourth lateral regions As1 to As4 may be positioned on the left and right sides of the central region Am in the horizontal direction, and on the lower and upper sides of the central region Am, which are both sides in the vertical direction. On the other hand, for example, the first lateral region As1 contacting the left side thereof is located on the left side of the central region Am, and the second lateral region As2 contacting the right side thereof is located on the right side of the central region Am. The third lateral region As3 in contact with the lower side thereof may be located below the central region Am, and the fourth lateral region As4 in contact with the upper side thereof may be located above the central region Am. .

Also, first to fourth corner regions (or first to fourth diagonal regions) Ac1 to Ac4 may be positioned in each of the four diagonal directions of the central region Am. In contrast to this, for example, in the lower left diagonal direction (or in the first diagonal direction) of the central area Am, the first corner area Ac1 including the first corner of the display area AA is located, and the center area Am The second corner area Ac2 including the corresponding second corner of the display area AA is positioned in the lower diagonal direction (or the second diagonal direction) of the display area AA, and the upper left diagonal direction (or the third diagonal direction) of the central area Am. A third corner area Ac3 including a corresponding third corner of the display area AA is located in the upper and right diagonal directions (or a fourth diagonal direction) of the central area Am, and a corresponding fourth corner of the display area AA is located at A fourth corner area Ac4 including

As described above, the display area AA is a plurality of divided areas, and may be divided into a central area Am positioned at an inner central portion, lateral areas As1 to As4 and corner areas Ac1 to Ac4 surrounding the display area AA. have.

In this case, in each of the divided regions Am, As1 to As4, and Ac1 to Ac4, a plurality of pixels P may be arranged in a matrix form along a plurality of row lines and a plurality of column lines.

When the arrangement of the divided regions Am, As1 to As4, and Ac1 to Ac4 is divided based on the horizontal direction, which is the row direction, the central region Am and the third lower and upper portions of the central region Am in the horizontal direction are shown. , the four lateral regions As3 and As4 are arranged, and the first lateral region As1 and the lower and upper first and third corner regions Ac1 and Ac3 are arranged on the left side in the horizontal direction. On the right side, the second lateral region As2 and the second and fourth corner regions Ac2 and Ac4 below and above the second side region As2 are disposed.

In addition, when the arrangement of the divided areas Am, As1 to As4 and Ac1 to Ac4 is divided based on the vertical direction, which is the column direction, the central area Am and the first left and right sides of the central area Am in the vertical direction are shown. , 2 lateral regions As1 and As2 are disposed, and a third lateral region As3 and first and second corner regions Ac1 and Ac2 on the left and right sides thereof are disposed in the lower portion in the vertical direction, The fourth lateral region As4 and the third and fourth corner regions Ac3 and Ac4 on the left and right sides thereof are disposed on the upper portion.

As described above, the divided areas Am, As1 to As4, and Ac1 to Ac4 arranged at different positions in the display area AA have different load sizes based on the gate voltage and the gate signal such as the gate clock CLK. do. For this reason, more specifically, a deviation occurs in the attenuation due to the delay of the gate high voltage, and thus the variation in the pixel voltage variation ΔVp for each divided region, that is, between the divided regions, may also occur, resulting in a deviation in the common voltage.

In order to improve this, in the present embodiment, the storage capacitor Cst is differentiated for each divided area to alleviate the variation in the pixel voltage variation ΔVp. A detailed description of a specific method for adjusting the capacity of the storage capacitor Cst for each area will be described later.

Referring to FIG. 2 together, each pixel P disposed in the display area AA of the liquid crystal panel 100 includes a switching transistor Ts, a liquid crystal capacitor Clc, and a storage capacitor Cst. can

The gate electrode of the switching transistor Ts may be connected to the gate line GL of the corresponding row line, and the source electrode may be connected to the data line DL of the corresponding column line.

The liquid crystal capacitor Clc is formed in each pixel P and is connected to the drain electrode of the switching transistor Ts to receive a data voltage, that is, a pixel voltage, a pixel electrode, a common electrode to which a common voltage is applied, a pixel electrode and It may be composed of a liquid crystal layer positioned between the common electrodes.

The liquid crystal layer of the liquid crystal capacitor Clc is driven by an electric field generated between the pixel electrode and the common electrode so that transmittance can be adjusted.

The storage capacitor Cst is connected to the pixel electrode of the liquid crystal capacitor Clc and the drain electrode of the switching transistor Ts. The storage capacitor Cst performs a function of maintaining the data voltage applied to the pixel electrode of the liquid crystal capacitor Clc until the data voltage of the next frame is applied.

In this case, the storage capacitor Cst is formed by an overlapping portion between the common electrode and the pixel electrode in the corresponding pixel P.

The data driving circuit 310 receives digital image data and a data control signal from the timing control circuit 330, and in response to the data control signal, converts the image data into an analog data voltage and outputs it to each data line DL. .

The data driving circuit 310 may include at least one driving IC, but is not limited thereto. Further, the data driving circuit 310 may be mounted on one edge of the array substrate 101 of the liquid crystal panel 100 in a chip on glass (COG) method, but is not limited thereto.

The data driving circuit 310 may be located, for example, at the lower end of the liquid crystal panel 100 , and in this case, the data voltage is transmitted in a vertical direction from the lower end to the upper end.

The gate driving circuit 320 receives a gate control signal from the timing control circuit 330 and sequentially outputs a gate voltage to the gate wiring GL.

In this regard, for example, the gate lines GL may be sequentially driven along an upper vertical direction that is a data voltage transmission direction.

The gate driving circuit 320 may include a plurality of stages connected to each of the plurality of gate lines GL to output a corresponding gate voltage, and the plurality of stages may be arranged in a vertical direction.

The gate control signal is a control signal supplied to the gate driving circuit 320 for outputting the gate voltage, for example, a start pulse, an initialization pulse, an n-phase shift clock (n is an integer of 2 or more), that is, a gate clock (CLK). and the like.

Such a gate driving circuit 320 may be configured in a GIP method, and may be directly formed in the non-display area NA of the array substrate 101 .

In this case, the gate driving circuit 320 is formed by the same process as the process of forming the array elements of the display area AA.

The gate driving circuit 320 may be formed in at least one side of the non-display area NA in the horizontal direction that is the extension direction of the gate line GL.

In this embodiment, a case in which the gate driving circuits 320 are respectively formed on both sides of the display area AA in the horizontal direction is taken as an example. In this case, the two gate driving circuits 320 positioned on the left and right sides, respectively, are referred to as first and second gate driving circuits 320a and 320b.

As such, when the gate driving circuits 320 are formed on both sides of the display area AA, the gate voltage applied to each gate line GL can be transferred to the inside of the display area AA from both left and right sides, so that the gate voltage signal attenuation can be alleviated.

On the other hand, in the non-display area NA in which the gate driving circuit 320 is formed, the transfer line TL for transmitting the gate control signal including the gate clock CLK is provided in the vertical direction in which the gate driving circuit 320 extends. It may be formed to extend along the

Accordingly, the gate clock CLK may be transmitted in the upper vertical direction through the corresponding transmission line TL and input to the corresponding stage of the gate driving circuit 320 . The stage outputs the gate clock CLK input at the corresponding output timing, and accordingly, the gate voltage, that is, the gate high voltage, can be output to the corresponding gate line GL.

The transmission wiring TL may include first and second transmission wirings TL1 and TL2 connected to correspond to the first and second gate driving circuits 320a and 320b, respectively.

The timing control circuit 330 receives, for example, a timing signal and digital image data from an external host system through an interface such as a low voltage differential signaling (LVDS) interface or a transition minimized differential signaling (TMDS) interface.

Using the input timing signal as described above, the timing control circuit 330 generates a data control signal and a gate control signal, respectively, and outputs them to the data driving circuit 310 and the gate driving circuit 320 , respectively. Then, the timing control circuit 330 processes the input image data and outputs it to the data driving circuit 310 .

Hereinafter, the structure of the pixel according to the first embodiment of the present invention will be described in more detail with reference to FIGS. 3 and 4 .

3 is a plan view illustrating a pixel according to an exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. 3 .

Referring to FIGS. 3 and 4 together with FIGS. 1 and 2 , each pixel P has a switching transistor Ts formed on the first substrate 101 , which is the array substrate 101 .

In this regard, in the pixel P, the gate electrode 121 is formed on the inner surface of the first substrate 101 . Meanwhile, when the gate electrode 121 is formed, a gate line GL connected thereto may be formed.

The gate insulating layer 130 is formed on the gate electrode 121 substantially along the entire surface of the first substrate 101 .

A semiconductor layer 131 is formed on the gate insulating layer 130 . In this case, the semiconductor layer 131 may be formed of amorphous silicon, polycrystalline silicon, an oxide semiconductor, or the like.

In addition, a source electrode 133 and a drain electrode 135 spaced apart from each other are formed on the semiconductor layer 131 . Meanwhile, when the source electrode 133 and the drain electrode 135 are formed, a data line DL connected to the source electrode 133 may be formed.

The switching transistor Ts of the pixel P may include the gate electrode 121 , the semiconductor layer 131 , the source electrode 133 , and the drain electrode 135 arranged as above.

At least one passivation layer covering the switching transistors Ts may be formed substantially over the entire surface of the first substrate 101 .

In this regard, for example, the first passivation layer 141 and the second passivation layer 142 thereon may be stacked.

In this case, the first passivation layer 141 may be formed of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx). In addition, the second passivation layer 142 may be formed of an organic insulating material such as benzocyclobutene or photoacrylic.

A common electrode 150 may be formed on the second passivation layer 142 to substantially correspond to all of the pixels P disposed in the display area AA.

The common electrode 150 is made of a transparent conductive material such as ITO, and receives a common voltage.

On the common electrode 150 , a third passivation layer 151 may be formed substantially over the entire surface of the first substrate 101 .

The third passivation layer 151 may be formed of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx), or an organic insulating material such as benzocyclobutene or photoacrylic.

A patterned pixel electrode 155 for each pixel P may be formed on the third passivation layer 151 of the display area AA.

The pixel electrode 155 may be connected to the drain electrode 135 of the corresponding pixel P through the drain contact hole CH. In this case, the drain contact hole CH may be formed in the first, second, and third passivation layers 141 , 142 , and 151 .

Here, the pixel electrode 155 has a plurality of electrode patterns (finger-shaped (or bar-shaped) forming a fringe field facing the common electrode 150 located in the corresponding pixel P) ( 156) may be included.

An opening op may be formed between the plurality of electrode patterns.

Furthermore, the pixel electrode 155 may include connecting portions 157 and 158 commonly connected to the plurality of electrode patterns 156 .

In this regard, for example, it may include a first connector 157 connected to the upper end of the plurality of electrode patterns 156 and a second connector 158 connected to the lower end of the plurality of electrode patterns 156 . can

The pixel electrode 155 configured as described above may be overlapped with the common electrode 150 and the third passivation layer 151 interposed therebetween to form the storage capacitor Cst. In this regard, substantially the entire pixel electrode 155 may be overlapped with the common electrode 150 to be completely covered by the common electrode 150 , and accordingly, the storage capacitor Cst may be configured in the corresponding pixel P. can

At this time, as mentioned above, in the present embodiment, in order to alleviate the deviation of the pixel voltage variation ΔVp between the divided regions Am, As1 to As4 and Ac1 to Ac4, the divided regions Am, As1 to As4, The capacity of the storage capacitor (Cst) is differentiated in units of Ac1~Ac4).

In this regard, first, reference is made to Equation (1) below for the pixel voltage variation ΔVp.

Equation (1): ΔVp =

In Equation (1), Clc is the capacitance of the liquid crystal capacitor, Cst is the storage capacitor capacitance, Cgs is the gate-source parasitic capacitance of the switching transistor Ts, and ΔVg is the gate high applied to the switching transistor Ts. A voltage difference (or variation) (Vgh-Vgl) between the voltage Vgh and the gate low voltage Vgl.

According to Equation (1) above, when the gate high voltage Vgh to the gate low voltage Vgl is changed, the pixel voltage Vp, which is the data voltage applied to the pixel P, is applied to the capacitors formed in the pixel P. , a pixel voltage fluctuation amount ΔVp is generated in the pixel P.

At this time, since the load of the gate signal such as the gate clock CLK and the gate voltage is different in the display area AA of the liquid crystal panel 100 depending on the area, the attenuation rate of the gate high voltage Vgh for each area is different. do.

As a result, the pixel voltage variation ΔVp for each area has a deviation, and accordingly, the optimum common voltage for each area also has a deviation, thereby deteriorating the uniformity of the common voltage of the display area AA.

Here, when the deviation of the common voltage (or the pixel voltage variation ΔVp) is greater than or equal to a specific value, image quality defects such as flicker may be recognized.

In contrast, if, for example, a deviation of the common voltage (or the pixel voltage variation ΔVp) between regions is about 10 mV or more, the image quality defect may be recognized.

As such, in the present embodiment, as described above, the display area AA is divided into a plurality of divided areas Am, As1 to As4, and Ac1 to Ac4, and the storage capacitor Cst capacity is differentiated for each divided area. do.

Here, with respect to the criterion for dividing the divided areas, for example, when all the pixels P of the display area AA are based on a conventional structure having the same storage capacitor capacity, the adjacently arranged divided areas are The divided regions Am, As1 to As4, Ac1 to such that the difference in common voltage (or pixel voltage variation) between (Am, As1 to As4, and Ac1 to Ac4) is greater than or equal to a specific value at which image quality is recognized, for example, about 10 mV or more Ac4) can be distinguished and defined.

That is, based on the conventional structure, the common voltage of the adjacent divided regions Am, As1 to As4, and Ac1 to Ac4 may have a deviation of about 10 mV or more.

Meanwhile, in the present embodiment, a left-right symmetric structure in which the gate driving circuit 320 is disposed on the left and right sides is taken as an example. Loads are substantially the same between (Ac2, As2, and Ac4), so that the storage capacitor (Cst) may be configured to be substantially the same.

As such, by differentiating the capacitance of the storage capacitor Cst, it is possible to offset the deviation of the gate voltage variation ΔVg between the divided regions, and as a result, the deviation of the pixel voltage variation ΔVp between the divided regions can be alleviated.

In this regard, for example, with respect to the horizontal direction, since the gate voltage is transmitted in the inward direction from each of the left and right sides, the divided regions of the same vertical position (that is, the same row) arranged symmetrically on the left and right sides are used as an example. The first and second corner regions Ac1 and Ac2 disposed on the lower portion have a relatively low load, and thus the gate voltage variation ΔVg thereof is relatively high. has a relatively high load, so its gate voltage variation (ΔVg) is relatively low.

In contrast, the storage capacitor Cst capacity is relatively increased for the first and second corner regions Ac1 and Ac2 with relatively low loads to offset the relatively high gate voltage variation ΔVg in these regions. A relatively high pixel voltage variation ΔVp in this region is lowered.

On the contrary, the capacity of the storage capacitor Cst is relatively lowered for the third lateral region As3, which has a relatively high load, so that the relatively low gate voltage variation ΔVg of this region can be offset. As a result, a low pixel voltage variation ΔVp increases.

As such, in order to compensate for the deviation of the gate voltage variation ΔVg between the divided regions arranged adjacent to each other in the horizontal direction, the storage capacitor Cst capacity is differentiated for each region so as to be inversely proportional to the deviation, so that the pixel voltage fluctuation amount ΔVp ), the deviation between the partitions can be mitigated.

Similarly to the above, the storage capacitor Cst capacity is differentiated to compensate for the difference in the gate voltage variation ΔVg between the divided regions arranged adjacent to each other in the vertical direction.

In contrast, for example, the gate clock CLK, which is a signal generating the gate high voltage, is transmitted in the upper vertical direction, so the divided regions arranged at the lower, center, and upper sides of the same horizontal position (ie, the same column) are used as an example. In the third lateral region As3, the central region Am, and the fourth lateral region As4, the loads are sequentially increased, so that the gate voltage variation ΔVg for each region is relatively low. That is, the gate voltage fluctuation amount ΔVg corresponds to the reference as the central region Am is relatively approximately in the middle, the third lateral region As3 is relatively high, and the fourth lateral region As4 is relatively high. as low as

In contrast, on the basis of the storage capacitor Cst capacity of the central region Am, the storage capacitor Cst capacity is relatively lowered for the fourth lateral region As4, which has a relatively high load. Since the gate voltage fluctuation amount ΔVg can be offset, a relatively low pixel voltage fluctuation amount ΔVp in this region increases.

On the contrary, on the basis of the storage capacitor Cst capacity of the central area Am, the storage capacitor Cst capacity is relatively increased with respect to the third lateral area As3, which has a relatively low load. Since the gate voltage fluctuation amount ΔVg can be offset, a relatively high pixel voltage fluctuation amount ΔVp in this region is lowered.

Meanwhile, in the present embodiment, the width of the electrode pattern 156 of the pixel electrode 155 is differentiated in order to differentiate the capacity of the storage capacitor Cst for each region as described above.

For this, reference can be made to Equation (2) below.

Equation (2): Cst = ε*(S/d).

In Equation (2), ε is the dielectric constant of the third passivation layer 151 , S is the area of the pixel electrode 155 overlapping the common electrode 150 , and d is the common electrode 150 and the pixel electrode 155 . As a distance between them, it substantially corresponds to the thickness of the third passivation layer 151 .

According to Equation (2), it can be seen that Cst is proportional to the area of the pixel electrode 155 , and the area of the pixel electrode 155 depends on the width of the electrode pattern 156 .

As such, by adjusting the width of the electrode pattern 156 of the pixel electrode 155, it is possible to differentiate the storage capacitor Cst for each region.

In this regard, it will be described with reference to FIGS. 5 and 6 together.

5 is a diagram schematically illustrating a pixel structure in divided regions arranged in a horizontal direction in a display region of a liquid crystal panel according to a first embodiment of the present invention, and FIG. 6 is a liquid crystal display according to the first embodiment of the present invention. It is a diagram schematically illustrating a pixel structure in divided areas arranged in a vertical direction in a display area of a panel.

Here, for convenience of explanation, the divided areas arranged in the lower portion of the display area are illustrated as examples in FIG. 5 , and the divided areas arranged in the middle portion of the display area are illustrated as examples in FIG. 6 .

First, referring to FIG. 5 , in the lower portion of the display area AA, a corresponding area is formed in each of the first and second corner areas Ac1 and Ac2, which are divided areas at the same vertical position symmetrically disposed on the left and right sides. The first and second corner pixels Pc1 and Pc2 constituting the pixels are located. In addition, the third lateral pixel Ps3 which is a pixel constituting the third lateral region As3 disposed between the first and second corner regions Ac1 and Ac2 is positioned.

Here, the electrode pattern 156 of the pixel electrode 155 formed in each of the first and second corner pixels Pc1 and Pc2 has a first width W1.

In addition, the electrode pattern 156 of the pixel electrode 155 formed in the third side pixel Ps3 has a second width W2 .

At this time, the first width W1 of the electrode pattern 156 of the first and second corner pixels Pc1 and Pc2 is larger than the second width W2 of the electrode pattern 156 of the third side pixel Ps3. is formed

Accordingly, the storage capacitor Cst capacity of the first and second corner pixels Pc1 and Pc2 is relatively increased, and on the contrary, the storage capacitor Cst capacity of the third side pixel Ps3 is relatively decreased. .

For this reason, the storage capacitor Cst increases the capacity of the first and second corner pixels Ac1 and Ac2 with a relatively low load and high gate voltage fluctuation ΔVg, resulting in a lower pixel voltage fluctuation ΔVp. be able to Conversely, in the third side pixel As3 having a relatively high load and low gate voltage variation ΔVg, the storage capacitor Cst has a reduced capacity, and as a result, the pixel voltage variation ΔVp can be increased.

Accordingly, the deviation of the pixel voltage variation ΔVp between the divided regions adjacent in the horizontal direction can be alleviated.

Next, referring to FIG. 6 , the third lateral region As3, the central region Am, and the fourth lateral region as an example of the divided regions disposed on the lower side, the center, and the upper side of the same vertical position of the display region AA. A third side pixel Ps3, a central pixel Pm, and a fourth side pixel Ps4, which are pixels constituting the corresponding area, are located in each of the area As4.

Here, the electrode pattern 156 of the pixel electrode 155 formed in the third layer fire-proofing pixel Ps3 has a second width W2. The electrode pattern 156 of the pixel electrode 155 formed in the central pixel Pm has a third width W3. The electrode pattern 156 of the pixel electrode 155 formed in the fourth layer fire extinguishing pixel Ps4 has a fourth width W4.

In this case, the second width W2 of the electrode pattern 156 of the third side pixel Ps3 is formed to be larger than the third width W3 of the electrode pattern 156 of the central pixel Pm. And, the third width W3 of the electrode pattern 156 of the central pixel Pm is formed to be larger than the fourth width W4 of the electrode pattern 156 of the fourth side pixel Ps4.

Accordingly, based on the central pixel Pm, the storage capacitor Cst capacity of the third side pixel Ps3 is relatively increased, and on the contrary, the storage capacitor Cst capacity of the fourth side pixel Ps4 is will decrease relatively.

In other words, the capacity of the storage capacitor Cst for each area decreases in the upper vertical direction and increases in the lower vertical direction.

Accordingly, with respect to the central pixel Pm, the storage capacitor Cst capacity of the third side pixel As3 increases, and as a result, the pixel voltage fluctuation amount ΔVp may decrease. Conversely, with respect to the central pixel Pm, the storage capacitor Cst capacity of the fourth side pixel As4 decreases, and as a result, the pixel voltage variation ΔVp may increase.

Accordingly, the deviation of the pixel voltage variation ΔVp between the vertically adjacent divided regions can be alleviated.

By differentiating the width of the electrode pattern 156 of the pixel electrode 155 as described above, the deviation of the pixel voltage variation ΔVp between the horizontally and vertically adjacent divided regions can be alleviated.

Accordingly, the deviation of the pixel voltage variation ΔVp for each divided area is alleviated in the entire display area AA, so that the optimum common voltage deviation is improved, so that the common voltage uniformity can be secured and the image quality can be improved.

In this case, it is preferable to differentiate the storage capacitor capacity so that the maximum deviation of the common voltage is less than a specific value at which image quality degradation is recognized, for example, less than about 10 mV.

Here, the maximum common voltage deviation is the deviation between the minimum common voltage in the first and second corner regions Ac1 and Ac2 that is the division region of the minimum load and the maximum common voltage of the fourth side region As4 that is the division region of the maximum load. can mean

Meanwhile, in the display area AA division structure of the present embodiment, looking at the relationship between the load sizes for each area, the first and second corner areas Ac1 and Ac2 / the first and second side areas As1 and As2 / the third side area The load may increase in the order of (As3)/the third and fourth corner areas (Ac3, Ac4)/the central area (Am)/the fourth floor area (As4).

In this case, as described above, the uniformity of the common voltage can be improved by differentiating the storage capacitor capacity of the divided area so as to be inversely proportional to the size of the load.

<Second embodiment>

In the above-described first embodiment, the width of the electrode pattern of the pixel electrode is differentiated in implementing the storage capacitor capacity differentiation between the divided regions to ensure common voltage uniformity.

As another embodiment, in the second embodiment, the storage capacitor capacity between the divided regions is differentiated by extending the connection part of the pixel electrode to the outside and differentiating the area of the extended part.

In this regard, it will be described with reference to FIGS. 7 to 9 .

7 is a block diagram schematically illustrating a liquid crystal display device according to a second embodiment of the present invention. 8 is a diagram schematically illustrating a pixel structure in divided regions arranged in a horizontal direction in a display region of a liquid crystal panel according to a second embodiment of the present invention, and FIG. 9 is a second embodiment of the present invention. A diagram schematically illustrating a pixel structure in divided regions arranged in a vertical direction in a display region of a liquid crystal panel according to the present invention.

Here, Fig. 7 is substantially the same as Fig. 1 of the first embodiment, and Figs. 8 and 9 correspond to Figs. 5 and 6 of the first embodiment, respectively.

7 to 9 , the pixel electrode 155 of the pixel P configured in each of the divided areas Am, Ac1 to Ac4, As1 to As4 of the display area AA of the present embodiment is connected from one end of the connection part to the outside. An extended (or extended) outer edge 159 is further provided.

In this case, the outer edge portion 159 may be formed to extend outwardly from one end of the first connection portion 156 , for example. As another example, the outer edge portion 159 may be configured to extend outwardly from one end of the second connection portion 157 .

The area of the outer edge portion 159 may be differentiated for each divided region, and the area of the outer edge portion 159 may be differentiated, for example, by differentiating the width thereof.

In this regard, referring to FIG. 8 first, the lower portion of the display area AA corresponds to the first and second corner areas Ac1 and Ac2, which are divided areas at the same horizontal position symmetrically disposed on the left and right sides. The first and second corner pixels Pc1 and Pc2, which are pixels constituting the area, are located. In addition, the third lateral pixel Ps3 which is a pixel constituting the third lateral region As3 disposed between the first and second corner regions Ac1 and Ac2 is positioned.

Here, the outer edge 159 of the pixel electrode 155 formed in each of the first and second corner pixels Pc1 and Pc2 has a first width We1.

In addition, the outer edge 159 of the pixel electrode 155 formed in the third side pixel Ps3 has a second width We2.

In this case, the first width We1 of the outer edge portion 159 of the first and second corner pixels Pc1 and Pc2 is larger than the second width We2 of the outer edge portion 159 of the third side pixel Ps3. is formed

Accordingly, the storage capacitor Cst capacity of the first and second corner pixels Pc1 and Pc2 is relatively increased, and on the contrary, the storage capacitor Cst capacity of the third side pixel Ps3 is relatively decreased. .

For this reason, the storage capacitor Cst capacity of the first and second corner pixels Ac1 and Ac2 having a relatively low load and high gate voltage fluctuation amount ΔVg increases, and as a result, the pixel voltage fluctuation amount ΔVp may be lowered. there will be Conversely, in the third lateral pixel As3 having a relatively high load and low gate voltage fluctuation amount ΔVg, the storage capacitor Cst capacity decreases, and as a result, the pixel voltage fluctuation amount ΔVp may increase.

Accordingly, the deviation of the pixel voltage variation ΔVp between the divided regions adjacent in the horizontal direction can be alleviated.

Next, referring to FIG. 9 , the third lateral region As3, the central region Am, and the fourth lateral region as an example of the divided regions disposed on the lower side, the center, and the upper side of the same horizontal position of the display region AA. A third side pixel Ps3, a central pixel Pm, and a fourth side pixel Ps4, which are pixels constituting the corresponding area, are located in each of the area As4.

Here, the outer edge 159 of the pixel electrode 155 formed in the third side pixel Ps3 has a second width We2. The outer edge 159 of the pixel electrode 155 formed in the central pixel Pm has a third width We3 . The outer edge 159 of the pixel electrode 155 formed in the fourth side pixel Ps4 has a fourth width We4.

In this case, the second width We2 of the outer edge portion 159 of the third side pixel Ps3 is formed to be larger than the third width We3 of the outer edge portion 159 of the central pixel Pm. In addition, the third width We3 of the outer edge portion 159 of the central pixel Pm is formed to be larger than the fourth width We4 of the outer edge portion 159 of the fourth lateral pixel Ps4.

Accordingly, based on the central pixel Pm, the storage capacitor Cst capacity of the third side pixel Ps3 is relatively increased, and on the contrary, the storage capacitor Cst capacity of the fourth side pixel Ps4 is relatively decreased.

In other words, the capacity of the storage capacitor Cst decreases in the upper vertical direction and increases in the lower vertical direction.

Accordingly, with respect to the central pixel Pm, the storage capacitor Cst capacity of the third side pixel As3 increases, and as a result, the pixel voltage fluctuation amount ΔVp may decrease. On the contrary, the capacity of the storage capacitor Cst is decreased in the fourth side pixel As4 based on the central pixel Pm, and as a result, the pixel voltage variation ΔVp may be increased.

Accordingly, the deviation of the pixel voltage variation ΔVp between the vertically adjacent divided regions can be alleviated.

As described above, by additionally forming the outer edge portion 159 on the pixel electrode 155 and differentiating the width thereof, the deviation of the pixel voltage variation ΔVp between the horizontally and vertically adjacent divided regions can be alleviated.

Accordingly, the deviation of the pixel voltage variation ΔVp between the divided areas in the entire display area AA is alleviated, so that the deviation of the optimum common voltage is improved, so that the common voltage uniformity can be secured and the image quality can be improved.

In this case, it is preferable to differentiate the capacity of the storage capacitor so that the maximum deviation of the common voltage is less than a specific value at which image quality degradation is recognized, for example, less than about 10 mV.

10 is a diagram illustrating experimental results for an optimal common voltage for each region in a storage capacitor differential structure for each region according to embodiments of the present invention.

In FIG. 10, the common voltage for each region in the same structure for each region of the conventional storage capacitor is displayed in black, and the common voltage for each region in the differential structure for each storage capacitor region of the embodiments of the present invention is displayed in red. .

On the other hand, in this simulation, the storage capacitor capacity of the conventional structure is approximately equal to about 408.4f in all partitions. And, in the structure of this embodiment, the storage capacitor capacity for each partition is about 408.4f for As4, about 412.2f for Am, about 414.9f for Ac3 and Ac4, about 419.4f for As1 and As2, and about 417.3f for As3, Ac1 and Ac2 are differentiated by approximately 426.4f.

Referring to FIG. 10 , in the conventional structure, the optimum common voltage deviation between horizontally and vertically adjacent divided regions is approximately 10mV or more, and the maximum common voltage deviation is approximately 29mV (that is, the deviation between the As4 region and the Ac1 region). Very large. Accordingly, image quality defects such as flicker occur in the entire display area.

On the other hand, in the structures of the present embodiments, the optimum common voltage deviation between the horizontally and vertically adjacent divided regions is generally less than 1 mV, and the maximum deviation of the common voltage is very large, about 1 mV. Accordingly, the uniformity of the common voltage is ensured throughout the display area, thereby improving image quality.

As described above, according to the embodiments of the present invention, the display area is divided into a plurality of divided areas according to the load deviation with respect to the gate signal, and the area of the pixel electrode is differentiated for each divided area to differentiate the storage capacitor capacity.

Accordingly, as the variation in the pixel voltage variation between the divided regions is alleviated, the optimum common voltage variation is improved and common voltage uniformity is secured, thereby improving image quality such as flicker.

The above-described embodiment of the present invention is an example of the present invention, and free modifications are possible within the scope included in the spirit of the present invention. Accordingly, the present invention includes modifications of the present invention provided they come within the scope of the appended claims and their equivalents thereto.

10: liquid crystal display device 100: liquid crystal panel
101: first substrate 121: gate electrode
130: gate insulating layer 131: semiconductor layer
133: source electrode 133: drain electrode
141: first protective film 142: second protective film
150: common electrode 151: third protective film
155: pixel electrode 156: electrode pattern
157: first connection part 158: second connection part
159: outer edge 310: data driving circuit
320: gate driving circuit 330: timing control circuit
P: pixel
GL: gate wiring
DL: data wiring
TL: transmission wiring
Ts: switching transistor
Clc: liquid crystal capacitor
Cst: storage capacitor
L1 to L4: first to fourth outer edges
AA: display area
NA: non-display area
Am: central area
Ac1 to Ac4: first to fourth corner regions
As1 to As4: first to fourth lateral regions

Claims (11)

A substrate comprising: a substrate in which a display area including a plurality of divided areas in which pixels are arranged in a horizontal direction and a vertical direction and a non-display area around the display area are defined;
a plurality of gate wirings extending in the horizontal direction to transmit a gate voltage to a corresponding pixel in the display area on the substrate;
a common electrode formed in the display area on the substrate;
A pixel electrode having a plurality of electrode patterns facing each other with the common electrode and an insulating layer interposed therebetween in the pixel
including,
The area of the pixel electrode is different between the divided regions adjacent in the horizontal direction or the vertical direction.
liquid crystal display.
The method of claim 1,
The width of the electrode pattern of the pixel electrode is different between the divided regions adjacent in the horizontal direction or the vertical direction.
liquid crystal display.
The method of claim 1,
The pixel electrode includes a connection portion connecting one end of the plurality of electrode patterns, and an outer edge portion extending outwardly of the connection portion,
The area of the outer edge of the pixel electrode is different between the divided regions adjacent in the horizontal direction or the vertical direction.
liquid crystal display.
4. The method of claim 3,
Between the divided regions adjacent in the horizontal or vertical direction, the width of the outer edge of the pixel electrode is different from each other.
liquid crystal display.
The method of claim 1,
a gate driving circuit connected to the plurality of gate lines on the substrate in the non-display area;
a transfer line extending in the vertical direction on the substrate of the non-display area to transmit the gate clock to the gate driving circuit
A liquid crystal display further comprising a.
6. The method according to any one of claims 1 to 5,
The area of the pixel electrode between the divided regions adjacent in the horizontal or vertical direction is inversely proportional to the magnitude of the load for the gate voltage between the divided regions.
liquid crystal display.
6. The method according to any one of claims 1 to 5,
The maximum deviation of the common voltage between the plurality of divisions is less than 10mV.
liquid crystal display.
6. The method according to any one of claims 1 to 5,
Between the divided regions adjacent in the horizontal or vertical direction, when the area of the pixel electrode is the same, a common voltage deviation is 10 mV or more.
liquid crystal display. The method of claim 1,
The capacity of the storage capacitor of the pixel is different between the divided areas adjacent to each other in the horizontal or vertical direction.
liquid crystal display.
10. The method of claim 9,
The capacity of the storage capacitor of the pixel between the divided regions adjacent in the horizontal or vertical direction is inversely proportional to the magnitude of the load for the gate voltage between the divided regions.
liquid crystal display.
The method of claim 1,
Each of the plurality of division areas includes a plurality of pixels arranged in a matrix form along the vertical and horizontal directions.
liquid crystal display.

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