JP4556828B2 - Method for manufacturing electrode structure - Google Patents

Method for manufacturing electrode structure Download PDF

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JP4556828B2
JP4556828B2 JP2005287046A JP2005287046A JP4556828B2 JP 4556828 B2 JP4556828 B2 JP 4556828B2 JP 2005287046 A JP2005287046 A JP 2005287046A JP 2005287046 A JP2005287046 A JP 2005287046A JP 4556828 B2 JP4556828 B2 JP 4556828B2
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film
electrode film
electrode
paste
antioxidant
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JP2007096231A (en
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泰徳 二宮
真志 都外川
学 富坂
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Denso Corp
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Description

本発明は、Ａｌ（アルミニウム）よりなるＡｌ電極膜の表面上に、Ａｕ（金）よりなるＡｕ膜を形成してなる電極構造体の製造方法に関する。   The present invention relates to a method for manufacturing an electrode structure in which an Au film made of Au (gold) is formed on the surface of an Al electrode film made of Al (aluminum).

ＡｌよりなるＡｌ電極膜の表面上に、ＡｕよりなるＡｕ膜を形成してなる電極構造体は、たとえば、半導体基板上へワイヤボンディングを行うためのパッドなどに用いられる。ここで、Ａｌ電極膜の表面上にＡｕ膜を形成するのは、ワイヤボンディング性を確保したり、Ａｌ電極膜の表面の腐食を防止するためである。   An electrode structure formed by forming an Au film made of Au on the surface of an Al electrode film made of Al is used, for example, as a pad for performing wire bonding on a semiconductor substrate. Here, the reason why the Au film is formed on the surface of the Al electrode film is to ensure wire bonding and to prevent corrosion of the surface of the Al electrode film.

従来では、このような電極構造体は、基板上にスパッタなどによりＡｌ電極膜を形成した後、その上へメッキ法によってＡｕ膜を形成することにより製造されていた（たとえば、非特許文献１参照）。
エレクトロニクス実装学会誌、Ｖｏｌ．８、Ｎｏ４（２００５）、Ｐ．３３０ Conventionally, such an electrode structure has been manufactured by forming an Al electrode film on a substrate by sputtering or the like and then forming an Au film thereon by plating (see, for example, Non-Patent Document 1). ).
Journal of Japan Institute of Electronics Packaging, Vol. 8, No 4 (2005), p. 330

しかしながら、Ａｌ電極膜の表面上へＡｕ膜を形成する場合、従来のメッキ法では、装置が大がかりであり、また、廃液処理に手間がかかるという問題がある。   However, when the Au film is formed on the surface of the Al electrode film, the conventional plating method has a problem that the apparatus is large and the waste liquid treatment is troublesome.

そこで、本発明者は、Ａｕよりなる粒子を含有するペーストすなわちＡｕペーストを用いてＡｕ膜を形成することを考えた。この場合、基板の上に形成されたＡｌ電極膜の表面上に、Ａｕペーストを塗布し、このペーストを焼成することによりＡｕ膜を形成する。   Therefore, the present inventor considered forming an Au film using a paste containing particles made of Au, that is, an Au paste. In this case, an Au paste is applied on the surface of the Al electrode film formed on the substrate, and the Au film is formed by baking this paste.

ここにおいて、Ａｌ電極膜の形成後には、酸化されやすいＡｌの特性上、Ａｌ電極膜の表面にはアルミナからなる酸化膜が存在するため、ペースト塗布の前には、従来のメッキ法と同様に、Ａｌ電極膜の表面に存在する酸化膜をエッチング等で除去する。そして、Ａｕペーストの塗布は、再びＡｌ電極膜の表面が酸化されないように、真空中で行うことになる。   Here, after the formation of the Al electrode film, an oxide film made of alumina exists on the surface of the Al electrode film due to the characteristics of Al that is easily oxidized. Therefore, before applying the paste, it is the same as the conventional plating method. Then, the oxide film present on the surface of the Al electrode film is removed by etching or the like. Then, the Au paste is applied in a vacuum so that the surface of the Al electrode film is not oxidized again.

しかしながら、Ａｕペーストの塗布を真空中で行うことは、非常に手間がかかるものであり、従来のメッキ法に対するコスト面などの優位性を確保するためには、大気中でＡｕペーストの塗布を行う必要がある。   However, it is very time-consuming to apply the Au paste in a vacuum, and in order to ensure cost advantages over the conventional plating method, the Au paste is applied in the air. There is a need.

しかし、大気中でＡｕペーストの塗布を行う場合、せっかく酸化膜を除去したＡｌ電極膜を再び大気にさらすことになるため、Ａｌ電極膜の表面に再び酸化膜が形成されてしまい、ＡｕペーストとＡｌ電極膜との導通性が阻害されてしまう。   However, when the Au paste is applied in the atmosphere, the Al electrode film from which the oxide film has been removed is exposed to the atmosphere again, so that an oxide film is formed again on the surface of the Al electrode film, Conductivity with the Al electrode film is hindered.

本発明は、上記問題に鑑みてなされたものであり、大気中にてＡｌ電極膜の上に、Ａｕペーストを塗布してＡｕ膜を形成するにあたって、Ａｌ電極膜の表面の酸化を防止できるようにすることを目的とする。   The present invention has been made in view of the above problems, and can prevent oxidation of the surface of the Al electrode film when the Au film is formed on the Al electrode film by applying Au paste in the atmosphere. The purpose is to.

本発明者は、ペーストの塗布前に、Ａｌ電極膜の表面の酸化膜を除去し、さらにその表面にＡｌの酸化を防止する膜を設ければ酸化防止は行えると考えた。   The present inventor considered that the oxidation could be prevented by removing the oxide film on the surface of the Al electrode film before applying the paste and further providing a film for preventing the oxidation of Al on the surface.

しかし、その場合、その膜がＡｕ膜の形成後にＡｌ電極膜とＡｕ膜との間に介在すると、Ａｌ電極膜とＡｕ膜との導通性が阻害されてしまう。これらの点に着眼して、本発明を創出するに至った。   However, in that case, if the film is interposed between the Al electrode film and the Au film after the formation of the Au film, the continuity between the Al electrode film and the Au film is hindered. Focusing on these points, the present invention has been created.

すなわち、本発明は、Ａｌ電極膜（１２）の表面の酸化膜（３０）を除去するとともに、当該表面上に、ペースト（５０）の焼成時に当該表面から少なくとも一部が除去される酸化防止膜（４０）を形成し、次に、大気中にて酸化防止膜（４０）の上にペースト（５０）の塗布を行い、続いて、ペースト（５０）の焼成を行うことを特徴とする。   That is, the present invention removes the oxide film (30) on the surface of the Al electrode film (12) and at least partially removes the antioxidant film on the surface from the surface when the paste (50) is baked. (40) is formed, and then the paste (50) is applied on the antioxidant film (40) in the atmosphere, and then the paste (50) is fired.

ここで、酸化防止膜（４０）は、ペースト（５０）の焼成時に全部除去されてもよいが、一部のみ除去されてもよい。   Here, the antioxidant film (40) may be completely removed during baking of the paste (50), or only a part thereof may be removed.

それによれば、大気中でのペースト（５０）の塗布時に、酸化防止膜（４０）によりＡｌ電極膜（１２）の表面が酸素から遮断されるとともに、ペースト（５０）の焼成時には、酸化防止膜（４０）の一部もしくは全部が除去され当該除去された領域にてＡｕ膜（１４）とＡｌ電極膜（１２）との導通性が確保される。   According to this, the surface of the Al electrode film (12) is shielded from oxygen by the antioxidant film (40) at the time of applying the paste (50) in the atmosphere, and the antioxidant film at the time of baking the paste (50). Part or all of (40) is removed, and the conductivity between the Au film (14) and the Al electrode film (12) is secured in the removed region.

そのため、本発明によれば、大気中にてＡｌ電極膜（１２）の上に、Ａｕペースト（５０）を塗布してＡｕ膜（１４）を形成するにあたって、Ａｌ電極膜（１２）の表面の酸化を防止することができる。   Therefore, according to the present invention, when forming the Au film (14) by applying the Au paste (50) on the Al electrode film (12) in the atmosphere, the surface of the Al electrode film (12) Oxidation can be prevented.

なお、特許請求の範囲およびこの欄で記載した各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示す一例である。   In addition, the code | symbol in the bracket | parenthesis of each means described in the claim and this column is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.

以下、本発明の実施形態について図に基づいて説明する。なお、以下の各図相互において、互いに同一もしくは均等である部分には、説明の簡略化を図るべく、図中、同一符号を付してある。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, parts that are the same or equivalent to each other are given the same reference numerals in the drawings for the sake of simplicity.

図１は、本発明の実施形態に係る電極構造体の概略断面構成を示す図である。本実施形態の電極構造体は、圧力センサや加速度センサ、角速度センサなどのセンサ素子におけるワイヤボンディングのパッドとして適用されるものである。   FIG. 1 is a diagram showing a schematic cross-sectional configuration of an electrode structure according to an embodiment of the present invention. The electrode structure of this embodiment is applied as a wire bonding pad in a sensor element such as a pressure sensor, an acceleration sensor, or an angular velocity sensor.

基板としての半導体基板１０は、シリコン半導体基板などからなるもので、この半導体基板１０には、図示しない圧力や加速度などの力学量に応じた信号を出力するセンサ素子が形成されている。   The semiconductor substrate 10 as a substrate is made of a silicon semiconductor substrate or the like, and a sensor element that outputs a signal corresponding to a mechanical quantity such as pressure or acceleration (not shown) is formed on the semiconductor substrate 10.

図１に示されるように、半導体基板１０の表面上にはＳｉＮなどで構成された絶縁膜１１が形成されている。この絶縁膜１１の表面にはＡｌよりなるＡｌ電極膜１２が形成されている。   As shown in FIG. 1, an insulating film 11 made of SiN or the like is formed on the surface of the semiconductor substrate 10. An Al electrode film 12 made of Al is formed on the surface of the insulating film 11.

ここで、Ａｌ電極膜１２を構成するＡｌは、Ａｌ単体でもよいが、Ａｌを主成分、具体的には５０％以上含むＡｌ合金もしくは混合物であってもよい。このＡｌ電極膜１２は、絶縁膜１１に形成された図示しないコンタクトホールを通じて上記センサ素子の所望部位と電気的に接続された構造となっている。   Here, Al constituting the Al electrode film 12 may be Al alone, or may be an Al alloy or a mixture containing Al as a main component, specifically, 50% or more. The Al electrode film 12 has a structure that is electrically connected to a desired portion of the sensor element through a contact hole (not shown) formed in the insulating film 11.

また、Ａｌ電極膜１２および絶縁膜１１の上には、ＳｉＮやＳｉＯ2などよりなる保護膜１３が形成されており、この保護膜１３に形成された開口部１３ａから、Ａｌ電極膜１２の中央部が露出している。 Further, a protective film 13 made of SiN, SiO 2 or the like is formed on the Al electrode film 12 and the insulating film 11, and the center of the Al electrode film 12 is formed from the opening 13 a formed in the protective film 13. The part is exposed.

そして、この開口部１３ａから露出するＡｌ電極膜１２の表面上には、耐腐食性を有するＡｕよりなるＡｕ膜１４が形成されている。ここで、このＡｕ膜１４を構成するＡｕは、Ａｕ単体でもよいが、Ａｕを主成分、具体的には５０％以上含むＡｕ合金もしくは混合物であってもよい。   An Au film 14 made of Au having corrosion resistance is formed on the surface of the Al electrode film 12 exposed from the opening 13a. Here, Au constituting the Au film 14 may be Au alone, but may be an Au alloy or a mixture containing Au as a main component, specifically, 50% or more.

本例では、Ａｕ膜１４は、Ａｕよりなる粒子としてのＡｕのナノオーダ粒子を焼結させたものであり、Ａｕ膜１４とＡｌ電極膜１２とは、金属結合することにより、導通性が確保されている。なお、ナノオーダ粒子とは、平均粒径が５００ｎｍ以下のもので、好ましくは１００ｎｍ以下のものである。   In this example, the Au film 14 is obtained by sintering Au nano-order particles as particles made of Au. The Au film 14 and the Al electrode film 12 are electrically connected to each other to ensure conductivity. ing. The nano-order particles are those having an average particle size of 500 nm or less, preferably 100 nm or less.

そして、このＡｕ膜１４の表面に、ＡｕやＡｌなどからなるボンディングワイヤ２０が接合されている。それによって、ボンディングワイヤ２０が、Ａｕ膜１４およびＡｌ電極膜１２を介して、半導体基板１０に形成された上記センサ素子と電気的に接合された構造となっている。   A bonding wire 20 made of Au, Al, or the like is bonded to the surface of the Au film 14. As a result, the bonding wire 20 is electrically connected to the sensor element formed on the semiconductor substrate 10 via the Au film 14 and the Al electrode film 12.

次に、本実施形態の電極構造体の製造方法について説明する。図２は、本製造方法の工程図であり、各工程におけるワークを断面的に示している。なお、図２では、本製造方法の主要部である基板１０、Ａｌ電極膜１２、Ａｕ膜１４以外の絶縁膜１１および保護膜１３は省略してある。   Next, the manufacturing method of the electrode structure of this embodiment is demonstrated. FIG. 2 is a process diagram of the present manufacturing method, showing a cross-section of a workpiece in each process. In FIG. 2, the insulating film 11 and the protective film 13 other than the substrate 10, the Al electrode film 12, and the Au film 14, which are main parts of the manufacturing method, are omitted.

本実施形態の製造方法は、大きくは、半導体基板１０の上にＡｌ電極膜１２を形成し、このＡｌ電極膜１２の上に、Ａｕよりなる粒子を含有するペースト５０（以下、Ａｕペースト５０という）を塗布し、このＡｕペースト５０を焼成することによりＡｕ膜１４を形成するものである。   In the manufacturing method of this embodiment, an Al electrode film 12 is generally formed on a semiconductor substrate 10, and a paste 50 containing particles made of Au (hereinafter referred to as an Au paste 50) is formed on the Al electrode film 12. ) And the Au paste 50 is baked to form the Au film 14.

まず、従来から周知となっている手法によって半導体基板１０に対して上記センサ素子を作り込み、その後、半導体基板１０の表面上に上記絶縁膜１１を形成する。   First, the sensor element is formed on the semiconductor substrate 10 by a well-known method, and then the insulating film 11 is formed on the surface of the semiconductor substrate 10.

次に、図２（ａ）に示されるように、半導体基板１０の上に、スパッタなどによる成膜法およびフォトリソグラフなどによるパターニング法を用いて、Ａｌ電極膜１２を形成する（Ａｌ電極膜形成工程）。このＡｌ電極膜１２の膜厚は、たとえば１μｍ程度のものである。   Next, as shown in FIG. 2A, an Al electrode film 12 is formed on the semiconductor substrate 10 by using a film formation method such as sputtering and a patterning method such as photolithography (Al electrode film formation). Process). The thickness of the Al electrode film 12 is, for example, about 1 μm.

続いて、Ａｌ電極膜１２および絶縁膜１１の表面に保護膜１３を成膜したのち、フォトエッチング等を行うことで、保護膜１３のうちＡｌ電極膜１２のパッドとなる領域の上部に形成された部分を除去する。これにより、Ａｌ電極膜１２のパッドとなる領域が露出した状態となる（図１参照）。   Subsequently, after a protective film 13 is formed on the surfaces of the Al electrode film 12 and the insulating film 11, photoetching or the like is performed, so that the protective film 13 is formed on the upper portion of the region serving as the pad of the Al electrode film 12. Remove the part. As a result, a region to be a pad of the Al electrode film 12 is exposed (see FIG. 1).

この後、図２（ｂ）、（ｃ）に示されるように、Ａｌ電極膜１２の表面の酸化膜３０を除去するとともに、Ａｌ電極膜１２の表面上に酸化防止膜４０を形成する（酸化防止膜形成工程）。   Thereafter, as shown in FIGS. 2B and 2C, the oxide film 30 on the surface of the Al electrode film 12 is removed, and an antioxidant film 40 is formed on the surface of the Al electrode film 12 (oxidation). Prevention film forming step).

ここで、酸化膜３０は、Ａｌ電極膜１２の表面において、たとえば１０ｎｍ程度の膜厚で形成される層である。また、酸化防止膜４０は、Ａｌの酸化を抑制する機能を有し含まず且つＡｕペースト５０の焼成時に少なくとも一部がＡｌ電極膜１２の表面から除去されるものである。本例では、酸化防止膜４０は、Ａｌ電極膜１２の表面のＡｌとＦ（フッ素）との化合物であり、その膜厚は１０ｎｍ程度である。   Here, the oxide film 30 is a layer formed with a film thickness of, for example, about 10 nm on the surface of the Al electrode film 12. Further, the antioxidant film 40 does not include a function of suppressing oxidation of Al, and at least a part thereof is removed from the surface of the Al electrode film 12 when the Au paste 50 is baked. In this example, the antioxidant film 40 is a compound of Al and F (fluorine) on the surface of the Al electrode film 12, and the film thickness is about 10 nm.

この場合、酸化防止膜形成工程は、フッ素化合物のガスと不活性ガスとの混合ガスよりなるガス雰囲気中において、Ａｌ電極膜１２の表面に対してプラズマ処理を行うことにより、Ａｌ電極膜１２の表面の酸化膜３０を除去するとともに、Ａｌ電極膜１２の表面上に、酸化防止膜４０としてのＡｌとＦとの化合物を形成する。   In this case, the antioxidant film forming step is performed by performing plasma treatment on the surface of the Al electrode film 12 in a gas atmosphere composed of a mixed gas of a fluorine compound gas and an inert gas. The oxide film 30 on the surface is removed, and a compound of Al and F as the antioxidant film 40 is formed on the surface of the Al electrode film 12.

具体的には、ワークを図示しない並行平板のプラズマ処理装置のチャンバ内に設置し、フッ素化合物のガスとしてのフロロカーボン（ＣＦ4）などのガスと、窒素（Ｎ2）、アルゴン（Ａｒ）、ヘリウム（Ｈｅ）などの不活性ガスとの混合ガス雰囲気とした状態でＲＩＥ（反応性イオンエッチング）処理を行う。 Specifically, a workpiece is placed in a chamber of a parallel plate plasma processing apparatus (not shown), a gas such as fluorocarbon (CF 4 ) as a fluorine compound gas, nitrogen (N 2 ), argon (Ar), helium. RIE (reactive ion etching) is performed in a mixed gas atmosphere with an inert gas such as (He).

本例において、Ａｌ電極膜１２の表面に対してＲＩＥ処理を行う場合の処理条件を示す。窒素ガスの流量を４０ｓｃｃｍ、ＣＦ4ガスの流量を５ｓｃｃｍ、チャンバ内の圧力を１０Ｐａ、プラズマパワーを４００Ｗ、プラズマ照射時間を３０秒以上とする。 In this example, processing conditions for performing RIE processing on the surface of the Al electrode film 12 are shown. The flow rate of nitrogen gas is 40 sccm, the flow rate of CF 4 gas is 5 sccm, the pressure in the chamber is 10 Pa, the plasma power is 400 W, and the plasma irradiation time is 30 seconds or more.

このような酸化防止膜形成工程を行うことにより、図２（ｂ）、（ｃ）に示されるように、Ａｌ電極膜１２の表面において、プラズマのパワーにより酸化膜３０が除去され、Ａｌ電極膜１２の表面のＡｌとＦとが反応し、ＡｌとＦとの化合物からなる酸化防止膜４０が形成される。   By performing such an anti-oxidation film forming step, as shown in FIGS. 2B and 2C, the oxide film 30 is removed by the power of plasma on the surface of the Al electrode film 12, and the Al electrode film Al and F on the surface of 12 react to form an antioxidant film 40 made of a compound of Al and F.

次に、ワークを大気中に取り出し、図２（ｄ）に示されるように、大気中にて酸化防止膜４０の上に、Ａｕよりなる粒子を含むＡｕペースト５０の塗布を行う（ペースト塗布工程）。   Next, the work is taken out into the atmosphere, and as shown in FIG. 2D, an Au paste 50 containing particles made of Au is applied on the antioxidant film 40 in the atmosphere (paste application step). ).

本例では、Ａｕペースト５０は、上述したＡｕのナノオーダ粒子を含むものであり、このＡｕのナノオーダ粒子が、有機溶媒に混合されてなるものである。ここで、有機溶媒としては、通常、電子装置の分野で用いられる導電性ペーストに適用されるものが挙げられる。   In this example, the Au paste 50 includes the above-described Au nano-order particles, and the Au nano-order particles are mixed with an organic solvent. Here, as an organic solvent, what is applied to the electrically conductive paste normally used in the field | area of an electronic device is mentioned.

そして、このＡｕペースト５０は、インクジェット印刷を用いて、酸化防止膜４０の上に塗布される。なお、ペーストの粘度によっては、スクリーン印刷、ディスペンサ印刷等も使用可能である。   And this Au paste 50 is apply | coated on the antioxidant film | membrane 40 using inkjet printing. Depending on the viscosity of the paste, screen printing, dispenser printing, or the like can be used.

また、このＡｕペースト５０を塗布する際の塗布精度を上げたい場合には、半導体基板１０を加熱することが有効であるが、Ａｌ電極膜１２の酸化が進行するため、１００℃以下、望ましくは５０℃以下での加熱を行う。   In order to increase the application accuracy when applying the Au paste 50, it is effective to heat the semiconductor substrate 10. However, since the oxidation of the Al electrode film 12 proceeds, it is preferably 100 ° C. or lower, preferably Heating is performed at 50 ° C. or lower.

こうしてＡｕペースト５０の塗布を行った後、図２（ｅ）に示されるように、Ａｕペースト５０の焼成を行い、Ａｕ膜１４を形成する（焼成工程）。このとき、酸化防止膜４０の一部もしくは全部が、Ａｌ電極膜１２の表面から除去され、当該除去された領域にてＡｕ膜１４とＡｌ電極膜１２とが金属結合し、これら両膜１２、１４間の導通性が確保される。   After the application of the Au paste 50 in this way, as shown in FIG. 2E, the Au paste 50 is fired to form the Au film 14 (firing step). At this time, a part or all of the antioxidant film 40 is removed from the surface of the Al electrode film 12, and the Au film 14 and the Al electrode film 12 are metal-bonded in the removed region. The continuity between 14 is ensured.

この焼成は、窒素ガスや大気中にて行うが、望ましくは窒素ガス中で行う。焼成温度や時間は、酸化防止膜４０による導通性の阻害を低減し、所望の導通性が得られる程度に酸化防止膜４０を除去しうるような温度、時間とする。本例の場合、焼成温度は、３００℃〜５００℃程度であり、焼成時間は１５分〜１時間程度である。   This calcination is performed in nitrogen gas or air, but is preferably performed in nitrogen gas. The firing temperature and time are set to such a temperature and time that the inhibition of conductivity by the antioxidant film 40 is reduced and the antioxidant film 40 can be removed to the extent that desired conductivity is obtained. In the case of this example, the firing temperature is about 300 ° C. to 500 ° C., and the firing time is about 15 minutes to 1 hour.

こうして、焼成工程の終了に伴い、本実施形態の電極構造体ができあがる。この後、超音波ボンディングなどによってボンディングワイヤ２０をＡｕ膜１４の表面に接合することで、上記図１に示した電気的な接続構造が完成する。   Thus, the electrode structure of the present embodiment is completed with the end of the firing step. After that, the electrical connection structure shown in FIG. 1 is completed by bonding the bonding wire 20 to the surface of the Au film 14 by ultrasonic bonding or the like.

次に、上記図２に示した本例の製造方法について、本発明者の考えた推定メカニズムを示しつつ、その具体的な作用効果について述べる。図３は、上記製造方法における各膜の接合の推定メカニズムを示す図である。   Next, with respect to the manufacturing method of the present example shown in FIG. 2, the specific operation and effect will be described while showing the estimation mechanism considered by the present inventor. FIG. 3 is a diagram illustrating an estimation mechanism of bonding of each film in the manufacturing method.

図３（ａ）は、上記図２（ｂ）、（ｃ）に示される酸化防止膜形成工程を示し、図３（ｂ）は大気中での再酸化防止のメカニズムを示し、図３（ｃ）は上記図２（ｄ）に示されるペースト塗布工程を示し、図３（ｄ）および（ｅ）は、上記図２（ｅ）に示される焼成工程を示している。   3A shows the antioxidant film forming process shown in FIGS. 2B and 2C, and FIG. 3B shows the mechanism for preventing reoxidation in the atmosphere. ) Shows the paste application step shown in FIG. 2 (d), and FIGS. 3 (d) and 3 (e) show the firing step shown in FIG. 2 (e).

図３（ａ）に示されるように、窒素ガスとＣＦ4ガスとの混合ガス雰囲気においてプラズマ処理としてのＲＩＥ処理を行うと、窒素とＣＦ4はそれぞれ下記の化学式１に示されるように、イオン化する。 As shown in FIG. 3A, when RIE treatment as a plasma treatment is performed in a mixed gas atmosphere of nitrogen gas and CF 4 gas, nitrogen and CF 4 are ionized as shown in the following chemical formula 1, respectively. To do.

（化１）
Ｎ2 → ２Ｎ3+ 、 ＣＦ4 → Ｃ4+ ＋ ４Ｆ-
そして、これらのイオンがＡｌ電極膜１２の表面にアタックして、Ａｌ電極膜１２の表面の酸化膜（Ａｌ2Ｏ3）におけるＯ原子（酸素原子）を引き抜くとともに、空きとなったＯ原子のサイトにＦが置換し結合する。 (Chemical formula 1)
N 2 → 2N 3+, CF 4 → C 4+ + 4F -
Then, these ions attack the surface of the Al electrode film 12 to extract O atoms (oxygen atoms) in the oxide film (Al 2 O 3 ) on the surface of the Al electrode film 12, and the vacant O atoms. F replaces and binds to the site.

こうして、Ａｌ電極膜１２の表面のＡｌとＦとが反応し、図３（ｂ）に示されるように、ＡｌとＦとの化合物が形成される。   In this way, Al and F on the surface of the Al electrode film 12 react to form a compound of Al and F as shown in FIG.

そして、この化合物において、Ａｌ−Ｆの結合エネルギーは１４０ｋｃａｌ／ｍｏｌであり、Ａｌ−Ｏの結合エネルギー：１１５ｋｃａｌ／ｍｏｌよりも大きいことから、酸素（Ｏ2）が存在しても、Ｆ原子層によって、酸素とＡｌとの反応が抑制され、再酸化が防止されると考えられる。 In this compound, the binding energy of Al—F is 140 kcal / mol, and is larger than the binding energy of Al—O: 115 kcal / mol. Therefore, even if oxygen (O 2 ) is present, It is considered that the reaction between oxygen and Al is suppressed and reoxidation is prevented.

続いて、ペースト塗布工程では、図３（ｃ）に示されるように、Ａｕの粒子がＡｌとＦとの化合物の上に配置される。   Subsequently, in the paste application step, as shown in FIG. 3C, Au particles are arranged on the compound of Al and F.

そして、焼成工程では、図３（ｄ）に示されるように、焼成の熱により、Ａｌ−Ｆの結合が切れてＡｌ電極膜１２の表面からＦ原子が離脱もしくはＡｌ電極膜１２の内部に拡散する。そして、空きとなったＦ原子のサイトにＡｕ原子が置換され、図３（ｅ）に示されるように、Ａｕ−Ａｌ金属結合が形成されると考えられる。   Then, in the firing step, as shown in FIG. 3D, due to the heat of firing, the Al—F bond is broken and F atoms are detached from the surface of the Al electrode film 12 or diffused into the Al electrode film 12. To do. Then, it is considered that Au atoms are substituted at the vacant F atom sites, and Au—Al metal bonds are formed as shown in FIG.

この図３に示されるような推定メカニズムの検証を行った。まず、上記図３（ｂ）に示されるＦ原子層の形成について、ＸＰＳ表面分析により検証を行った。その結果を図４、図５に示す。   The estimation mechanism as shown in FIG. 3 was verified. First, the formation of the F atomic layer shown in FIG. 3B was verified by XPS surface analysis. The results are shown in FIGS.

この分析は、上記図２（ｂ）に示されるようにＡｌ電極膜１２の表面に酸化膜３０が形成された状態のものに対して、比較例として上記ＲＩＥ処理を行わなかったもの（ＲＩＥ処理なし）と、本実施形態としての上記ＲＩＥ処理を行ったもの（ＲＩＥ処理あり）について、Ａｌ電極膜１２の表面側から行った。   In this analysis, the oxide film 30 is formed on the surface of the Al electrode film 12 as shown in FIG. 2B, and the RIE process is not performed as a comparative example (RIE process). None) and those subjected to the RIE treatment as the present embodiment (with RIE treatment) were performed from the surface side of the Al electrode film 12.

図４は、ＲＩＥ処理なしのものについての分析結果、図５は、ＲＩＥ処理ありのものについての分析結果である。これら図４、図５において、横軸はＡｌ電極膜１２の表面からの深さ（単位：ｎｍ）であり、縦軸は元素量（単位：原子％）であり、白四角プロットは酸素、白丸プロットはＡｌ、黒丸プロットはフッ素である。   FIG. 4 shows the analysis results for those without RIE processing, and FIG. 5 shows the analysis results for those with RIE processing. 4 and 5, the horizontal axis represents the depth (unit: nm) from the surface of the Al electrode film 12, the vertical axis represents the element amount (unit: atomic%), and the white square plot represents oxygen and white circles. The plot is Al, and the black circle plot is fluorine.

図４に示されるように、比較例であるＲＩＥ処理なしのものでは、Ａｌ電極膜１２の表面にて酸素が約６０原子％、Ａｌが約４０原子％であり、その元素比から酸化膜３０としてのＡｌ2Ｏ3の存在を確認した。 As shown in FIG. 4, in the comparative example without RIE treatment, oxygen is about 60 atomic% and Al is about 40 atomic% on the surface of the Al electrode film 12, and the oxide film 30 is obtained from the element ratio. The presence of Al 2 O 3 was confirmed.

一方、図５に示されるように、本実施形態のＲＩＥ処理ありのものでは、Ａｌ電極膜１２の表面において、酸素は微量であり、ほとんど除去されており、その代わりに、フッ素が７０〜８０原子％と非常に多く検出されている。このことから、上記図３（ｂ）に示されるＦ原子層の形成、すなわち、Ａｌ−Ｆの化合物の存在を確認した。   On the other hand, as shown in FIG. 5, in the case of the present embodiment with RIE treatment, the surface of the Al electrode film 12 has a very small amount of oxygen and is almost removed. Instead, fluorine is 70-80. Very many atoms are detected. This confirmed the formation of the F atomic layer shown in FIG. 3B, that is, the presence of the Al—F compound.

次に、上記図３（ｂ）に示されるＦ原子層の形成による再酸化の防止効果について、同じくＸＰＳ表面分析により検証を行った。その結果を図６に示す。   Next, the effect of preventing reoxidation due to the formation of the F atomic layer shown in FIG. 3B was also verified by XPS surface analysis. The result is shown in FIG.

この分析は、上記図４、図５にて述べたのと同様に、比較例としてのＲＩＥ処理なしのものと、本実施形態としてのＲＩＥ処理ありのものとについて、Ａｌ電極膜１２の表面側から行い、その表面における酸素量を調査した。ここで、ＲＩＥ処理ありのものについては、処理直後のものと、処理後さらに常温で７日間放置した後のものについて分析を行った。   Similar to the analysis described above with reference to FIGS. 4 and 5, the analysis is performed on the surface side of the Al electrode film 12 for the comparative example without the RIE treatment and with the RIE treatment as the present embodiment. The amount of oxygen on the surface was investigated. Here, the analysis was performed on the sample with RIE treatment and the sample immediately after the treatment and after the treatment and after standing at room temperature for 7 days.

図６においては、ＲＩＥ処理なしのもの、ＲＩＥ処理直後のもの、常温７日放置後のもののそれぞれについて、Ａｌ電極膜１２の表面における酸素量（単位：原子％）を調べた結果を示している。   FIG. 6 shows the results of examining the oxygen amount (unit: atomic%) on the surface of the Al electrode film 12 for each of those without RIE treatment, those immediately after RIE treatment, and those after standing at room temperature for 7 days. .

なお、図６においては、もうひとつの比較例として、Ａｒ（アルゴン）プラズマによりＡｌ電極膜１２の表面の酸化膜３０を除去したものについて、処理直後、常温７日放置後にＡｌ電極膜１２の表面における酸素量を調べた結果も、白三角プロットとして並記してある。   In FIG. 6, as another comparative example, the surface of the Al electrode film 12 after removing the oxide film 30 on the surface of the Al electrode film 12 by Ar (argon) plasma immediately after treatment and standing at room temperature for 7 days. The results of examining the oxygen content in are also shown as white triangle plots.

図６において、Ａｒプラズマの比較例をみると、いったんＡｒプラズマによりＡｌ電極膜１２の表面の酸化膜３０を除去したとしても、大気にさらされた瞬間に、Ａｌ電極膜１２の表面は再酸化されてしまうことがわかる。   In the comparative example of Ar plasma in FIG. 6, even if the oxide film 30 on the surface of the Al electrode film 12 is once removed by Ar plasma, the surface of the Al electrode film 12 is re-oxidized at the moment of exposure to the atmosphere. It turns out that it will be done.

それに対して、本実施形態の酸化防止膜工程すなわちＲＩＥ処理を行ったものでは、ＲＩＥ処理直後のみならず、７日間という長期に渡って大気にさらされた場合であっても、Ａｌ電極膜１２の表面における酸素の増加は見られず、再酸化防止の効果が継続していることが確認された。   On the other hand, in the case of performing the antioxidant film process, that is, the RIE process of the present embodiment, not only immediately after the RIE process but also when exposed to the atmosphere for a long period of 7 days, the Al electrode film 12 No increase in oxygen was observed on the surface of the film, and it was confirmed that the effect of preventing reoxidation continued.

次に、上記図３（ｄ）に示されるＦ原子の除去とＡｕ原子の置換について、焼成温度による依存性を、同じくＸＰＳ表面分析により検証を行った。その結果を図７に示す。   Next, the dependence on the firing temperature on the removal of F atoms and the replacement of Au atoms shown in FIG. 3 (d) was also verified by XPS surface analysis. The result is shown in FIG.

この分析は、上記焼成工程において焼成温度を、２５０℃〜５００℃まで変えていき、そのときのＡｌ電極膜１２の表面におけるフッ素およびＡｕの元素量の変化を調査したものである。   In this analysis, the firing temperature was changed from 250 ° C. to 500 ° C. in the firing step, and changes in the element amounts of fluorine and Au on the surface of the Al electrode film 12 at that time were investigated.

図７においては、横軸に焼成温度（単位：℃）、縦軸に元素量（単位：原子％）を示しており、黒丸プロットはフッ素、白丸プロットはＡｕを示している。   In FIG. 7, the horizontal axis represents the firing temperature (unit: ° C.), the vertical axis represents the element amount (unit: atomic%), the black circle plot represents fluorine, and the white circle plot represents Au.

この図７に示されるように、焼成温度を上げるにしたがい、フッ素量が低下し、Ａｕ量が増加している。つまり、焼成温度が高いほど、Ａｌ電極膜１２の表面からのフッ素の除去、すなわちＡｌとＦとの化合物の除去が促進され、代わりにＡｕ原子が、Ａｌ電極膜１２の表面上に置換される。   As shown in FIG. 7, the amount of fluorine decreases and the amount of Au increases as the firing temperature is increased. That is, the higher the firing temperature, the more the fluorine removal from the surface of the Al electrode film 12, that is, the removal of the compound of Al and F is promoted, and instead, Au atoms are replaced on the surface of the Al electrode film 12. .

そして、この図７に示されるような関係を求めておくことにより、酸化防止膜４０としてのＡｌとＦとの化合物の除去量を見積もることができる。つまり、所望の導通性が得られる程度に酸化防止膜４０の除去が行える焼成温度を、求めることができる。   Then, by obtaining the relationship as shown in FIG. 7, the removal amount of the compound of Al and F as the antioxidant film 40 can be estimated. That is, the firing temperature at which the antioxidant film 40 can be removed to such an extent that desired conductivity is obtained can be obtained.

また、本発明者は、Ａｕペースト５０の焼成時に、酸化防止膜４０の少なくとも一部が除去され、当該除去された領域にてＡｕ膜１４とＡｌ電極膜１２との金属結合がなされていることを断面ＴＥＭ観察により確認している。   Further, the inventor has confirmed that at least a part of the antioxidant film 40 is removed when the Au paste 50 is baked, and the Au film 14 and the Al electrode film 12 are metal-bonded in the removed region. Is confirmed by cross-sectional TEM observation.

このような酸化防止膜４０の除去に伴うＡｕ膜１４とＡｌ電極膜１２との金属結合の形成によって、Ａｕ膜１４とＡｌ電極膜１２との導通性が確保されるが、その具体的な効果について、調査した。その結果を図８に示す。   The formation of the metal bond between the Au film 14 and the Al electrode film 12 along with the removal of the antioxidant film 40 assures electrical conductivity between the Au film 14 and the Al electrode film 12, but its specific effect Was investigated. The result is shown in FIG.

図８は、比較例としての上記ＲＩＥ処理なしのもの、本実施形態において焼成条件を３００℃、１時間で行ったもの、同じく本実施形態において焼成条件を５００℃、１５分で行ったもの、それぞれについて、Ａｌ膜１４とＡｌ電極膜１２との間の界面抵抗（単位：ｍΩ）を調べた結果を示す図である。   FIG. 8 shows a comparative example without the RIE treatment, in the present embodiment, the firing conditions were performed at 300 ° C. for 1 hour, and in the present embodiment, the firing conditions were performed at 500 ° C. for 15 minutes. It is a figure which shows the result of having investigated the interface resistance (unit: m (ohm)) between the Al film 14 and the Al electrode film 12 about each.

図８に示されるように、比較例に比べて、本実施形態のものは大幅に界面抵抗を低くできており、実用可能な導通性を確保できている。また、焼成条件を３００℃、１時間としたものは、Ａｌ電極膜１２の表面のフッ素量が２８原子％であり、焼成条件を５００℃、１５分としたものは、同フッ素量が６原子％であった。   As shown in FIG. 8, the interface resistance of the present embodiment can be greatly reduced compared to the comparative example, and practical conductivity can be secured. In addition, when the firing condition is 300 ° C. for 1 hour, the amount of fluorine on the surface of the Al electrode film 12 is 28 atomic%, and when the firing condition is 500 ° C. for 15 minutes, the amount of fluorine is 6 atoms. %Met.

つまり、上述したように、焼成温度が高いほど、酸化防止膜４０であるＡｌとＦとの化合物が多く除去され、代わりにＡｕ原子が置換されて、ＡｕとＡｌとの金属結合が多くなされるため、導通性が向上しているといえる。   In other words, as described above, the higher the baking temperature, the more the compound of Al and F that is the antioxidant film 40 is removed, and instead, Au atoms are replaced, and the metal bond between Au and Al is increased. Therefore, it can be said that the conductivity is improved.

さらに、本発明者は、この図８に示される各サンプルを用いて、Ａｕ膜１４とＡｌ電極膜１２との接合強度についても調査した。この接合強度の調査は、引っ張り強度により行った。   Furthermore, the present inventor also investigated the bonding strength between the Au film 14 and the Al electrode film 12 using each sample shown in FIG. This joint strength was investigated by the tensile strength.

図９は、その引っ張り強度試験の方法を示す図である。各サンプルについて、Ａｕ膜１４の表面に引張を行うためのナット６０をエポキシ系樹脂からなる接着剤７０により接着する。この接着剤７０とＡｕ膜１４との接着面積は、２ｍｍ□とする。そして、この状態で、ナット６０を引っ張り上げていき、引っ張り強度を求める。   FIG. 9 is a diagram showing a method of the tensile strength test. About each sample, the nut 60 for performing tension | tensile_strength on the surface of Au film | membrane 14 is adhere | attached with the adhesive agent 70 which consists of epoxy resin. The bonding area between the adhesive 70 and the Au film 14 is 2 mm □. In this state, the nut 60 is pulled up to obtain the tensile strength.

図１０は、上記図８に示される各サンプル、すなわち比較例としての上記ＲＩＥ処理なしのもの、本実施形態としての焼成条件を３００℃、１時間としたもの、焼成条件を５００℃、１５分としたもの、それぞれについて、引っ張り強度（単位：Ｎ／ｍｍ2）を調べた結果を示す図である。 FIG. 10 shows each sample shown in FIG. 8, that is, the sample without the RIE treatment as a comparative example, the firing conditions as this embodiment at 300 ° C. for 1 hour, and the firing conditions at 500 ° C. for 15 minutes. It is a figure which shows the result of having investigated the tensile strength (unit: N / mm < 2 >) about each.

図１０に示されるように、本実施形態のものでは、比較例に比べて大幅に引っ張り強度が向上している。ここで、比較例では、Ａｌ電極膜１２とＡｕ膜１４との界面にて剥離が発生したが、これは、この界面に酸化膜３０が介在しているため、その部分にて強度が弱くなっているためである。   As shown in FIG. 10, the tensile strength is significantly improved in the present embodiment as compared with the comparative example. Here, in the comparative example, peeling occurred at the interface between the Al electrode film 12 and the Au film 14, but this is because the oxide film 30 is interposed at this interface, and the strength is weakened at that portion. This is because.

それに対して、本実施形態のものでは、Ａｌ電極膜１２とＡｕ膜１４との界面では剥離は発生せず、問題はなかった。つまり、本実施形態は、導通性だけでなく接合強度の面でも効果があることがわかった。   On the other hand, in the present embodiment, no peeling occurred at the interface between the Al electrode film 12 and the Au film 14, and there was no problem. That is, it was found that this embodiment is effective not only in terms of conductivity but also in terms of bonding strength.

また、焼成条件を５００℃、１５分としたものは、焼成条件を３００℃、１時間としたものに比べて、引っ張り強度が向上している。前者の破壊形態は接着剤７０の破壊であり、後者の破壊形態はＡｕ膜１４自身の破壊であった。これは、前者は、後者よりも高い焼成温度としたことにより、Ａｕ膜１４の焼結が進行し、膜強度が向上したためと考えられる。   Moreover, the tensile strength is improved in the case where the baking conditions are 500 ° C. and 15 minutes compared to the case where the baking conditions are 300 ° C. and 1 hour. The former destruction mode was the destruction of the adhesive 70, and the latter destruction mode was the destruction of the Au film 14 itself. This is presumably because the former was set at a higher firing temperature than the latter, so that the sintering of the Au film 14 progressed and the film strength was improved.

以上述べてきたように、本実施形態の製造方法によれば、大気中でのＡｕペースト５０の塗布時に、酸化防止膜４０によりＡｌ電極膜１２の表面が酸素から遮断されるとともに、Ａｕペースト５０の焼成時には、酸化防止膜４０の一部もしくは全部が除去され当該除去された領域にてＡｕ膜１４とＡｌ電極膜１２との導通性が確保される。   As described above, according to the manufacturing method of the present embodiment, the surface of the Al electrode film 12 is shielded from oxygen by the antioxidant film 40 when the Au paste 50 is applied in the atmosphere, and the Au paste 50 At the time of firing, a part or all of the antioxidant film 40 is removed, and electrical conductivity between the Au film 14 and the Al electrode film 12 is ensured in the removed region.

そのため、本実施形態によれば、大気中にてＡｌ電極膜１２の上に、Ａｕペースト５０を塗布してＡｕ膜１４を形成するにあたって、電極構造体としての機能を維持しつつ、Ａｌ電極膜１２の表面の酸化を防止することができる。   Therefore, according to the present embodiment, in forming the Au film 14 by applying the Au paste 50 on the Al electrode film 12 in the atmosphere, the Al electrode film is maintained while maintaining the function as the electrode structure. 12 surface oxidation can be prevented.

（他の実施形態）
なお、上記実施形態では、酸化防止膜４０は、Ａｌ電極膜１２の表面のＡｌとＦとの化合物であり、上記ＲＩＥ処理による酸化膜３０の除去とともに形成されたが、このようなＡｌとＦとの化合物よりなる酸化防止膜４０を形成する方法としては、ＨＦ溶液を用いてＡｌ電極膜１２の表面を処理する方法でもよい。この場合、強酸であるＨＦによる酸化膜３０の除去およびＡｌとＦとの反応による化合物の形成が期待できる。 (Other embodiments)
In the above embodiment, the antioxidant film 40 is a compound of Al and F on the surface of the Al electrode film 12 and is formed along with the removal of the oxide film 30 by the RIE process. As a method of forming the antioxidant film 40 made of the compound, a method of treating the surface of the Al electrode film 12 using an HF solution may be used. In this case, removal of the oxide film 30 by HF, which is a strong acid, and formation of a compound by reaction between Al and F can be expected.

また、酸化防止膜４０としては、Ａｌ電極膜１２の表面のＡｌとＢｒ、Ｃｌ、Ｉとの化合物であってもよい。これらＢｒ、Ｃｌ、Ｉは、Ｆと同じハロゲン元素であり、Ｆの場合と同様の効果が期待できる。   The antioxidant film 40 may be a compound of Al and Br, Cl, I on the surface of the Al electrode film 12. These Br, Cl, and I are the same halogen elements as F, and the same effect as in the case of F can be expected.

なお、これらＢｒ、Ｃｌ、Ｉの場合も、Ｆの場合と同様に、上記ＲＩＥ処理によって酸化防止膜形成工程が行える。つまり、上記実施形態におけるＲＩＥ処理において、ＣＦ4ガスを、ＣＢｒ4ガス、ＣＣｌ4ガス、ＣＩ4ガスに置き換えればよい。 In the case of Br, Cl, and I, as in the case of F, the antioxidant film forming step can be performed by the RIE process. That is, in the RIE process in the above embodiment, the CF 4 gas may be replaced with CBr 4 gas, CCl 4 gas, or CI 4 gas.

また、酸化防止膜４０としては、上記したＡｌ電極膜１２の表面のＡｌとハロゲンとの化合物以外にも、酸素を含まず且つＡｕペースト５０の焼成時に少なくとも一部がＡｌ電極膜１２の表面から除去されるものであればよい。   In addition to the compound of Al and halogen on the surface of the Al electrode film 12 described above, the antioxidant film 40 does not contain oxygen and at least a part of the surface of the Al electrode film 12 is formed when the Au paste 50 is baked. Anything that can be removed is acceptable.

たとえば、Ｃｒ、Ｎａ、Ｚｎなどの金属膜であってもよい。これらＣｒ、Ｎａ、Ｚｎは、Ａｌ中への拡散係数が比較的大きいものであり、Ａｕペースト５０の焼成時の熱によって、Ａｌ電極膜１２の表面からＡｌの内部へ拡散することで、Ａｌ電極膜１２の表面から除去されると推定される。   For example, a metal film such as Cr, Na, or Zn may be used. These Cr, Na, and Zn have a relatively large diffusion coefficient into Al, and are diffused from the surface of the Al electrode film 12 to the inside of Al by the heat at the time of firing the Au paste 50, whereby the Al electrode It is estimated that it is removed from the surface of the film 12.

これらＣｒ、Ｎａ、Ｚｎを用いた場合、酸化防止膜形成工程は、Ｃｒ、Ｎａ、Ｚｎから選択された粒子を含むアルカリ系または酸系の溶液を、Ａｌ電極膜１２の表面に塗布し、これを乾燥させることで行えばよい。   When these Cr, Na, and Zn are used, the antioxidant film forming step applies an alkaline or acid-based solution containing particles selected from Cr, Na, and Zn to the surface of the Al electrode film 12. What is necessary is just to dry.

それによれば、アルカリまたは酸によってＡｌ電極膜１２の表面の酸化膜を除去できるとともに、Ａｌ電極膜１２の表面には、Ｃｒ、Ｎａ、Ｚｎの膜が酸化防止膜として形成される。   According to this, the oxide film on the surface of the Al electrode film 12 can be removed by alkali or acid, and a film of Cr, Na, Zn is formed on the surface of the Al electrode film 12 as an antioxidant film.

また、上記実施形態にて示したような所望の導通性を得るための焼成温度は、あくまで一例であり、上記実施形態に限定されるものではない。また、基板としては半導体基板に限定されるものではなく、たとえば絶縁性のセラミック基板などであってもよい。   Moreover, the firing temperature for obtaining the desired electrical conductivity as shown in the above embodiment is merely an example, and is not limited to the above embodiment. Further, the substrate is not limited to a semiconductor substrate, and may be, for example, an insulating ceramic substrate.

また、上記実施形態の電極構造体は、センサ素子におけるワイヤボンディングのパッドとして適用されたものであったが、本発明の電極構造体の用途は、これに限定されるものではない。   Moreover, although the electrode structure of the said embodiment was applied as a wire bonding pad in a sensor element, the use of the electrode structure of this invention is not limited to this.

本発明の実施形態に係る電極構造体の概略断面図である。It is a schematic sectional drawing of the electrode structure which concerns on embodiment of this invention. 上記実施形態の電極構造体の製造方法の工程図である。It is process drawing of the manufacturing method of the electrode structure of the said embodiment. 上記実施形態の製造方法における各膜の接合の推定メカニズムを示す図である。It is a figure which shows the estimation mechanism of joining of each film | membrane in the manufacturing method of the said embodiment. ＲＩＥ処理なしのものについてのＸＰＳ表面分析によるＦ原子層の調査結果を示す図である。It is a figure which shows the investigation result of F atomic layer by XPS surface analysis about the thing without RIE process. ＲＩＥ処理ありのものについてのＸＰＳ表面分析によるＦ原子層の調査結果を示す図である。It is a figure which shows the investigation result of F atomic layer by XPS surface analysis about a thing with RIE process. Ｆ原子層の形成による再酸化の防止効果についてＸＰＳ表面分析により調査した結果を示す図である。It is a figure which shows the result investigated by XPS surface analysis about the prevention effect of reoxidation by formation of F atomic layer. Ｆ原子の除去とＡｕ原子の置換について焼成温度による依存性をＸＰＳ表面分析により調査した結果を示す図である。It is a figure which shows the result of having investigated the dependence by the calcination temperature about the removal of F atom and substitution of Au atom by XPS surface analysis. 酸化防止膜の除去によるＡｕ膜とＡｌ電極膜との導通性確保の効果について調査した結果を示す図である。It is a figure which shows the result of having investigated about the effect of ensuring the electroconductivity of Au film | membrane and Al electrode film by removal of an antioxidant film | membrane. 引っ張り強度試験の方法を示す図である。It is a figure which shows the method of a tensile strength test. 上記実施形態におけるＡｕ膜とＡｌ電極膜との接合強度の効果について調査した結果を示す図である。It is a figure which shows the result of having investigated about the effect of the joint strength of Au film | membrane and Al electrode film in the said embodiment.

符号の説明Explanation of symbols

１０…基板としての半導体基板、１２…Ａｌ電極膜、１４…Ａｕ膜、３０…酸化膜、
４０…酸化防止膜、５０…Ａｕペースト。 DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate as a substrate, 12 ... Al electrode film, 14 ... Au film, 30 ... Oxide film,
40 ... Antioxidation film, 50 ... Au paste.

Claims (4)

基板（１０）の上にＡｌよりなるＡｌ電極膜（１２）を形成し、
前記Ａｌ電極膜（１２）の上に、Ａｕよりなる粒子を含有するペースト（５０）を塗布し、このペースト（５０）を焼成することによりＡｕ膜（１４）を形成してなる電極構造体の製造方法であって、
前記Ａｌ電極膜（１２）の表面の酸化膜（３０）を除去するとともに、当該表面上に、前記ペースト（５０）の焼成時に少なくとも一部が当該表面から除去される酸化防止膜（４０）を形成する酸化防止膜形成工程と、
大気中にて前記酸化防止膜（４０）の上に、前記ペースト（５０）の塗布を行うペースト塗布工程と、
続いて、前記ペースト（５０）の焼成を行い前記Ａｕ膜（１４）を形成する焼成工程とを備えることを特徴とする電極構造体の製造方法。 An Al electrode film (12) made of Al is formed on the substrate (10),
An electrode structure in which an Au film (14) is formed by applying a paste (50) containing particles made of Au on the Al electrode film (12) and firing the paste (50). A manufacturing method comprising:
An oxide film (30) on the surface of the Al electrode film (12) is removed, and an antioxidant film (40) is formed on the surface, at least part of which is removed from the surface when the paste (50) is baked. An antioxidant film forming step to be formed;
A paste application step of applying the paste (50) on the antioxidant film (40) in the atmosphere;
Then, the manufacturing method of the electrode structure characterized by including the baking process of baking the said paste (50) and forming the said Au film | membrane (14). 前記酸化防止膜（４０）は、前記Ａｌ電極膜（１２）の表面のＡｌとハロゲンとの化合物であることを特徴とする請求項１に記載の電極構造体の製造方法。 The method for manufacturing an electrode structure according to claim 1, wherein the antioxidant film (40) is a compound of Al and halogen on the surface of the Al electrode film (12). 前記化合物は、前記Ａｌ電極膜（１２）の表面のＡｌとＦとの化合物であることを特徴とする請求項２に記載の電極構造体の製造方法。 The method for producing an electrode structure according to claim 2, wherein the compound is a compound of Al and F on the surface of the Al electrode film (12). 前記酸化防止膜形成工程は、フッ素化合物のガスと不活性ガスとの混合ガスよりなるガス雰囲気中において前記Ａｌ電極膜（１２）の表面に対してプラズマ処理を行うことにより、前記Ａｌ電極膜（１２）の表面の酸化膜（３０）を除去するとともに、前記Ａｌ電極膜（１２）の表面上に前記ＡｌとＦとの化合物を形成することを特徴とする請求項３に記載の電極構造体の製造方法。
In the oxidation film forming step, the surface of the Al electrode film (12) is subjected to a plasma treatment in a gas atmosphere composed of a mixed gas of a fluorine compound gas and an inert gas, whereby the Al electrode film ( The electrode structure according to claim 3, wherein the oxide film (30) on the surface of 12) is removed and the compound of Al and F is formed on the surface of the Al electrode film (12). Manufacturing method.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06340901A (en) * 1994-03-28 1994-12-13 Hitachi Ltd Sintering method
JP2925960B2 (en) * 1994-11-29 1999-07-28 三洋電機株式会社 Method for manufacturing semiconductor device
JP3274533B2 (en) * 1993-05-12 2002-04-15 ローム株式会社 Semiconductor element
JP2004214345A (en) * 2002-12-27 2004-07-29 Renesas Technology Corp Semiconductor device and its manufacturing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3274533B2 (en) * 1993-05-12 2002-04-15 ローム株式会社 Semiconductor element
JPH06340901A (en) * 1994-03-28 1994-12-13 Hitachi Ltd Sintering method
JP2925960B2 (en) * 1994-11-29 1999-07-28 三洋電機株式会社 Method for manufacturing semiconductor device
JP2004214345A (en) * 2002-12-27 2004-07-29 Renesas Technology Corp Semiconductor device and its manufacturing method

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