JP4471730B2 - Double-sided wiring board and manufacturing method thereof - Google Patents

Double-sided wiring board and manufacturing method thereof Download PDF

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JP4471730B2
JP4471730B2 JP2004140236A JP2004140236A JP4471730B2 JP 4471730 B2 JP4471730 B2 JP 4471730B2 JP 2004140236 A JP2004140236 A JP 2004140236A JP 2004140236 A JP2004140236 A JP 2004140236A JP 4471730 B2 JP4471730 B2 JP 4471730B2
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hole
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wiring board
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alloy
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JP2005322805A (en
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憲道 安中
隆 伏江
涼司 宮田
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Hoya Corp
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本発明は、基板両面(表裏面)に設けられた配線層が、基板両面を貫通して配線される貫通配線によって接続可能にされた両面配線基板であって、特に、微細な貫通孔の内部を金属導体によって充填し、両面の配線層を導体接続するようにした両面配線基板及びその製造方法に関する。   The present invention is a double-sided wiring board in which wiring layers provided on both sides (front and back surfaces) of the board are connectable by through wirings that pass through both sides of the board, and in particular, the inside of fine through holes. The present invention relates to a double-sided wiring board and a method of manufacturing the same.

例えば、近年のMEMS(マイクロ・エレクトロ・メカニカル・システム)技術を応用した電子デバイスや光デバイス等の技術分野においては、小型化、高機能化が進められており、これに伴って、これらに用いられる両面配線基板の配線パターンの微細化・高密度化が望まれている。この両面配線基板は、基板両面(表裏面)に設けられた配線層が、基板両面を貫通して配線される貫通配線によって接続可能にされている。この貫通配線としては、基板に微細な貫通孔を形成し、その内部に導体を形成することによって両面の配線層を導体接続するようにしたものが用いられる。両面配線基板の配線パターンの微細化・高密度化を実現するには、この貫通孔に導体を形成した貫通配線の微細化が必須である。すなわち、貫通孔の径の微細化が必須である。また、例えば、この種の両面配線基板にマイクロスイッチなどの気密性が必要とされるものを設ける場合には、封止や接合のための高耐熱性も要求される。   For example, in the technical fields such as electronic devices and optical devices applying recent MEMS (micro electro mechanical system) technology, miniaturization and high functionality have been promoted. There is a demand for miniaturization and high density of the wiring pattern of the double-sided wiring board. In this double-sided wiring board, wiring layers provided on both sides (front and back surfaces) of the board are connectable by through wirings that are wired through both sides of the board. As the through wiring, a fine through hole is formed in a substrate, and a conductor is formed in the inside to form a conductive connection between the wiring layers on both sides. In order to realize a finer and higher density wiring pattern on the double-sided wiring board, it is essential to refine the through wiring in which a conductor is formed in the through hole. That is, it is essential to reduce the diameter of the through hole. Further, for example, in the case of providing a double-sided wiring board of this type that requires airtightness such as a microswitch, high heat resistance for sealing and bonding is also required.

ここで、両面配線基板の両面(表裏面)を貫通する貫通孔の内部に導体が形成されて両面の配線層を導体接続可能とする貫通配線を得る手法としては、従来から以下の方法が知られている。
(1)貫通孔の側壁部に、導体層をめっき法により形成後、貫通孔に樹脂を充填する方法(特許文献1参照)。
(2)メッキ法によって貫通孔を金属材料で充填する方法(特許文献2参照)。
(3)差圧を利用した溶融金属を貫通孔内に吸引、充填する方法(特許文献3参照)。
特開2001−44639号公報 特開平11−177200号公報 特開2003−133410号公報
Here, conventionally, the following methods are known as methods for obtaining a through wiring in which a conductor is formed inside a through hole penetrating both surfaces (front and back surfaces) of a double-sided wiring board and the wiring layers on both surfaces can be connected to each other. It has been.
(1) A method of filling a resin in a through hole after forming a conductor layer on the side wall of the through hole by a plating method (see Patent Document 1).
(2) A method of filling the through hole with a metal material by a plating method (see Patent Document 2).
(3) A method of sucking and filling molten metal using differential pressure into a through hole (see Patent Document 3).
JP 2001-44639 A JP-A-11-177200 JP 2003-133410 A

しかしながら、貫通孔を樹脂で充填した場合には、樹脂の耐熱性が低いこと、及び樹脂のガス透過性が高いことから、両面配線基板としての耐熱性及び気密性が問題となる。また、メッキ法を用いて貫通孔に金属を充填する方法は、耐熱性及び気密性の点においては問題ないが、貫通孔内部のボイドの発生を抑えるのが困難であり、かつ当該ボイドの中にはメッキ液が残留し、両面配線基板としての信頼性を損なうことになる。この問題は、特に、高アスペクト比の貫通孔の場合に顕在化する。さらに、溶融金属を貫通孔内に吸引、充填する方法は、作業性等の観点から、比較的融点の低い金属に限定されることから、両面配線基板としての耐熱性が問題となる。
本発明は、上述の背景のもとでなされたものであり、両面配線基板の微細化に対応でき、耐熱性、気密性及び信頼性に優れ、かつ、量産性に富んだ両面配線基板及びその製造方法を提供することを目的としている。
However, when the through-holes are filled with resin, the heat resistance and airtightness of the double-sided wiring board are problematic because the resin has low heat resistance and the resin has high gas permeability. In addition, the method of filling the through hole with a metal using a plating method is not problematic in terms of heat resistance and air tightness, but it is difficult to suppress the generation of voids in the through hole, and the inside of the voids. In this case, the plating solution remains, which impairs the reliability of the double-sided wiring board. This problem is particularly apparent in the case of through holes with a high aspect ratio. Furthermore, the method of sucking and filling the molten metal into the through-hole is limited to a metal having a relatively low melting point from the viewpoint of workability and the like, so the heat resistance as a double-sided wiring board becomes a problem.
The present invention has been made under the above-mentioned background, and can be used for miniaturization of a double-sided wiring board, has excellent heat resistance, airtightness and reliability, and has high mass productivity. The object is to provide a manufacturing method.

上述の課題を解決するための手段として第1の手段は、
基板と、この基板の両面に設けられた配線層と、前記基板の両面を貫通する貫通孔と、この貫通孔内に導電性材料が充填形成されて前記両面の配線層を電気的に接続可能にする導電部とを有し、前記導電性材料の平均組成が、CuxSnyM100-(x+y)であることを特徴とする両面配線基板である。
ただし、x,yは重量100分率で、30≦x≦99、1≦y≦70であり、MはAu,Ag,Niから選定された少なくとも1種の金属であるものとする。
As a means for solving the above-mentioned problem, the first means is:
A board, a wiring layer provided on both sides of the board, a through-hole penetrating both sides of the board, and a conductive material filled in the through-hole to electrically connect the wiring layers on both sides A double-sided wiring board, wherein the conductive material has an average composition of Cu x Sn y M 100- (x + y) .
However, x and y are weight fractions of 100, 30 ≦ x ≦ 99, and 1 ≦ y ≦ 70, and M is at least one metal selected from Au, Ag, and Ni.

第2の手段は、
前記導電性材料のCu濃度が前記貫通孔の径方向で一様ではなく、前記貫通孔の側壁部近傍から貫通孔の中心線近傍に向かうにしたがって減少していることを特徴とする第1の手段にかかる両面配線基板である。
The second means is
The Cu concentration of the conductive material is not uniform in the radial direction of the through hole, and decreases from the vicinity of the side wall portion of the through hole toward the vicinity of the center line of the through hole. It is the double-sided wiring board concerning a means.

第3の手段は、
前記導電性材料のCu濃度が前記貫通孔の径方向で一様ではなく、前記貫通孔の側壁部近傍で最大であり、かつ前記貫通孔の中心線近傍で最小であることを特徴とする第1又は第2の手段にかかる両面配線基板である。
The third means is
The Cu concentration of the conductive material is not uniform in the radial direction of the through hole, is maximum near the side wall portion of the through hole, and is minimum near the center line of the through hole. This is a double-sided wiring board according to the first or second means.

第4の手段は、
基板の両面を貫通する貫通孔内に導電性材料を充填形成することによって前記基板両面に形成された配線層を電気的に接続可能にする導電部形成工程を有する両面配線基板の製造方法であって、
前記導電部形成工程は、前記貫通孔の側壁部にCu若しくはCuを含む合金を、前記貫通孔の中央部に基板両面に連通する空隙部を残して付着させる第1の工程と、
前記貫通孔の側壁部に付着されたCu若しくはCuを含む合金表面にSn若しくはSnを含む合金を付着させるとともに前記空隙部に充填させる第2の工程と、
前記第1の工程で付着させたCu若しくはCuを含む合金と、前記第2の工程で付着・充填させたSn若しくはSnを含む合金とを、熱処理により相互に拡散合金化させる第3の工程とを有することを特徴とする両面配線基板の製造方法である。
The fourth means is
A method for manufacturing a double-sided wiring board, comprising: a conductive part forming step for electrically connecting wiring layers formed on both sides of the substrate by filling a through hole penetrating both sides of the substrate with a conductive material. And
The conductive portion forming step includes a first step of attaching Cu or an alloy containing Cu to the side wall portion of the through hole, leaving a void portion communicating with both surfaces of the substrate at the center portion of the through hole,
A second step of attaching Sn or an alloy containing Sn to the surface of Cu or an alloy containing Cu attached to the side wall portion of the through hole and filling the void portion;
A third step in which the Cu or Cu-containing alloy deposited in the first step and the Sn or Sn-containing alloy deposited / filled in the second step are formed into a diffusion alloy with each other by heat treatment; It is a manufacturing method of the double-sided wiring board characterized by having.

第5の手段は、
前記第1の工程が、メッキ法によりCu若しくはCuを含む合金を前記貫通孔の側壁部に付着させる工程であることを特徴とする第4の手段にかかる両面配線基板の製造方法である。
The fifth means is
The method for producing a double-sided wiring board according to the fourth means, wherein the first step is a step of attaching Cu or an alloy containing Cu to the side wall portion of the through hole by a plating method.

第6の手段は、
前記第2の工程が、Sn若しくはSnを含む合金を加熱溶融した溶融金属に、前記第1の工程を経た基板を接触させ、毛細管現象により前記Sn若しくはSnを含む合金を、前記空隙部に充填させるものであることを特徴とする第4又は第5の手段にかかる両面配線基板の製造方法である。
The sixth means is
In the second step, the substrate obtained through the first step is brought into contact with the molten metal obtained by heating and melting Sn or an alloy containing Sn, and the void portion is filled with the alloy containing Sn or Sn by capillary action. It is a manufacturing method of the double-sided wiring board concerning the 4th or 5th means characterized by the above-mentioned.

第7の手段は、
前記貫通孔内部に充填されたCuSn合金、若しくは少なくともCuとSnとを含む合金における平均的なCu濃度を、前記第1の工程で付着させるCu、若しくはCuを含む合金の体積によって制御することを特徴とする第4乃至第6のいずれかの手段にかかる両面配線基板の製造方法である。
The seventh means is
Controlling the average Cu concentration in the CuSn alloy filled in the through-hole or an alloy containing at least Cu and Sn by the volume of Cu or the alloy containing Cu deposited in the first step. A method for manufacturing a double-sided wiring board according to any one of the fourth to sixth features.

なお、上述の手段において、「導電性材料の平均組成」とは、導電性材料の各部の組成値を貫通孔全体で平均化した値をいう。貫通孔内部で導電性材料の組成が一様であれば、いずれの部位の組成も同じであるので単に「組成」という概念を用いることで足りるが、貫通孔内部の場所によって導電性材料の組成が異なる場合においては、貫通孔全体の組成を表すために、上記「平均組成」という概念を用いたものである。   In the above-described means, the “average composition of the conductive material” means a value obtained by averaging the composition value of each part of the conductive material over the entire through hole. If the composition of the conductive material is uniform inside the through hole, the composition of any part is the same, so it is sufficient to simply use the concept of “composition”, but the composition of the conductive material depends on the location inside the through hole. Are different from each other, the concept of “average composition” is used to represent the composition of the entire through-hole.

上述の第1〜第3の手段により、貫通孔に充填する導電性材料の平均組成を前記組成にしたことよって、十分な耐熱性が確保され、また、その材料の物理的・機械的性質から、両面配線基板の機密性及び信頼性を充分なものとすることができる。すなわち、上記組成の合金にしたことにより、貫通孔を樹脂や低融点金属で充填したような場合に比較して、耐熱性や気密性が問題になることはない。さらには、上記組成の合金は容易に歩留まりよく貫通孔内に形成可能であるので、量産性にも優れる。また、第2及び第3の手段のように、組成分布をもたせるようにすれば、貫通孔中心線近傍は、充分な耐熱性を有する範囲内での低融点合金で、かつ貫通孔側壁部近傍は、高融点合金で充填されることになる。一般的に金属材料においては、融点と剛性率とは相関があり、低融点金属は、高融点金属に比べて、剛性率は低い傾向にある。このことより、貫通孔中心線近傍は、低融点の剛性率が低い合金によって充填され、貫通孔側壁部近傍は、高融点の剛性率が高い合金によって充填されることになる。この結果、貫通孔中心線近傍に充填された低融点合金、すなわち剛性率が低い合金は、後続のプロセスを経ることによって発生する貫通孔近傍の応力に対する緩衝作用を有し、応力によるクラック発生等を阻止することが可能となる。
なお、貫通孔に充填された合金の組成分布は、後述する熱処理条件により制御することができる。
By setting the average composition of the conductive material filled in the through holes to the above composition by the first to third means described above, sufficient heat resistance is ensured, and from the physical and mechanical properties of the material. The confidentiality and reliability of the double-sided wiring board can be made sufficient. That is, by using the alloy having the above composition, heat resistance and airtightness do not become a problem as compared with the case where the through hole is filled with a resin or a low melting point metal. Furthermore, since the alloy having the above composition can be easily formed in the through hole with a high yield, it is excellent in mass productivity. Further, if the composition distribution is provided as in the second and third means, the vicinity of the through hole center line is a low melting point alloy within a range having sufficient heat resistance and the vicinity of the side wall of the through hole. Is filled with a high melting point alloy. Generally, in a metal material, there is a correlation between the melting point and the rigidity, and the low melting point metal tends to have a lower rigidity than the high melting point metal. Thus, the vicinity of the through hole center line is filled with an alloy having a low melting point and a low rigidity, and the vicinity of the side wall of the through hole is filled with an alloy having a high melting point and a high rigidity. As a result, the low melting point alloy filled in the vicinity of the center line of the through hole, that is, the alloy having a low rigidity has a buffering action against the stress in the vicinity of the through hole generated by the subsequent process, and the generation of cracks due to the stress, etc. Can be prevented.
The composition distribution of the alloy filled in the through holes can be controlled by the heat treatment conditions described later.

上述の第4〜第7の手段によれば、第1〜第3の手段にかかる両面配線基板を確実に製造することができる。すなわち、メッキ法を用いた場合のように、貫通孔内部にボイドが発生したり、ボイドの中にメッキ液が残留する等々のおそれがなく、高融点合金を貫通孔内に充填形成することが可能になる。しかも、先に貫通孔側壁にCuをメッキし、しかる後にその貫通孔内に低融点金属を毛細管現象を利用して充填するようにしているので、非常に小径で高アスペクト比の貫通孔にも密に充填できる。しかも、その後に熱処理して貫通孔の側壁のCuを合金化しているのでその熱処理条件を選定することにより上記充填金属を所望の高融点の合金にすることができると共に、貫通孔内で合金組成に分布を持たせることもできる。また、貫通孔側壁部に形成するCu若しくはCu合金の膜厚を制御することにより、貫通孔内に充填する合金の平均組成を制御することもできる。これ等により、両面配線基板の微細化に対応でき、耐熱性、気密性及び信頼性に優れた両面配線基板を歩留まりよく量産することを可能としている。   According to the fourth to seventh means described above, the double-sided wiring board according to the first to third means can be reliably manufactured. That is, unlike the case where the plating method is used, there is no fear that voids are generated in the through holes or the plating solution remains in the voids, and the high melting point alloy can be filled and formed in the through holes. It becomes possible. Moreover, Cu is plated on the side wall of the through hole first, and then the low melting point metal is filled in the through hole by utilizing the capillary phenomenon, so that even a through hole with a very small diameter and a high aspect ratio is used. Can be packed closely. In addition, since the Cu on the side wall of the through hole is alloyed by heat treatment after that, by selecting the heat treatment conditions, the filled metal can be made into a desired high melting point alloy and the alloy composition in the through hole. Can also have a distribution. Moreover, the average composition of the alloy with which a through-hole is filled can also be controlled by controlling the film thickness of Cu or Cu alloy formed in the through-hole side wall. As a result, it is possible to deal with the miniaturization of the double-sided wiring board and to mass-produce the double-sided wiring board excellent in heat resistance, airtightness and reliability with a high yield.

図1は本発明の実施の形態にかかる両面配線基板の断面図である。図1に示されるように、実施の形態にかかる両面配線基板10は、基板1の両面(表裏面)1a,1bに、配線層2a,2bがそれぞれ形成され、これらは配線層2a,2bが、貫通孔3内に充填された導電性材料4によって導体接続されたものである。なお、この場合、配線層2a,2bには、配線パターンが形成され、また、これら配線層2a,2bは、導電性の接着層2c,2dによって基板1の表面及び上記導電性材料4に強固に固着されている。   FIG. 1 is a sectional view of a double-sided wiring board according to an embodiment of the present invention. As shown in FIG. 1, a double-sided wiring board 10 according to an embodiment has wiring layers 2a and 2b formed on both sides (front and back) 1a and 1b of a substrate 1, respectively. The conductive material 4 filled in the through hole 3 is conductively connected. In this case, a wiring pattern is formed on the wiring layers 2a and 2b, and the wiring layers 2a and 2b are firmly attached to the surface of the substrate 1 and the conductive material 4 by the conductive adhesive layers 2c and 2d. It is fixed to.

上記導電性材料4は、その平均組成が、CuxSnyM100-(x+y)である。ただし、x,yは重量100分率で、30≦x≦99、1≦y≦70であり、MはAu,Ag,Niから選定された少なくとも1種の金属である。また、上記導電性材料4のCu濃度が貫通孔3の径方向で一様ではなく、貫通孔3の側壁部近傍から貫通孔3の中心線近傍に向かうにしたがって減少しており、貫通孔3の側壁部近傍で最大であり、貫通孔3の中心線近傍で最小である。
この導電性材料のCu濃度分布は、前述したように、貫通孔近傍に発生する応力を緩和する効果を有するものであるが、本発明に採って不可欠のものではない。また、後述する拡散合金化のための熱処理を充分行うことにより、貫通孔内の合金組成を一様なものとすることも可能である。
The conductive material 4 has an average composition of Cu x Sn y M 100- (x + y) . However, x and y are weight fractions of 100, 30 ≦ x ≦ 99, and 1 ≦ y ≦ 70, and M is at least one metal selected from Au, Ag, and Ni. Further, the Cu concentration of the conductive material 4 is not uniform in the radial direction of the through-hole 3, and decreases from the vicinity of the side wall portion of the through-hole 3 toward the vicinity of the center line of the through-hole 3. It is the maximum in the vicinity of the side wall portion and the minimum in the vicinity of the center line of the through hole 3.
As described above, the Cu concentration distribution of the conductive material has an effect of relaxing the stress generated in the vicinity of the through hole, but is not indispensable for the present invention. Further, it is possible to make the alloy composition in the through hole uniform by sufficiently performing heat treatment for diffusion alloying described later.

基板1としては、絶縁基板である感光性ガラス基板、ガラス基板、セラミックス基板もしくはシリコン基板のいずれでも良い。シリコン基板の場合は、貫通孔形成後に全面に対して、熱酸化膜を成長させるか,あるいは絶縁膜を形成する。これらの中では、感光性ガラス基板が最も望ましい。感光性ガラス基板は、十分に耐熱性を有し、平滑性・剛性に優れ微細配線形成が容易であり、微細かつ高アスペクト比の貫通孔を一括して形成することが可能だからである。この感光性ガラス基板としては、例えば重量%で、SiO2:55〜85%、Al23:2〜20%、Li2O:5〜15%、SiO2+Al23+Li2O>85%を基本成分とし、Au:0.001〜0.05%、Ag:0.001〜0.5%、Cu2O:0.001〜1%を感光性金属成分とし、更にCeO2:0.001〜0.2%を光増感剤として含有する感光性ガラスを用いることが特に好ましい。 The substrate 1 may be any of a photosensitive glass substrate, a glass substrate, a ceramic substrate, or a silicon substrate that is an insulating substrate. In the case of a silicon substrate, a thermal oxide film is grown on the entire surface after the through hole is formed, or an insulating film is formed. Of these, a photosensitive glass substrate is most desirable. This is because the photosensitive glass substrate has sufficient heat resistance, is excellent in smoothness and rigidity, and can easily form fine wiring, and can form fine and high aspect ratio through-holes at once. As this photosensitive glass substrate, for example, by weight, SiO 2 : 55 to 85%, Al 2 O 3 : 2 to 20%, Li 2 O: 5 to 15%, SiO 2 + Al 2 O 3 + Li 2 O> 85% as a basic component, Au: 0.001 to 0.05%, Ag: 0.001 to 0.5%, Cu 2 O: 0.001 to 1% as a photosensitive metal component, and CeO 2 : It is particularly preferable to use a photosensitive glass containing 0.001 to 0.2% as a photosensitizer.

配線層2a,2bとしては、導電性材料の薄膜であればよいが、好ましくはCu薄膜が用いられる。また、接着層2c、2dとしては、基板1と配線層2a,2bとの接着性もしくは密着性が確保できる導電性材料であればよいが、好ましくはCrあるいはチタン薄膜が用いられる。   The wiring layers 2a and 2b may be a thin film made of a conductive material, but a Cu thin film is preferably used. The adhesive layers 2c and 2d may be any conductive material that can ensure adhesion or adhesion between the substrate 1 and the wiring layers 2a and 2b, but a Cr or titanium thin film is preferably used.

図2〜図4は本発明の実施の形態にかかる両面配線基板の製造方法の説明図である。以下、図2〜図4を参照にしながら実施の形態にかかる両面配線基板の製造方法について説明する。実施の形態にかかる両面配線基板の製造方法は、大きく分けて、貫通孔形成工程と導電性材料形成工程とを有する。   2-4 is explanatory drawing of the manufacturing method of the double-sided wiring board concerning embodiment of this invention. Hereinafter, a method for manufacturing a double-sided wiring board according to the embodiment will be described with reference to FIGS. The method for manufacturing a double-sided wiring board according to the embodiment roughly includes a through-hole forming step and a conductive material forming step.

(貫通孔形成工程)
図2は貫通孔形成工程の説明図である。まず、感光性ガラス基板1を用意し(図2-1)、次に、図2-2に示されるように、上記感光性ガラス1上に、貫通孔(スルホール)を形成する部分を光通過部分とするパターンが形成されたマスクを密着させ、このマスクを通して貫通孔形成部分3aに紫外光を照射し、露光部分に対応する潜像を形成する。次に、感光した基板1に熱処理を加え、露光部分3aのみを結晶化させる(図2-3参照)。次に、結晶化させた部分をエッチング液等の溶剤で除去して(図2-4参照)貫通孔3を形成する。貫通孔形成後、熱処理を施し、基板全体を結晶化させる。そして、熱処理後、基板1の厚さ方向の貫通孔径の一様性を確保するため、基板表裏面近傍の同径が拡大した部分を研削除去するとともに、基板の厚さを所定の厚さにする。
(Through hole forming process)
FIG. 2 is an explanatory diagram of the through hole forming step. First, a photosensitive glass substrate 1 is prepared (FIG. 2-1). Next, as shown in FIG. 2-2, light passes through a portion where a through hole (through hole) is formed on the photosensitive glass 1. A mask on which a pattern to be a part is formed is brought into close contact, and the through hole forming part 3a is irradiated with ultraviolet light through the mask to form a latent image corresponding to the exposed part. Next, heat treatment is applied to the exposed substrate 1 to crystallize only the exposed portion 3a (see FIG. 2-3). Next, the crystallized portion is removed with a solvent such as an etching solution (see FIG. 2-4) to form the through hole 3. After forming the through holes, heat treatment is performed to crystallize the entire substrate. And after heat processing, in order to ensure the uniformity of the through-hole diameter of the thickness direction of the board | substrate 1, while removing the part where the same diameter near the board | substrate front and back surface was expanded, the thickness of a board | substrate was made into predetermined thickness. To do.

(導電性材料形成工程)
次に、上記基板1の貫通孔3に、導電性材料を形成する。図3〜図4は導電性材料形成工程の説明図である。この導電性材料形成工程は、前記貫通孔3の側壁部にCu若しくはCuを含む合金を、前記貫通孔の中央部に基板両面に連通する空隙部を残して付着させる第1の工程と、上記貫通孔3の側壁部に付着されたCu若しくはCuを含む合金表面にSn若しくはSnを含む合金を付着させるとともに前記空隙部に充填させる第2の工程と、前記第1の工程で付着させたCu若しくはCuを含む合金と、前記第2の工程で付着・充填させたSn若しくはSnを含む合金とを、熱処理により相互に拡散合金化させる第3の工程とを有する。
(Conductive material formation process)
Next, a conductive material is formed in the through hole 3 of the substrate 1. 3-4 is explanatory drawing of an electroconductive material formation process. The conductive material forming step includes a first step of attaching Cu or an alloy containing Cu to the side wall portion of the through hole 3 while leaving a gap portion communicating with both surfaces of the substrate at the center portion of the through hole; A second step of attaching Sn or an alloy containing Sn to the surface of the alloy containing Cu or Cu attached to the side wall portion of the through hole 3 and filling the void portion, and Cu attached in the first step Alternatively, there is a third step in which the alloy containing Cu and the alloy containing Sn or Sn deposited and filled in the second step are formed into a diffusion alloy with each other by heat treatment.

まず、基板1の両面にメッキ層を形成させるための前処理をする。この前処理は、スパッタ法等により両面(表裏面)にCr膜等の接着層膜6aを形成し、この接着層6aの上にCu膜等の給電層6bを順次成膜する(図3−1参照)。この成膜を行う方法としては、スパッタ法に関わらず、CVD法,蒸着法,イオンビームスパッタ法などいずれでもよい。   First, a pretreatment for forming plating layers on both surfaces of the substrate 1 is performed. In this pretreatment, an adhesive layer film 6a such as a Cr film is formed on both surfaces (front and back surfaces) by sputtering or the like, and a power feeding layer 6b such as a Cu film is sequentially formed on the adhesive layer 6a (FIG. 3). 1). As a method for forming the film, any method such as a CVD method, a vapor deposition method, and an ion beam sputtering method may be used regardless of the sputtering method.

次に、公知の貫通孔メッキ法により、貫通孔3の側壁部及び基板1の両面に無電解銅めっき薄膜7aを形成し、この無電解銅めっき薄膜7aを給電層とし、電解銅めっきにより貫通孔側壁および両面に対し、Cu膜7bを成長させ、貫通孔3の側壁のCu膜7bの膜厚が所望の値になるようにする(図3−2参照)。次いで、基板両面の少なくともどちらか1面あるいは両面、および貫通孔3の内部に対してフラックス溶剤8を塗布してフラックス処理をすることにより、Cu膜表面を活性化させる(図3-3参照)。この時、Cu表面のヌレ性を良好にするものであれば限定されるものではないが、活性ロジン系フラックスが望ましい。   Next, an electroless copper plating thin film 7a is formed on the side wall portion of the through hole 3 and both surfaces of the substrate 1 by a known through hole plating method. A Cu film 7b is grown on the side wall and both sides of the hole so that the film thickness of the Cu film 7b on the side wall of the through hole 3 becomes a desired value (see FIG. 3-2). Next, the surface of the Cu film is activated by applying flux solvent 8 to at least one or both surfaces of the substrate and the inside of the through-hole 3 to perform flux treatment (see FIG. 3-3). . At this time, an active rosin-based flux is desirable, although it is not limited as long as it improves the wettability of the Cu surface.

一方で、上記貫通孔3内に充填する導電性材料としての低融点金属であるSnを溶解させて準備しておく。この際、Snを選定した理由はCuとの拡散合金化が容易であるということからであるが、これに限定されるものではなく、市販されているSn-Au,Sn-Ag,Sn-Cu,Sn-Ag-Cu,Sn-Cu-Ni,Sn-Pbなどの低融点共晶はんだなどでも対応可能である。好ましくは、Snを含有するものが望ましいが、低融点でありCuとの拡散が容易で、かつ拡散によって形成される合金が十分な耐熱性を有するものであれば、同様の結果を得られる。表裏配線層は、低抵抗などの理由から一般にCuあるいはCu合金が選定される為、貫通孔側壁部に成長する導体層は同種のCuあるいはCu合金にするのが好ましい。   On the other hand, Sn, which is a low melting point metal as a conductive material filled in the through hole 3, is dissolved and prepared. At this time, the reason for selecting Sn is that it is easy to form a diffusion alloy with Cu. However, the present invention is not limited to this, and commercially available Sn—Au, Sn—Ag, Sn—Cu. , Sn-Ag-Cu, Sn-Cu-Ni, Sn-Pb and other low melting point eutectic solders are also available. Preferably, those containing Sn are desirable, but similar results can be obtained if the melting point is low, diffusion with Cu is easy, and the alloy formed by diffusion has sufficient heat resistance. Since Cu or Cu alloy is generally selected as the front and back wiring layers for reasons such as low resistance, it is preferable that the conductor layer grown on the side wall portion of the through hole be the same kind of Cu or Cu alloy.

次いで、溶解したSnと活性化されたCu表面を接触させることによって、毛細管現象を利用して貫通孔内部へのSn充填を行う(図3−4参照)。この状態では貫通孔3の中心部はSnのままであり、必要な高耐熱性は得られない。そこで、所定の温度により熱処理を実施することによって、貫通孔側壁側に形成されたCuと貫通孔中央部に充填されたSnの拡散合金化を促進させ、高耐熱性を有するCu−Sn化合物を得る(図4−1参照)。この場合、充分な熱処理を施した場合には、貫通孔内部の合金組成は部位に依らずほぼ一様となり、そうでない場合には、Cu濃度が貫通孔側壁部近傍において最大で、かつ貫通孔中心線近傍において最小となるような濃度分布が生じる。いずれにしても、熱処理温度、及び時間によって各部位の濃度は制御可能であり、要求される両面配線基板の耐熱性を考慮して、これ等の熱処理条件を選定することができる。また熱処理条件の選定に際しては、拡散理論の教えるところにより、熱処理温度と熱処理時間は互いに相補的な関係にあることは、あらためて言及するまでもない。
最後に、基板表裏面を機械研磨等によりCr膜,Cu膜 さらにSn充填面側のCu−Sn拡散混合層を除去するとともに、基板の平坦化処理を行う(図4−2参照)。そして、前記貫通配線基板の表裏面に対し、再度表裏に配線用導体、例えば、Cr膜等の接着層2c及びCu膜等の配線層2bを、スパッタ法等により順次成膜形成し(図4−3参照)、通常のフォトリソグラフィ技術によりパターンニングを行い、図1に示されるような両面配線基板10を得る。
Next, by bringing the dissolved Sn and the activated Cu surface into contact with each other, the inside of the through hole is filled with Sn using a capillary phenomenon (see FIG. 3-4). In this state, the central portion of the through hole 3 remains Sn, and the necessary high heat resistance cannot be obtained. Therefore, by performing heat treatment at a predetermined temperature, Cu alloy formed on the side wall of the through hole and Sn filled in the central part of the through hole are promoted to form a Cu-Sn compound having high heat resistance. Obtain (see FIG. 4-1). In this case, when sufficient heat treatment is performed, the alloy composition inside the through-hole is almost uniform regardless of the site, otherwise, the Cu concentration is maximum in the vicinity of the side wall of the through-hole, and the through-hole A concentration distribution is minimized in the vicinity of the center line. In any case, the concentration of each part can be controlled by the heat treatment temperature and time, and these heat treatment conditions can be selected in consideration of the required heat resistance of the double-sided wiring board. In selecting heat treatment conditions, it is needless to mention again that the heat treatment temperature and the heat treatment time are complementary to each other as taught by diffusion theory.
Finally, the front and back surfaces of the substrate are subjected to mechanical polishing or the like to remove the Cr film, the Cu film, and the Cu-Sn diffusion mixed layer on the Sn-filled surface side, and the substrate is planarized (see FIG. 4-2). Then, wiring conductors, for example, an adhesive layer 2c such as a Cr film and a wiring layer 2b such as a Cu film are sequentially formed on the front and back surfaces of the through wiring substrate by sputtering or the like (FIG. 4). 3), patterning is performed by a normal photolithography technique to obtain a double-sided wiring board 10 as shown in FIG.

以下、本発明を実施例に基づいてより詳細に説明する。
(実施例1)
本実施例では、ガラス基板としてとして下記の組成を有する感光性ガラス(商品名:HOYA株式会社製PEG3)を用いた。ガラス組成は、SiO:78.0wt%、LiO:10.0wt%、Al:6.0wt%、KO:4.0wt%、NaO:1.0wt%、ZnO:1.0wt%、Au:0.003wt%、Ag:0.08wt%、CeO:0.08wt%。で、基板厚は0.5mm、大きさは5インチ角である。
Hereinafter, the present invention will be described in more detail based on examples.
Example 1
In this example, photosensitive glass (trade name: PEG3 manufactured by HOYA Corporation) having the following composition was used as the glass substrate. Glass composition, SiO 2: 78.0wt%, Li 2 O: 10.0wt%, Al 2 O 3: 6.0wt%, K 2 O: 4.0wt%, Na 2 O: 1.0wt%, ZnO : 1.0wt%, Au: 0.003wt% , Ag: 0.08wt%, CeO 2: 0.08wt%. The substrate thickness is 0.5 mm and the size is 5 inch square.

(貫通孔形成工程)
上記感光性ガラス上にマスクを密着させ、該マスクを通してスルーホール部分に紫外光を照射し、露光部分に対応する潜像を形成した(図2-2参照)。マスクは、石英ガラスをCr/酸化Crでパターニングしたものを使用した。その後、400℃で3時間熱処理を行ない、露光部分のみを結晶化させた(図2-3参照)。用いた光源はディープUVランプで照射エネルギーは、800mJ/cm2であった。次いで、薄いフッ化水素酸(10%溶液)を感光性ガラスの表裏にスプレーし、結晶化したスルーホール部分のガラスを溶解除去し、径が0.04mm(40μm)の貫通孔を形成した(図2-4参照)。貫通孔形成後、熱処理温度:800℃、保持時間:3時間の熱処理を施すことにより、基板全体を結晶化させた。熱処理後、基板厚さ方向の貫通孔径の一様性を確保するため、基板表裏面近傍の同径が拡大した部分を研削除去し、基板厚さを0.3mmとした。
(Through hole forming process)
A mask was brought into close contact with the photosensitive glass, and the through hole portion was irradiated with ultraviolet light through the mask to form a latent image corresponding to the exposed portion (see FIG. 2-2). As the mask, quartz glass patterned with Cr / Cr oxide was used. Thereafter, heat treatment was performed at 400 ° C. for 3 hours to crystallize only the exposed portion (see FIG. 2-3). The light source used was a deep UV lamp, and the irradiation energy was 800 mJ / cm 2 . Next, thin hydrofluoric acid (10% solution) was sprayed on the front and back of the photosensitive glass to dissolve and remove the crystallized through-hole glass, thereby forming a through-hole having a diameter of 0.04 mm (40 μm) ( (See Figure 2-4). After forming the through holes, the entire substrate was crystallized by performing a heat treatment temperature of 800 ° C. and a holding time of 3 hours. After the heat treatment, in order to ensure the uniformity of the through-hole diameter in the substrate thickness direction, the portion with the same diameter enlarged in the vicinity of the front and back surfaces of the substrate was ground and removed, so that the substrate thickness was 0.3 mm.

(貫通孔充填工程)
板厚が0.3mmで、径が40μmの貫通孔を全面に有する5インチ角ガラス基板に対して、表裏面同時に接着層たるCr膜を0.05μm厚になるように、Cu膜を2μm厚になるように、それぞれ同一真空中で連続的に、DCマグネトロンスパッタ法により成膜した。次いで、表裏面および貫通孔側壁に無電解銅めっき被膜を0.3μm厚に形成し、さらに無電解銅めっき層を給電層(陰極)とし、硫酸銅タイプ電解銅めっきにより貫通孔側壁に、10μm厚のCu層を析出させた。この時、貫通孔中央部に残存する基板表裏面に連通する空隙の孔径は20μmである(図3-2参照)。
(Through hole filling process)
For a 5-inch square glass substrate with a plate thickness of 0.3 mm and a through-hole with a diameter of 40 μm on the entire surface, the Cu film is 2 μm thick so that the Cr film as the adhesion layer at the same time on the front and back surfaces is 0.05 μm thick. Thus, the films were continuously formed in the same vacuum by the DC magnetron sputtering method. Next, an electroless copper plating film is formed to a thickness of 0.3 μm on the front and back surfaces and the side wall of the through hole, and the electroless copper plating layer is used as a power feeding layer (cathode). A thick Cu layer was deposited. At this time, the hole diameter of the air gap communicating with the front and back surfaces of the substrate remaining in the central portion of the through hole is 20 μm (see FIG. 3-2).

次いで、ロジン系フラックス(株式会社日本スペリア社製:NS−828A:活性化温度200〜300℃)をアルコール(C2H5OH)により50vol%希釈したフラックス浴槽に、前記貫通孔側壁に10μm厚のCu層を析出させた結晶化ガラス基板を30分間浸漬させた後、90℃で10分間、クリーンオーブン内で希釈溶剤を十分に乾燥させた。以上で、表裏面および貫通孔内Cu表面のフラックス処理により活性化を完了した(図3-3参照)。 Next, a rosin flux (manufactured by Nippon Superior Co., Ltd .: NS-828A: activation temperature 200-300 ° C.) diluted to 50 vol% with alcohol (C 2 H 5 OH) was added to the through hole side wall at a thickness of 10 μm. After the crystallized glass substrate on which the Cu layer was deposited was immersed for 30 minutes, the diluted solvent was sufficiently dried in a clean oven at 90 ° C. for 10 minutes. Thus, the activation was completed by the flux treatment of the front and back surfaces and the Cu surface in the through hole (see FIG. 3-3).

別に、SiC製耐熱ボート内に、粒状Sn(三津和化学株式会社製:純度4N)を液相線温度(融点:232℃)以上である250℃で溶融した。但し、オーブン内熱対流の影響により、一部液相線温度に達しない部分が存在した為、250℃まで昇温させたが、温度均一性が良好なオーブンであれば232℃でも十分である。次いで、フラックス処理を施した基板を、200℃のオーブンで5分程度予備加熱した後、表層の酸化物を除去した液相Sn上にフローさせる。この時点から、毛細管現象により2分後には貫通孔空隙部にSnの充填が確認された(図3-4参照)。ガラス基板の予備加熱は、室温にある基板を液相Sn上にフローさせる時、温度差による基板破損の要因になる為であるが、十分に強度を持った、例えば板厚0.6mmの場合などは、予備加熱は必要ない。さらに、フラックス希釈溶剤乾燥90℃直後に投入しても良いし、200℃に限定したものではない。但し、本実施例で使用したフラックスは、300℃より高温では急激に酸化が進行し、活性化の意味をなさない。予備加熱が無い場合に、10%程度(10回に1回程度)の基板破損を確認したが、初期基板に欠陥を有していた為であって、無欠陥の基板であれば、あえて予備加熱の必要性はない。   Separately, granular Sn (manufactured by Mitsuwa Chemical Co., Ltd .: purity 4N) was melted in a SiC heat-resistant boat at a liquidus temperature (melting point: 232 ° C.) or higher at 250 ° C. However, because there was a part that did not reach the liquidus temperature due to the effect of thermal convection in the oven, the temperature was raised to 250 ° C, but 232 ° C is sufficient if the oven has good temperature uniformity. . Next, the substrate subjected to the flux treatment is preheated in an oven at 200 ° C. for about 5 minutes, and then is flowed onto the liquid phase Sn from which the surface layer oxide is removed. From this point of time, it was confirmed that Sn was filled in the through hole voids after 2 minutes due to capillary action (see FIG. 3-4). This is because preheating of the glass substrate causes damage to the substrate due to a temperature difference when a substrate at room temperature is flowed onto the liquid phase Sn. For example, preheating is not necessary. Further, it may be added immediately after the flux dilution solvent drying 90 ° C., and is not limited to 200 ° C. However, the flux used in this example rapidly oxidizes at a temperature higher than 300 ° C., and does not make sense for activation. In the absence of preheating, we confirmed about 10% (about once in 10 times) of substrate breakage, but because the initial substrate had a defect and it was a defect-free substrate, it was intentionally reserved There is no need for heating.

充填完了後、液相Snから基板を取り出し、公知慣用の研磨手法により、基板表裏面に付着している合金層を除去した。
次いで、Snが充填され、かつ表裏面にガラス面が露出された基板の熱処理を実施した。熱処理は、クリーンオーブン内において、窒素気流中で、300℃、400℃、500℃、及び600℃の各温度で10分間実施した。熱処理前、及び熱処理後の貫通孔内の状態、及び合金組成の分布を、貫通孔断面のSEM像分析およびEPMA(電子線マイクロアナライザー)による特性X線分析によるSn及びCu濃度のマッピングにより相互拡散を確認した。このときの電子線加速電圧は15kV、照射電流は100nA、及び電子ビーム径は1μmである。図5〜図7に、熱処理前、500℃で10分間、及び600℃10分間の熱処理を施した場合のCu及びSnの濃度分布を示す。図中、横軸は貫通孔を横断する方向の位置を、縦軸は濃度を任意単位で示したものである。
熱処理前においては、貫通孔中心線近傍のCu濃度、及び貫通孔端部のSn濃度は、ほぼノイズレベルであり、殆ど合金化が進行していなかった。
500℃、10分間の熱処理を施した場合、貫通孔中心線近傍において顕著な合金化が認められたが、貫通孔端部においては合金化が殆ど進行しておらず、貫通孔端部でのCu濃度が高く、中心線近傍では低い、と云うCu濃度分布が認められた。このとき、貫通孔中央部近傍の合金組成は、Cu:65wt%、Sn:35wt%であった。この場合、Cu−Sn2元系平衡状態図(例えば、文献:T.B. Massalski著Binary Alloy Phase Diagrams (2nd edition) P.1482 (ASM社1990年発行) 参照)から予測される合金の融点は、約750℃で、充分な耐熱性が得られていることが確認できた。
また、600℃、10分間の熱処理を施した場合には、貫通孔内部での組成分布は認められず、ほぼ一様であり、その合金組成は、Cu:79wt%、Sn:21wt%であった。この場合、上記Cu−Sn2元系平衡状態図から予測される合金の融点は、910℃で、500℃、10分間の熱処理を施した場合に比べて、更に高い耐熱性が得られていることが確認できた。
なお、熱処理温度:300℃、400℃の場合には、顕著な合金化は認められなかった。
最後に、前記基板(露出ガラス)面の平滑性および平坦性を得るために、周知のコロイダルシリカを利用したCMP法により、貫通配線絶縁基板を得た(図4-2参照)。
After the completion of filling, the substrate was taken out from the liquid phase Sn, and the alloy layer adhering to the front and back surfaces of the substrate was removed by a known and usual polishing technique.
Next, heat treatment was performed on the substrate filled with Sn and the glass surfaces exposed on the front and back surfaces. The heat treatment was performed in a clean oven in a nitrogen stream at 300 ° C., 400 ° C., 500 ° C., and 600 ° C. for 10 minutes. Interdiffusion of the state of through-holes before and after heat treatment, and the distribution of the alloy composition by mapping the Sn and Cu concentrations by cross-sectional SEM image analysis and characteristic X-ray analysis by EPMA (electron beam microanalyzer) It was confirmed. At this time, the electron beam acceleration voltage is 15 kV, the irradiation current is 100 nA, and the electron beam diameter is 1 μm. 5 to 7 show Cu and Sn concentration distributions when heat treatment is performed at 500 ° C. for 10 minutes and at 600 ° C. for 10 minutes before heat treatment. In the figure, the horizontal axis indicates the position in the direction crossing the through hole, and the vertical axis indicates the concentration in arbitrary units.
Prior to the heat treatment, the Cu concentration in the vicinity of the through-hole center line and the Sn concentration at the end of the through-hole were almost at the noise level, and almost no alloying proceeded.
When heat treatment was performed at 500 ° C. for 10 minutes, remarkable alloying was observed in the vicinity of the center line of the through hole, but alloying hardly progressed at the end of the through hole, and at the end of the through hole. A Cu concentration distribution was observed with high Cu concentration and low near the center line. At this time, the alloy composition in the vicinity of the central portion of the through hole was Cu: 65 wt% and Sn: 35 wt%. In this case, Cu-Sn2 ternary equilibrium diagram (e.g., the literature: TB Massalski al Binary Alloy Phase Diagrams (2 nd edition ) P.1482 (ASM , published 1990) refer) melting point of the alloy to be predicted from, about It was confirmed that sufficient heat resistance was obtained at 750 ° C.
In addition, when heat treatment was performed at 600 ° C. for 10 minutes, the composition distribution inside the through-hole was not recognized and was almost uniform, and the alloy composition was Cu: 79 wt% and Sn: 21 wt%. It was. In this case, the melting point of the alloy predicted from the Cu—Sn binary system equilibrium diagram is 910 ° C., and higher heat resistance is obtained compared to the case where heat treatment is performed at 500 ° C. for 10 minutes. Was confirmed.
When the heat treatment temperature was 300 ° C. or 400 ° C., significant alloying was not observed.
Finally, in order to obtain the smoothness and flatness of the substrate (exposed glass) surface, a through wiring insulating substrate was obtained by a CMP method using well-known colloidal silica (see FIG. 4-2).

(配線用導体パターンの形成)
スパッタ装置を使用し、前記ガラス基板の表裏に、Cr膜を0.05μm厚に成膜した。次にスパッタ装置を使用し、2μm厚のCu膜を成膜した。次に、ポジ型の液状レジスト(東京応化工業社製ポジ型レジストTGMR−1000)をスピンナーで約4μmの厚さで塗布した後、ガラスマスクを使い、平行光露光機で400mJ/cm2露光を行った。続いて、現像液(東京応化工業社製 現像液NMD−3)により2分間室温でディップ現像し、レジストパターンを形成した。レジストパターンが形成された上記配線層に40ボーメの塩化第二鉄溶液をスプレーしてCuエッチングを行った後、レジストをアセトンにより除去した。続いて、Cuパターンを金属レジストとしてCr層をエッチングして、線幅:10μm、間隙:10μm、スルーホールランド幅:120μmの配線パターンを形成した。これにより両面配線基板を得た。なお、Crエッチング液として、フェリシアン化カリを主成分とする薬品を使用した。
(Formation of conductor pattern for wiring)
Using a sputtering apparatus, a Cr film having a thickness of 0.05 μm was formed on the front and back of the glass substrate. Next, a Cu film having a thickness of 2 μm was formed using a sputtering apparatus. Next, a positive liquid resist (positive resist TGMR-1000 manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied with a spinner to a thickness of about 4 μm, and then exposed to 400 mJ / cm 2 with a parallel light exposure machine using a glass mask. went. Subsequently, dip development was performed for 2 minutes at room temperature with a developer (developer NMD-3 manufactured by Tokyo Ohka Kogyo Co., Ltd.) to form a resist pattern. After the Cu layer was sprayed by spraying a 40 Baume ferric chloride solution onto the wiring layer on which the resist pattern was formed, the resist was removed with acetone. Subsequently, the Cr layer was etched using the Cu pattern as a metal resist to form a wiring pattern having a line width of 10 μm, a gap of 10 μm, and a through-hole land width of 120 μm. This obtained the double-sided wiring board. In addition, the chemical | medical agent which has potassium ferricyanide as a main component was used as Cr etching liquid.

(実施例2)
この実施例は、貫通孔形成等の多くの構成が実施例1と共通するので、以下では、実施例1と異なる部分を主として説明する。板厚が0.3mm、径が40μmの貫通孔を全面に有する5インチ角ガラス基板に対して、表裏面同時に接着層たるCr膜を0.05μm厚に、及びCu膜を2μm厚にを同一真空中で連続的に、DCマグネトロンスパッタ法により成膜した。次いで、表裏面および貫通孔側壁に無電解銅めっき被膜を0.3μm厚に形成し、さらに無電解銅めっき層を給電層(陰極)とし、硫酸銅タイプ電解銅めっきにより貫通孔側壁部に、C5μm厚のCu層を析出させた。この時、貫通孔中央部に残存する基板表裏面に連通する空隙の孔径は30μmである。
(Example 2)
Since this embodiment has many configurations such as through-hole formation in common with the first embodiment, the following description will mainly focus on differences from the first embodiment. For a 5-inch square glass substrate with through-holes with a plate thickness of 0.3 mm and a diameter of 40 μm on the entire surface, the Cr film as the adhesion layer at the same time on the front and back surfaces is 0.05 μm thick, and the Cu film is 2 μm thick. Films were continuously formed in a vacuum by a DC magnetron sputtering method. Next, an electroless copper plating film is formed to a thickness of 0.3 μm on the front and back surfaces and the side wall of the through hole, and the electroless copper plating layer is used as a power feeding layer (cathode). A C5 μm thick Cu layer was deposited. At this time, the hole diameter of the gap communicating with the front and back surfaces of the substrate remaining in the central portion of the through hole is 30 μm.

実施例1と同様に、フラックス処理施し、次に、基板を、250℃液相Sn上にフローさせ、2分間毛細管現象によりSn充填を実施した。次いで、両面厚膜を除去後、クリーンオーブン内において、窒素気流中で600℃、10分間の拡散熱処理を実施した。熱処理後の合金組成は、貫通孔内部で一様であり、Cu:49wt%、Sn:51wt%であった。この場合、上記Cu−Sn2元系平衡状態図から予測される合金の融点は、700℃で、高い耐熱性が得られていることが確認できた。   In the same manner as in Example 1, flux treatment was performed, and then the substrate was flowed onto liquid phase Sn at 250 ° C., and Sn filling was performed by capillary action for 2 minutes. Next, after removing the double-sided thick film, diffusion heat treatment was performed in a clean oven at 600 ° C. for 10 minutes in a nitrogen stream. The alloy composition after the heat treatment was uniform inside the through hole, and was Cu: 49 wt% and Sn: 51 wt%. In this case, it was confirmed that the melting point of the alloy predicted from the Cu—Sn binary system equilibrium diagram is 700 ° C. and high heat resistance is obtained.

(実施例3)
この実施例も、貫通孔形成等の多くの構成が実施例1と共通するので、以下では、実施例1と異なる部分を主として説明する。板厚が0.3mm、径が40μmの貫通孔を全面に有する5インチ角ガラス基板に対して、表裏面同時にCr膜を0.05μm厚に、及びCu膜を2μm厚に同一真空中で連続的に、DCマグネトロンスパッタ法により成膜した。次いで、表裏面および貫通孔側壁に無電解銅めっき被膜を0.3μm厚に形成し、さらに無電解銅めっき層を給電層(陰極)とし、硫酸銅タイプ電解銅めっきにより貫通孔側壁に、Cu層を10μm厚に析出させた。この時、貫通孔中央部に残存する基板表裏面に連通する空隙の孔径は20μmである。
(Example 3)
Since this embodiment also has many configurations such as the formation of through-holes in common with the first embodiment, the following description will mainly focus on differences from the first embodiment. For a 5-inch square glass substrate with through-holes with a plate thickness of 0.3 mm and a diameter of 40 μm on the entire surface, the Cr film is continuously 0.05 μm thick and the Cu film is 2 μm thick at the same time in the same vacuum. Specifically, the film was formed by DC magnetron sputtering. Next, an electroless copper plating film is formed to a thickness of 0.3 μm on the front and back surfaces and the side wall of the through hole, and the electroless copper plating layer is used as a power feeding layer (cathode). The layer was deposited to a thickness of 10 μm. At this time, the hole diameter of the air gap communicating with the front and back surfaces of the substrate remaining in the central portion of the through hole is 20 μm.

市販の低融点はんだ(日本スペリア社製:型番SN96Cl)、Ag:3.8wt%、Cu:1.0wt%、Sn:bal.(融点:217℃)を、クリーンオーブン内で液相を形成した(液温:230℃)。実施例1と同様に、フラックス処理施した基板を、230℃液相低融点はんだ上にフローさせ、2分間毛細管現象によりはんだを充填した。次いで、両面厚膜を除去後、クリーンオーブン内において、窒素気流中で600℃、10分間の拡散熱処理を実施した。熱処理後の合金組成は、貫通孔内部で一様であり、Cu:85wt%、Sn:14wt%、Ag:1wt%であった。
本実施例により成る両面配線基板の耐熱性を評価するために、温度:600℃のクリーンオーブン中に3時間放置した。その結果、充填された貫通孔近傍に於いて、形状等の変化は認められず、良好な耐熱性を有していることが確認できた。
Commercially available low melting point solder (Nippon Superior Co., Ltd .: Model No. SN96Cl), Ag: 3.8 wt%, Cu: 1.0 wt%, Sn: bal. (Melting point: 217 ° C.) formed a liquid phase in a clean oven (liquid temperature: 230 ° C.). As in Example 1, the flux-treated substrate was flowed onto a 230 ° C. liquid phase low melting point solder and filled with solder by capillary action for 2 minutes. Next, after removing the double-sided thick film, diffusion heat treatment was performed in a clean oven at 600 ° C. for 10 minutes in a nitrogen stream. The alloy composition after the heat treatment was uniform inside the through hole, and was Cu: 85 wt%, Sn: 14 wt%, and Ag: 1 wt%.
In order to evaluate the heat resistance of the double-sided wiring board according to this example, the substrate was left in a clean oven at a temperature of 600 ° C. for 3 hours. As a result, no change in shape or the like was observed in the vicinity of the filled through hole, and it was confirmed that the film had good heat resistance.

(実施例4)
この実施例も、貫通孔形成等の多くの構成が実施例1と共通するので、以下では、実施例1と異なる部分を主として説明する。板厚が0.3mmで、径が40μmの貫通孔を全面に有する5インチ角ガラス基板に対して、表裏面同時にCr膜を0.05μm厚に、及びCu膜を2μm厚に同一真空中で連続的に、DCマグネトロンスパッタ法により成膜した。次いで、表裏面および貫通孔側壁に無電解銅めっき被膜を0.3μm厚に形成し、さらに無電解銅めっき層を給電層(陰極)とし、硫酸銅タイプ電解銅めっきにより貫通孔側壁部に、5μm厚のCu層を析出させた。この時、貫通孔中央部に残存する基板表裏面に連通する空隙の孔径は30μmである。
Example 4
Since this embodiment also has many configurations such as the formation of through-holes in common with the first embodiment, the following description will mainly focus on differences from the first embodiment. For a 5-inch square glass substrate with a plate thickness of 0.3 mm and a through-hole with a diameter of 40 μm on the entire surface, the Cr film has a thickness of 0.05 μm and the Cu film has a thickness of 2 μm at the same time in the same vacuum. Films were continuously formed by DC magnetron sputtering. Next, an electroless copper plating film is formed to a thickness of 0.3 μm on the front and back surfaces and the side wall of the through hole, and the electroless copper plating layer is used as a power feeding layer (cathode). A 5 μm thick Cu layer was deposited. At this time, the hole diameter of the gap communicating with the front and back surfaces of the substrate remaining in the central portion of the through hole is 30 μm.

市販の低融点はんだ(日本スペリア社製:型番SN100C)、Cu:0.7wt%、Ni:0.1wt%、Sn:bal(融点:227℃)を、クリーンオーブン内(液温:250℃)で液相を形成した。実施例1と同様に、フラックス処理施した基板を、250℃液相低融点はんだ上にフローさせ、2分間毛細管現象によりはんだを充填をした。次いで、両面厚膜を除去後、クリーンオーブン内において、窒素気流中で600℃、10分間の拡散熱処理を実施した。熱処理後の合金組成は、貫通孔内部で一様であり、Cu:85wt%、Sn:46.7wt%、Ni:0.3wt%であった。
本実施例により成る両面配線基板の耐熱性を評価するために、温度:600℃のクリーンオーブン中に3時間放置した。その結果、充填された貫通孔近傍に於いて、形状等の変化は認められず、良好な耐熱性を有していることが確認できた。
Commercially available low melting point solder (Nippon Superior Co., Ltd .: Model No. SN100C), Cu: 0.7 wt%, Ni: 0.1 wt%, Sn: bal (melting point: 227 ° C) in a clean oven (liquid temperature: 250 ° C) A liquid phase was formed. As in Example 1, the flux-treated substrate was flowed onto a 250 ° C. liquid phase low melting point solder and filled with solder by capillary action for 2 minutes. Next, after removing the double-sided thick film, diffusion heat treatment was performed in a clean oven at 600 ° C. for 10 minutes in a nitrogen stream. The alloy composition after the heat treatment was uniform inside the through hole, and was Cu: 85 wt%, Sn: 46.7 wt%, and Ni: 0.3 wt%.
In order to evaluate the heat resistance of the double-sided wiring board according to this example, the substrate was left in a clean oven at a temperature of 600 ° C. for 3 hours. As a result, no change in shape or the like was observed in the vicinity of the filled through hole, and it was confirmed that the film had good heat resistance.

(比較例)
この比較例は、上述の特許文献3に記載の方法によって、貫通孔内にSn100%の導電性材料を充填形成したものである。この比較例では、230℃の耐熱性しか得られなかった。
以上、本発明について実施例を用いて詳細に説明したが、貫通孔充填後に施される熱処理の条件は、本実施例に記載した条件に限定されるものではない。すなわち、拡散過程における温度と時間との相補性を考慮すれば、本実施例で得られた結果は、本実施例で記載した温度、時間条件のみで得られるものではなく、異なる熱処理温度、熱処理時間においても実現されるものである。従って、本実施例においては、熱処理温度が300℃、及び400℃の場合、顕著な合金化の進行は認められなかったが、熱処理時間を充分長くすることにより合金化を顕在化させることが可能である。
(Comparative example)
In this comparative example, a conductive material of 100% Sn is filled in the through hole by the method described in Patent Document 3 described above. In this comparative example, only heat resistance of 230 ° C. was obtained.
As mentioned above, although this invention was demonstrated in detail using the Example, the conditions of the heat processing performed after through-hole filling are not limited to the conditions described in the present Example. That is, considering the complementarity between temperature and time in the diffusion process, the results obtained in this example are not obtained only with the temperature and time conditions described in this example, but different heat treatment temperatures and heat treatments. It is also realized in time. Therefore, in this example, when the heat treatment temperatures were 300 ° C. and 400 ° C., remarkable progress of alloying was not recognized, but the alloying can be made obvious by sufficiently increasing the heat treatment time. It is.

本発明は、両面配線基板の微細化に対応でき、耐熱性、気密性及び信頼性に優れ、かつ、量産性に富んだ両面配線基板及びその製造方法を提供するもので、近年のMEMS(マイクロ・エレクトロ・メカニカル・システム)技術を応用した電子デバイスや光デバイス等の技術分野等において利用できる。   The present invention provides a double-sided wiring board that can cope with the miniaturization of a double-sided wiring board, is excellent in heat resistance, airtightness, reliability, and mass production, and a manufacturing method thereof. (Electro-mechanical system) It can be used in technical fields such as electronic devices and optical devices applying technology.

本発明の実施の形態にかかる両面配線基板の断面図である。It is sectional drawing of the double-sided wiring board concerning embodiment of this invention. 貫通孔形成工程の説明図である。It is explanatory drawing of a through-hole formation process. 導電性材の形成工程の説明図である。It is explanatory drawing of the formation process of an electroconductive material. 導電性材の形成工程の説明図である。It is explanatory drawing of the formation process of an electroconductive material. Sn充填後の貫通孔内におけるCu及びSnの濃度分布を示す図である。It is a figure which shows the density | concentration distribution of Cu and Sn in the through-hole after Sn filling. 500℃で10分間熱処理した後の貫通孔内におけるCu及びSnの濃度分布を示す図である。It is a figure which shows Cu and Sn density | concentration distribution in the through-hole after heat-processing for 10 minutes at 500 degreeC. 600℃で10分間熱処理した後の貫通孔内におけるCu及びSnの濃度分布を示す図である。It is a figure which shows the density | concentration distribution of Cu and Sn in the through-hole after heat-processing for 10 minutes at 600 degreeC.

符号の説明Explanation of symbols

1・・・基板
1a,1b・・・基板両面(表裏面)
2a.2b・・・配線層
2c.2d・・・接着層
3・・・貫通孔
4・・・導電性材料
1 ... Substrate 1a, 1b ... Both sides of substrate (front and back)
2a. 2b ... wiring layer 2c. 2d ... adhesive layer 3 ... through hole 4 ... conductive material

Claims (6)

基板と、この基板の両面に設けられた配線層と、前記基板の両面を貫通する貫通孔と、この貫通孔内に導電性材料が充填形成されて前記両面の配線層を電気的に接続可能にする導電部とを有し、前記導電性材料は、Cu、Sn、Mからなり、Cu、Sn、Mの組成比が重量%(wt%)で、49%≦Cu≦85%、14%≦Sn≦51%、0%≦M<1%であって、
前記導電性材料のCu濃度が前記貫通孔の径方向で一様ではなく、前記貫通孔の側壁部近傍から貫通孔の中心線近傍に向かうにしたがって減少していることを特徴とする両面配線基板。
ただし、MはAu,Ag,Niから選定された少なくとも1種の金属であるものとする。
A board, a wiring layer provided on both sides of the board, a through-hole penetrating both sides of the board, and a conductive material filled in the through-hole to electrically connect the wiring layers on both sides The conductive material is made of Cu, Sn, and M, and the composition ratio of Cu, Sn, and M is wt% (wt%), and 49% ≦ Cu ≦ 85%, 14%. ≦ Sn ≦ 51%, 0% ≦ M <1%,
The double-sided wiring board , wherein the Cu concentration of the conductive material is not uniform in the radial direction of the through hole, and decreases from the vicinity of the side wall portion of the through hole toward the vicinity of the center line of the through hole .
Here, M is at least one metal selected from Au, Ag, and Ni.
前記導電性材料のCu濃度が前記貫通孔の径方向で一様ではなく、前記貫通孔の側壁部近傍で最大であり、かつ前記貫通孔の中心線近傍で最小であることを特徴とする請求項1に記載の両面配線基板。 Claims Cu concentration of the conductive material is not uniform in the radial direction of the through hole is greatest side wall portion near the through hole, and characterized in that it is a minimum at the center line near the through hole Item 2. The double-sided wiring board according to item 1 . 基板の両面を貫通する貫通孔内に導電性材料を充填形成することによって前記基板両面に形成された配線層を電気的に接続可能にする導電部形成工程を有する両面配線基板の製造方法であって、
前記導電部形成工程は、前記貫通孔の側壁部にCu若しくはCuを含む合金を、前記貫通孔の中央部に基板両面に連通する空隙部を残して付着させる第1の工程と、
前記貫通孔の側壁部に付着されたCu若しくはCuを含む合金表面にSn若しくはSnを含む合金を付着させるとともに前記空隙部に充填させる第2の工程と、
前記第1の工程で付着させたCu若しくはCuを含む合金と、前記第2の工程で付着・充填させたSn若しくはSnを含む合金とを、熱処理により相互に拡散合金化させる第3の工程とを有することを特徴とする両面配線基板の製造方法。
A method for manufacturing a double-sided wiring board, comprising: a conductive part forming step for electrically connecting wiring layers formed on both sides of the substrate by filling a through hole penetrating both sides of the substrate with a conductive material. And
The conductive portion forming step is a first step of attaching Cu or an alloy containing Cu to the side wall portion of the through hole, leaving a gap portion communicating with both surfaces of the substrate at the central portion of the through hole;
A second step of attaching Sn or an alloy containing Sn to the surface of Cu or an alloy containing Cu attached to the side wall portion of the through hole and filling the void portion;
A third step of forming a diffusion alloy with each other by heat treatment of Cu or an alloy containing Cu deposited in the first step and an alloy containing Sn or Sn deposited and filled in the second step; A method for producing a double-sided wiring board, comprising:
前記第1の工程が、メッキ法によりCu若しくはCuを含む合金を前記貫通孔の側壁部に付着させる工程であることを特徴とする請求項3に記載の両面配線基板の製造方法。 4. The method for manufacturing a double-sided wiring board according to claim 3 , wherein the first step is a step of attaching Cu or an alloy containing Cu to the side wall portion of the through hole by a plating method. 前記第2の工程が、Sn若しくはSnを含む合金を加熱溶融した溶融金属に、前記第1
の工程を経た基板を接触させ、毛細管現象により前記Sn若しくはSnを含む合金を、前記空隙部に充填させるものであることを特徴とする請求項3又は4に記載の両面配線基板の製造方法。
In the second step, the first metal is added to the molten metal obtained by heating and melting Sn or an alloy containing Sn.
5. The method for manufacturing a double-sided wiring board according to claim 3 , wherein the substrate having undergone the step is brought into contact, and the gap or the alloy containing Sn is filled into the gap portion by capillary action.
前記貫通孔内部に充填されたCuSn合金、若しくは少なくともCuとSnとを含む合金における平均的なCu濃度を、前記第1の工程で付着させるCu若しくはCuを含む合金の体積によって制御することを特徴とする請求項3乃至5のいずれかに記載の両面配線基板の製造方法。 An average Cu concentration in the CuSn alloy filled in the through-hole or an alloy containing at least Cu and Sn is controlled by the volume of Cu or Cu-containing alloy deposited in the first step. A method for manufacturing a double-sided wiring board according to any one of claims 3 to 5 .
JP2004140236A 2004-05-10 2004-05-10 Double-sided wiring board and manufacturing method thereof Expired - Fee Related JP4471730B2 (en)

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