JP4552407B2 - Thin film transistor - Google Patents

Description

  The present invention relates to a thin film transistor.

  In a conventional thin film transistor manufacturing method, an amorphous silicon thin film formed on a glass substrate is irradiated with an excimer laser to polycrystallize the amorphous silicon thin film into a polysilicon thin film, and pattern the polysilicon thin film. The polysilicon thin film is left only in the thin film transistor forming region on the glass substrate, and the remaining polysilicon thin film is covered with a gate insulating film made of a silicon oxide film formed using TEOS (tetraethoxysilane) as a raw material, By performing discharge reverse sputtering with hydrogen, a surface reduction layer is formed on the surface of the gate insulating film, and a gate electrode made of Mo or Mo-W alloy is formed on the gate insulating film on the central portion of the polysilicon thin film, Impurities are implanted using the gate electrode as a mask. Thus, the polysilicon thin film on both sides of the gate electrode is used as the impurity implantation region, and an interlayer insulating film made of normal silicon oxide is formed on the gate insulating film including the gate electrode, corresponding to the impurity implantation region of the polysilicon thin film. Contact hole is formed in interlayer insulating film, surface reduction layer and gate insulating film in region, and source electrode and drain electrode are formed on interlayer insulating film by connecting to impurity implanted region of polysilicon thin film through contact hole (For example, refer to Patent Document 1).

Japanese Patent Laid-Open No. 2001-242489

  In the above conventional example, the gate insulating film is formed of a silicon oxide film formed using TEOS as a raw material in order to form a dense gate insulating film at a relatively low temperature. Further, the surface reduction layer is for improving adhesion between a gate insulating film made of a silicon oxide film formed using TEOS as a raw material and a gate electrode made of Mo or Mo—W alloy.

  By the way, when the gate insulating film is formed of a silicon oxide film formed using TEOS as a raw material, a dense gate insulating film can be formed at a relatively low temperature. No consideration has been given to. As a result of investigation by the present inventors, when a gate electrode made of Mo or Mo—W alloy is formed on a gate insulating film made of a silicon oxide film formed using TEOS as a raw material, a high temperature voltage application test (Bias Temperature As a result of performing Stress (hereinafter referred to as BT test), it was found that the threshold voltage Vth of the thin film transistor is greatly shifted.

  Therefore, the present invention provides a thin film transistor that can prevent the threshold voltage Vth of the thin film transistor by the BT test from shifting substantially even if the gate insulating film is formed of a silicon oxide film formed using TEOS as a raw material. The purpose is to do.

In the first aspect of the invention, a gate insulating film is provided between a gate electrode and a semiconductor thin film having a channel region, a source region and a drain region into which impurities are implanted, and the gate insulating film is formed using TEOS as a raw material. In the thin film transistor formed of the formed silicon oxide film, the gate electrode is disposed so as to be in contact with the first gate electrode layer and the first gate electrode layer disposed so as to be in contact with the gate insulating film. is formed in a multilayer structure having a second gate electrode layer, the second gate electrode layer, Mo as the material, Cr, Ri Do either from or their alloys of Ta, the first gate electrode layer, and characterized in that it is formed in the material W or W-based metal of the easily oxidized metal than the material for forming the second gate electrode layer Is shall.
According to a second aspect of the present invention, in the first aspect of the present invention, the contact surface of the first gate electrode layer with the gate insulating film is oxidized.
According to a third aspect of the invention, in the first aspect of the invention, the first gate electrode layer has a block layer that blocks moisture from the gate insulating film on a contact surface with the gate insulating film. Ru der those characterized by that it is.

According to the present invention, even if the gate insulating film is formed of a silicon oxide film formed using TEOS as a raw material, the threshold voltage Vth of the thin film transistor by the BT test can be hardly shifted.

  FIG. 1 shows a cross-sectional view of a main part of an example of a liquid crystal display element having a thin film transistor as one embodiment of the present invention. The liquid crystal display element includes a glass substrate 1. A polysilicon thin film 2 is provided at a predetermined location on the upper surface of the glass substrate 1. The central portion of the polysilicon thin film 2 is a channel region 2a made of an intrinsic region, and both sides thereof are a source region 2b and a drain region 2c made of an n-type impurity implantation region.

  On the upper surface of the glass substrate 1 including the polysilicon thin film 2, a gate insulating film 3 made of a silicon oxide film formed using TEOS as a raw material is provided. A gate electrode 4 is provided on the upper surface of the gate insulating film 3 on the channel region 2 a of the polysilicon thin film 2. In this case, the gate electrode 4 has a two-layer structure including a lower gate electrode 4a made of Al and an upper gate electrode 4b made of Mo. The reason why the gate electrode 4 has such a structure will be described later.

  An interlayer insulating film 5 made of silicon nitride is provided on the upper surface of the gate insulating film 3 including the gate electrode 4. Contact holes 6 and 7 are provided in the interlayer insulating film 5 and the gate insulating film 3 on the source region 2 b and the drain region 2 c of the polysilicon thin film 2. A source electrode 8 and a drain electrode 9 made of Al are connected to the source region 2b and the drain region 2c of the polysilicon thin film 2 through contact holes 6 and 7, respectively, at predetermined positions on the upper surface of the interlayer insulating film 5. ing.

  The polysilicon thin film 2, the gate insulating film 3, the gate electrode 4, the interlayer insulating film 5, the source electrode 8 and the drain electrode 9 constitute a thin film transistor 10.

  An overcoat film 11 made of silicon nitride is provided on the upper surface of the interlayer insulating film 5 including the source electrode 8 and the drain electrode 9. A contact hole 12 is provided in the overcoat film 11 on the source electrode 8. A pixel electrode 13 made of ITO is connected to the source electrode 8 through a contact hole 12 at a predetermined location on the upper surface of the overcoat film 11.

  Next, an example of a method for manufacturing the liquid crystal display element will be described. First, as shown in FIG. 2, an amorphous silicon thin film 21 is formed on the upper surface of the glass substrate 1 by PECVD using silane-based gas. Next, the amorphous silicon thin film 21 is polycrystallized by irradiating an excimer laser to form the polysilicon thin film 2.

  Next, by patterning the polysilicon thin film 2, the polysilicon thin film 2 is left only in the thin film transistor formation region on the upper surface of the glass substrate 1, as shown in FIG. Next, a gate insulating film 3 made of silicon oxide is formed on the upper surface of the glass substrate 1 including the polysilicon thin film 2 at a temperature of 250 to 350 ° C. by PECVD, APCVD, or LPCVD using TEOS gas. Film.

  Next, an Al-based metal film and a Mo film are continuously formed on the upper surface of the gate insulating film 3 on the center of the polysilicon thin film 2 by a PVD (Physical Vapor Deposition) method such as a vacuum deposition method or a sputtering method, By patterning, the gate electrode 4 having a two-layer structure including the lower layer gate electrode 4a and the upper layer gate electrode 4b is formed. In this case, the film thickness of the lower gate electrode 4a is 50 to 500 mm, and the film thickness of the upper gate electrode 4b is about 2000 mm to 3000 mm.

  Next, as shown in FIG. 4, by implanting n-type impurities using the gate electrode 4 as a mask, the polysilicon thin film 2 on both sides of the gate electrode 4 is transformed into a source region 2b and a drain region 2c made of n-type impurity implanted regions. And Therefore, in this state, the channel region 2a is formed in a self-aligned manner in the central portion of the polysilicon thin film 2 below the gate electrode 4. Next, impurity activation treatment is performed by an appropriate method such as laser annealing or furnace annealing.

  Next, as shown in FIG. 1, an interlayer insulating film 5 made of silicon nitride is formed on the upper surface of the gate insulating film 3 including the gate electrode 4 by PECVD. Next, contact holes 6 and 7 are formed in the interlayer insulating film 5 and the gate insulating film 3 on the source region 2 b and the drain region 2 c of the polysilicon thin film 2.

  Next, an Al film formed by the PVD method is patterned on each predetermined portion of the upper surface of the interlayer insulating film 5 to connect the source electrode 8 and the drain electrode 9 to the polysilicon thin film via the contact holes 6 and 7. Two source regions 2b and a drain region 2c are connected. Next, an overcoat film 11 made of silicon nitride is formed on the upper surface of the interlayer insulating film 5 including the source electrode 8 and the drain electrode 9 by PECVD.

  Next, a contact hole 12 is formed in the overcoat film 11 on the source electrode 8. Next, the ITO film formed by the PVD method is patterned at a predetermined position on the upper surface of the overcoat film 11 so that the pixel electrode 13 is connected to the source electrode 8 through the contact hole 12. Thus, a liquid crystal display element including the thin film transistor 10 is obtained.

  Next, experimental results will be described. For comparison, the thin film transistor having the two-layered gate electrode 4 (hereinafter referred to as the present invention) manufactured by the above manufacturing method is the same manufacturing method as the above manufacturing method, but the gate electrode is made of only Mo. A thin film transistor formed (hereinafter referred to as a comparative product) is prepared, and a BT test is performed for 2 hours at a temperature of 100 ° C. with the source electrode and the drain electrode grounded and +12 V applied to the gate electrode. It was.

  When the Vg (gate voltage) -Id (drain current) characteristics of the thin film transistors of the present invention and the comparative product before and after the BT test were examined, the results shown in FIG. 5 were obtained in the case of the present invention. In the case of the product, the result shown in FIG. 6 was obtained.

  In the case of the comparative product shown in FIG. 6, the solid line is the Vg-Id characteristic before the BT test, the dotted line is the Vg-Id characteristic after the BT test, and the threshold voltage Vth is after the BT test indicated by the dotted line. Compared to before the BT test indicated by the solid line, it is greatly shifted to the minus side. On the other hand, in the case of the invention shown in FIG. 5, the Vg-Id characteristic is shown by only one solid line, but this is almost the same between the Vg-Id characteristic before the BT test and after the BT test. As a result, the shift of the threshold voltage Vth could hardly be confirmed.

  In consideration of the above, when the gate insulating film is formed of a silicon oxide film formed using TEOS as a raw material, external energy (BT test) is caused by moisture taken into the gate insulating film. In the case of the comparative product, the surface side of the gate electrode that is in contact with the gate insulating film is oxidized, and positive fixed charges are generated in the gate insulating film. The threshold voltage Vth of the thin film transistor is greatly shifted to the negative side.

  On the other hand, in the case of the product of the present invention, the gate electrode 4 has a two-layer structure of a lower gate electrode 4a made of Al and an upper gate electrode 4b made of Mo. The history promotes the reaction between the lower gate electrode 4a made of Al which is easily oxidized and the moisture taken into the gate insulating film 3, and the Al oxide film is formed on the surface side of the lower gate electrode 4a in contact with the gate insulating film 3. It is formed.

  As a result, in the case of the product of the present invention, the Al oxide film is formed on the surface side of the lower gate electrode 4a in contact with the gate insulating film 3 before the BT test. The Al oxide film functions as a block layer that blocks moisture from the gate insulating film 3, and the generation of positive fixed charges in the gate insulating film 3 is prevented in advance, whereby the threshold of the thin film transistor 10 by the BT test is achieved. The value voltage Vth can be hardly shifted, and the reliability of the thin film transistor 10 can be increased.

  The material of the lower gate electrode 4a may be any metal that is more easily oxidized than the material of the upper gate electrode 4b. For example, when the upper gate electrode 4b is formed of Mo, Cr, Ta or an alloy thereof, the lower gate electrode 4a is made of an alloy of Al, Al and Nd or Ni (Al-based metal) or W, Or you may form with the alloy (W type metal) of W, Si, Mo, etc. When the upper gate electrode 4b is formed of W, the lower gate electrode 4a may be formed of Al-based metal or Cr. Note that another metal material may be formed on the upper gate electrode 4b, and a multilayer gate electrode structure having three or more layers may be employed.

  In the above embodiment, the top gate thin film transistor is described. However, the present invention can also be applied to a bottom gate thin film transistor shown in FIG. The bottom gate type thin film transistor is greatly different from that shown in FIG. 1 in that a gate electrode 4 is provided on the upper surface of the glass substrate 1 and a polysilicon thin film 2 is provided on the upper surface of the gate insulating film 3. is there. In this case, the lower gate electrode 4a is made of Mo or the like, and the upper gate electrode 4b is made of Al or the like.

  Also in this bottom gate type thin film transistor, since the Al oxide film or the like (not shown) is formed on the surface of the upper gate electrode 4b made of Al or the like, the threshold voltage of the thin film transistor 10 by the BT test is formed. Vth can hardly be shifted, and the reliability of the thin film transistor 10 can be increased.

  Here, an example of injecting an n-type impurity in the thin film transistor illustrated in FIG. 7 will be described with reference to FIGS. First, a resist mask 22 is formed at the center of the upper surface of the polysilicon thin film 2 provided on the upper surface of the gate insulating film 3 by backside exposure using the gate electrode 4 as a mask. Then, by implanting n-type impurities using the resist mask 22 as a mask, the polysilicon thin film 2 on both sides of the resist mask 22 is made into a source region 2b and a drain region 2c composed of n-type impurity implanted regions. Therefore, in this state, the channel region 2a is formed in a self-aligned manner at the center of the polysilicon thin film 2 under the resist mask 14.

Sectional drawing of the principal part of an example of the liquid crystal display element provided with the thin-film transistor as one Embodiment of this invention. Sectional drawing of an original process in the case of manufacture of the liquid crystal display element shown in FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. The figure which shows the Vg-Id characteristic before and after the BT test of this invention goods. The figure which shows the Vg-Id characteristic before and behind the BT test of a comparative product. FIG. 6 is a cross-sectional view of a main part of an example of a liquid crystal display element including a bottom-gate thin film transistor. FIG. 8 is a cross-sectional view for explaining an example of injecting an n-type impurity in the thin film transistor shown in FIG. 7.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Polysilicon thin film 3 Gate insulating film 4 Gate electrode 4a Lower layer gate electrode 4b Upper layer gate electrode 5 Interlayer insulating film 8 Source electrode 9 Drain electrode 10 Thin film transistor 11 Overcoat film 13 Pixel electrode

Claims (3)

A gate insulating film is provided between a gate electrode and a semiconductor thin film having a channel region, a source region and a drain region into which impurities are implanted
In the thin film transistor in which the gate insulating film is formed of a silicon oxide film formed using TEOS as a raw material,
The gate electrode has a multi-layer structure including a first gate electrode layer disposed so as to contact the gate insulating film and a second gate electrode layer disposed so as to contact the first gate electrode layer. Formed ,
The second gate electrode layer, Mo as the material, Cr, Ri Do either from or their alloys Ta,
The thin film transistor according to claim 1, wherein the first gate electrode layer is formed of a W or W-based metal among metals that are more easily oxidized than the forming material of the second gate electrode layer .   2. The thin film transistor according to claim 1, wherein a contact surface of the first gate electrode layer with the gate insulating film is oxidized.   2. The thin film transistor according to claim 1, wherein the first gate electrode layer has a block layer that blocks moisture from the gate insulating film on a contact surface with the gate insulating film.

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