JP4548110B2 - Manufacturing method of chip parts - Google Patents

Manufacturing method of chip parts Download PDF

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JP4548110B2
JP4548110B2 JP2004359411A JP2004359411A JP4548110B2 JP 4548110 B2 JP4548110 B2 JP 4548110B2 JP 2004359411 A JP2004359411 A JP 2004359411A JP 2004359411 A JP2004359411 A JP 2004359411A JP 4548110 B2 JP4548110 B2 JP 4548110B2
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frame
gap
chip
manufacturing
insulating resin
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JP2006173159A (en
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美智央 大庭
伸哉 松谷
浩司 下山
祐一 ▲高▼橋
慎一 守本
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Priority to CN 200510134262 priority patent/CN1801415B/en
Priority to US11/301,097 priority patent/US20060091534A1/en
Publication of JP2006173159A publication Critical patent/JP2006173159A/en
Priority to US12/815,784 priority patent/US8426249B2/en
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本発明は各種電子機器等に用いるチップ部品に関するものである。   The present invention relates to a chip component used for various electronic devices and the like.

以下、従来のチップ部品について図面を参照しながら説明する。   A conventional chip component will be described below with reference to the drawings.

図5は従来のチップ部品の製造工程を示す工程図、図6は図5のA部の分解斜視図である。   FIG. 5 is a process diagram showing a manufacturing process of a conventional chip component, and FIG. 6 is an exploded perspective view of part A of FIG.

図5に示すように、チップ部品の製造工程は、シート形成工程(A)と、コイル部形成工程(B)と、素体分離工程(C)と、電極形成工程(D)とを備えている。   As shown in FIG. 5, the chip component manufacturing process includes a sheet forming process (A), a coil part forming process (B), an element body separating process (C), and an electrode forming process (D). Yes.

まず、図5(A)に示すように、グリーンシート1を複数形成する(シート形成工程(A))。   First, as shown in FIG. 5A, a plurality of green sheets 1 are formed (sheet forming step (A)).

次に、図5(B)および図6に示すように、複数のグリーンシート1上にAgペーストからなる弧状導体2を印刷し、これらのグリーンシート1を積層して、螺旋状導体からなるコイル部3を形成する(コイル部形成工程(B))。このとき、上下に隣接するグリーンシート1に印刷された弧状導体2は、互いにグリーンシート1に形成したスルーホール4を介して電気的に接続され、コイル部3を形成する。   Next, as shown in FIGS. 5B and 6, an arc-shaped conductor 2 made of Ag paste is printed on a plurality of green sheets 1, and these green sheets 1 are laminated to form a coil made of a spiral conductor. The part 3 is formed (coil part forming step (B)). At this time, the arcuate conductors 2 printed on the vertically adjacent green sheets 1 are electrically connected to each other through through holes 4 formed in the green sheet 1 to form a coil portion 3.

次に、図5(C)に示すように、ダイシング切断法やトムソン切断法等を用いて、隣接する素体5を切断機6で切断し、チップ部品7を複数形成する(素体分離工程(C))。   Next, as shown in FIG. 5C, using a dicing cutting method, a Thomson cutting method, or the like, adjacent element bodies 5 are cut by a cutting machine 6 to form a plurality of chip parts 7 (element body separation step). (C)).

そして、このチップ部品7に電極等を形成するとともに、焼成して完成品を製造する(電極形成工程(D))。   And while forming an electrode etc. in this chip component 7, it bakes and manufactures a finished product (electrode formation process (D)).

なお、この出願の発明に関連する先行技術文献情報としては、例えば、特許文献1が知られている。
特開平11−186084号公報
For example, Patent Document 1 is known as prior art document information related to the invention of this application.
JP 11-186084 A

上記従来の構成では、素体分離工程(C)において、ダイシング切断法やトムソン切断法等を用いて、隣接する素体5を切断機6で切断するので、切断機6の刃の厚み分だけ切断幅が必要となる。   In the conventional configuration, since the adjacent element body 5 is cut by the cutting machine 6 using a dicing cutting method, a Thomson cutting method, or the like in the element body separating step (C), only the thickness of the blade of the cutting machine 6 is used. Cutting width is required.

すなわち、グリーンシート1の単位面積に対するチップ部品の取り数を多くするために、切断機6の切断幅を小さくすると、切断機6による切断応力がチップ部品7に加わりやすくなり、チップ部品7の変形を生ずるという問題点を有していた。   That is, if the cutting width of the cutting machine 6 is reduced in order to increase the number of chip parts to be taken per unit area of the green sheet 1, the cutting stress by the cutting machine 6 is easily applied to the chip parts 7, and the chip parts 7 are deformed. It had the problem of producing.

本発明は上記問題点を解決するもので、チップ部品の変形が抑制された分離工程を有するチップ部品の製造方法を提供することを目的としている。   The present invention solves the above-described problems, and an object of the present invention is to provide a chip component manufacturing method having a separation step in which deformation of the chip component is suppressed.

上記目的を達成するために本発明は以下の構成を有する。   In order to achieve the above object, the present invention has the following configuration.

本発明の請求項1記載の発明は、少なくとも連結部で互いに連結された複数のチップ部品を分離する工程を有し、前記連結部は、複数の枠状空隙部と前記枠状空隙部の内側に配置した電極を形成するための電極用空隙部とを有する絶縁樹脂層を形成する第1の工程と、前記枠状空隙部、前記電極用空隙部および前記絶縁樹脂層を覆うように同一の前記金属層を同時に形成する第2の工程と、前記絶縁樹脂層の少なくとも上面まで前記金属層を研磨する第3の工程を有し、前記第1〜3の工程を複数回繰返して積層することにより、前記枠状空隙部に金属層が埋め込まれた前記連結部が形成され、前記連結部のみをエッチング剤により溶融して除去することにより前記連結部で互いに連結された複数の前記チップ部品を個片に分離する構成である。 The invention according to claim 1 of the present invention includes a step of separating a plurality of chip parts connected to each other at least by a connecting portion, and the connecting portion includes a plurality of frame-like void portions and an inner side of the frame-like void portion. A first step of forming an insulating resin layer having an electrode gap for forming an electrode disposed on the same, and covering the frame-like gap, the electrode gap and the insulating resin layer A second step of simultaneously forming the metal layer and a third step of polishing the metal layer to at least the upper surface of the insulating resin layer, and repeating the first to third steps a plurality of times. Accordingly, the connection portion where the metal layer is embedded is formed in the frame-like gap portion, a plurality of the chip components which are connected to each other by the connecting portion by removing by melting only the connecting portion by etching agent configuration der to separate into pieces .

上記構成により、複数のチップ部品は金属からなる連結部で予め互いに連結されており、この金属をエッチング剤により溶融して除去し、連結部で互いに連結された複数のチップ部品を分離するので、チップ部品に切断応力が発生しにくい。   With the above configuration, the plurality of chip components are connected to each other in advance by a connecting portion made of metal, and the metal is melted and removed by an etching agent, so that the plurality of chip components connected to each other at the connecting portion is separated. Cutting stress is unlikely to occur in chip parts.

すなわち、チップ部品の変形が抑制されたチップ部品の製造方法を提供することができる。   That is, it is possible to provide a chip component manufacturing method in which deformation of the chip component is suppressed.

以下、本発明の全請求項に記載の発明について図面を参照しながら説明する。   Hereinafter, the invention described in all claims of the present invention will be described with reference to the drawings.

図1は本発明の一実施の形態におけるチップ部品の透視斜視図、図2は複数連結された同チップ部品の平面図、図3は図2のA部の拡大平面図、図4は同チップ部品の製造工程を示す工程図である。   FIG. 1 is a perspective view of a chip component according to an embodiment of the present invention, FIG. 2 is a plan view of the chip components connected together, FIG. 3 is an enlarged plan view of part A in FIG. 2, and FIG. It is process drawing which shows the manufacturing process of components.

図1において、本発明の一実施の形態におけるチップ部品は、チップコイル部品であって、方形状の透明な素体12と、この素体12の下面に配置した電極14と、素体12に埋設した螺旋状金属16からなるコイル部18を備えており、素体12は感光性樹脂を硬化させた感光性樹脂硬化物からなる絶縁樹脂層20で積層して形成している。   In FIG. 1, a chip component according to an embodiment of the present invention is a chip coil component, and includes a rectangular transparent element 12, an electrode 14 disposed on the lower surface of the element 12, and an element 12. The coil part 18 which consists of the embedded helical metal 16 is provided, and the element | base_body 12 is laminated | stacked and formed by the insulating resin layer 20 which consists of photosensitive resin hardened | cured material which hardened photosensitive resin.

また、実装面に対して垂直な面が互いに隣接して形成される第1角部22を略弧状にするとともに、実装面に対して垂直な面と平行な面が互いに隣接して形成される第2角部24を略直角状に形成しており、第1角部22を素体12に形成するとともに、第2角部24を電極14に形成している。素体12の側面にも電極14を配置した場合は、第1角部22および第2角部24を電極14に形成することとなる。   Further, the first corners 22 formed with the surfaces perpendicular to the mounting surface adjacent to each other are formed in a substantially arc shape, and the surfaces parallel to the surfaces perpendicular to the mounting surface are formed adjacent to each other. The second corner portion 24 is formed in a substantially right angle, the first corner portion 22 is formed in the element body 12, and the second corner portion 24 is formed in the electrode 14. When the electrode 14 is also disposed on the side surface of the element body 12, the first corner portion 22 and the second corner portion 24 are formed on the electrode 14.

さらに、コイル部18の最外周の螺旋状金属16と素体12の側面との最小距離(端面マージン(W))は5μm以上で50μm以下とし、コイル部18の最大径は5μm〜150μmとし、複数の積層した絶縁樹脂層20からなる素体の高さは50μm〜1mmとしている。   Further, the minimum distance (end surface margin (W)) between the outermost spiral metal 16 of the coil portion 18 and the side surface of the element body 12 is 5 μm or more and 50 μm or less, and the maximum diameter of the coil portion 18 is 5 μm to 150 μm. The height of the element body composed of a plurality of laminated insulating resin layers 20 is set to 50 μm to 1 mm.

次に、上記のチップ部品26の製造工程を説明する。   Next, the manufacturing process of the chip component 26 will be described.

上記のチップ部品26は、図2、図3に示すように、複数のチップ部品26を互いに連結した状態で、一度に複数個形成し、最終的に、枠状連結部28で連結された複数のチップ部品26を分離し個片化して製造する。   As shown in FIGS. 2 and 3, a plurality of the chip components 26 are formed at a time in a state where the plurality of chip components 26 are connected to each other, and finally the plurality of chip components 26 connected by the frame-shaped connecting portion 28. The chip parts 26 are separated and separated into pieces.

図4において、チップ部品26の製造工程は次の通りである。   In FIG. 4, the manufacturing process of the chip component 26 is as follows.

第1に、素体12の下面に配置する電極14を形成する(電極形成工程(A))。   First, the electrode 14 disposed on the lower surface of the element body 12 is formed (electrode formation step (A)).

剥離層が形成された基板30に、フォトリソグラフィ工法により、所定の空隙部を有する絶縁樹脂層20を形成する。この空隙部は、互いに隣接する複数の枠状空隙部32と、この枠状空隙部32の内側に配置した電極用空隙部34とからなり、この枠状空隙部32の内側にチップ部品26を形成し、この枠状空隙部32に複数のチップ部品26を連結するための枠状連結部28を形成する。   An insulating resin layer 20 having a predetermined gap is formed on the substrate 30 on which the release layer is formed by a photolithography method. The gap portion includes a plurality of frame-like gap portions 32 adjacent to each other and an electrode gap portion 34 arranged inside the frame-like gap portion 32, and the chip component 26 is placed inside the frame-like gap portion 32. The frame-shaped connecting portion 28 for connecting the plurality of chip components 26 to the frame-shaped gap portion 32 is formed.

この枠状空隙部32および電極用空隙部34および絶縁樹脂層20上には金属層36を形成する。この金属層36は、無電解めっき工法またはスパッタまたは蒸着工法等により形成した下地導体層38を有し、この下地導体層38上に電解めっき工法により形成している。   A metal layer 36 is formed on the frame-shaped gap 32, the electrode gap 34 and the insulating resin layer 20. The metal layer 36 has a base conductor layer 38 formed by an electroless plating method, a sputtering method, a vapor deposition method, or the like, and is formed on the base conductor layer 38 by an electrolytic plating method.

この金属層36は、絶縁樹脂層20の少なくとも上面まで研磨して、電極用空隙部34に金属からなる電極14を形成するとともに、枠状空隙部32に金属からなる枠状連結部28を形成し、かつ、電極14と枠状連結部28との絶縁を図っている。   The metal layer 36 is polished to at least the upper surface of the insulating resin layer 20 to form the electrode 14 made of metal in the electrode gap 34 and the frame-shaped connecting portion 28 made of metal in the frame-shaped gap 32. In addition, insulation between the electrode 14 and the frame-shaped connecting portion 28 is achieved.

第2に、さらに、フォトリソグラフィ工法により、所定の空隙部を有する絶縁樹脂層20を形成する(絶縁樹脂層形成工程(B))。   Second, an insulating resin layer 20 having a predetermined gap is further formed by a photolithography method (insulating resin layer forming step (B)).

この空隙部は、互いに隣接する複数の枠状空隙部32と、この枠状空隙部32の内側に配置した螺旋状空隙部40と、スルーホール用空隙部42とからなり、この枠状空隙部32は、電極形成工程(A)で形成した枠状空隙部32に重なるように形成している。   This void portion is composed of a plurality of frame-shaped void portions 32 adjacent to each other, a helical void portion 40 disposed inside the frame-shaped void portion 32, and a through-hole void portion 42. 32 is formed so as to overlap with the frame-shaped gap 32 formed in the electrode forming step (A).

第3に、枠状空隙部32、螺旋状空隙部40、スルーホール用空隙部42、絶縁樹脂層20上に金属層36を形成する(金属層形成工程(C))。   Third, the metal layer 36 is formed on the frame-shaped gap 32, the spiral gap 40, the through-hole gap 42, and the insulating resin layer 20 (metal layer forming step (C)).

この金属層36は、無電解めっき工法、スパッタまたは蒸着工法等により形成した下地導体層38を有し、この下地導体層38上に電解めっき工法により形成している。   The metal layer 36 has a base conductor layer 38 formed by an electroless plating method, a sputtering method, a vapor deposition method, or the like, and is formed on the base conductor layer 38 by an electrolytic plating method.

第4に、螺旋状金属16からなる2層のコイル部18を形成する(コイル部形成工程(D))。   Fourth, a two-layer coil portion 18 made of the spiral metal 16 is formed (coil portion forming step (D)).

金属層形成工程(C)で形成した金属層36は、絶縁樹脂層20の少なくとも上面まで研磨して、螺旋状空隙部40に螺旋状金属16からなるコイル部18を形成し、枠状空隙部32に金属からなる枠状連結部28を形成し、スルーホール用空隙部42に金属からなるスルーホール44を形成し、かつ、コイル部18と枠状連結部28との絶縁を図る。   The metal layer 36 formed in the metal layer forming step (C) is polished to at least the upper surface of the insulating resin layer 20 to form the coil part 18 made of the spiral metal 16 in the spiral gap 40, and the frame-like gap A frame-shaped connecting portion 28 made of metal is formed in 32, a through-hole 44 made of metal is formed in the through-hole gap portion 42, and insulation between the coil portion 18 and the frame-shaped connecting portion 28 is achieved.

さらに、絶縁樹脂層形成工程(B)、金属層形成工程(C)を繰り返し、2層のコイル部18を形成する。2層のコイル部18、電極14とコイル部18とは、スルーホール44により導通させている。   Further, the insulating resin layer forming step (B) and the metal layer forming step (C) are repeated to form the two-layer coil portion 18. The two layers of the coil part 18, the electrode 14 and the coil part 18 are electrically connected by a through hole 44.

第5に、さらに、絶縁樹脂層20を形成するとともに、フォトリソグラフィ工法により、所定の空隙部を有する絶縁樹脂層20を形成して保護層とする(保護層形成工程(E))。   Fifth, the insulating resin layer 20 is further formed, and the insulating resin layer 20 having a predetermined gap is formed by a photolithography method to form a protective layer (protective layer forming step (E)).

この空隙部は、互いに隣接する複数の枠状空隙部32からなり、この枠状空隙部32は、絶縁樹脂層形成工程(B)で形成した枠状空隙部32に重なるように形成している。   This void portion is composed of a plurality of frame-shaped void portions 32 adjacent to each other, and this frame-shaped void portion 32 is formed so as to overlap the frame-shaped void portion 32 formed in the insulating resin layer forming step (B). .

第6に、枠状空隙部32に形成した金属をエッチング剤により溶融して除去し、枠状連結部28により互いに連結された複数のチップ部品26を分離するとともに、基板30の剥離層からチップ部品26を剥離して(溶剤やアルカリ等で溶融して)個片化する(分離工程(F))。   Sixth, the metal formed in the frame-shaped gap portion 32 is removed by melting with an etching agent, and a plurality of chip components 26 connected to each other by the frame-shaped connection portion 28 are separated, and the chip is separated from the release layer of the substrate 30. The component 26 is peeled off (melted with a solvent, alkali or the like) and separated into pieces (separation step (F)).

このようにして、素体12は、電極形成工程(A)、絶縁樹脂層形成工程(B)、保護層形成工程(E)による積層された絶縁樹脂層20で形成され、この素体12の下面または側面には電極14が配置され、素体12にはコイル部18が埋設されることとなる。   Thus, the element body 12 is formed by the insulating resin layer 20 laminated by the electrode forming process (A), the insulating resin layer forming process (B), and the protective layer forming process (E). The electrode 14 is disposed on the lower surface or the side surface, and the coil portion 18 is embedded in the element body 12.

この製造方法において、金属層36はCu、Al、Ag、Au、Niあるいは金属の合金等の良導電性金属が好ましい。また、その下地導体層38としてCu、Al、Ag、Au、Ni、Cr、Ti等の絶縁樹脂層20との密着性の高い金属が好ましく、無電解めっき工法、スパッタまたは蒸着工法等で形成することが好ましい。   In this manufacturing method, the metal layer 36 is preferably a highly conductive metal such as Cu, Al, Ag, Au, Ni, or a metal alloy. Further, the base conductor layer 38 is preferably a metal having high adhesion to the insulating resin layer 20 such as Cu, Al, Ag, Au, Ni, Cr, Ti, and is formed by an electroless plating method, a sputtering method or a vapor deposition method. It is preferable.

この製造方法において、絶縁樹脂層20は、感光性樹脂を硬化させた透明な感光性樹脂硬化物からなる。この絶縁樹脂層20は、エポキシ系、フェノール系、ポリイミド系等の樹脂を用いて、フォトリソグラフィ工法により所定形状に加工するが、一般的なフォトリソグラフィ工法で用いるレジストとは異なり、最終的なチップ部品26の素体12を構成する樹脂であるため、一般的には静電気が発生しやすいので、静電気の発生を抑制した樹脂を選択したり、静電気を発散する構成を付加したりしてもよい。   In this manufacturing method, the insulating resin layer 20 is made of a transparent photosensitive resin cured product obtained by curing a photosensitive resin. This insulating resin layer 20 is processed into a predetermined shape by a photolithography method using an epoxy-based resin, a phenol-based resin, a polyimide-based resin, or the like, but unlike a resist used in a general photolithography method, the final chip Since the resin constituting the element body 12 of the component 26 is generally easy to generate static electricity, a resin that suppresses the generation of static electricity may be selected, or a configuration that dissipates static electricity may be added. .

研磨方法は、CMPスラリーを用いたCMP(ケミカルメカニカルポリッシング)研磨を用いるとよい。金属層36をCMP研磨によりエッチングしながら、金属のみを選択的に研磨するので、精度が向上する。その他の研磨方法としては、ダイヤモンドスラリー、アルミナスラリーを用いた機械的研磨を用いてもよいが、精度の点でCMP研磨よりも不利である。金属層36として、エッチングに適さないものを用いた場合は、その部分の研磨を機械的研磨で行ってもよい。   As a polishing method, CMP (chemical mechanical polishing) polishing using a CMP slurry may be used. Since only the metal is selectively polished while etching the metal layer 36 by CMP polishing, the accuracy is improved. As another polishing method, mechanical polishing using diamond slurry or alumina slurry may be used, but it is disadvantageous in comparison with CMP polishing in terms of accuracy. When the metal layer 36 is not suitable for etching, the portion may be polished by mechanical polishing.

上記構成により、複数のチップ部品26は金属からなる枠状連結部28で予め互いに連結されており、この金属をエッチング剤により溶融して除去し、枠状連結部28で互いに連結された複数のチップ部品26を分離するので、チップ部品26に切断応力が発生しにくい。すなわち、チップ部品26の変形を抑制して、チップ部品26を製造することができる。   With the above configuration, the plurality of chip components 26 are connected to each other in advance by a frame-shaped connecting portion 28 made of metal, and the metal is melted and removed by an etching agent, and the plurality of chip components 26 connected to each other by the frame-shaped connecting portion 28. Since the chip component 26 is separated, cutting stress is hardly generated in the chip component 26. That is, the chip component 26 can be manufactured while suppressing deformation of the chip component 26.

また、フォトリソグラフィ工程で枠状連結部28、螺旋状金属16を形成し、応力が発生しにくい個片化工程を行うため、チップ部品26の端面からの端面マージン(W)を極小化でき、チップ部品26のサイズを最大限に生かした導体位置精度の良い設計が可能である。そのため、チップ部品26のサイズが、例えば1005、0603等の小型になればなるほど端面からの端面マージン(W)の影響が大きくなり、チップ特性、例えばチップインダクタの場合はインダクタンス値およびQ値を、従来工法に比べより高特性にできる。   In addition, since the frame-like connecting portion 28 and the spiral metal 16 are formed by a photolithography process and an individualization process in which stress is hardly generated is performed, the end surface margin (W) from the end surface of the chip component 26 can be minimized, It is possible to design with good conductor position accuracy by making the best use of the size of the chip component 26. Therefore, the smaller the size of the chip component 26 is, for example, 1005, 0603, etc., the greater the influence of the end face margin (W) from the end face, and the chip characteristics, for example, in the case of a chip inductor, the inductance value and the Q value are Higher performance than conventional methods.

特に、枠状空隙部32および絶縁樹脂層20上に金属層36を形成し、この金属層36を絶縁樹脂層20の少なくとも上面まで研磨して、枠状空隙部32にチップ部品26を連結する金属からなる枠状連結部28を形成するので容易に枠状連結部28を形成できる。   In particular, the metal layer 36 is formed on the frame-shaped gap 32 and the insulating resin layer 20, the metal layer 36 is polished to at least the upper surface of the insulating resin layer 20, and the chip component 26 is connected to the frame-shaped gap 32. Since the frame-shaped connecting portion 28 made of metal is formed, the frame-shaped connecting portion 28 can be easily formed.

枠状空隙部32は、略方形状にするとともに内周角部を弧状にしているので、チップ部品26は、実装面に対して垂直な面が互いに隣接して形成される第1角部22を略弧状にすることができる。これにより、パーツフィーダ等で複数のチップ部品26を実装機に供給する際、互いのチップ部品26が接触し合っても、チップ部品26の第1角部22が略弧状なので、滑らかに供給可動させ、チップ部品26の割れや欠けを抑制できる。一方、実装面に対して垂直な面と平行な面が互いに隣接して形成される第2角部24は略直角状に形成しているので、実装時には、チップ立ちを抑制できる。なお、枠状空隙部32の内周角部を面取り形状やその他の形状にすることも上記方法によれば容易である。   Since the frame-shaped gap portion 32 has a substantially rectangular shape and the inner peripheral corner portion has an arc shape, the chip component 26 has a first corner portion 22 in which surfaces perpendicular to the mounting surface are formed adjacent to each other. Can be substantially arcuate. As a result, when supplying a plurality of chip components 26 to the mounting machine with a parts feeder or the like, even if the chip components 26 come into contact with each other, the first corner portion 22 of the chip components 26 is substantially arc-shaped, so that the supply can be smoothly performed. Thus, cracking and chipping of the chip component 26 can be suppressed. On the other hand, since the second corner portion 24 formed by mutually adjoining surfaces perpendicular to the mounting surface is formed in a substantially right angle, chip standing can be suppressed during mounting. In addition, according to the said method, it is easy to make the internal peripheral corner | angular part of the frame-shaped space | gap part 32 into a chamfering shape or another shape.

また、絶縁樹脂層20は、フォトリソグラフィ工法により形成するので、導体位置精度、チップ寸法精度等が容易に高精度に形成できる。また、絶縁樹脂層20に、透明な感光性樹脂を用いることにより素体12は透明となり、一層ごとに導体の外観検査が容易となるとともに、アスペクト比を大きくし、コイル部18の厚みを容易に厚くすることができる。   Further, since the insulating resin layer 20 is formed by a photolithography method, the conductor position accuracy, the chip dimensional accuracy, etc. can be easily formed with high accuracy. In addition, by using a transparent photosensitive resin for the insulating resin layer 20, the element body 12 becomes transparent, facilitating the appearance inspection of the conductor for each layer, increasing the aspect ratio, and facilitating the thickness of the coil portion 18. Can be thickened.

さらに、金属層36は、無電解めっき工法またはスパッタまたは蒸着工法等により形成した下地導体層38を有し、この下地導体層38上に電解めっき工法により形成することにより、密度を大きくしたコイル部18を容易に形成できる。   Further, the metal layer 36 has a base conductor layer 38 formed by an electroless plating method, a sputtering method, a vapor deposition method, or the like, and is formed on the base conductor layer 38 by an electrolytic plating method, thereby increasing the density of the coil portion. 18 can be formed easily.

以上のように本発明にかかるチップ部品の製造方法は、チップ部品の変形を抑制して製造できるので、各種電子機器に適用できる。   As described above, since the chip component manufacturing method according to the present invention can be manufactured while suppressing deformation of the chip component, it can be applied to various electronic devices.

本発明の一実施の形態におけるチップ部品の透視斜視図The perspective view of the chip component in one embodiment of this invention 複数連結された同チップ部品の平面図Plan view of multiple connected chip components 図2のA部の拡大平面図Enlarged plan view of part A in FIG. 同チップ部品の製造工程を示す工程図Process chart showing the manufacturing process of the same chip component 従来のチップ部品の製造工程を示す工程図Process diagram showing the manufacturing process of conventional chip parts 図5のA部の分解斜視図5 is an exploded perspective view of part A in FIG.

符号の説明Explanation of symbols

12 素体
14 電極
16 螺旋状金属
18 コイル部
20 絶縁樹脂層
22 第1角部
24 第2角部
26 チップ部品
28 枠状連結部
30 基板
32 枠状空隙部
34 電極用空隙部
36 金属層
38 下地導体層
40 螺旋状空隙部
42 スルーホール用空隙部
44 スルーホール
DESCRIPTION OF SYMBOLS 12 Element body 14 Electrode 16 Spiral metal 18 Coil part 20 Insulating resin layer 22 1st corner | angular part 24 2nd corner | angular part 26 Chip component 28 Frame-like connection part 30 Substrate 32 Frame-like gap part 34 Electrode gap part 36 Metal layer 38 Base conductor layer 40 Spiral air gap 42 Through hole air hole 44 Through hole

Claims (7)

少なくとも連結部で互いに連結された複数のチップ部品を分離する工程を有し、
前記連結部は
複数の枠状空隙部と前記枠状空隙部の内側に配置した電極を形成するための電極用空隙部とを有する絶縁樹脂層を形成する第1の工程と、
前記枠状空隙部、前記電極用空隙部および前記絶縁樹脂層を覆うように同一の金属層を同時に形成する第2の工程と、
前記絶縁樹脂層の少なくとも上面まで前記金属層を研磨する第3の工程を有し、
前記第1〜3の工程を複数回繰返して積層することにより、前記枠状空隙部に前記金属層が埋め込まれた前記連結部が形成され、前記連結部のみをエッチング剤により溶融して除去することにより前記連結部で互いに連結された複数の前記チップ部品を個片に分離するチップ部品の製造方法。
Having a step of separating a plurality of chip parts connected to each other at least by a connecting part;
The connecting portion is
A first step of forming an insulating resin layer having a plurality of frame-shaped voids and an electrode void for forming an electrode disposed inside the frame-shaped void;
A second step of simultaneously forming the same metal layer so as to cover the frame-shaped gap, the electrode gap and the insulating resin layer;
A third step of polishing the metal layer to at least the upper surface of the insulating resin layer;
By stacking repeatedly a plurality of times said first to third step, the said connection portion in which the metal layer is embedded in the frame-like gap portion is formed, to remove only the connecting portion is melted by an etchant method of manufacturing a chip component that separates a plurality of the chip components which are connected to each other by the connecting portions into individual pieces by.
前記電極用空隙部は、螺旋状に形成する、請求項1記載の前記チップ部品の製造方法。The method for manufacturing the chip component according to claim 1, wherein the gap for the electrode is formed in a spiral shape. 前記枠状空隙部は、略方形状にするとともに内周角部を弧状にした請求項2記載のチップ部品の製造方法。 The chip part manufacturing method according to claim 2, wherein the frame-shaped gap is formed in a substantially rectangular shape and an inner peripheral corner is arcuate. 前記枠状空隙部と前記螺旋状空隙部とを有する前記絶縁樹脂層は、フォトリソグラフィ工法により形成する請求項2記載のチップ部品の製造方法。 The method for manufacturing a chip part according to claim 2, wherein the insulating resin layer having the frame-like gap and the spiral gap is formed by a photolithography method. 前記絶縁樹脂層は、感光性樹脂を硬化させた感光性樹脂硬化物からなる請求項4記載のチップ部品の製造方法。 The method for manufacturing a chip part according to claim 4, wherein the insulating resin layer is made of a cured photosensitive resin obtained by curing a photosensitive resin. 前記金属層は、めっき工法により形成する請求項2記載のチップ部品の製造方法。 The chip part manufacturing method according to claim 2, wherein the metal layer is formed by a plating method. 前記金属層は、無電解めっき工法またはスパッタまたは蒸着工法により形成した下地導体層を有し、前記下地導体層上に電解めっき工法により形成する請求項2記載のチップ部品の製造方法。 3. The method of manufacturing a chip part according to claim 2, wherein the metal layer has a base conductor layer formed by an electroless plating method, a sputtering method, or a vapor deposition method, and is formed on the base conductor layer by an electrolytic plating method.
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