JPH1187115A - Manufacture of chip component - Google Patents

Manufacture of chip component

Info

Publication number
JPH1187115A
JPH1187115A JP9241447A JP24144797A JPH1187115A JP H1187115 A JPH1187115 A JP H1187115A JP 9241447 A JP9241447 A JP 9241447A JP 24144797 A JP24144797 A JP 24144797A JP H1187115 A JPH1187115 A JP H1187115A
Authority
JP
Japan
Prior art keywords
chip
slurry
molding frame
cavity
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP9241447A
Other languages
Japanese (ja)
Inventor
Masayuki Inai
雅之 稲井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP9241447A priority Critical patent/JPH1187115A/en
Publication of JPH1187115A publication Critical patent/JPH1187115A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Non-Adjustable Resistors (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a chip component with high quality of all times by eliminating defective factors when cutting or dividing the substrate. SOLUTION: A forming frame 1 with a plurality of cavities 1a fitted into the shape of a unit chip 3 is eliminated by heat at a burning step. After the cavity 1a of the forming frame 1 is filled with slurry to be burned, the formation frame 1 is heated at a burning temperature for making the slurry burnt and form the unit chip 3, while the formation frame 1 is eliminated by the heat at burning. Then, the cutting step for obtaining a chip from a ceramic substrate as in the conventional step can be omitted, and a defective factor such as dipping or burs caused by the cutting or separation can be eliminated. In this way, a unit chip with a given shape can be obtained easily whit high precision, and a chip resistor with high quality can be manufactured.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、チップ抵抗器等の
チップ部品に好適な製造方法に係り、特に単位チップの
作成手法に改良を加えたチップ部品の製造方法に関する
ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a chip component such as a chip resistor, and more particularly, to a method for manufacturing a chip component in which a method for forming a unit chip is improved.

【0002】[0002]

【従来の技術】チップ部品として周知のチップ抵抗器
は、概ね以下のようにして製造されている。
2. Description of the Related Art A chip resistor known as a chip component is generally manufactured as follows.

【0003】まず、多数個取りに応じた大きさを備えた
アルミナ磁器等から成るセラミック基板を用意し、該セ
ラミック基板の一面に、銀,ニッケル等の金属粉末にバ
インダ及び溶剤等を混合して調製した電極ペーストを、
スクリーン印刷等の手法を利用して所定の形状及び配列
で塗布し、これをペースト組成に応じた温度で焼き付け
て引出電極を形成する。
[0003] First, a ceramic substrate made of alumina porcelain or the like having a size corresponding to a large number of pieces is prepared. One surface of the ceramic substrate is mixed with a metal powder such as silver, nickel or the like by mixing a binder and a solvent. The prepared electrode paste is
It is applied in a predetermined shape and arrangement using a technique such as screen printing, and is baked at a temperature according to the paste composition to form an extraction electrode.

【0004】次に、同セラミック基板の一面に、酸化ル
テニウム等の金属粉末にバインダ及び溶剤等を混合して
調製した抵抗ペーストを、スクリーン印刷等の手法を利
用して所定の形状及び配列で塗布、詳しくは、両端部が
前記一対の引出電極と重なるように塗布し、これをペー
スト組成に応じた温度で焼き付けて抵抗膜を形成する。
Next, a resistor paste prepared by mixing a binder and a solvent with a metal powder such as ruthenium oxide is applied to one surface of the ceramic substrate in a predetermined shape and arrangement by using a technique such as screen printing. More specifically, the resistive film is formed by coating the both ends so as to overlap the pair of extraction electrodes, and baking this at a temperature according to the paste composition.

【0005】次に、引出電極及び抵抗膜を形成したセラ
ミック基板を、該セラミック基板に対して予め設定した
X・Y方向の複数ラインに沿って切断する。この切断に
はダイヤモンドブレード等のカッティングブレードを備
えたダイシング装置が用いられており、切断後の個々の
チップは1つの抵抗膜とこれと導通する一対の引出電極
をその一面に備えたものとなる。
Next, the ceramic substrate on which the lead electrodes and the resistive film are formed is cut along a plurality of lines in the X and Y directions which are set in advance with respect to the ceramic substrate. A dicing machine equipped with a cutting blade such as a diamond blade is used for this cutting, and each chip after cutting has one resistive film and a pair of extraction electrodes connected to the resistive film on one surface thereof. .

【0006】この後、個々のチップには、各引出電極と
導通するように一対の外部電極が形成され、且つ抵抗膜
と引出電極の一部を覆うように外装膜が形成されて、所
期のチップ抵抗器が製造される。
Thereafter, a pair of external electrodes is formed on each chip so as to be electrically connected to each extraction electrode, and an exterior film is formed so as to cover a part of the resistance film and the extraction electrode. Chip resistors are manufactured.

【0007】ちなみに、個々のチップを得る方法として
は、セラミック基板に予めチップ寸法に合わせて分割溝
を格子状に形成しておき、該セラミック基板に引出電極
と抵抗膜を形成した後にこれを溝に沿って分割して個々
のチップを得る方法も存在する。また、外装膜を基板切
断前または基板分割前に形成しておき、切断または分割
後のチップに外部電極を形成する製造手順も存在する。
Incidentally, as a method of obtaining individual chips, divided grooves are formed in a ceramic substrate in advance in accordance with the chip size in a lattice pattern, and after forming an extraction electrode and a resistive film on the ceramic substrate, the grooves are formed. There is also a method of obtaining individual chips by dividing along the line. There is also a manufacturing procedure in which an exterior film is formed before cutting a substrate or before dividing a substrate, and external electrodes are formed on the cut or divided chip.

【0008】[0008]

【発明が解決しようとする課題】ところで、前述のチッ
プ抵抗器に限らず、セラミック基板をカッティングブレ
ードを用いて個々のチップに切断する場合、基板自体の
硬度が高いためにダイヤモンドブレードを用いてもその
切断は容易ではなく、切断条件を適正に設定しないと切
断時の応力によってチッピングや寸法不良を生じる不具
合がある。また、セラミック基板を予め形成された溝に
沿って個々のチップに分割する場合、分割時の応力によ
ってチッピングやバリを生じる頻度が前記の切断に比べ
て高いため、チップ部品の品質が低下し易い不具合があ
る。
When a ceramic substrate is cut into individual chips using a cutting blade, not only the above-described chip resistor, even if a diamond blade is used due to the high hardness of the substrate itself. The cutting is not easy, and if the cutting conditions are not properly set, there is a problem that chipping and dimensional defects occur due to stress at the time of cutting. Further, when the ceramic substrate is divided into individual chips along the grooves formed in advance, the frequency of chipping and burrs caused by the stress at the time of division is higher than that of the above-described cutting, so that the quality of the chip component is likely to deteriorate. There is a defect.

【0009】本発明は前記事情に鑑みてなされたもの
で、その目的とするところは、基板切断や基板分割の手
法を用いる場合の不具合を解消して、高品質のチップ部
品を安定に得ることができるチップ部品の製造方法を提
供することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to eliminate the disadvantages when using a method of cutting or dividing a substrate and to stably obtain a high-quality chip component. To provide a method for manufacturing a chip component.

【0010】[0010]

【課題を解決するための手段】前記目的を達成するた
め、本発明に係るチップ部品の製造方法は、請求項1に
記載のように、単位チップに整合した形状を有する複数
のキャビティを備え、且つ焼成時の付加熱によって消失
可能な成形枠を使用し、成形枠のキャビティに焼成可能
なスラリーを充填する工程と、スラリー充填後の成形枠
を焼成温度で加熱してキャビティ内のスラリーを焼成し
て単位チップ化すると共に、焼成時の付加熱によって成
形枠を消失させて単位チップを得る工程とを備えたこと
をその特徴としている。
According to a first aspect of the present invention, there is provided a method for manufacturing a chip component, comprising a plurality of cavities having a shape matched to a unit chip. A step of filling a cavity of the molding frame with a calcinable slurry using a molding frame that can be lost by additional heat during firing, and heating the molding frame after the slurry filling at a firing temperature to bake the slurry in the cavity. And a step of obtaining a unit chip by erasing the molding frame by additional heat during firing.

【0011】また、請求項2に記載のように、単位チッ
プに整合した形状を有する複数のキャビティを備え、且
つ焼成時の付加熱に対して耐熱性を有する成形枠を使用
し、成形枠のキャビティに焼成可能なスラリーを充填す
る工程と、スラリー充填後の成形枠を焼成温度で加熱し
てキャビティ内のスラリーを焼成して単位チップ化する
工程と、成形枠のキャビティから単位チップを取り出す
工程とを備えたことをその特徴としている。
According to a second aspect of the present invention, a molding frame having a plurality of cavities having a shape matched to a unit chip and having heat resistance to additional heat during firing is used. A step of filling the cavity with a calcinable slurry, a step of heating the molding frame after filling the slurry at a baking temperature to calcine the slurry in the cavity to form unit chips, and a step of removing unit chips from the cavity of the molding frame It is characterized by having.

【0012】さらに、請求項3に記載のように、単位チ
ップに整合した形状を有する複数のキャビティを備えた
成形枠を使用し、成形枠のキャビティに自然硬化可能な
スラリーを充填し、該スラリーを硬化させて単位チップ
化する工程と、成形枠のキャビティから単位チップを取
り出す工程とを備えたことをその特徴としている。
Further, as set forth in claim 3, a molding frame having a plurality of cavities having a shape matched to the unit chip is used, and a cavity of the molding frame is filled with a slurry which can be naturally cured, and And a step of taking out the unit chip from the cavity of the molding frame.

【0013】請求項1に記載の製造方法では、成形枠の
キャビティに焼成可能なスラリーを充填した後、スラリ
ー充填後の成形枠全体を焼成温度で加熱してキャビティ
内のスラリーを焼成して単位チップ化すると共に、焼成
時の付加熱によって成形枠を消失させて単位チップを得
ることにより、従来のような基板切断や基板分割の手法
を用いることなく、所定形状の単位チップを容易且つ高
精度で得ることができる。
In the manufacturing method according to the first aspect, after filling the cavity of the molding frame with the sinterable slurry, the entire molding frame after the slurry filling is heated at the sintering temperature to sinter the slurry in the cavity to obtain a unit. By forming chips and losing the molding frame by the additional heat during firing to obtain unit chips, unit chips of a predetermined shape can be easily and accurately formed without using the conventional method of cutting or dividing the substrate. Can be obtained at

【0014】また、請求項2に記載の製造方法では、成
形枠のキャビティに焼成可能なスラリーを充填した後、
スラリー充填後の成形枠を焼成温度で加熱してキャビテ
ィ内のスラリーを焼成して単位チップ化し、そして成形
枠のキャビティから単位チップを取り出すことにより、
従来のような基板切断や基板分割の手法を用いることな
く、所定形状の単位チップを容易且つ高精度で得ること
ができる。
Further, in the manufacturing method according to the second aspect, after filling the cavity of the molding frame with the slurry capable of being fired,
By heating the forming frame after the slurry filling at the firing temperature, firing the slurry in the cavity into unit chips, and taking out the unit chips from the cavity of the forming frame,
A unit chip having a predetermined shape can be obtained easily and with high accuracy without using a conventional method of cutting or dividing a substrate.

【0015】さらに、請求項3に記載の製造方法では、
成形枠のキャビティに自然硬化可能なスラリーを充填
し、該スラリーを硬化させて単位チップ化した後、成形
枠のキャビティから単位チップを取り出すことにより、
従来のような基板切断や基板分割の手法を用いることな
く、所定形状の単位チップを容易且つ高精度で得ること
ができる。
Further, in the manufacturing method according to the third aspect,
Filling the cavity of the molding frame with a slurry that can be naturally cured, curing the slurry to form unit chips, and then taking out the unit chips from the cavity of the molding frame,
A unit chip having a predetermined shape can be obtained easily and with high accuracy without using a conventional method of cutting or dividing a substrate.

【0016】[0016]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

[第1実施形態]図1乃至図6は本発明をチップ抵抗器
に適用した第1実施形態に係るもので、以下、同図に従
ってチップ抵抗器の製造手順を説明する。
[First Embodiment] FIGS. 1 to 6 relate to a first embodiment in which the present invention is applied to a chip resistor, and the manufacturing procedure of the chip resistor will be described below with reference to FIG.

【0017】製造に際しては、まず、図1に示すような
成形枠1を用意する。この成形枠1は、後述の単位チッ
プ3に整合した形状(図示例では直方体形状)を有する
複数のキャビティ1aを所定の配列で備えている。ま
た、成形枠1は、後述の焼成時の付加熱(アルミナ磁器
の場合は1300〜1500℃)で消失可能な材料、例
えば、前記の焼成温度下での燃焼を可能とした樹脂や木
材等から形成されている。材料の種類に拘わらず、燃焼
負荷が低くなるように成形枠1の肉厚は極力薄くすると
よく、特に樹脂の場合には発泡樹脂(好ましくは表面に
気孔の存在しないもの)を用いると消失を容易に行うこ
とができる。また、木材の場合にはセラミックスラリー
が浸透する恐れがあるので、その表面に樹脂コーティン
グ等を施すとよい。
In manufacturing, first, a molding frame 1 as shown in FIG. 1 is prepared. The molding frame 1 includes a plurality of cavities 1a having a shape (a rectangular parallelepiped shape in the illustrated example) aligned with a unit chip 3 described later in a predetermined arrangement. The molding frame 1 is made of a material that can be eliminated by additional heat during firing (1300 to 1500 ° C. in the case of alumina porcelain) described later, for example, a resin or wood capable of burning at the above firing temperature. Is formed. Regardless of the type of material, the thickness of the molding frame 1 should be as thin as possible so as to reduce the combustion load. In particular, in the case of a resin, the foaming resin (preferably having no pores on the surface) will be eliminated. It can be done easily. Further, in the case of wood, there is a possibility that the ceramic slurry may penetrate, so it is preferable to apply a resin coating or the like to the surface thereof.

【0018】次に、図2に示すように、成形枠1のキャ
ビティ1aそれぞれにセラミックスラリー2をほぼ一杯
に充填する。このセラミックスラリー2は、アルミナ等
のセラミック粉末にバインダ及び溶剤等を混合して調製
された周知のものである。
Next, as shown in FIG. 2, each of the cavities 1a of the molding frame 1 is almost completely filled with the ceramic slurry 2. The ceramic slurry 2 is a well-known one prepared by mixing a binder, a solvent, and the like with ceramic powder such as alumina.

【0019】次に、スラリー充填後の成形枠1を焼成用
加熱炉(図示省略)に投入して、前記セラミックスラリ
ー2の組成に応じた所定の条件によって、キャビティ1
a内のセラミックスラリー2の焼成を行う。また、この
焼成課程では、焼成時の付加熱によって成形枠1が消失
する。つまり、焼成を完了した状態では、図3に示すよ
うに、成形枠1が消失し(実際のものでは多少の残骸は
残る)、焼成後の単位チップ3がキャビティ1aに応じ
た配列で並ぶ。
Next, the molding frame 1 after filling with the slurry is put into a heating furnace (not shown) for firing, and the cavity 1 is formed under predetermined conditions according to the composition of the ceramic slurry 2.
The ceramic slurry 2 in a is fired. In this firing step, the molding frame 1 disappears due to the additional heat during firing. That is, in the state where the firing is completed, as shown in FIG. 3, the molding frame 1 disappears (some debris remains in the actual case), and the fired unit chips 3 are arranged in an array corresponding to the cavity 1a.

【0020】次に、複数の単位チップ3を焼成用加熱炉
から取り出して隙間なく整列し、図4に示すように、整
列された各単位チップ3の一面に、銀,ニッケル等の金
属粉末にバインダ及び溶剤等を混合して調製した周知の
電極ペーストを、スクリーン印刷等の手法を利用して所
定の形状及び配列で塗布し、これをペースト組成に応じ
た温度で焼き付けて引出電極4を形成する。
Next, the plurality of unit chips 3 are taken out of the heating furnace for firing and aligned without gaps. As shown in FIG. 4, one surface of each aligned unit chip 3 is coated with a metal powder such as silver or nickel. A well-known electrode paste prepared by mixing a binder, a solvent, and the like is applied in a predetermined shape and arrangement using a method such as screen printing, and is baked at a temperature according to the paste composition to form the extraction electrode 4. I do.

【0021】次に、図5に示すように、整列された各単
位チップ3の同一面に、酸化ルテニウム等の金属粉末に
バインダ及び溶剤等を混合して調製した周知の抵抗ペー
ストを、スクリーン印刷等の手法を利用して所定の形状
及び配列で塗布、詳しくは、両端部が前記一対の引出電
極と重なるように塗布し、これをペースト組成に応じた
温度で焼き付けて抵抗膜5を形成する。
Next, as shown in FIG. 5, a well-known resistance paste prepared by mixing a binder, a solvent and the like with a metal powder such as ruthenium oxide is screen-printed on the same surface of each of the aligned unit chips 3. The resist film 5 is formed by applying a predetermined shape and arrangement using a technique such as the method described above. Specifically, the resist film 5 is formed by applying the both ends so as to overlap with the pair of extraction electrodes and baking it at a temperature according to the paste composition. .

【0022】勿論、前記の引出電極4及び抵抗膜5は、
スパッタリングや電解・無電解メッキ等の薄膜手法によ
って形成することも可能である。
Of course, the above-mentioned extraction electrode 4 and resistance film 5
It can also be formed by a thin film technique such as sputtering or electrolytic / electroless plating.

【0023】次に、整列された各単位チップ3をばら
し、図6に示すように、各単位チップ3に対し、引出電
極5と導通するように一対の外部電極6を形成し、且つ
抵抗膜5と引出電極4の一部を覆うように外装膜7を形
成する。外部電極6と外装膜7の形成順序はどちらが先
でもよい。ちなみに、外部電極6は、銀,ニッケル等の
金属粉末にバインダ及び溶剤等を混合して調製した周知
の電極ペーストを、ディップやローラ塗布等の手法を利
用して塗布し、これをペースト組成に応じた温度で焼き
付けることにより作成される。また、外装膜7は、エポ
キシ等のプラスチックやシリコン系等のガラスを主成分
とした周知の外装ペーストを、スクリーン印刷やローラ
塗布や転写等の手法を利用して塗布し、これをペースト
組成に応じた温度で焼き付けることにより作成される。
以上で、図6に示すような縦断面形状を備えたチップ抵
抗器を得ることができる。
Next, the aligned unit chips 3 are separated, and as shown in FIG. 6, a pair of external electrodes 6 is formed on each unit chip 3 so as to be electrically connected to the extraction electrode 5, and a resistive film is formed. An exterior film 7 is formed so as to cover 5 and a part of the extraction electrode 4. Either of the formation order of the external electrode 6 and the package film 7 may be performed first. The external electrode 6 is coated with a well-known electrode paste prepared by mixing a binder, a solvent, and the like with a metal powder such as silver, nickel, or the like, using a technique such as dip or roller coating. It is created by baking at the appropriate temperature. The exterior film 7 is formed by applying a known exterior paste mainly composed of plastic such as epoxy or silicon-based glass by using a method such as screen printing, roller coating or transfer, and converting the paste into a paste composition. It is created by baking at the appropriate temperature.
As described above, a chip resistor having a vertical sectional shape as shown in FIG. 6 can be obtained.

【0024】本第1実施形態では、単位チップ3に整合
した形状を有する複数のキャビティ1aを備え、且つ焼
成時の付加熱によって消失可能な成形枠1を使用し、成
形枠のキャビティ1aに焼成可能なスラリー2を充填し
た後、スラリー充填後の成形枠1を焼成温度で加熱して
キャビティ1a内のスラリー2を焼成して単位チップ化
すると共に、焼成時の付加熱によって成形枠1を消失さ
せて単位チップ3を得るようにしているので、単位チッ
プ3を得るため従来のようにセラミック基板を切断した
り分割する必要がなく、基板切断や基板分割によって生
じていたチッピングやバリ等の不具合を解消して、所定
形状の単位チップ3を容易且つ高精度で得ることがで
き、これにより高品質のチップ抵抗器を製造できる。
In the first embodiment, a molding frame 1 having a plurality of cavities 1a having a shape conforming to the unit chip 3 and capable of being eliminated by the additional heat during firing is used. After filling the possible slurry 2, the molding frame 1 after the slurry filling is heated at a firing temperature, and the slurry 2 in the cavity 1a is fired to form a unit chip, and the molding frame 1 disappears due to additional heat during firing. Since the unit chip 3 is obtained by cutting the substrate, it is not necessary to cut or divide the ceramic substrate to obtain the unit chip 3 as in the related art, and defects such as chipping and burrs caused by substrate cutting or substrate division are obtained. Can be obtained, and the unit chip 3 having a predetermined shape can be obtained easily and with high accuracy, whereby a high-quality chip resistor can be manufactured.

【0025】尚、前述の第1実施形態では、成形枠1の
キャビティ1aに1種類のセラミックスラリー2を充填
したものを示したが、図7(a)(b)に示すように、
組成の異なる2種類のセラミックスラリー8,9を所定
量ずつ充填すれば、同図(c)に示すように、組成が異
なる2つの層10a,10bを持つ単位チップ10を得
ることができる。同様にして、図8(a)に示すような
3層構造の単位チップ11や、図8(b)に示すような
5層構造の単位チップ12を任意に形成することができ
る。
In the first embodiment, the cavity 1a of the molding frame 1 is filled with one type of ceramic slurry 2. However, as shown in FIGS. 7 (a) and 7 (b),
When two types of ceramic slurries 8 and 9 having different compositions are filled in a predetermined amount, a unit chip 10 having two layers 10a and 10b having different compositions can be obtained as shown in FIG. Similarly, a unit chip 11 having a three-layer structure as shown in FIG. 8A and a unit chip 12 having a five-layer structure as shown in FIG. 8B can be arbitrarily formed.

【0026】このような多層構造の場合に、抵抗膜等が
形成される表面側の一方の層10a,11a,12aを
気孔率の低い緻密なものとし、他方の層10b,11
b,11cを気孔率の高いものとしておけば、抵抗膜等
を高精度に形成できると共に、単位チップ1個当たりの
重量を減らして軽量化を図ることができる。
In the case of such a multi-layer structure, one of the layers 10a, 11a, 12a on the surface side on which the resistive film or the like is formed has a low porosity and is dense, while the other layers 10b, 11a have a low porosity.
If b and 11c are made to have a high porosity, a resistive film or the like can be formed with high precision, and the weight per unit chip can be reduced to reduce the weight.

【0027】[第2実施形態]図9乃至図11は本発明
をチップ抵抗器に適用した第2実施形態に係るもので、
以下、同図に従ってチップ抵抗器の製造手順を説明す
る。
[Second Embodiment] FIGS. 9 to 11 relate to a second embodiment in which the present invention is applied to a chip resistor.
Hereinafter, the manufacturing procedure of the chip resistor will be described with reference to FIG.

【0028】製造に際しては、まず、図9に示すような
成形枠21を用意する。この成形枠21は、後述の単位
チップ23に整合した形状(図示例では直方体形状)を
有する複数のキャビティ21aを所定の配列で備えてい
る。また、成形枠21は、後述の焼成時の付加熱(アル
ミナ磁器の場合は1300〜1500℃)に対して耐熱
性を有する材料、例えば、前記の焼成温度よりも融点の
高い金属等から形成されている。
In manufacturing, first, a molding frame 21 as shown in FIG. 9 is prepared. The molding frame 21 is provided with a plurality of cavities 21a having a shape (in the illustrated example, a rectangular parallelepiped shape) aligned with a unit chip 23 described later in a predetermined arrangement. The molding frame 21 is formed of a material having heat resistance to additional heat during firing (1300 to 1500 ° C. in the case of alumina porcelain) described later, such as a metal having a melting point higher than the above firing temperature. ing.

【0029】次に、図10に示すように、成形枠21の
キャビティ21aそれぞれにセラミックスラリー22を
ほぼ一杯に充填する。このセラミックスラリー22は、
アルミナ等のセラミック粉末にバインダ及び溶剤等を混
合して調製された周知のものである。
Next, as shown in FIG. 10, each of the cavities 21a of the molding frame 21 is almost completely filled with the ceramic slurry 22. This ceramic slurry 22
It is a well-known material prepared by mixing a binder, a solvent, and the like with ceramic powder such as alumina.

【0030】次に、スラリー充填後の成形枠21を焼成
用加熱炉(図示省略)に投入して、前記セラミックスラ
リー22の組成に応じた所定の条件によって、キャビテ
ィ21a内のセラミックスラリー22の焼成を行う。先
に述べたように、成形枠21は焼成時の付加熱に対して
耐熱性を有しているので、焼成課程で該成型枠21の形
状が崩れるようなことはない。つまり、焼成を完了した
状態では、成形枠21のキャビティ21a内に焼成後の
単位チップ3がそのまま残る。
Next, the molding frame 21 after the slurry filling is put into a heating furnace (not shown) for firing, and firing of the ceramic slurry 22 in the cavity 21a is performed under predetermined conditions according to the composition of the ceramic slurry 22. I do. As described above, since the molding frame 21 has heat resistance against additional heat during firing, the shape of the molding frame 21 does not collapse during the firing process. That is, in a state where the firing is completed, the fired unit chip 3 remains in the cavity 21a of the molding frame 21 as it is.

【0031】次に、焼成用加熱炉から成形枠21を取り
出し、図11に示すように、該成形枠21を逆さにし
て、キャビティ21a内にある焼成後の単位チップ23
を抜き出す。単位チップ23がキャビティ21aの内面
とくっついているような場合でも、成形枠21に捻り力
を加えたり衝撃を与えれば該単位チップ23を簡単に取
り出すことができる。
Next, the molding frame 21 is taken out of the firing furnace, and as shown in FIG. 11, the molding frame 21 is turned upside down and the fired unit chips 23 in the cavity 21a are placed.
Take out. Even when the unit chip 23 is stuck to the inner surface of the cavity 21a, the unit chip 23 can be easily taken out by applying a twisting force or giving an impact to the molding frame 21.

【0032】次に、成形枠21から抜き出した複数の単
位チップ23を隙間なく整列し、図4と同様に、整列さ
れた各単位チップ23の一面に、引出電極を所定の形状
及び配列で形成する。次に、図5と同様に、整列された
各単位チップ23の同一面に、抵抗膜を所定の形状及び
配列で形成する。勿論、前記の引出電極及び抵抗膜は、
スパッタリングや電解・無電解メッキ等の薄膜手法によ
って形成することも可能である。
Next, the plurality of unit chips 23 extracted from the molding frame 21 are aligned without gaps, and the extraction electrodes are formed in a predetermined shape and arrangement on one surface of each aligned unit chip 23 as in FIG. I do. Next, similarly to FIG. 5, a resistive film is formed in a predetermined shape and arrangement on the same surface of the aligned unit chips 23. Of course, the extraction electrode and the resistive film
It can also be formed by a thin film technique such as sputtering or electrolytic / electroless plating.

【0033】次に、整列された各単位チップ23をばら
し、図6と同様に、各単位チップ3に対し、各引出電極
と導通するように一対の外部電極を形成し、且つ抵抗膜
と引出電極の一部を覆うように外装膜7を形成する。外
部電極と外装膜の形成順序はどちらが先でもよい。以上
で、図6同様の縦断面形状を備えたチップ抵抗器を得る
ことができる。
Next, as shown in FIG. 6, a pair of external electrodes is formed on each unit chip 3 so as to be electrically connected to each extraction electrode, and the unit chips 23 are separated from each other. An exterior film 7 is formed so as to cover a part of the electrode. Either of the formation order of the external electrode and the package film may be performed first. As described above, a chip resistor having the same vertical cross-sectional shape as in FIG. 6 can be obtained.

【0034】本第2実施形態では、単位チップ23に整
合した形状を有する複数のキャビティ21aを備え、且
つ焼成時の付加熱に対して耐熱性を有する成形枠21を
使用し、成形枠21のキャビティ21aに焼成可能なス
ラリー22を充填した後、スラリー充填後の成形枠21
を焼成温度に加熱してキャビティ21a内のスラリー2
2を焼成して単位チップ化し、これを成形枠21のキャ
ビティ21aから取り出すようにしているので、単位チ
ップ23を得るため従来のようにセラミック基板を切断
したり分割する必要がなく、基板切断や基板分割によっ
て生じていたチッピングやバリ等の不具合を解消して、
所定形状の単位チップ23を容易且つ高精度で得ること
ができ、これにより高品質のチップ抵抗器を製造でき
る。
In the second embodiment, a molding frame 21 having a plurality of cavities 21a having a shape matched to the unit chip 23 and having heat resistance against additional heat during firing is used. After filling the cavity 22a with the sinterable slurry 22, the molding frame 21 after the slurry filling is filled.
Is heated to the firing temperature to obtain slurry 2 in cavity 21a.
2 is baked to form a unit chip, which is taken out from the cavity 21a of the molding frame 21, so that it is not necessary to cut or divide the ceramic substrate to obtain the unit chip 23 as in the conventional case. Eliminates problems such as chipping and burrs caused by substrate division,
A unit chip 23 having a predetermined shape can be obtained easily and with high accuracy, and a high-quality chip resistor can be manufactured.

【0035】尚、前述の第2実施形態では、成形枠21
のキャビティ21aに1種類のセラミックスラリー22
を充填したものを示したが、図7及び図8と同様に、組
成の異なる複数種類のセラミックスラリーを所定量ずつ
充填すれば、多層構造の単位チップを簡単に得ることが
できる。
In the second embodiment, the molding frame 21
Ceramic slurry 22 in cavity 21a
However, as shown in FIGS. 7 and 8, when a plurality of types of ceramic slurries having different compositions are filled in predetermined amounts, a unit chip having a multilayer structure can be easily obtained.

【0036】また、前述の第2実施形態では、焼成後の
単位チップ23を成形枠21のキャビティ21aから取
り出してから、これら単位チップ23に引出電極や抵抗
膜を形成したが、図12に示すように、成形枠21のキ
ャビティ21aから単位チップ23を取り出す前に、キ
ャビティ21a内にある単位チップ23の露出面に引出
電極24や抵抗膜25等を形成するようにしてもよく、
このようにすれば、引出電極や抵抗膜等を形成するため
に単位チップ23を整列させる必要がなく、整列に要す
る治具や装置も省略できる利点がある。
In the above-described second embodiment, after the fired unit chips 23 are taken out of the cavities 21a of the molding frame 21, extraction electrodes and resistive films are formed on these unit chips 23, as shown in FIG. As described above, before taking out the unit chip 23 from the cavity 21a of the molding frame 21, the extraction electrode 24, the resistance film 25, and the like may be formed on the exposed surface of the unit chip 23 in the cavity 21a.
In this case, there is an advantage that the unit chips 23 do not need to be aligned to form the extraction electrodes and the resistive film, and the jigs and devices required for the alignment can be omitted.

【0037】[第3実施形態]図13及び図14は本発
明をチップ抵抗器に適用した第3実施形態に係るもの
で、以下、同図に従ってチップ抵抗器の製造手順を説明
する。
[Third Embodiment] FIGS. 13 and 14 relate to a third embodiment in which the present invention is applied to a chip resistor. Hereinafter, a manufacturing procedure of the chip resistor will be described with reference to FIG.

【0038】製造に際しては、まず、図13に示すよう
な成形枠31を用意する。この成形枠31は、単位チッ
プに整合した形状(図示例では直方体形状)を有する複
数のキャビティ31aを所定の配列で備えている。ま
た、成形枠31には第1,第2実施形態のような物性制
限は特段なく、該成形枠31は樹脂,金属等から任意に
形成することができる。
In manufacturing, first, a molding frame 31 as shown in FIG. 13 is prepared. The molding frame 31 is provided with a plurality of cavities 31a having a shape (a rectangular parallelepiped shape in the illustrated example) aligned with the unit chip in a predetermined arrangement. There is no particular limitation on the physical properties of the molding frame 31 as in the first and second embodiments, and the molding frame 31 can be arbitrarily formed of resin, metal, or the like.

【0039】次に、図14に示すように、成形枠31の
キャビティ31aそれぞれに自然硬化を可能したスラリ
ー32、例えば、石膏スラリーをほぼ一杯に充填する。
この石膏スラリーは、焼き石膏または無水石膏プラスタ
ーを水で練った周知のものである。
Next, as shown in FIG. 14, each of the cavities 31a of the molding frame 31 is almost completely filled with a slurry 32 which can be naturally hardened, for example, a gypsum slurry.
This gypsum slurry is a well-known gypsum or anhydrous gypsum plaster kneaded with water.

【0040】次に、スラリー充填後の成形枠31を前記
スラリー32の組成に応じた時間だけ放置し、キャビテ
ィ31a内のスラリー32の硬化を行う。つまり、硬化
を完了した状態では、成形枠31のキャビティ31a内
に焼成後の単位チップがそのまま残る。
Next, the molding frame 31 after the slurry filling is left for a time corresponding to the composition of the slurry 32, and the slurry 32 in the cavity 31a is hardened. In other words, after the curing is completed, the fired unit chip remains in the cavity 31a of the molding frame 31 as it is.

【0041】次に、図11と同様に、成形枠31を逆さ
にして、キャビティ31a内にある硬化後の単位チップ
を抜き出す。
Next, similarly to FIG. 11, the molding frame 31 is turned upside down, and the cured unit chip in the cavity 31a is extracted.

【0042】次に、成形枠31から抜き出した複数の単
位チップを隙間なく整列し、図4と同様に、整列された
各単位チップの一面に、引出電極を所定の形状及び配列
で形成する。次に、図5と同様に、整列された各単位チ
ップの同一面に、抵抗膜を所定の形状及び配列で形成す
る。勿論、前記の引出電極及び抵抗膜は、スパッタリン
グや電解・無電解メッキ等の薄膜手法によって形成する
ことも可能である。
Next, a plurality of unit chips extracted from the molding frame 31 are aligned without gaps, and the extraction electrodes are formed in a predetermined shape and arrangement on one surface of each aligned unit chip as in FIG. Next, similarly to FIG. 5, a resistive film is formed in a predetermined shape and arrangement on the same surface of each aligned unit chip. Needless to say, the extraction electrode and the resistive film can be formed by a thin film method such as sputtering or electrolytic / electroless plating.

【0043】次に、整列された各単位チップをばらし、
図6と同様に、各単位チップに対し、各引出電極と導通
するように一対の外部電極を形成し、且つ抵抗膜と引出
電極の一部を覆うように外装膜を形成する。外部電極と
外装膜の形成順序はどちらが先でもよい。以上で、図6
同様の縦断面形状を備えたチップ抵抗器を得ることがで
きる。
Next, the aligned unit chips are separated,
As in FIG. 6, a pair of external electrodes is formed for each unit chip so as to be electrically connected to each extraction electrode, and an exterior film is formed to cover a part of the resistance film and the extraction electrode. Either of the formation order of the external electrode and the package film may be performed first. FIG. 6
A chip resistor having a similar vertical cross-sectional shape can be obtained.

【0044】本第3実施形態では、単位チップに整合し
た形状を有する複数のキャビティ31aを備えた成形枠
31を使用し、成形枠31のキャビティ31aに自然硬
化可能なスラリー32を充填した後、キャビティ31a
内のスラリー32を硬化させて単位チップ化し、これを
成型枠31のキャビティ31aから取り出すようにして
いるので、単位チップを得るため従来のようにセラミッ
ク基板を切断したり分割する必要がなく、基板切断や基
板分割によって生じていたチッピングやバリ等の不具合
を解消して、所定形状の単位チップを容易且つ高精度で
得ることができ、これにより高品質のチップ抵抗器を製
造できる。
In the third embodiment, a molding frame 31 having a plurality of cavities 31a having a shape matched to a unit chip is used, and after a cavity 32a of the molding frame 31 is filled with a slurry 32 which can be naturally hardened, Cavity 31a
The slurry 32 in the inside is hardened into unit chips, which are taken out from the cavities 31a of the molding frame 31, so that it is not necessary to cut or divide the ceramic substrate to obtain the unit chips as in the conventional case. Problems such as chipping and burrs caused by cutting or dividing the substrate can be resolved, and a unit chip having a predetermined shape can be obtained easily and with high accuracy, whereby a high-quality chip resistor can be manufactured.

【0045】尚、前述の第3実施形態では、成形枠31
のキャビティ31aに1種類のセラミックスラリー32
を充填したものを示したが、図7及び図8と同様に、組
成の異なる複数種類のセラミックスラリーを所定量ずつ
充填すれば、多層構造の単位チップを簡単に得ることが
できる。
In the third embodiment, the molding frame 31 is used.
Ceramic slurry 32 in cavity 31a
However, as shown in FIGS. 7 and 8, when a plurality of types of ceramic slurries having different compositions are filled in predetermined amounts, a unit chip having a multilayer structure can be easily obtained.

【0046】また、前述の第3実施形態では、硬化後の
単位チップを成形枠31のキャビティ31aから取り出
してから、これら単位チップに引出電極や抵抗膜を形成
したが、図12と同様に、成形枠31のキャビティ31
aから単位チップを取り出す前に、キャビティ31a内
にある単位チップの露出面に引出電極や抵抗膜等を形成
するようにしてもよく、このようにすれば、引出電極や
抵抗膜等を形成するために単位チップを整列させる必要
がなく、整列に要する治具や装置も省略できる利点があ
る。
In the third embodiment described above, after the cured unit chips are taken out from the cavity 31a of the molding frame 31, the extraction electrodes and the resistive films are formed on these unit chips. Cavity 31 of molding frame 31
Before taking out the unit chip from a, an extraction electrode, a resistance film and the like may be formed on the exposed surface of the unit chip in the cavity 31a. In this case, the extraction electrode and the resistance film are formed. Therefore, there is an advantage that it is not necessary to align the unit chips and jigs and devices required for the alignment can be omitted.

【0047】以上、前述の各実施形態では何れもチップ
抵抗器に本発明を適用したものを示したが、本発明はチ
ップ抵抗器以外のチップ部品、例えば、回路構成部が平
面形状を有するインダクタやジャンパ等にも広く適用で
き、同様の効果を得ることができる。
As described above, in each of the above embodiments, the present invention is applied to a chip resistor. However, the present invention relates to a chip component other than the chip resistor, for example, an inductor in which a circuit component has a planar shape. And can be widely applied to jumpers and the like, and similar effects can be obtained.

【0048】[0048]

【発明の効果】以上詳述したように、本発明によれば、
単位チップを得るため従来のようにセラミック基板を切
断したり分割する必要がなく、基板切断や基板分割によ
って生じていたチッピングやバリ等の不具合を解消し
て、所定形状の単位チップを容易且つ高精度で得ること
ができ、これにより高品質のチップ部品を製造できる。
As described in detail above, according to the present invention,
In order to obtain a unit chip, it is not necessary to cut or divide the ceramic substrate as in the conventional case. It is possible to obtain with high precision, and it is possible to manufacture high quality chip components.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1実施形態に係る成形枠の斜視図FIG. 1 is a perspective view of a molding frame according to a first embodiment of the present invention.

【図2】成形枠にスラリーを充填した状態を示す斜視図FIG. 2 is a perspective view showing a state in which a molding frame is filled with slurry.

【図3】焼成によって型枠が消失して単位チップのみが
残った状態を示す斜視図
FIG. 3 is a perspective view showing a state in which a mold has disappeared by firing and only a unit chip remains.

【図4】単位チップに引出電極を形成した状態を斜視図FIG. 4 is a perspective view showing a state in which an extraction electrode is formed on a unit chip.

【図5】単位チップに抵抗膜を形成した状態を示す斜視
FIG. 5 is a perspective view showing a state in which a resistive film is formed on a unit chip.

【図6】単位チップに外部電極と外装膜を形成した状態
を示す縦断面図
FIG. 6 is a longitudinal sectional view showing a state in which an external electrode and an exterior film are formed on a unit chip.

【図7】他のスラリー充填方法と、同方法に準じて得ら
れた多層構造の単位チップの縦断面図
FIG. 7 is a vertical sectional view of a unit chip having a multilayer structure obtained according to another slurry filling method and the same method.

【図8】図7に示した以外の多層構造の単位チップの縦
断面図
8 is a longitudinal sectional view of a unit chip having a multilayer structure other than that shown in FIG. 7;

【図9】本発明の第2実施形態に係る成形枠の斜視図FIG. 9 is a perspective view of a molding frame according to a second embodiment of the present invention.

【図10】成形枠にスラリーを充填した状態を示す斜視
FIG. 10 is a perspective view showing a state where a slurry is filled in a molding frame.

【図11】成形枠から単位チップを取り出した状態を示
す斜視図
FIG. 11 is a perspective view showing a state in which a unit chip is taken out from a molding frame.

【図12】成形枠のキャビティ内にある単位チップに引
出電極及び抵抗膜を形成した状態を示す斜視図
FIG. 12 is a perspective view showing a state in which a lead electrode and a resistive film are formed on a unit chip in a cavity of a molding frame.

【図13】本発明の第3実施形態に係る成形枠の斜視図FIG. 13 is a perspective view of a molding frame according to a third embodiment of the present invention.

【図14】成形枠にスラリーを充填した状態を示す斜視
FIG. 14 is a perspective view showing a state where a slurry is filled in a molding frame.

【符号の説明】[Explanation of symbols]

1…成形枠、1a…キャビティ、2…スラリー、3…単
位チップ、4…引出電極、5…抵抗膜、6…外部電極、
7…保護膜、8,9…スラリー、10,11,12…単
位チップ、21…成形枠、21a…キャビティ、22…
スラリー、23…単位チップ、24…引出電極、25…
抵抗膜、31…成形枠、31a…キャビティ、32…ス
ラリー。
DESCRIPTION OF SYMBOLS 1 ... Mold frame, 1a ... Cavity, 2 ... Slurry, 3 ... Unit chip, 4 ... Extraction electrode, 5 ... Resistive film, 6 ... External electrode,
7: protective film, 8, 9: slurry, 10, 11, 12: unit chip, 21: molding frame, 21a: cavity, 22:
Slurry, 23 ... unit chip, 24 ... extraction electrode, 25 ...
Resistive film, 31: molding frame, 31a: cavity, 32: slurry.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 所定形状の単位チップを得る工程の少な
くとも前または後の工程で、単位チップに対応した回路
構築用の各種膜を形成するチップ部品の製造方法におい
て、 単位チップに整合した形状を有する複数のキャビティを
備え、且つ焼成時の付加熱によって消失可能な成形枠を
使用し、 成形枠のキャビティに焼成可能なスラリーを充填する工
程と、 スラリー充填後の成形枠を焼成温度で加熱してキャビテ
ィ内のスラリーを焼成して単位チップ化すると共に、焼
成時の付加熱によって成形枠を消失させて単位チップを
得る工程とを備えた、 ことを特徴とするチップ部品の製造方法。
In a method of manufacturing a chip component for forming various films for circuit construction corresponding to a unit chip in at least a step before or after a step of obtaining a unit chip having a predetermined shape, a shape matched to the unit chip is determined. Using a molding frame that has a plurality of cavities and that can be dissipated by additional heat during firing, filling a cavity of the molding frame with a slurry that can be sintered, and heating the molding frame after the slurry filling at a firing temperature. And baking the slurry in the cavity to form unit chips, and losing the forming frame by the additional heat during firing to obtain unit chips, the method comprising the steps of:
【請求項2】 所定形状の単位チップを得る工程の少な
くとも前または後の工程で、単位チップに対応した回路
構築用の各種膜を形成するチップ部品の製造方法におい
て、 単位チップに整合した形状を有する複数のキャビティを
備え、且つ焼成時の付加熱に対して耐熱性を有する成形
枠を使用し、 成形枠のキャビティに焼成可能なスラリーを充填する工
程と、 スラリー充填後の成形枠を焼成温度で加熱してキャビテ
ィ内のスラリーを焼成して単位チップ化する工程と、 成形枠のキャビティから単位チップを取り出す工程とを
備えた、 ことを特徴とするチップ部品の製造方法。
2. A method of manufacturing a chip component for forming various films for circuit construction corresponding to a unit chip in at least a step before or after a step of obtaining a unit chip having a predetermined shape. Using a molding frame having a plurality of cavities and having heat resistance against additional heat during firing, filling a cavity of the molding frame with a sinterable slurry, and firing the slurry after filling the slurry with a firing temperature. And baking the slurry in the cavity to form a unit chip by heating the slurry in the cavity; and taking out the unit chip from the cavity of the molding frame.
【請求項3】 所定形状の単位チップを得る工程の少な
くとも前または後の工程で、単位チップに対応した回路
構築用の各種膜を形成するチップ部品の製造方法におい
て、 単位チップに整合した形状を有する複数のキャビティを
備えた成形枠を使用し、 成形枠のキャビティに自然硬化可能なスラリーを充填
し、該スラリーを硬化させて単位チップ化する工程と、 成形枠のキャビティから単位チップを取り出す工程とを
備えた、 ことを特徴とするチップ部品の製造方法。
3. A method for manufacturing a chip component for forming various films for circuit construction corresponding to a unit chip in at least a step before or after a step of obtaining a unit chip having a predetermined shape. Using a molding frame having a plurality of cavities, filling a cavity of the molding frame with a slurry that can be naturally cured, curing the slurry to form unit chips, and removing a unit chip from the cavity of the molding frame A method for manufacturing a chip component, comprising:
【請求項4】 成形枠のキャビティから単位チップを取
り出す工程の前に、キャビティ内にある単位チップの露
出面に回路構築用の各種膜の一部を形成する工程を備え
た、 ことを特徴とする請求項2または3記載のチップ部品の
製造方法。
4. The method according to claim 1, further comprising, before the step of taking out the unit chip from the cavity of the molding frame, a step of forming a part of various films for circuit construction on the exposed surface of the unit chip in the cavity. 4. The method for manufacturing a chip component according to claim 2, wherein
JP9241447A 1997-09-05 1997-09-05 Manufacture of chip component Withdrawn JPH1187115A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9241447A JPH1187115A (en) 1997-09-05 1997-09-05 Manufacture of chip component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9241447A JPH1187115A (en) 1997-09-05 1997-09-05 Manufacture of chip component

Publications (1)

Publication Number Publication Date
JPH1187115A true JPH1187115A (en) 1999-03-30

Family

ID=17074450

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9241447A Withdrawn JPH1187115A (en) 1997-09-05 1997-09-05 Manufacture of chip component

Country Status (1)

Country Link
JP (1) JPH1187115A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006121053A (en) * 2004-09-14 2006-05-11 Stmicroelectronics Sa Thin glass chip for electronic components, and manufacturing method of the same
JP2006173159A (en) * 2004-12-13 2006-06-29 Matsushita Electric Ind Co Ltd Method of manufacturing chip component
US8426249B2 (en) 2004-12-13 2013-04-23 Panasonic Corporation Chip part manufacturing method and chip parts

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006121053A (en) * 2004-09-14 2006-05-11 Stmicroelectronics Sa Thin glass chip for electronic components, and manufacturing method of the same
JP2006173159A (en) * 2004-12-13 2006-06-29 Matsushita Electric Ind Co Ltd Method of manufacturing chip component
JP4548110B2 (en) * 2004-12-13 2010-09-22 パナソニック株式会社 Manufacturing method of chip parts
US8426249B2 (en) 2004-12-13 2013-04-23 Panasonic Corporation Chip part manufacturing method and chip parts

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