JP4544044B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP4544044B2
JP4544044B2 JP2005168773A JP2005168773A JP4544044B2 JP 4544044 B2 JP4544044 B2 JP 4544044B2 JP 2005168773 A JP2005168773 A JP 2005168773A JP 2005168773 A JP2005168773 A JP 2005168773A JP 4544044 B2 JP4544044 B2 JP 4544044B2
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semiconductor
semiconductor device
lead
resin sheet
wiring board
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JP2006344756A (en
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智彦 石田
弘人 杉浦
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TDK Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

本発明は、半導体ベアチップを配線基板に搭載したフリップチップ実装構造を備える半導体装置とその製造方法に関する。   The present invention relates to a semiconductor device having a flip chip mounting structure in which a semiconductor bare chip is mounted on a wiring board, and a method for manufacturing the same.

従来、パッケージの小型化、実装面積の縮小化を図るため、基板上のリードと半導体ベアチップ上に形成された突起電極とを電気的に接続する、いわゆるフリップチップ実装構造が用いられている。また、基板として、特に可撓性のあるフレキシブル配線基板を用いることで、更なる実装効率の向上が図られている。   Conventionally, a so-called flip chip mounting structure in which leads on a substrate and protruding electrodes formed on a semiconductor bare chip are electrically connected has been used to reduce the size of the package and the mounting area. Further, by using a flexible wiring board that is particularly flexible as the substrate, the mounting efficiency is further improved.

半導体ベアチップを配線基板にフリップチップ実装した従来の半導体装置８０を図６に示す。半導体装置８０は、図６に示すように、電極パッド８１ａを備える半導体ベアチップ８１と、可撓性のフレキシブル配線基板からなる配線基板８２と、配線基板８２上に銅箔等から形成されたリード８３と、金バンプ等からなり電極パッド８１ａ上に形成された突起電極８４と、リード８３を覆うように形成されたカバーレイフィルム８５と、半導体ベアチップ８１と配線基板８２との間に充填された封止樹脂８６と、を備える。また、リード８３と突起電極８４は、熱圧着や金属拡散等の手法で電気的に接続されており、突起電極８４やリード８３等の導電部材は、封止樹脂８６によって湿気や埃等から保護される。   FIG. 6 shows a conventional semiconductor device 80 in which a semiconductor bare chip is flip-chip mounted on a wiring board. As shown in FIG. 6, the semiconductor device 80 includes a semiconductor bare chip 81 having electrode pads 81a, a wiring board 82 made of a flexible flexible wiring board, and leads 83 formed on the wiring board 82 from copper foil or the like. A protruding electrode 84 made of a gold bump or the like, formed on the electrode pad 81a, a coverlay film 85 formed so as to cover the lead 83, and a seal filled between the semiconductor bare chip 81 and the wiring board 82. A stop resin 86. In addition, the lead 83 and the protruding electrode 84 are electrically connected by a technique such as thermocompression bonding or metal diffusion, and the conductive members such as the protruding electrode 84 and the lead 83 are protected from moisture, dust, and the like by the sealing resin 86. Is done.

図６に示す半導体装置８０は、リード８３と突起電極８４との接続強度が不十分で、配線基板８２を折り曲げた際の応力で、突起電極８４とリード８３との接点が離れることがあった。また、リード８３と封止樹脂８６の密着力が弱く、配線基板８２を折り曲げた際の応力で封止樹脂８６が剥離し、吸湿等の問題が生じることがあった。このため、図６に示すような従来の半導体装置８０は、応力による破損によって信頼性が低下するおそれがあり、ハンドリングに注意が必要であった。   In the semiconductor device 80 shown in FIG. 6, the connection strength between the lead 83 and the protruding electrode 84 is insufficient, and the contact between the protruding electrode 84 and the lead 83 may be separated due to the stress when the wiring board 82 is bent. . In addition, the adhesive force between the lead 83 and the sealing resin 86 is weak, and the sealing resin 86 is peeled off due to the stress when the wiring board 82 is bent, causing problems such as moisture absorption. For this reason, the conventional semiconductor device 80 as shown in FIG. 6 may be deteriorated in reliability due to breakage due to stress, and attention must be paid to handling.

そこで、図７に示すように配線基板８２を折り曲げた際に、突起電極８４とリード８３との剥離、封止樹脂８６の剥離等を防ぐよう半導体ベアチップ８１全体を樹脂層９５で覆い、強度を高めた半導体装置９１が開発されている（例えば、特許文献１参照）。   Therefore, when the wiring board 82 is bent as shown in FIG. 7, the entire semiconductor bare chip 81 is covered with the resin layer 95 so as to prevent the peeling between the protruding electrode 84 and the lead 83, the peeling of the sealing resin 86, and the like. An enhanced semiconductor device 91 has been developed (see, for example, Patent Document 1).

また、半導体ベアチップ８１が、特にフォトダイオード等の受光部を有する光学半導体素子８１ｂを含む場合、図８に示す半導体装置９２のように、配線基板８２に開口部８２ａを設け、この開口部８２ａに透光性樹脂９６を充填していた。または、図９に示す半導体装置９３のように、突起電極８４を樹脂層９８によって封止し、開口部８２ａを覆うようにガラス等の透光性基板９７を接着材によって接着し、光学半導体素子８１ｂ表面を保護していた。（例えば、特許文献２参照）
特開平１０−１９９９３６号公報 特許第３２０７３１９号公報 When the semiconductor bare chip 81 includes an optical semiconductor element 81b having a light receiving portion such as a photodiode, an opening 82a is provided in the wiring board 82 as in the semiconductor device 92 shown in FIG. 8, and the opening 82a is provided in the opening 82a. The translucent resin 96 was filled. Alternatively, as in the semiconductor device 93 shown in FIG. 9, the protruding electrode 84 is sealed with a resin layer 98, and a light-transmitting substrate 97 such as glass is adhered with an adhesive so as to cover the opening 82a, thereby providing an optical semiconductor element. The surface of 81b was protected. (For example, see Patent Document 2)
JP-A-10-199936 Japanese Patent No. 3307319

図７に示す半導体装置９１では、樹脂層９５の分だけ半導体装置９１の厚みが増すため、小型化、薄型化には適さず、樹脂層９５の使用量が多くなると、製造コストの面でも適当ではない。さらに、半導体ベアチップ８１上に樹脂層９５を形成するための樹脂供給作業の工程が増える分、生産効率が低下する問題があった。   In the semiconductor device 91 shown in FIG. 7, the thickness of the semiconductor device 91 is increased by the resin layer 95. Therefore, the semiconductor device 91 is not suitable for downsizing and thinning. If the amount of the resin layer 95 used is increased, the manufacturing cost is appropriate. is not. Furthermore, there is a problem that the production efficiency is lowered by the increase in the number of steps of the resin supply operation for forming the resin layer 95 on the semiconductor bare chip 81.

また、図８に示すように半導体ベアチップ８１が光学半導体素子８１ｂを備える場合、光学半導体素子８１ｂの受光部（又は発光面）に対向するように、配線基板８２に開口部８２ａを形成するため、強度が低下する問題があった。   Further, when the semiconductor bare chip 81 includes the optical semiconductor element 81b as shown in FIG. 8, the opening 82a is formed in the wiring substrate 82 so as to face the light receiving part (or light emitting surface) of the optical semiconductor element 81b. There was a problem that the strength decreased.

また、図９に示すように配線基板８２の開口部８２ａを透光性基板９７で覆った場合、透光性基板９７の厚み分だけ半導体装置９３も厚くなり、半導体装置９３を小型化、薄型化することが困難となる。また、開口部８２ａを設けて透光性基板９７を設ける等製造工程が増加し、製造コストが増加する、生産効率が低下する等の問題があった。図８に示すように配線基板８２の開口部８２ａを透明樹脂で充填する場合も、同様に樹脂材料が多量に必要となり、製造コストおよび作業工程が増加する問題があった。   Further, as shown in FIG. 9, when the opening 82 a of the wiring substrate 82 is covered with the translucent substrate 97, the semiconductor device 93 becomes thicker by the thickness of the translucent substrate 97, and the semiconductor device 93 is reduced in size and thickness. It becomes difficult to make it. In addition, there are problems such as an increase in manufacturing steps such as providing the opening 82a and providing the translucent substrate 97, increasing the manufacturing cost, and reducing the production efficiency. As shown in FIG. 8, when the opening 82a of the wiring board 82 is filled with a transparent resin, a large amount of resin material is similarly required, resulting in an increase in manufacturing cost and work process.

本発明は、上記実情に鑑みてなされたものであり、配線基板上にフリップチップ実装された半導体装置において、フレキシブル配線基板を折り曲げたときの突起電極とリードとの接点の乖離及び封止樹脂のクラックを防ぐことができ、高い信頼性を備える半導体装置を提供することを目的とする。また、本発明は、小型化、薄型化が可能であり、製造コスト及び生産効率に優れる半導体装置とその製造方法を提供することを目的とする。   The present invention has been made in view of the above circumstances, and in a semiconductor device flip-chip mounted on a wiring board, the contact between the protruding electrode and the lead when the flexible wiring board is bent and the sealing resin An object is to provide a semiconductor device that can prevent cracks and has high reliability. Another object of the present invention is to provide a semiconductor device that can be reduced in size and thickness, and that is excellent in manufacturing cost and production efficiency, and a manufacturing method thereof.

上記目的を達成するため、本発明の第１の観点にかかる半導体装置は、
配線基板と、
前記配線基板上に形成されたリードと、
前記リードに電気的に接続された突起電極と半導体素子とを有する半導体チップと、
前記半導体チップと、前記リードとを一括して被覆する樹脂シートと、を備え、
前記半導体チップの前記半導体素子は、前記突起電極が形成された面とは反対側の面に形成され、
前記半導体チップは、前記半導体チップの前記半導体素子が形成された面に設けられた電極パッドを更に備え、
前記電極パッドと前記突起電極とが、前記半導体チップを貫通する導電部材を介して、電気的に接続され、
前記半導体チップの前記半導体素子は、受光部又は発光部を有する光学半導体素子であり、
前記樹脂シートは透光性を備えることを特徴とする。 In order to achieve the above object, a semiconductor device according to the first aspect of the present invention includes:
A wiring board;
A lead formed on the wiring board;
A semiconductor chip having a protruding electrode and a semiconductor element electrically connected to the lead;
A resin sheet that collectively covers the semiconductor chip and the leads ;
The semiconductor element of the semiconductor chip is formed on a surface opposite to the surface on which the protruding electrode is formed,
The semiconductor chip further includes an electrode pad provided on a surface of the semiconductor chip where the semiconductor element is formed,
The electrode pad and the protruding electrode are electrically connected via a conductive member penetrating the semiconductor chip,
The semiconductor element of the semiconductor chip is an optical semiconductor element having a light receiving part or a light emitting part,
The resin sheet is characterized Rukoto with translucency.

前記半導体チップと前記配線基板との間に、少なくとも前記リードと前記突起電極とを覆うように封止樹脂が形成されていてもよい。 Wherein between the semiconductor chip and the wiring substrate may have a sealing resin so as to cover and at least the lead said projection electrodes are formed.

前記配線基板は、フレキシブル基板からなっていてもよい。The wiring board may be a flexible board.

前記樹脂シートは、前記半導体チップと対向する面に接着層を備え、該接着層によって前記半導体チップと、リードとを覆うように前記半導体チップに貼り付けられていてもよい。The resin sheet may include an adhesive layer on a surface facing the semiconductor chip, and may be attached to the semiconductor chip so as to cover the semiconductor chip and the lead with the adhesive layer.

本発明によれば、配線基板上にフリップチップ実装された半導体ベアチップとリードとを、一括して樹脂シートで覆うことによって、突起電極とリードとの乖離を防止することができ、また封止樹脂がなくとも、水分や埃等からの汚染を防止できるため、高い信頼性を備える半導体装置とその製造方法を提供することができる。
また、本発明によれば、樹脂シートによって、突起電極とリード、リードと封止樹脂等の剥離を防ぐことができるため、小型化、薄型化することが可能な半導体装置とその製造方法を提供することができる。
また、本発明によれば、樹脂シート製作工程が配線基板のカバーレイフィルム製作工程を兼ねることができるため、生産効率が良くコスト削減が可能な半導体装置とその製造方法を提供することができる。 According to the present invention, the semiconductor bare chip flip-chip mounted on the wiring substrate and the lead are collectively covered with the resin sheet, so that separation between the protruding electrode and the lead can be prevented, and the sealing resin Even without this, since contamination from moisture, dust and the like can be prevented, a highly reliable semiconductor device and a manufacturing method thereof can be provided.
In addition, according to the present invention, the resin sheet can prevent the protruding electrode and the lead, the lead and the sealing resin, and the like from being peeled off, so that a semiconductor device that can be reduced in size and thickness and a manufacturing method thereof are provided. can do.
In addition, according to the present invention, since the resin sheet manufacturing process can also serve as a wiring board cover lay film manufacturing process, it is possible to provide a semiconductor device with high production efficiency and cost reduction, and a manufacturing method thereof.

本発明の実施の形態に係る半導体装置及び製造方法について図を用いて説明する。   A semiconductor device and a manufacturing method according to an embodiment of the present invention will be described with reference to the drawings.

（第１の実施の形態）
本発明の第１の実施の形態に係る半導体装置１０を図１に示す。半導体装置１０は、図１に示すように、半導体ベアチップ１１と、配線基板１２と、リード１３と、突起電極１４と、樹脂シート１５と、を備える。 (First embodiment)
A semiconductor device 10 according to the first embodiment of the present invention is shown in FIG. As shown in FIG. 1, the semiconductor device 10 includes a semiconductor bare chip 11, a wiring substrate 12, leads 13, protruding electrodes 14, and a resin sheet 15.

半導体ベアチップ１１は、所定機能を備える半導体素子が搭載される。また、半導体ベアチップ１１は、配線基板１２と対向する面に電極パッド１１ａを備えており、電極パッド１１ａ上に突起電極１４が形成される。   A semiconductor element having a predetermined function is mounted on the semiconductor bare chip 11. Further, the semiconductor bare chip 11 includes an electrode pad 11a on a surface facing the wiring substrate 12, and a protruding electrode 14 is formed on the electrode pad 11a.

配線基板１２は、ポリイミド樹脂、ガラスエポキシ等から形成された可撓性のフレキシブル配線基板から構成される。   The wiring board 12 is composed of a flexible flexible wiring board formed of polyimide resin, glass epoxy, or the like.

リード１３は、銅箔等から構成され、配線基板１２上に複数形成される。また、リード１３は電極パッド部１３ａを備え、電極パッド部１３ａと突起電極１４とは熱圧着や金属拡散等の方法で電気的に接続される。リード１３の電極パッド部１３ａを備える一端は図１に示すように樹脂シート１５に覆われているが、リード１３の他方の端は樹脂シート１５から露出する。   The leads 13 are made of copper foil or the like, and a plurality of leads 13 are formed on the wiring board 12. The lead 13 includes an electrode pad portion 13a, and the electrode pad portion 13a and the protruding electrode 14 are electrically connected by a method such as thermocompression bonding or metal diffusion. One end of the lead 13 having the electrode pad portion 13 a is covered with the resin sheet 15 as shown in FIG. 1, but the other end of the lead 13 is exposed from the resin sheet 15.

突起電極１４は、例えば金バンプ等から構成され、半導体ベアチップ１１の電極パッド１１ａ上に形成される。突起電極１４は、リード１３の電極パッド部１３ａに電気的に接続されている。   The protruding electrode 14 is composed of, for example, a gold bump or the like, and is formed on the electrode pad 11 a of the semiconductor bare chip 11. The protruding electrode 14 is electrically connected to the electrode pad portion 13 a of the lead 13.

樹脂シート１５は、ポリイミドやエポキシ樹脂等から構成される。樹脂シート１５の半導体ベアチップ１１と対向する面に熱硬化性又は紫外線硬化性樹脂からなる接着層（図示せず）が形成される。接着層によって樹脂シート１５は、半導体ベアチップ１１と、リード１３とに密着する。   The resin sheet 15 is composed of polyimide, epoxy resin, or the like. An adhesive layer (not shown) made of a thermosetting or ultraviolet curable resin is formed on the surface of the resin sheet 15 facing the semiconductor bare chip 11. The resin sheet 15 is in close contact with the semiconductor bare chip 11 and the lead 13 by the adhesive layer.

このように本発明の半導体装置１０は、半導体ベアチップ１１とリード１３とを樹脂シート１５で覆うことによって、突起電極１４とリード１３との乖離を防止することができる。従って、樹脂シート１５によって半導体装置１０の強度が増すことから、樹脂シートを備えない従来の半導体装置と比較して、配線基板１２を薄く形成することができ、半導体装置１０を小型化、薄型化することができる。また、本発明の半導体装置１０は、樹脂シート１５によって半導体ベアチップ１１及びリード１３が覆われているため、水分や埃等の進入を防ぐことができ、高い信頼性を得ることができる。   Thus, the semiconductor device 10 of the present invention can prevent the protrusion electrode 14 and the lead 13 from being separated by covering the semiconductor bare chip 11 and the lead 13 with the resin sheet 15. Therefore, since the strength of the semiconductor device 10 is increased by the resin sheet 15, the wiring substrate 12 can be formed thinner than the conventional semiconductor device not provided with the resin sheet, and the semiconductor device 10 can be reduced in size and thickness. can do. Moreover, since the semiconductor bare chip 11 and the lead 13 are covered with the resin sheet 15, the semiconductor device 10 of the present invention can prevent entry of moisture, dust, and the like, and can obtain high reliability.

また、本発明の半導体装置１０は、樹脂シート１５によって突起電極１４とリード１３との接点を補強することができるため、従来接点を補強するために必要とされた樹脂材料を大量に使用することがない。また、樹脂シート１５をリード１３上に覆うことで、従来リード上に必要とされたカバーレイフィルムが不要となり、コストを削減することができる。   Moreover, since the semiconductor device 10 of the present invention can reinforce the contact point between the protruding electrode 14 and the lead 13 with the resin sheet 15, a large amount of resin material that has been conventionally required to reinforce the contact point is used. There is no. Further, by covering the resin sheet 15 on the lead 13, a coverlay film that has been conventionally required on the lead becomes unnecessary, and the cost can be reduced.

次に、本実施形態に係る半導体装置の製造方法を説明する。
なお、以下に記載する製造方法は一例であって、同様の結果物が得られるのであればこれに限定されない。 Next, a method for manufacturing the semiconductor device according to the present embodiment will be described.
In addition, the manufacturing method described below is an example, and if the same result is obtained, it will not be limited to this.

まず、配線基板１２上の所定の位置にリード１３を形成する。
次に、突起電極１４が形成された半導体ベアチップ１１を、突起電極１４がリード１３の電極パッド部１３ａに位置するように搭載する。 First, leads 13 are formed at predetermined positions on the wiring board 12.
Next, the semiconductor bare chip 11 on which the protruding electrode 14 is formed is mounted so that the protruding electrode 14 is positioned on the electrode pad portion 13 a of the lead 13.

続いて、半導体ベアチップ１１の突起電極１４とリード１３とを、熱圧着や金属拡散等の手法、あるいはハンダ、ロウ材、導電性接着剤、異方性導電膜等を用いて電気的に接続する。   Subsequently, the protruding electrode 14 and the lead 13 of the semiconductor bare chip 11 are electrically connected using a technique such as thermocompression bonding or metal diffusion, or using solder, brazing material, conductive adhesive, anisotropic conductive film, or the like. .

次に、片面に接着層を形成した樹脂シート１５を、半導体ベアチップ１１及びリード１３を一括して覆うように貼り合わせる。   Next, the resin sheet 15 having an adhesive layer formed on one side is bonded so as to cover the semiconductor bare chip 11 and the leads 13 together.

次に、樹脂シート１５をローラープレス、真空プレス等の手法で配線基板１２に密着させる。そして、樹脂シート１５の接着層を熱硬化、又は紫外線硬化によって硬化させる。
このようにして半導体装置１０が製造される。 Next, the resin sheet 15 is brought into close contact with the wiring board 12 by a method such as roller press or vacuum press. Then, the adhesive layer of the resin sheet 15 is cured by heat curing or ultraviolet curing.
In this way, the semiconductor device 10 is manufactured.

本実施の形態の半導体装置の製造方法によれば、片面に接着層を形成した樹脂シート１５を半導体ベアチップ１１とリード１３上に配置した上で硬化させることにより、半導体ベアチップ１１と配線基板１２との間に封止樹脂を形成しなくとも、リード１３、突起電極１４等を水分、埃等による汚染から保護することができる。従って、封止樹脂を形成する工程を省略することができ、生産効率が良くコスト削減が可能な製造方法を提供することができる。   According to the method for manufacturing a semiconductor device of the present embodiment, the resin sheet 15 having an adhesive layer formed on one side is disposed on the semiconductor bare chip 11 and the lead 13 and then cured, whereby the semiconductor bare chip 11 and the wiring substrate 12 are Even if no sealing resin is formed between them, the lead 13, the protruding electrode 14 and the like can be protected from contamination by moisture, dust and the like. Therefore, the process of forming the sealing resin can be omitted, and a manufacturing method with high production efficiency and cost reduction can be provided.

また、樹脂シート１５によって、突起電極１４とリード１３との接点を補強することができるため配線基板１２を薄く形成することができ、半導体装置１０の小型化、薄型化を図ることができる。また、本発明によれば樹脂シート１５が、カバーレイフィルム作製工程を兼ねるため、工程数を削減し、コスト削減を図ることが可能となる。   Further, since the contact between the protruding electrode 14 and the lead 13 can be reinforced by the resin sheet 15, the wiring board 12 can be formed thin, and the semiconductor device 10 can be reduced in size and thickness. Further, according to the present invention, since the resin sheet 15 also serves as a coverlay film manufacturing process, it is possible to reduce the number of processes and reduce costs.

（第２の実施形態）
本発明の第２の実施の形態に係る半導体装置２０を図２に示す。
本実施の形態の半導体装置２０が第１の実施の形態の半導体装置１０と異なるのは、封止樹脂２１が形成される点にある。第１の実施の形態と同様の構成を採る部分に関する詳細な説明は、同一の引用符号を用いて省略する。 (Second Embodiment)
A semiconductor device 20 according to a second embodiment of the present invention is shown in FIG.
The semiconductor device 20 of the present embodiment is different from the semiconductor device 10 of the first embodiment in that a sealing resin 21 is formed. Detailed descriptions of parts having the same configuration as in the first embodiment will be omitted using the same reference numerals.

半導体装置２０は、図２に示すように半導体ベアチップ１１と、配線基板１２と、リード１３と、突起電極１４と、樹脂シート１５と、に加えて、封止樹脂２１を備える。   As shown in FIG. 2, the semiconductor device 20 includes a sealing resin 21 in addition to the semiconductor bare chip 11, the wiring substrate 12, the leads 13, the protruding electrodes 14, and the resin sheet 15.

封止樹脂２１は、例えばエポキシ樹脂等から形成される。封止樹脂１２は、半導体ベアチップ１１と、配線基板１２との間に形成され、リード１３、突起電極１４を覆う。   The sealing resin 21 is formed from, for example, an epoxy resin. The sealing resin 12 is formed between the semiconductor bare chip 11 and the wiring substrate 12 and covers the leads 13 and the protruding electrodes 14.

本実施の形態の半導体装置２０は、樹脂シート１５だけでなく、リード１３と、突起電極１４とを覆って封止樹脂２１が形成されるため、リード１３と突起電極１４の腐食を良好に防ぐことができる。
また、図６に示す従来の半導体装置８０では、封止樹脂８６にクラックが発生する恐れがあったが、本実施の形態では、樹脂シート１５によって、半導体装置２０は良好に補強されるため、封止樹脂２１内に生じるクラックの発生を防ぐことができる。このように本実施の形態の半導体装置２０は、高い信頼性を備えることができる。 In the semiconductor device 20 according to the present embodiment, the sealing resin 21 is formed to cover not only the resin sheet 15 but also the lead 13 and the protruding electrode 14, so that corrosion of the lead 13 and the protruding electrode 14 can be satisfactorily prevented. be able to.
Further, in the conventional semiconductor device 80 shown in FIG. 6, there is a risk that cracks may occur in the sealing resin 86, but in the present embodiment, the semiconductor device 20 is reinforced well by the resin sheet 15, Generation of cracks occurring in the sealing resin 21 can be prevented. Thus, the semiconductor device 20 of the present embodiment can have high reliability.

（第３の実施形態）
本発明の第３の実施の形態に係る半導体装置３０を図３に示す。
本実施の形態の半導体装置３０が第１の実施の形態の半導体装置１０と異なるのは、半導体ベアチップ１１が光学半導体素子１１ｂを備える点にある。第１の実施の形態と同様の構成を採る部分に関する詳細な説明は、同一の引用符号を用いて省略する。 (Third embodiment)
A semiconductor device 30 according to a third embodiment of the present invention is shown in FIG.
The semiconductor device 30 of this embodiment is different from the semiconductor device 10 of the first embodiment in that the semiconductor bare chip 11 includes an optical semiconductor element 11b. Detailed descriptions of parts having the same configuration as in the first embodiment will be omitted using the same reference numerals.

半導体装置３０は、図３に示すように半導体ベアチップ１１と、リード１３と、突起電極１４と、樹脂シート１５と、配線基板３１と、を備える。   As shown in FIG. 3, the semiconductor device 30 includes a semiconductor bare chip 11, leads 13, protruding electrodes 14, a resin sheet 15, and a wiring substrate 31.

半導体ベアチップ１１の下面に、光学半導体素子１１ｂの受光面又は発光面が形成される。半導体ベアチップ１１の電極パッド１１ａは、光学半導体素子１１ｂと同一面に形成される。   The light receiving surface or light emitting surface of the optical semiconductor element 11 b is formed on the lower surface of the semiconductor bare chip 11. The electrode pad 11a of the semiconductor bare chip 11 is formed on the same surface as the optical semiconductor element 11b.

配線基板３１は、第１の実施の形態と同様にフレキシブル配線基板から構成される。配線基板３１は、光学半導体素子１１ｂの受光面に十分な光が到達するように、又は発光面から発せられる光が十分透過するように、第１の実施の形態の配線基板１２より薄く形成される。   The wiring board 31 is composed of a flexible wiring board as in the first embodiment. The wiring substrate 31 is formed thinner than the wiring substrate 12 of the first embodiment so that sufficient light reaches the light receiving surface of the optical semiconductor element 11b or light transmitted from the light emitting surface is sufficiently transmitted. The

このように、本実施の形態の半導体装置３０は、樹脂シート１５によって半導体ベアチップ１１等が覆われるため、樹脂シート１５が形成されない場合と比較し、より配線基板３１の厚みを薄くすることができる。従って、あえて透明な材料を配線基板３１として用いなくとも、光学半導体素子１１ｂに求められる透光性を確保することができる。   Thus, since the semiconductor bare chip 11 etc. are covered with the resin sheet 15, the semiconductor device 30 of this Embodiment can make the thickness of the wiring board 31 thinner compared with the case where the resin sheet 15 is not formed. . Therefore, the translucency required for the optical semiconductor element 11b can be ensured without using a transparent material as the wiring substrate 31.

なお、半導体ベアチップ１１に搭載された光学半導体素子１１ｂが、高い透光性を必要とする場合、配線基板３１の厚さを薄くするのみでは対応できない場合等、配線基板３１は、透明な材料から形成されても良い。この場合、配線基板３１として従来のフレキシブル基板を利用する場合より、配線基板３１をやや厚く形成することが可能となる。   When the optical semiconductor element 11b mounted on the semiconductor bare chip 11 requires high translucency, or when the thickness of the wiring substrate 31 cannot be reduced, the wiring substrate 31 is made of a transparent material. It may be formed. In this case, it is possible to form the wiring substrate 31 slightly thicker than when a conventional flexible substrate is used as the wiring substrate 31.

（第４の実施形態）
本発明の第４の実施の形態に係る半導体装置４０を図４に示す。
本実施の形態の半導体装置４０が第１の実施の形態の半導体装置と異なるのは、配線基板１２が開口部１２ａを備え、開口部１２ａが透明樹脂シート４１で覆われている点にある。第１の実施の形態と同様の構成を採る部分に関する詳細な説明は、同一の引用符号を用いて省略する。 (Fourth embodiment)
A semiconductor device 40 according to a fourth embodiment of the present invention is shown in FIG.
The semiconductor device 40 of the present embodiment is different from the semiconductor device of the first embodiment in that the wiring board 12 includes an opening 12 a and the opening 12 a is covered with a transparent resin sheet 41. Detailed descriptions of parts having the same configuration as in the first embodiment will be omitted using the same reference numerals.

半導体装置４０は、図４に示すように、半導体ベアチップ１１と、配線基板１２と、リード１３と、突起電極１４と、樹脂シート１５と、透明樹脂シート４１と、を備える。   As shown in FIG. 4, the semiconductor device 40 includes a semiconductor bare chip 11, a wiring substrate 12, leads 13, protruding electrodes 14, a resin sheet 15, and a transparent resin sheet 41.

半導体ベアチップ１１の下面に、光学半導体素子１１ｂの受光面又は発光面が形成される。半導体ベアチップ１１の電極パッド１１ａは、光学半導体素子１１ｂと同一面に形成される。   The light receiving surface or light emitting surface of the optical semiconductor element 11 b is formed on the lower surface of the semiconductor bare chip 11. The electrode pad 11a of the semiconductor bare chip 11 is formed on the same surface as the optical semiconductor element 11b.

配線基板１２は、光学半導体素子１１ｂの受光面又は発光面に対応して形成された開口部１２ａを備える。開口部１２ａは、透明樹脂シート４１によって覆われている。   The wiring board 12 includes an opening 12a formed corresponding to the light receiving surface or the light emitting surface of the optical semiconductor element 11b. The opening 12 a is covered with a transparent resin sheet 41.

透明樹脂シート４１は、例えばエポキシ樹脂等から構成され、配線基板１２に形成された開口部１２ａを塞ぐように、配線基板１２の下面に設置される。   The transparent resin sheet 41 is made of, for example, epoxy resin or the like, and is installed on the lower surface of the wiring board 12 so as to close the opening 12a formed in the wiring board 12.

本実施の形態の半導体装置４０によれば、配線基板１２に開口部１２ａを設け、開口部１２ａを透明樹脂シート４１で覆うことによって、光学半導体素子１１ｂに必要とされる十分な透光性を得ることができる。なお、半導体装置４０は、樹脂シート１５によって覆われるため、配線基板１２が開口部１２ａを備えても、十分な強度を確保することができる。また、半導体装置４０は、樹脂シート１５及び透明樹脂シート４１で覆われるため、リード１３、突起電極１４等を埃、水分等から保護することができ、高い信頼性を得ることができる。   According to the semiconductor device 40 of the present embodiment, the opening 12a is provided in the wiring board 12, and the opening 12a is covered with the transparent resin sheet 41, thereby providing sufficient translucency required for the optical semiconductor element 11b. Obtainable. In addition, since the semiconductor device 40 is covered with the resin sheet 15, even if the wiring board 12 includes the opening 12a, sufficient strength can be ensured. In addition, since the semiconductor device 40 is covered with the resin sheet 15 and the transparent resin sheet 41, the leads 13, the protruding electrodes 14 and the like can be protected from dust, moisture, and the like, and high reliability can be obtained.

（第５の実施形態）
本発明の第５の実施の形態に係る半導体装置５０を図５に示す。
本実施の形態の半導体装置５０が第１実施の形態の半導体装置１０等と異なるのは、半導体ベアチップ５１の上面に光学半導体素子５１ａが形成される点にある。他の実施の形態と同様の構成を採る部分に関する詳細な説明は省略する。 (Fifth embodiment)
FIG. 5 shows a semiconductor device 50 according to the fifth embodiment of the present invention.
The semiconductor device 50 according to the present embodiment is different from the semiconductor device 10 according to the first embodiment in that an optical semiconductor element 51 a is formed on the upper surface of the semiconductor bare chip 51. A detailed description of a part having the same configuration as that of the other embodiments is omitted.

半導体装置５０は、図５に示すように半導体ベアチップ５１と、配線基板５２と、リード５３と、突起電極５４と、樹脂シート５５と、貫通電極５１ｃと、を備える。   As shown in FIG. 5, the semiconductor device 50 includes a semiconductor bare chip 51, a wiring substrate 52, leads 53, protruding electrodes 54, a resin sheet 55, and a through electrode 51c.

半導体ベアチップ５１は、上面に光学半導体素子５１ｂの受光面又は発光面を備え、電極パッド５１ａを上面に備える。また、半導体ベアチップ５１は、貫通電極５１ｃを備えており、この貫通電極５１ｃを介して電極パッド５１ａと、突起電極５４とは電気的に接続される。   The semiconductor bare chip 51 includes a light receiving surface or a light emitting surface of the optical semiconductor element 51b on the upper surface, and an electrode pad 51a on the upper surface. Further, the semiconductor bare chip 51 includes a through electrode 51c, and the electrode pad 51a and the protruding electrode 54 are electrically connected through the through electrode 51c.

配線基板５２は、フレキシブル配線基板からなる。
また、突起電極５４は、金バンプ等からなり、リード５３の電極パッド部５３と電気的に接続される。 The wiring board 52 is a flexible wiring board.
The protruding electrode 54 is made of a gold bump or the like and is electrically connected to the electrode pad portion 53 of the lead 53.

また、樹脂シート５５は、光学半導体素子５１ｂに必要な透光性を備える透明性樹脂材料から形成される。樹脂シート５５は、半導体ベアチップ５１と対向する面に接着層を備えており、半導体ベアチップ５１と、リード５３とを覆うように一括して貼り付けられる。   The resin sheet 55 is formed from a transparent resin material having translucency necessary for the optical semiconductor element 51b. The resin sheet 55 has an adhesive layer on the surface facing the semiconductor bare chip 51, and is bonded together so as to cover the semiconductor bare chip 51 and the leads 53.

本実施の形態の半導体装置５０は、樹脂シート５５を透光性を備える樹脂から形成することによって、半導体ベアチップ１１上面に光学半導体素子５１ｂの受光面又は発光面が形成された場合であっても、光学半導体素子５１ｂに必要とされる透光性を確保しつつ、半導体装置５０の強度を確保することができる。   Even in the case where the light receiving surface or the light emitting surface of the optical semiconductor element 51b is formed on the upper surface of the semiconductor bare chip 11, the semiconductor device 50 of the present embodiment is formed by forming the resin sheet 55 from a resin having translucency. The strength of the semiconductor device 50 can be ensured while ensuring the translucency required for the optical semiconductor element 51b.

また、他の実施の形態と同様に、樹脂シート５５によってリード５３、突起電極５４等は水分、埃等から保護されるため、高い信頼性を備えることが可能である。また、配線基板５２を従来と比較して薄く形成することが可能であるため、半導体装置５０は、小型化、薄型化することが可能である。   Further, as in the other embodiments, the resin sheet 55 protects the leads 53, the protruding electrodes 54, and the like from moisture, dust, and the like, and thus can have high reliability. In addition, since the wiring substrate 52 can be formed thinner than the conventional one, the semiconductor device 50 can be reduced in size and thickness.

本発明は上述した各実施の形態に限られず様々な修正及び応用が可能である。
例えば、上述した第３〜第５の実施の形態では突起電極とリードとが樹脂で封止されていない場合を例に挙げて説明したが、これに限られず第２の実施の形態と同様に突起電極とリードの周囲に封止樹脂が形成されていても良い。
例えば第３の実施の形態のように半導体ベアチップ１１に光学半導体素子１１ｂが形成されている場合、封止樹脂は透光性を備える樹脂を用いてもよいし、透光性を備えない樹脂を用いて、リード１３と突起電極１４の周囲のみに封止樹脂を形成しても良い。 The present invention is not limited to the above-described embodiments, and various modifications and applications are possible.
For example, in the above-described third to fifth embodiments, the case where the protruding electrodes and the leads are not sealed with the resin has been described as an example. However, the present invention is not limited to this and is similar to the second embodiment. A sealing resin may be formed around the protruding electrode and the lead.
For example, when the optical semiconductor element 11b is formed on the semiconductor bare chip 11 as in the third embodiment, the sealing resin may be a resin having translucency or a resin having no translucency. Alternatively, the sealing resin may be formed only around the lead 13 and the protruding electrode 14.

本発明の第１の実施の形態に係る半導体装置の構成例を示す図である。It is a figure which shows the structural example of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第２の実施の形態に係る半導体装置の構成例を示す図である。It is a figure which shows the structural example of the semiconductor device which concerns on the 2nd Embodiment of this invention. 本発明の第３の実施の形態に係る半導体装置の構成例を示す図である。It is a figure which shows the structural example of the semiconductor device which concerns on the 3rd Embodiment of this invention. 本発明の第４の実施の形態に係る半導体装置の構成例を示す図である。It is a figure which shows the structural example of the semiconductor device which concerns on the 4th Embodiment of this invention. 本発明の第５の実施の形態に係る半導体装置の構成例を示す図である。It is a figure which shows the structural example of the semiconductor device which concerns on the 5th Embodiment of this invention. 従来の半導体装置の構成例を示す図である。It is a figure which shows the structural example of the conventional semiconductor device. 従来の半導体装置の構成例を示す図である。It is a figure which shows the structural example of the conventional semiconductor device. 従来の半導体装置の構成例を示す図である。It is a figure which shows the structural example of the conventional semiconductor device. 従来の半導体装置の構成例を示す図である。It is a figure which shows the structural example of the conventional semiconductor device.

符号の説明Explanation of symbols

１０，２０，３０，４０，５０ 半導体装置
１１ 半導体ベアチップ
１１ａ 電極パッド
１１ｂ 光学半導体素子
１２，３１ 配線基板
１２ａ 開口部
１３ リード
１４ 突起電極
１５ 樹脂シート
２１ 封止樹脂
４１ 透明樹脂シート 10, 20, 30, 40, 50 Semiconductor device 11 Semiconductor bare chip 11a Electrode pad 11b Optical semiconductor element 12, 31 Wiring board 12a Opening part 13 Lead 14 Protruding electrode 15 Resin sheet 21 Sealing resin 41 Transparent resin sheet

Claims (4)

配線基板と、
前記配線基板上に形成されたリードと、
前記リードに電気的に接続された突起電極と半導体素子とを有する半導体チップと、
前記半導体チップと、前記リードとを一括して被覆する樹脂シートと、を備え、
前記半導体チップの前記半導体素子は、前記突起電極が形成された面とは反対側の面に形成され、
前記半導体チップは、前記半導体チップの前記半導体素子が形成された面に設けられた電極パッドを更に備え、
前記電極パッドと前記突起電極とが、前記半導体チップを貫通する導電部材を介して、電気的に接続され、
前記半導体チップの前記半導体素子は、受光部又は発光部を有する光学半導体素子であり、
前記樹脂シートは透光性を備えることを特徴とする半導体装置。 A wiring board;
A lead formed on the wiring board;
A semiconductor chip having a protruding electrode and a semiconductor element electrically connected to the lead;
A resin sheet that collectively covers the semiconductor chip and the leads ;
The semiconductor element of the semiconductor chip is formed on a surface opposite to the surface on which the protruding electrode is formed,
The semiconductor chip further includes an electrode pad provided on a surface of the semiconductor chip where the semiconductor element is formed,
The electrode pad and the protruding electrode are electrically connected via a conductive member penetrating the semiconductor chip,
The semiconductor element of the semiconductor chip is an optical semiconductor element having a light receiving part or a light emitting part,
The resin sheet wherein a Rukoto with translucency. 前記半導体チップと前記配線基板との間に、少なくとも前記リードと前記突起電極とを覆うように封止樹脂が形成されていることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein a sealing resin is formed between the semiconductor chip and the wiring board so as to cover at least the lead and the protruding electrode. 前記配線基板は、フレキシブル基板からなることを特徴とする請求項１又は２に記載の半導体装置。The semiconductor device according to claim 1, wherein the wiring substrate is a flexible substrate. 前記樹脂シートは、前記半導体チップと対向する面に接着層を備え、該接着層によって前記半導体チップと、リードとを覆うように前記半導体チップに貼り付けられることを特徴とする請求項１乃至３のいずれか１項に記載の半導体装置。The said resin sheet is provided with the contact bonding layer on the surface facing the said semiconductor chip, and is affixed on the said semiconductor chip so that the said semiconductor chip and a lead may be covered by this contact bonding layer. The semiconductor device according to any one of the above.
JP2005168773A 2005-06-08 2005-06-08 Semiconductor device Expired - Fee Related JP4544044B2 (en)

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JPH09260433A (en) * 1996-03-22 1997-10-03 Nitto Denko Corp Manufacture of semiconductor device and semiconductor device provided thereby
JPH10125825A (en) * 1996-10-23 1998-05-15 Nec Corp Seal structure of chip device and method of sealing the same
JP2000260819A (en) * 1999-03-10 2000-09-22 Toshiba Corp Manufacture of semiconductor device
JP2001237277A (en) * 2000-02-24 2001-08-31 Matsushita Electric Ind Co Ltd Taped wiring board and method for assembling the same
JP2004537178A (en) * 2001-07-27 2004-12-09 エプコス　アクチエンゲゼルシャフト Method for hermetically sealing components
JP2005101250A (en) * 2003-09-25 2005-04-14 Seiko Epson Corp Semiconductor device and its manufacturing method, circuit board and electronic equipment

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