JP2008226876A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2008226876A
JP2008226876A JP2007058363A JP2007058363A JP2008226876A JP 2008226876 A JP2008226876 A JP 2008226876A JP 2007058363 A JP2007058363 A JP 2007058363A JP 2007058363 A JP2007058363 A JP 2007058363A JP 2008226876 A JP2008226876 A JP 2008226876A
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substrate
semiconductor device
resin
flip
mechanical switch
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Japanese (ja)
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Takashi Nakayama
高志 中山
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Olympus Corp
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Olympus Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device being capable of mounting a device such as a MEMS structure not allowing adhesion of a resin for connection and sealing to realize improvement in the fabrication yield and reduction in cost by realizing reduction in size and simplification of fabrication method even when a hollow structure is provided. <P>SOLUTION: The semiconductor device 8 is formed by mounting a first substrate 2 with a mechanical switch 6 of the MEMS structure on a second substrate 2 with circuits formed with a flip-chip mounting and sealing resin 1. In the structure thereof, a water repellent processing part 3 not sufficiently wettable with the flip-chip mounting and sealing resin is previously formed to a corresponding second substrate part facing the mechanical switch formed on the first substrate, and a hollow part 7 is formed within the sealed inside. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

この発明は、メカニカルスイッチなどのＭＥＭＳ構造物やイメージセンサなどのデバイスを設けた半導体基板と回路基板とを接続する際の実装に関し、特にフリップチップ実装を用いた半導体装置の封止構造に関する。   The present invention relates to mounting when connecting a semiconductor substrate provided with a MEMS structure such as a mechanical switch or a device such as an image sensor and a circuit board, and more particularly to a sealing structure of a semiconductor device using flip-chip mounting.

現在、半導体素子を回路基板に実装する際には小型化などの要求からフリップチップ実装することが多くなってきている。この実装形態がいかに小型化できるかによって、半導体装置全体の小型化も大きく左右される。このような状況において、例えば半導体素子を回路基板に実装した半導体装置の一例が特開２００２−１６１０４号公報に開示されている。   Currently, flip-chip mounting is increasingly used for mounting semiconductor elements on circuit boards due to demands for miniaturization and the like. The size reduction of the entire semiconductor device depends greatly on how the mounting form can be reduced. Under such circumstances, for example, an example of a semiconductor device in which a semiconductor element is mounted on a circuit board is disclosed in Japanese Patent Laid-Open No. 2002-16104.

上記公報開示の半導体装置の構成を図10の（Ａ）〜（Ｃ）に基づいて説明する。この半導体装置においては、図10の（Ａ）に示すように、回路基板20上に導電性粒子19が含有されている絶縁樹脂からなる絶縁層18が形成されている。このように、絶縁樹脂の中に導電性粒子を含有させた樹脂は一般的に異方導電性樹脂と称されている。この回路基板20に図10の（Ｂ）に示すように、半導体素子21を該半導体素子21に形成されたバンプ22を回路基板20の電極（図示せず）と位置合わせした後圧着させ、その状態で加熱させることで絶縁層18の樹脂が硬化され、接続及び封止が完了し、図10の（Ｃ）に示す半導体装置23が得られる。   The configuration of the semiconductor device disclosed in the above publication will be described with reference to FIGS. In this semiconductor device, as shown in FIG. 10A, an insulating layer 18 made of an insulating resin containing conductive particles 19 is formed on a circuit board 20. As described above, a resin in which conductive particles are contained in an insulating resin is generally called an anisotropic conductive resin. As shown in FIG. 10B, the bump 22 formed on the semiconductor element 21 is aligned with the electrode (not shown) of the circuit board 20 and then crimped to the circuit board 20, By heating in the state, the resin of the insulating layer 18 is cured, connection and sealing are completed, and the semiconductor device 23 shown in FIG. 10C is obtained.

この方式により構成される半導体装置においては、半導体素子21が絶縁層18と接触するので、メカニカルスイッチなどのＭＥＭＳ構造物もしくはイメージセンサーなど樹脂の付着が許されないデバイスが形成された半導体基板の実装には適用できない。このような状況において、例えばイメージセンサーを実装した固体撮像装置の一例が、特開２００６−５０２９号公報に開示されている。   In a semiconductor device configured by this method, since the semiconductor element 21 is in contact with the insulating layer 18, it is used for mounting a semiconductor substrate on which a device such as a mechanical structure such as a mechanical switch or an image sensor such as an image sensor is not allowed to adhere. Is not applicable. In such a situation, for example, an example of a solid-state imaging device in which an image sensor is mounted is disclosed in Japanese Patent Laid-Open No. 2006-5029.

上記公報開示の固体撮像装置の構成を図11に基づいて説明する。この固体撮像装置は、撮像素子24上に形成されたマイクロレンズ26にガラスＬＩＤ25を搭載した後、接着剤28で周囲を封止した構成となっている。このとき、撮像素子24上のマイクロレンズ26の外周部及びガラスＬＩＤ25の外周部には、それぞれ疎水性材料層27を形成しており、それにより接着剤28の内部31への進入を防止し、内部31が中空状態を保った固体撮像装置30が得られるようにしている。
特開２００２−１６１０４号公報 特開２００６−５０２９号公報 The configuration of the solid-state imaging device disclosed in the above publication will be described with reference to FIG. This solid-state imaging device has a configuration in which a glass LID 25 is mounted on a microlens 26 formed on an imaging element 24 and then the periphery is sealed with an adhesive 28. At this time, a hydrophobic material layer 27 is formed on each of the outer peripheral portion of the microlens 26 on the image sensor 24 and the outer peripheral portion of the glass LID 25, thereby preventing the adhesive 28 from entering the interior 31; A solid-state imaging device 30 in which the interior 31 is kept hollow is obtained.
JP 2002-16104 A JP 2006-5029 A

ところで、図11に示した構成の固体撮像装置においては、ガラスＬＩＤ25の外周に精度よく接着剤28を塗布するには工程が複雑になり、且つ良好な封止性を確保するためにはある程度の接着剤厚み29が必要となり、撮像素子24の形状に制約が出てくると共に固体撮像装置30としてもサイズが大きくなってしまう。また、撮像素子24上のマイクロレンズ26の外周部及びガラスＬＩＤ25の外周部それぞれに疎水性材料層27の形成が必要であり、工程が複雑且つ大変になってしまい、部材の歩留まり低下の恐れもある。   By the way, in the solid-state imaging device having the configuration shown in FIG. 11, the process is complicated to apply the adhesive 28 on the outer periphery of the glass LID 25 with high accuracy, and in order to ensure a good sealing property, a certain amount is required. The adhesive thickness 29 is required, and the shape of the image pickup element 24 is restricted, and the size of the solid-state image pickup device 30 is increased. In addition, it is necessary to form the hydrophobic material layer 27 on each of the outer peripheral portion of the microlens 26 on the image pickup device 24 and the outer peripheral portion of the glass LID 25, and the process becomes complicated and difficult, and the yield of the member may be reduced. is there.

本発明は、上記課題を解消するためになされたもので、中空構造をもちながら小型化と共に製法を簡略化し、歩留まりの向上及びコストダウンを達成できるＭＥＭＳ構造物などの接続封止用樹脂の付着が許されないデバイスの実装が可能な半導体装置を提供することを目的とする。   The present invention has been made to solve the above-mentioned problems, and it is possible to reduce the size and simplify the manufacturing method while having a hollow structure, and to attach a connection sealing resin such as a MEMS structure that can achieve a yield improvement and a cost reduction. An object of the present invention is to provide a semiconductor device capable of mounting a device that does not allow the above.

上記課題を解決するため請求項１に係る発明は、ＭＥＭＳ構造物などのデバイスを形成した第１の基板を回路が形成された第２の基板に絶縁樹脂もしくは異方導電性樹脂を用いてフリップチップ実装してなる半導体装置において、少なくとも前記第１の基板のデバイスと向かい合わせになる前記第２の基板の対応部分にあらかじめ前記樹脂とは濡れ性の悪い樹脂にてコート処理を施したことを特徴とするものである。   In order to solve the above-mentioned problem, the invention according to claim 1 flips a first substrate on which a device such as a MEMS structure is formed using an insulating resin or an anisotropic conductive resin to a second substrate on which a circuit is formed. In a semiconductor device that is mounted in a chip, at least a corresponding portion of the second substrate that faces the device of the first substrate is previously coated with a resin having poor wettability with the resin. It is a feature.

請求項２に係る発明は、請求項１に係る半導体装置において、前記第２の基板のコート処理を施す部分に、略凸部が設けられていることを特徴とするものである。   According to a second aspect of the present invention, in the semiconductor device according to the first aspect, a substantially convex portion is provided in a portion of the second substrate to be coated.

請求項３に係る発明は、請求項１に係る半導体装置において、前記第２の基板に施すコート処理が、前記第１の基板と接続する部分以外に設けられていることを特徴とするものである。   According to a third aspect of the present invention, in the semiconductor device according to the first aspect, a coating process applied to the second substrate is provided in a portion other than a portion connected to the first substrate. is there.

請求項４に係る発明は、ＭＥＭＳ構造物などのデバイスを形成した第１の基板を、ＬＩＤなどの保護部材に絶縁樹脂もしくは異方導電性樹脂を用いてフリップチップ実装してなる半導体装置において、少なくとも前記第１の基板のデバイスと向かい合わせになる前記保護部材の対応部分にあらかじめ前記樹脂とは濡れ性の悪い樹脂でコート処理を施したことを特徴とするものである。   The invention according to claim 4 is a semiconductor device in which a first substrate on which a device such as a MEMS structure is formed is flip-chip mounted on a protective member such as LID using an insulating resin or an anisotropic conductive resin. At least the corresponding portion of the protective member facing the device on the first substrate is previously coated with a resin having poor wettability with the resin.

請求項５に係る発明は、請求項４に係る半導体装置において、前記保護部材のコート処理を施す部分に、略凸部が設けられていることを特徴とするものである。   According to a fifth aspect of the present invention, in the semiconductor device according to the fourth aspect, a substantially convex portion is provided in a portion where the coating process of the protective member is performed.

請求項６に係る発明は、請求項４に係る半導体装置において、前記保護部材を施すコート処理が、前記第１の基板と接続する部分以外に設けられていることを特徴とするものである。   According to a sixth aspect of the present invention, in the semiconductor device according to the fourth aspect, the coating treatment for applying the protective member is provided in a portion other than the portion connected to the first substrate.

本発明によれば、ＮＣＰ接続による中空部をもった半導体装置の形成が可能となり、また製造方法の簡略化が図られ、歩留まりの向上及びコストダウンを達成できると共に、半導体装置の小型化を実現できる。請求項毎の効果を述べると、請求項１に係る発明によれば、ＭＥＭＳ構造物などのデバイスの中空実装が可能となり、製法の簡略化が図られるため、歩留まりの向上及びコストダウンが期待できる。請求項２に係る発明によれば、接続封止に用いる樹脂を疎外する効果がより向上し、ＭＥＭＳ構造物などのデバイスの中空実装がより確実に可能となり、歩留まりの向上及びコストダウンが期待できる。請求項３に係る発明によれば、接続封止に用いる樹脂は確実に第１の基板と接続する部分にのみ存在するので、接続の信頼性が向上すると共に、ＭＥＭＳ構造物などのデバイスの中空実装が可能となる。また、歩留まりの向上及びコストダウンが期待できる。請求項４に係る発明によれば、デバイスを形成した第１の基板を他の部材と電気的接続をとらない構成とする場合であっても、ＭＥＭＳ構造物などのデバイスの中空実装が可能となり、また歩留まりの向上及びコストダウンが期待できる。請求項５に係る発明によれば、接続封止に用いる樹脂を疎外する効果がより向上し、ＭＥＭＳ構造物などのデバイスの中空実装がより確実に可能となる。また、歩留まりの向上及びコストダウンが期待できる。請求項６に係る発明によれば、接続封止に用いる樹脂は確実に第１の基板と接続する部分にのみ存在するので、接続の信頼性が向上すると共に、ＭＥＭＳ構造物などのデバイスの中空実装が可能となる。また、歩留まりの向上及びコストダウンが期待できる。   According to the present invention, it is possible to form a semiconductor device having a hollow portion by NCP connection, simplify the manufacturing method, achieve improvement in yield and cost, and realize miniaturization of the semiconductor device. it can. To describe the effect of each claim, according to the invention according to claim 1, it is possible to hollow-mount a device such as a MEMS structure and simplify the manufacturing method, so that an improvement in yield and a reduction in cost can be expected. . According to the invention of claim 2, the effect of alienating the resin used for connection sealing is further improved, and hollow mounting of a device such as a MEMS structure can be performed more reliably, and improvement in yield and cost reduction can be expected. . According to the invention of claim 3, since the resin used for the connection sealing is present only in the portion that is surely connected to the first substrate, the reliability of the connection is improved and the hollow of a device such as a MEMS structure is provided. Implementation is possible. Moreover, improvement in yield and cost reduction can be expected. According to the invention of claim 4, even when the first substrate on which the device is formed is configured not to be electrically connected to other members, it is possible to hollowly mount a device such as a MEMS structure. In addition, improvement in yield and cost reduction can be expected. According to the invention which concerns on Claim 5, the effect which alienates resin used for connection sealing improves more, and the hollow mounting of devices, such as a MEMS structure, becomes possible more reliably. Moreover, improvement in yield and cost reduction can be expected. According to the invention of claim 6, since the resin used for connection sealing is present only in the portion that is surely connected to the first substrate, the connection reliability is improved and the hollow of a device such as a MEMS structure is provided. Implementation is possible. Moreover, improvement in yield and cost reduction can be expected.

次に、発明を実施するための最良の形態について説明する。   Next, the best mode for carrying out the invention will be described.

（実施例１）
まず、本発明に係る半導体装置の実施例１について図面を参照しながら説明する。図１の（Ａ）〜（Ｃ）は、実施例１に係る半導体装置の製造工程を示す図である。。本実施例に係る半導体装置は、回路が形成された第２の基板とＭＥＭＳ構造によるメカニカルスイッチが形成された第１の基板（半導体基板）との接続及び封止用として絶縁樹脂を用い、第１の基板のバンプと回路基板の電極とを熱圧着によるフリップチップにて電気的に接続をとるものであり、一般的にＮＣＰ（ Non Conductive Paste ）接続と呼ばれる形態のものである。 (Example 1)
First, a first embodiment of a semiconductor device according to the present invention will be described with reference to the drawings. FIGS. 1A to 1C are diagrams illustrating manufacturing steps of the semiconductor device according to the first embodiment. . The semiconductor device according to this example uses an insulating resin for connection and sealing between the second substrate on which the circuit is formed and the first substrate (semiconductor substrate) on which the mechanical switch having the MEMS structure is formed. A bump on one substrate and an electrode on a circuit board are electrically connected by a flip chip by thermocompression bonding, and is of a form generally called NCP (Non Conductive Paste) connection.

まず、図１の（Ａ）に示すように、回路が形成された第２の基板２は、次に述べる第１の基板４に形成されたメカニカルスイッチ６と向かい合う部分に、フリップチップ実装封止用樹脂１とは濡れ性の悪い樹脂がコートされている。便宜上、今後この処理部のことを撥水処理部３という。撥水処理部３を設けた第２の基板２の上からフリップチップ実装封止用樹脂１を滴下すると、第２の基板２の撥水処理部３が施された部分以外にフリップチップ実装封止用樹脂１が移動する。例えば、フリップチップ実装封止用樹脂１にエポキシ系樹脂を用いる場合には、フッ素系樹脂を撥水処理部３として施せば上記効果が得られる。   First, as shown in FIG. 1A, a second substrate 2 on which a circuit is formed is flip-chip mounted and sealed in a portion facing a mechanical switch 6 formed on the first substrate 4 described below. The resin 1 is coated with a resin having poor wettability. For convenience, this processing unit will be referred to as the water repellent processing unit 3 in the future. When the flip-chip mounting sealing resin 1 is dropped from above the second substrate 2 provided with the water-repellent treatment portion 3, the flip-chip mounting seal is formed on the second substrate 2 other than the portion provided with the water-repellent treatment portion 3. The stopping resin 1 moves. For example, when an epoxy resin is used for the flip chip mounting sealing resin 1, the above effect can be obtained by applying a fluorine resin as the water repellent treatment portion 3.

次に、図１の（Ｂ）に示すように、第１の基板４に例えばＡu 線によるスタッドバンプ法などで形成されたバンプ５を、第２の基板２の電極（図示せず）に位置合わせしたのち、第１の基板４と第２の基板２とを加圧・加熱することで、図１の（Ｃ）に示すようにフリップチップ実装封止用樹脂１が硬化し、接続及び封止が完了した半導体装置８が得られる。このようにして作成された半導体装置においては、メカニカルスイッチ６の周囲には中空部７が形成され、本来のスイッチとしての機能を確保することができる。   Next, as shown in FIG. 1B, bumps 5 formed on the first substrate 4 by, for example, a stud bump method using Au wires are positioned on electrodes (not shown) of the second substrate 2. After the alignment, the first substrate 4 and the second substrate 2 are pressurized and heated to cure the flip chip mounting sealing resin 1 as shown in FIG. The semiconductor device 8 that has been stopped is obtained. In the semiconductor device thus produced, the hollow portion 7 is formed around the mechanical switch 6, and the function as the original switch can be ensured.

ここで、第２の基板２としては、ガラス繊維強化エポキシ樹脂やポリイミド樹脂などの有機材料からなる基板もしくはセラミックなどの無機材料からなる基板等その種類は問わない。また、第１の基板に形成されるものとしては、メカニカルスイッチに限らず、他のＭＥＭＳ構造物やイメージセンサーなどのデバイスでもよい。   Here, the second substrate 2 may be of any kind, such as a substrate made of an organic material such as glass fiber reinforced epoxy resin or polyimide resin, or a substrate made of an inorganic material such as ceramic. Moreover, what is formed on the first substrate is not limited to a mechanical switch, and may be another MEMS structure or a device such as an image sensor.

また、第１の基板と第２の基板とを接続・封止するフリップチップ実装封止用樹脂として絶縁性樹脂を用いたものを示したが、異方導電性樹脂を用いてもかまわない。更には、熱硬化樹脂やＵＶ硬化樹脂を用いても、本実施例による効果が得られる。また、撥水処理部３はフッ素系樹脂を用いて形成したものを示したが、これに限られるものではなく、フリップチップ実装封止用樹脂の性質に合わせて濡れ性の悪いものを選択して形成すればよい。   Further, although an insulating resin is used as the flip chip mounting sealing resin for connecting and sealing the first substrate and the second substrate, anisotropic conductive resin may be used. Furthermore, the effect of this embodiment can be obtained even when a thermosetting resin or a UV curable resin is used. In addition, the water-repellent treatment portion 3 is formed using a fluorine-based resin. However, the water-repellent treatment portion 3 is not limited to this, and a water-repellent treatment portion 3 having poor wettability is selected according to the properties of the flip-chip mounting sealing resin. May be formed.

図２は、実施例１に係る半導体装置の水平断面を模式的に示す図であり、第２の基板２内で中空部７が設けられており、撥水処理部３を施すことで中空部７が確保できていることを示している。。   FIG. 2 is a diagram schematically illustrating a horizontal cross section of the semiconductor device according to the first embodiment. A hollow portion 7 is provided in the second substrate 2, and a hollow portion is formed by applying the water repellent treatment portion 3. 7 indicates that it has been secured. .

図３は、実施例１に係る半導体装置の変形例の水平断面を模式的に示す図である。この変形例では，第２の基板２内で中空部７が複数設けられている。第２の基板２の任意の部分に撥水処理部３を施すことで中空部７が確保できるため、中空部７の形状は矩形にとどまらず、種々の形状のものへの対応が可能である。   FIG. 3 is a schematic diagram illustrating a horizontal cross section of a modification of the semiconductor device according to the first embodiment. In this modification, a plurality of hollow portions 7 are provided in the second substrate 2. Since the hollow portion 7 can be secured by applying the water-repellent treatment portion 3 to an arbitrary portion of the second substrate 2, the shape of the hollow portion 7 is not limited to a rectangle, and can correspond to various shapes. .

図４は、実施例１に係る半導体装置の更なる変形例を示す垂直断面図である。この変形例は、第１の基板４のメカニカルスイッチ６が形成された周辺にも撥水処理部９を施したもので、これにより中空部７の形成がより確実に行えるという効果が得られる。   FIG. 4 is a vertical sectional view showing a further modification of the semiconductor device according to the first embodiment. In this modified example, the water-repellent treatment part 9 is also provided on the periphery of the first substrate 4 where the mechanical switch 6 is formed, thereby obtaining the effect that the hollow part 7 can be formed more reliably.

以上のように、実施例１及びその変形例に係る半導体装置によれば、回路が形成された第２の基板の中空部を作りたい部分に撥水処理部を施すことにより、ＭＥＭＳ構造物のデバイスなどを用いても通常のＮＣＰ接続が確実に行われると共に、従来のように積極的に接着厚みを確保するスペースを設ける必要がないため、半導体装置の小型化も可能となる。また、回路が形成された基板側だけに撥水処理部を施せばよいので、製造方法が簡単となり、作業の簡略化が図られ、歩留まりの向上、コストダウンが実現できる。   As described above, according to the semiconductor device according to the first embodiment and the modification thereof, the water repellent treatment portion is applied to the portion where the hollow portion of the second substrate on which the circuit is formed is to be formed. Even if a device or the like is used, normal NCP connection is reliably performed, and it is not necessary to provide a space for positively securing the adhesive thickness as in the conventional case, so that the semiconductor device can be miniaturized. Further, since the water-repellent treatment portion only needs to be provided on the substrate side on which the circuit is formed, the manufacturing method is simplified, the operation is simplified, and the yield can be improved and the cost can be reduced.

（実施例２）
次に、図５に基づいて実施例２に係る半導体装置の構成について説明する。本実施例は、回路が形成された第２の基板のＭＥＭＳ構造物と向かい合う部分に略凸部を形成した構成のものである。すなわち、回路が形成された第２の基板２には、第１の基板４に形成されたメカニカルスイッチ６と向かい合う部分に、略凸部10を形成し、その略凸部10上に撥水処理部３が施されている。そして、第２の基板２上からフリップチップ実装封止用樹脂１を滴下すると、第２の基板２の撥水処理部３が施された部分以外にフリップチップ実装封止用樹脂１が移動する作用が更に効果的に働く。この際、例えば、フリップチップ実装封止用樹脂１としてエポキシ系樹脂を用いる場合には、フッ素系樹脂を用いて撥水処理部３を施せば、上記効果が得られる。 (Example 2)
Next, the configuration of the semiconductor device according to the second embodiment will be described with reference to FIG. In this embodiment, a substantially convex portion is formed in a portion of the second substrate on which the circuit is formed, facing the MEMS structure. That is, on the second substrate 2 on which the circuit is formed, a substantially convex portion 10 is formed in a portion facing the mechanical switch 6 formed on the first substrate 4, and a water repellent treatment is performed on the substantially convex portion 10. Part 3 is applied. When the flip chip mounting sealing resin 1 is dropped from the second substrate 2, the flip chip mounting sealing resin 1 moves to a portion other than the portion of the second substrate 2 where the water repellent treatment portion 3 is applied. The action works more effectively. At this time, for example, when an epoxy resin is used as the flip chip mounting sealing resin 1, the above-described effect can be obtained by applying the water repellent treatment portion 3 using a fluorine resin.

次に、メカニカルスイッチ６を形成した第１の基板４に例えばＡu 線によるスタッドバンプ法などで形成されたバンプ５を、第２の基板２の電極（図示せず）に位置合わせしたのち、第１の基板４と第２の基板２とを加圧・加熱することでフリップチップ実装封止用樹脂１が硬化し、接続及び封止が完了した半導体装置８が得られる。このように構成した半導体装置においては、メカニカルスイッチ６の周囲は中空部７となり、メカニカルスイッチ６は本来のスイッチとしての機能を確保することができる。   Next, after aligning the bump 5 formed on the first substrate 4 on which the mechanical switch 6 is formed by the stud bump method using Au wire or the like with the electrode (not shown) of the second substrate 2, By pressing and heating the first substrate 4 and the second substrate 2, the flip-chip mounting sealing resin 1 is cured, and the semiconductor device 8 in which the connection and sealing are completed is obtained. In the semiconductor device configured as described above, the periphery of the mechanical switch 6 becomes the hollow portion 7, and the mechanical switch 6 can ensure the function as an original switch.

図６は、実施例２に係る半導体装置の第２の基板への略凸部10の形成方法の一例を示す図である。この例は、第２の基板２に回路を形成する際に、メカニカルスイッチ６と向かい合う部分の中央部に、どの回路パターンとも導通していないダミーパターン11を、例えばランド形状に同時に形成する。その上に撥水処理部３を施せば、ダミーパターン11の段差形状にならって撥水処理部３を施した部分は略凸部10となる。   FIG. 6 is a diagram illustrating an example of a method of forming the substantially convex portion 10 on the second substrate of the semiconductor device according to the second embodiment. In this example, when a circuit is formed on the second substrate 2, a dummy pattern 11 that is not electrically connected to any circuit pattern is simultaneously formed in a land shape, for example, at the center of a portion facing the mechanical switch 6. If the water-repellent treatment portion 3 is applied thereon, the portion where the water-repellent treatment portion 3 is applied in accordance with the step shape of the dummy pattern 11 becomes a substantially convex portion 10.

図７に、実施例２に係る半導体装置の更なる第２の基板への略凸部10の形成方法を示す。この例は、第２の基板２に回路を形成する際に、メカニカルスイッチ６と向かい合う部分の中央部に、例えばソルダーレジスト12がそのサイズを変えて数段塗り重ねられている。その上に撥水処理部３を施せば、ソルダーレジスト12の段差形状にならって撥水処理部３を施した部分は略凸部10となる。ここで、ソルダーレジスト12の代わりにカバーレイを用いてもかまわない。また、数段塗り重ねなくても、徐々に厚みが変わる形成方法であれば、それを採用することは全く問題ない。   FIG. 7 shows a method of forming the substantially convex portion 10 on the second substrate of the semiconductor device according to the second embodiment. In this example, when a circuit is formed on the second substrate 2, for example, a solder resist 12 is applied in several stages with different sizes at the center of the portion facing the mechanical switch 6. If the water-repellent treatment portion 3 is applied thereon, the portion where the water-repellent treatment portion 3 is applied in accordance with the stepped shape of the solder resist 12 becomes a substantially convex portion 10. Here, a coverlay may be used instead of the solder resist 12. Moreover, even if it is a formation method in which thickness changes gradually even if it does not repeat several steps of coating, there is no problem in adopting it.

以上のような構成により、本実施例２に係る半導体装置は実施例１にて得られる効果のほかに、第２の基板に形成した略凸部により絶縁性樹脂の移動がより確実に可能となるという効果が得られる。   With the configuration as described above, in addition to the effects obtained in the first embodiment, the semiconductor device according to the second embodiment can more reliably move the insulating resin by the substantially convex portion formed on the second substrate. The effect of becoming is obtained.

（実施例３）
次に、図８の（Ａ）〜（Ｃ）に基づいて実施例３に係る半導体装置の構成について説明する。本実施例は、回路が形成された第２の基板のバンプ接続部周辺にも撥水処理部を施したものである。すなわち、図８の（Ａ）に示すように、まず、回路が形成された第２の基板２は、第１の基板４に形成されたメカニカルスイッチ６と向かい合う部分に、撥水処理３が施されている。このとき、第２の基板２には、第１の基板４に形成されたバンプ５と接続される電極部（図示せず）外側にも撥水処理部３ａが施されている。このように撥水処理３，３ａが形成された第２の基板２の上からフリップチップ実装封止用樹脂１を滴下すると、第２の基板２の撥水処理部３，３ａが施された部分以外にフリップチップ実装封止用樹脂１が移動する。すなわち、フリップチップ実装封止用樹脂１は第１の基板４と接続される部分にのみ存在することとなる。 (Example 3)
Next, the configuration of the semiconductor device according to the third embodiment will be described with reference to FIGS. In this embodiment, a water repellent portion is also provided around the bump connection portion of the second substrate on which the circuit is formed. That is, as shown in FIG. 8A, first, the second substrate 2 on which the circuit is formed is subjected to the water repellent treatment 3 on the portion facing the mechanical switch 6 formed on the first substrate 4. Has been. At this time, the water repellent treatment portion 3 a is also applied to the second substrate 2 outside the electrode portion (not shown) connected to the bumps 5 formed on the first substrate 4. When the flip chip mounting sealing resin 1 is dropped from above the second substrate 2 on which the water repellent treatments 3 and 3a are formed in this manner, the water repellent treatment portions 3 and 3a of the second substrate 2 are performed. The flip chip mounting sealing resin 1 moves to other than the portion. That is, the flip-chip mounting sealing resin 1 exists only in the portion connected to the first substrate 4.

次に、図８の（Ｂ）に示すように、第１の基板４に例えばＡu 線によるスタッドバンプ法などで形成されたバンプ５を、第２の基板２の電極（図示せず）に位置合わせしたのち加圧・加熱することでフリップチップ実装封止用樹脂１が硬化し、図８の（Ｃ）に示すように、接続及び封止が完了した半導体装置８が得られる。このように構成することにより、メカニカルスイッチ６の周囲は中空部７となり、メカニカルスイッチ６は本来のスイッチとしての機能を確保することができる。   Next, as shown in FIG. 8B, bumps 5 formed on the first substrate 4 by, for example, a stud bump method using Au wires are positioned on the electrodes (not shown) of the second substrate 2. After being combined, pressurization and heating are performed to cure the flip-chip mounting sealing resin 1, and as shown in FIG. 8C, a semiconductor device 8 in which connection and sealing are completed is obtained. By comprising in this way, the circumference | surroundings of the mechanical switch 6 become the hollow part 7, and the mechanical switch 6 can ensure the function as an original switch.

以上のような構成により、本実施例３に係る半導体装置は実施例１に係る半導体装置による効果のほかに、フリップチップ実装封止用樹脂がバンプ接続部にのみ存在することとなり、フリップチップ実装封止用樹脂量のコントロールが容易になると同時に、基板の外側への流れ出しも考慮しないでよいため、より少量の封止用樹脂で接続及び封止が可能になるという効果が得られる。   With the configuration as described above, the semiconductor device according to the third embodiment has the flip chip mounting sealing resin only in the bump connection portion in addition to the effects of the semiconductor device according to the first embodiment. Control of the amount of sealing resin is facilitated, and at the same time, there is no need to consider the flow to the outside of the substrate, so that an effect of enabling connection and sealing with a smaller amount of sealing resin is obtained.

（実施例４）
次に、図９に基づいて実施例４に係る半導体装置の構成について説明する。本実施例は、貫通配線を施しＭＥＭＳ構造物を形成した第１の基板を実装する構成に関するものである。そして、この実施例では、回路が形成された第２の基板の代わりにＭＥＭＳ構造物であるメカニカルスイッチの保護部材として、ＬＩＤを用いＮＣＰ装着している。すなわち、第１の基板４には、一方の面にメカニカルスイッチ６及びスペーサ13が、他方の面に貫通配線14を介して外部電極15が形成されている。そして、第１の基板４は、スペーサ13を介してＬＩＤ16と接着され、中空部７を有する半導体装置17が構成されている。なお、ＬＩＤ16には、実施例１の第２の基板２と同様にメカニカルスイッチ６に向き合う位置に撥水処理部３を施してあるが、第１の基板４との導通をとるための電極などは存在しない。このように構成された半導体装置17は、別個の回路基板（図示せず）と外部電極15を介して電気的に接続して用いられる。ここで、スペーサ13及びＬＩＤ16の材質は、有機・無機のいずれの材料でもかまわない。 Example 4
Next, the configuration of the semiconductor device according to the fourth embodiment will be described with reference to FIG. The present embodiment relates to a configuration for mounting a first substrate on which a through wiring is formed to form a MEMS structure. In this embodiment, instead of the second substrate on which the circuit is formed, NCP is attached using a LID as a protective member of a mechanical switch which is a MEMS structure. That is, on the first substrate 4, the mechanical switch 6 and the spacer 13 are formed on one surface, and the external electrode 15 is formed on the other surface through the through wiring 14. The first substrate 4 is bonded to the LID 16 through the spacer 13 to constitute a semiconductor device 17 having the hollow portion 7. The LID 16 is provided with a water repellent treatment portion 3 at a position facing the mechanical switch 6 in the same manner as the second substrate 2 of the first embodiment, but an electrode for conducting the first substrate 4 and the like. Does not exist. The semiconductor device 17 configured as described above is used by being electrically connected to a separate circuit board (not shown) via the external electrode 15. Here, the material of the spacer 13 and the LID 16 may be either organic or inorganic.

以上のような構成により、本実施例４の半導体装置は、実施例１に係る半導体装置とは異なり、回路が形成された第２の基板と第１の基板を電気的に接続する構成が必須ではなく、単なる中空部を必要とする気密封止構成にも応用が可能であるという効果が得られる。なお、本実施例に、上記実施例２及び実施例３の構成を組み合わせた際にも、個々の実施例の効果と同様もしくはそれ以上の相乗の効果が得られることは言うまでもない。   With the configuration as described above, unlike the semiconductor device according to the first embodiment, the semiconductor device according to the fourth embodiment must have a configuration in which the second substrate on which the circuit is formed and the first substrate are electrically connected. Instead, an effect is obtained that the present invention can be applied to a hermetic sealing configuration requiring a simple hollow portion. Needless to say, when this embodiment is combined with the configurations of the above embodiments 2 and 3, synergistic effects similar to or higher than those of the individual embodiments can be obtained.

本発明に係る半導体装置の実施例１の構成を説明するための製造工程図である。It is a manufacturing process figure for demonstrating the structure of Example 1 of the semiconductor device which concerns on this invention. 図１に示した実施例１に係る半導体装置の水平断面を示す図である。FIG. 2 is a diagram illustrating a horizontal cross section of the semiconductor device according to the first embodiment illustrated in FIG. 1. 実施例１の変形例の水平断面を示す模式図である。6 is a schematic diagram showing a horizontal cross section of a modified example of Example 1. FIG. 実施例１の他の変形例を示す垂直断面図である。FIG. 6 is a vertical sectional view showing another modification of the first embodiment. 実施例２に係る半導体装置の構成を示す垂直断面図である。6 is a vertical cross-sectional view showing a configuration of a semiconductor device according to Example 2. FIG. 図５に示した実施例２に係る半導体装置の略凸部の構成を示す拡大図である。FIG. 6 is an enlarged view illustrating a configuration of a substantially convex portion of the semiconductor device according to the second embodiment illustrated in FIG. 5. 実施例２に係る半導体装置の略凸部の他の構成を示す拡大図である。6 is an enlarged view showing another configuration of the substantially convex portion of the semiconductor device according to Example 2. FIG. 実施例３に係る半導体装置の構成を説明するための製造工程図である。FIG. 10 is a manufacturing process diagram for describing a configuration of a semiconductor device according to Example 3; 実施例４に係る半導体装置の構成を示す垂直断面図である。FIG. 10 is a vertical sectional view showing the configuration of a semiconductor device according to Example 4. 従来の半導体装置の構成例を説明するための製造工程図である。It is a manufacturing process figure for demonstrating the structural example of the conventional semiconductor device. 従来の固体撮像装置の構成例を示す垂直断面図である。It is a vertical sectional view showing a configuration example of a conventional solid-state imaging device.

符号の説明Explanation of symbols

１ フリップチップ実装封止用樹脂
２ 第２の基板
３，３ａ 撥水処理部
４ 第１の基板
５ バンプ
６ メカニカルスイッチ
７ 中空部
８ 半導体装置
９ 撥水処理部
10 略凸部
11 ダミーパターン
12 ソルダーレジスト
13 スペーサ
14 貫通配線
15 外部電極
16 ＬＩＤ
17 半導体装置 DESCRIPTION OF SYMBOLS 1 Flip chip mounting sealing resin 2 2nd board | substrate 3, 3a Water repellent treatment part 4 1st board | substrate 5 Bump 6 Mechanical switch 7 Hollow part 8 Semiconductor device 9 Water repellent treatment part
10 substantially convex
11 Dummy pattern
12 Solder resist
13 Spacer
14 Through wiring
15 External electrode
16 LID
17 Semiconductor devices

Claims (6)

ＭＥＭＳ構造物などのデバイスを形成した第１の基板を、回路が形成された第２の基板に絶縁樹脂もしくは異方導電性樹脂を用いてフリップチップ実装してなる半導体装置において、少なくとも前記第１の基板のデバイスと向かい合わせになる前記第２の基板の対応部分にあらかじめ前記樹脂とは濡れ性の悪い樹脂でコート処理を施したことを特徴とする半導体装置。   In a semiconductor device in which a first substrate on which a device such as a MEMS structure is formed is flip-chip mounted on a second substrate on which a circuit is formed using an insulating resin or an anisotropic conductive resin, at least the first substrate A semiconductor device, wherein the corresponding portion of the second substrate facing the device of the substrate is previously coated with a resin having poor wettability with the resin. 前記第２の基板のコート処理を施す部分に、略凸部が設けられていることを特徴とする請求項１に係る半導体装置。   2. The semiconductor device according to claim 1, wherein a substantially convex portion is provided in a portion of the second substrate to be coated. 前記第２の基板に施すコート処理が、前記第１の基板と接続する部分以外に施されていることを特徴とする請求項１に係る半導体装置。   The semiconductor device according to claim 1, wherein a coating process applied to the second substrate is performed on a portion other than a portion connected to the first substrate. ＭＥＭＳ構造物などのデバイスを形成した第１の基板を、ＬＩＤなどの保護部材に絶縁樹脂もしくは異方導電性樹脂を用いてフリップチップ実装してなる半導体装置において、少なくとも前記第１の基板のデバイスと向かい合わせになる前記保護部材の対応部分にあらかじめ前記樹脂とは濡れ性の悪い樹脂でコート処理を施したことを特徴とする半導体装置。   In a semiconductor device in which a first substrate on which a device such as a MEMS structure is formed is flip-chip mounted on a protective member such as an LID using an insulating resin or an anisotropic conductive resin, at least the device of the first substrate A semiconductor device characterized in that a coating process is performed in advance on a corresponding portion of the protective member facing the substrate with a resin having poor wettability with the resin. 前記保護部材のコート処理を施す部分に、略凸部が設けられていることを特徴とする請求項４に係る半導体装置。   The semiconductor device according to claim 4, wherein a substantially convex portion is provided in a portion of the protective member to be coated. 前記保護部材に施すコート処理が、前記第１の基板と接続する部分以外に施されていることを特徴とする請求項４に係る半導体装置。   5. The semiconductor device according to claim 4, wherein a coating process applied to the protective member is applied to a portion other than a portion connected to the first substrate.
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Cited By (8)

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JP2009184067A (en) * 2008-02-06 2009-08-20 Mitsubishi Electric Corp Device with hollow structure and method of manufacturing the same
JP2010089209A (en) * 2008-10-08 2010-04-22 Fujitsu Ltd Micro movable element and optical switching device
JP2010089233A (en) * 2008-10-10 2010-04-22 Fujitsu Ltd Micro movable element and optical switching device
JP2010177470A (en) * 2009-01-29 2010-08-12 Toshiba Corp Electronic apparatus and circuit board
JP2010198991A (en) * 2009-02-26 2010-09-09 Oki Semiconductor Co Ltd Electrostatically driven mems element and method of manufacturing the same
JP2012182362A (en) * 2011-03-02 2012-09-20 Dainippon Printing Co Ltd Electronic component and manufacturing method of the same
JP2012182361A (en) * 2011-03-02 2012-09-20 Dainippon Printing Co Ltd Electronic component and manufacturing method of the same
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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009184067A (en) * 2008-02-06 2009-08-20 Mitsubishi Electric Corp Device with hollow structure and method of manufacturing the same
JP2010089209A (en) * 2008-10-08 2010-04-22 Fujitsu Ltd Micro movable element and optical switching device
JP2010089233A (en) * 2008-10-10 2010-04-22 Fujitsu Ltd Micro movable element and optical switching device
JP2010177470A (en) * 2009-01-29 2010-08-12 Toshiba Corp Electronic apparatus and circuit board
JP4621778B2 (en) * 2009-01-29 2011-01-26 株式会社東芝 Electronic equipment and circuit board
JP2010198991A (en) * 2009-02-26 2010-09-09 Oki Semiconductor Co Ltd Electrostatically driven mems element and method of manufacturing the same
JP2012182362A (en) * 2011-03-02 2012-09-20 Dainippon Printing Co Ltd Electronic component and manufacturing method of the same
JP2012182361A (en) * 2011-03-02 2012-09-20 Dainippon Printing Co Ltd Electronic component and manufacturing method of the same
WO2021059898A1 (en) * 2019-09-23 2021-04-01 株式会社デンソー Flow rate detection device, and method for manufacturing said flow rate detection device
JP7379994B2 (en) 2019-09-23 2023-11-15 株式会社デンソー Flow rate detection device and method for manufacturing the flow rate detection device

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