JP4542452B2 - Thin film transistor manufacturing method - Google Patents

Description

The present invention relates to a method of manufacturing a thin film transistor (hereinafter referred to as “TFT”) by inkjet coating.

  In a TFT manufacturing process of a liquid crystal display device, a TFT manufacturing method using halftone exposure is performed to shorten the exposure process. In addition, a TFT by inkjet coating is described in Patent Document 1 below.

  In the following Patent Document 1, a gate electrode film of a TFT is formed by an inkjet method using a liquid material containing a conductive material, and a source material and a drain region of the TFT are made of a liquid material containing a semiconductor material. And forming by an ink-jet method.

JP 2003-318193 A

  The halftone exposure in the TFT manufacturing process of the liquid crystal display device has the following problems. (1) Due to the increase in size of the liquid crystal display substrate, it is difficult to produce a halftone mask, (2) It is difficult to produce a halftone mask corresponding to TFT miniaturization, and (3) The resist is uneven in the halftone exposure area For this reason, since the base film configuration is limited, only one exposure process can be shortened.

  Therefore, in the present invention, at the time of so-called island formation in the TFT manufacturing process of the liquid crystal display device, resist pattern formation by exposure and resist pattern formation by ink jet coating are used in combination as halftone exposure.

  Shortening the exposure process using the halftone exposure method used for conventional small substrates is possible even when using ultra-large substrates, and there are no restrictions on the underlying material, so it is possible to shorten processes other than exposure. It becomes.

  That is, (1) halftone exposure can be performed by inkjet coating. (2) No need for advanced ink jet coating technology, (3) No limitation on substrate size (can be used with ultra-large substrates), (4) No limitation on halftone exposure area size (also supports fine TFT), 5) The effect more than shortening the exposure process can be aimed at.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1A is a schematic diagram of an active matrix liquid crystal display device using the TFT 10 according to the present invention, and FIG. 1B is an enlarged view of the pixel portion 300 shown in FIG.

  In FIG. 1A, data (voltage) is applied to the TFT 10 in the pixel portion 300 of the display panel 400 from the data wiring driving circuit 200 via the source wiring 201 corresponding to the gate wiring 101 selected by the scanning wiring driving circuit 100. Is supplied.

  In FIG. 1B, the TFT 10 is provided at the intersection of the gate wiring 101 and the source wiring 201, the gate wiring 101 is connected to the gate electrode 11 of the TFT 10, and the source electrode (or drain electrode) 12 of the TFT 10. Is connected to a source wiring 201.

  The drain electrode (or source electrode) 13 of the TFT 10 is connected to the pixel electrode 21 of the liquid crystal element 20, and the liquid crystal element 20 is between the pixel electrode 21 and the common electrode 22 and is supplied with data (voltage) supplied to the pixel electrode 21. ). A storage capacitor 30 for temporarily storing data is connected between the drain electrode 13 and the storage capacitor wiring 301.

  2 is a plan view and a cross-sectional view of the pixel portion 300 and the TFT 10 in the display panel 400 shown in FIG. 1. FIG. 2A is a plan view of the pixel portion 300 arranged in a matrix form shown in FIG. FIG. 4B is a cross-sectional view taken along the dotted line AA ′ of the TFT 10 in the pixel unit 300 shown in FIG.

  In FIG. 2A, in the pixel portion 300 arranged in a matrix, the TFT 10 is arranged at the intersection of the gate wiring 101 and the source wiring 201. Further, the pixel electrode 21 is connected to the TFT 10 and forms an auxiliary capacitance with the auxiliary capacitance wiring 301.

  2B, in the TFT 10, a gate electrode 11 and a gate insulating film 52 are formed on the insulating substrate 51 so as to cover the electrode. A semiconductor layer (a-Si) 53 and an ohmic contact are formed on the insulating film. A layer (n + Si) 54, the source electrode 12 and the drain electrode 13 are sequentially stacked, and a protective film 55 for protecting the semiconductor layer 53 between the source electrode 12 and the ohmic contact layer 54 and the drain electrode 13 and the ohmic contact layer 54. Is formed.

  3 is a partial cross-sectional view of the TFT 10 shown in FIG. 2B, in which the protective film 55, the source electrode 12, and the drain electrode 13 in FIG. 2B are omitted.

  FIG. 4 is a manufacturing process diagram of the TFT 10 shown in FIG. 3. In FIGS. 4A to 4E, the left side is a plan view and the right side is a sectional view.

  First, as shown in FIG. 4A, a gate electrode 11 is formed on an insulating substrate (not shown), and a gate insulating film 52 is formed so as to cover the electrode. Further, the semiconductor layer 53 and the ohmic contact layer 54 are sequentially stacked on the insulating film. Next, a resist 62 having a half exposure portion 61 is formed using a half exposure resist pattern mask.

Next, in FIG. 4B, in order to form an island, the ohmic contact layer 54 and the semiconductor layer 53 except for the island portion are etched.

  Next, in FIG. 4C, the resist of the half-exposure portion 61 is etched, and as shown in FIG. 4D, the ohmic contact layer 54 is etched to form the gap portion 63. Finally, as shown in FIG. 4E, the resist 62 is removed.

  FIG. 5 shows a step of forming a resist corresponding to half exposure by ink-jet coating in the manufacturing process shown in FIG. 4. In FIGS. 5A to 5E, the left side is a plan view and the right side is a cross section. The figure is shown.

  First, as shown in FIG. 5A, a gate electrode 11 is formed on an insulating substrate (not shown), and a gate insulating film 52 is formed so as to cover the electrode. Further, the semiconductor layer 53 and the ohmic contact layer 54 are sequentially stacked on the insulating film. Next, a resist 62 is formed using a resist pattern mask.

Next, in FIG. 5B, the gap portion 63 is formed by etching the ohmic contact layer 54.

  Next, in FIG. 5C, an ink 71 containing metal fine particles is formed in the gap portion 63 by inkjet coating.

Next, in FIG. 5D, the semiconductor layer 53 is etched using the resist 62 and the ink 71 as a mask to form islands.

  Finally, as shown in FIG. 5E, the resist 62 and the ink 71 are peeled off.

  As described above, FIG. 5 differs from FIG. 4 because the etching of the semiconductor layer 53 is performed through the ink 71, and therefore the etched semiconductor layer 53 in the vicinity of the gap 63 where the ink 71 is dropped is included in the ink 71. The trace part 72 which dripped is formed. The trace portion 72 forms a recess toward the inside of the gap portion 63.

  FIG. 6 is an enlarged view for grasping the shape of the trace portion 72. FIGS. 6A and 6B correspond to FIG. 5C, and FIG. ).

  In FIG. 6A, ink 71 is dropped into the gap portion 63, and the ink 71 wets and spreads along the gap portion as shown in FIG. 6B. As a result, as shown in FIG. 5C, after the resist and the ink are peeled off, a trace portion 72 of the semiconductor layer 53 is formed. Here, the diameter of the dropped ink 71 is 20 μm, the length of the gap 63 is 4 μm, and the width is 30 to 40 μm.

Schematic of a liquid crystal display device according to the present invention Enlarged view of the pixel unit 300 and the TFT 10 shown in FIG. Partial sectional view of the TFT 10 shown in FIG. Manufacturing process diagram of TFT 10 shown in FIG. Other manufacturing process diagram of TFT 10 shown in FIG. Partial enlarged view of the manufacturing process shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Thin-film transistor (TFT), 11 ... Gate electrode, 12 ... Source electrode (or drain electrode), 13 ... Drain electrode (or source electrode), 20 ... Liquid crystal element, 21 ... Pixel electrode, 22 ... Common electrode, 30 ... Auxiliary Capacitance 51 ... Insulating substrate 52 ... Gate insulating film 53 ... Semiconductor layer (a-Si) 54 ... Ohmic contact layer 55 ... Protective film 61 ... Half exposure part 62 ... Resist 63 ... Gap part 71 DESCRIPTION OF SYMBOLS Ink, 72 ... Trace part, 100 ... Scanning wiring drive circuit, 101 ... Gate wiring, 200 ... Data wiring driving circuit, 201 ... Source wiring, 300 ... Pixel part, 301 ... Auxiliary capacitance wiring, 400 ... Display panel

Claims (1)

A gate electrode formed on an insulating substrate, a gate insulating film covering the electrode, an ohmic contact layer formed was separated by a gap portion on the island and the islands are sequentially formed on the gate insulating film In a method for manufacturing a thin film transistor comprising:
Forming the gate electrode on the insulating substrate;
Forming the gate insulating film so as to cover the gate electrode;
Sequentially stacking a semi-conductor layer and the Au over ohmic contact layer on the gate insulating film,
Using a resist pattern mask, a resist pattern is formed on the semiconductor layer and the ohmic contact layer,
The gap portion of the ohmic contact layer is removed by etching to form the gap portion,
An ink containing metal fine particles is applied to the gap portion by inkjet,
Etching the semiconductor layer using the resist and the ink as a mask to form the islands,
Method for manufacturing a thin film transistor of removing the ink together with the resist.