JP4540262B2 - Wiring substrate and semiconductor device using the same - Google Patents

Wiring substrate and semiconductor device using the same Download PDF

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JP4540262B2
JP4540262B2 JP2001197518A JP2001197518A JP4540262B2 JP 4540262 B2 JP4540262 B2 JP 4540262B2 JP 2001197518 A JP2001197518 A JP 2001197518A JP 2001197518 A JP2001197518 A JP 2001197518A JP 4540262 B2 JP4540262 B2 JP 4540262B2
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wiring
wiring board
conductor layer
signal
layer
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JP2003017613A (en
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健一郎 春田
貴志 井上
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子を搭載するために用いられる配線基板およびこの配線基板に半導体素子を搭載して成る半導体装置に関する。
【０００２】
【従来の技術】
一般に、現在の電子機器は、移動体通信機器に代表されるように小型・薄型・軽量・高性能・高機能・高品質・高信頼性が要求されてきており、このような電子機器に搭載される電子装置も小型・高密度化が要求されるようになってきている。そのため、半導体装置を構成する配線基板にも小型化・薄型化・多端子化が求められてきており、それを実現するために信号配線等の配線の幅を細くするとともにその間隔を狭くし、さらに配線の多層化・配線間を接続する貫通導体の小径化により高密度化が図られている。
【０００３】
このような高密度配線が可能な配線基板として、ビルドアップ法を採用して製作された多層配線基板が知られている。ビルドアップ法とは、例えば、ガラスクロスやアラミド不布織等の補強材に耐熱性や耐薬品性を有するエポキシ樹脂に代表される熱硬化性樹脂を含浸させて複合化した絶縁基板上に、間に配線導体を挟んでエポキシ樹脂等の熱硬化性樹脂から成る接着材を塗布して絶縁層を形成するとともに絶縁層を加熱硬化させた後、配線導体上部の絶縁層にレーザで径が50〜200μｍ程度の貫通孔を形成し、しかる後、絶縁層表面を化学粗化し、さらに無電解銅めっき法および電解銅めっき法を用いて貫通孔側面および貫通孔底面の配線導体上に導体膜を被着して貫通導体を形成するとともに絶縁層表面に貫通導体と接続する配線導体を形成し、さらに、絶縁層や貫通導体・配線導体の形成を複数回繰り返すことにより配線基板を製作する方法である。
【０００４】
このような配線基板の配線導体は、用途によって、電源導体層・接地導体層および信号配線に機能化されている。このうち電源導体層は、配線基板に実装される半導体素子に電源を供給するために機能し、絶縁層の略全面をめっきしたベタパターンの薄膜導体から構成されている。また、信号配線は、電気信号を電磁波障害なしに伝播させるために機能し、所定の回路形状にパターン化した導体から構成されている。さらに、接地導体層は、電源導体層や信号配線を流れる電流によって発生する電磁波をシールドし、他の配線導体に生じるノイズを防止するために機能し、電源導体層と同様に絶縁層の略全面をめっきしたベタパターンの薄膜導体から構成されている。すなわち、信号配線などから発生する電磁波を、接地導体層で渦電流に変換することによってシールドし、かかるシールド効果によって他の信号配線でノイズが発生しないように構成されている。
【０００５】
このような役割を担う電源導体層・信号配線および接地導体層は、それぞれ配線基板の表面に設けられた外部電気回路接続用の実装用電極に貫通導体を介して電気的に接続され、配線基板に実装される電子部品への電力の供給・信号の伝達あるいは電磁波のシールドを行うことができるような積層構造に配置されている。
【０００６】
また、電源導体層および接地導体層のベタパターンには、絶縁層の樹脂が硬化する際に発生するガスを逃すために格子状に配列された方形開口部が設けられている。このような格子状に配列された方形開口部は、配線基板を平面視した時に、電源導体層および接地導体層の全面にわたって均一に配列されているとともに信号配線と平行に配列されている。
【０００７】
【発明が解決しようとする課題】
しかしながら従来の配線基板では、これを平面視した時に、格子状に配列された方形開口部と信号配線とが平行に配列されているので、信号配線によっては、絶縁層を介して対向配置された開口部と重なって形成されたりあるいは開口部と重ならずに形成され、各信号配線間で特性インピーダンスが異なってしまい、高周波領域で特性インピーダンスの不整合による反射ノイズが発生し搭載する半導体素子が誤作動してしまうという問題点を有していた。
【０００８】
また、従来の配線基板は、その開口部が大きすぎるとベタパターンによるシールド効果が小さくなり、信号の漏れによるクロストークノイズが発生してしまい、逆に開口部が小さすぎると絶縁層の樹脂が硬化する際に発生するガスが容易に抜けず、接地または電源導体層が膨れたり剥れたりしまうという問題点を有していた。
【０００９】
本発明は、かかる従来技術の問題点に鑑み完成されたものであり、その目的は、各信号配線間の特性インピーダンスの不整合を小さくして反射ノイズの発生を低減するとともに、接地または電源導体層の膨れや剥れのない配線基板およびそれを用いた半導体装置を提供するものである。
【００１０】
【課題を解決するための手段】
本発明の配線基板は、一方向に伸びる配線導体および一方向に対して45度の方向に伸びる配線導体で形成された信号配線と、この信号配線に絶縁層を介して対向配置され、格子状に配列された方形開口部を有する接地または電源導体層とを具備した配線基板であって、方形開口部は、前記一方向に対して15〜30度の方向に配列されており、開口の一辺が0.10〜0.15ｍｍであるとともに開口間の間隔が0.3〜0.6ｍｍであることを特徴とするものである。
【００１２】
さらに、本発明の半導体装置は、上記の配線基板の表面に信号配線と電気的に接続された半導体素子の実装用電極を有するとともに、この実装用電極に半導体素子の電極を電気的に接続して成ることを特徴とするものである。
【００１３】
本発明の配線基板によれば、一方向に伸びる配線導体および一方向に対して45度の方向に伸びる配線導体で形成された信号配線に対して接地または電源導体層に形成した方形開口部を15〜30度の方向に配列したことから、配線基板を平面視した時、信号配線と方形開口部とが平均的に重ね合わさり各信号配線間で特性インピーダンスの差が生じることはなく、その結果、反射ノイズの発生が抑制され、高周波信号領域でも安定して信号が伝達される配線基板とすることができる。
【００１４】
また、本発明の配線基板によれば、方形開口部の開口の一辺を0.10〜0.15ｍｍとするとともに開口間の間隔を0.3〜0.6ｍｍとしたことから、接地および電源導体層のシールド効果で高周波領域における信号配線間のクロストークノイズが低減できるとともに、絶縁層の樹脂が硬化する際に発生するガスを容易に逃がすことができ、その結果、接地または電源導体層に膨れや剥れのない配線基板とすることができる。
【００１５】
さらに、本発明の半導体装置によれば、上記の配線基板の表面に信号配線と電気的に接続された半導体素子の実装用電極を有するとともに、実装用電極に半導体素子の電極を電気的に接続して成ることから、配線基板を平面視した時に、信号配線と方形開口部とが平均的に重ね合わさり各信号配線間で特性インピーダンスの差が生じることはなく、その結果、反射ノイズの発生が抑制され、高周波信号領域でも安定的に信号が伝達される半導体装置とすることができる。
【００１６】
【発明の実施の形態】
次に、本発明の配線基板およびこれを用いた半導体装置を添付の図面に基づいて詳細に説明する。
【００１７】
図１は、本発明の配線基板に半導体素子を搭載して成る半導体装置の実施の形態の一例を示す断面図であり、図２は、本発明の配線基板の信号配線と接地導体層とを平面視した時の実施の形態の一例を示す透過平面図である。なお、図２の接地導体層は、電源導体層であってもよい。
【００１８】
これらの図において、１は絶縁基板、２は絶縁層、３は信号配線、４は接地導体層、５は電源導体層、６は貫通導体、７は方形開口部で、主にこれらで本発明の配線基板８が構成される。また、この配線基板８に半導体素子９を搭載し、実装用電極10と半導体素子９の電極とを電気的に接続することにより本発明の半導体装置11と成る。なお、本発明の配線基板８の接地導体層４および電源導体層５には、格子状に配列された方形開口部７が形成されている。
【００１９】
配線基板８は、半導体素子９の支持部材としての機能を有し、絶縁基板１の表面および／または裏面の主面に複数の絶縁層２が積層されている
配線基板８を構成する絶縁基板１は、絶縁層２の支持体としての機能を有し、例えばガラスクロス−エポキシ樹脂やガラスクロス−ビスマレイミドトリアジン樹脂・ガラスクロス−ポリフェニレンエーテル樹脂・アラミド繊維−エポキシ樹脂等から成り、常法により製作される。また、絶縁基板１の主面には、電源導体層５等の導体層が被着形成されており、これらの導体層は、絶縁基板１内部に形成されたスルーホール導体15で電気的に接続されている。さらに、絶縁基板１の主面には、銅や金・ニッケル・アルミニウム等の金属薄膜からなる信号配線３や接地導体層４・電源導体層５が絶縁層３を介して積層されている。
【００２０】
絶縁層２は、信号配線３や接地導体層４・電源導体層５を支持する支持部材として機能し、例えばエポキシ樹脂やビスマレイミドトリアジン樹脂・ポリフェニレンエーテル樹脂等の熱硬化性樹脂とエラストマーと無機絶縁性フィラーとから成る。なお、信号配線３や接地導体層４・電源導体層５等の金属薄膜との密着性を良好となすために、表面を粗化できる熱可塑性樹脂成分も含有してもよい。
【００２１】
このような絶縁層２は、例えばエポキシ樹脂と熱可塑性樹脂・エラストマー・無機絶縁性フィラーに溶剤等を添加した混合物を混練して液状ワニスを得、この液状ワニスをポリエチレンテレフタレート（ＰＥＴ）製離型シート上に塗布し、60〜100℃の温度で乾燥することによりフィルム状に成形される。また、絶縁層２には、炭酸ガスレーザやＹＡＧレーザ・ＵＶレーザ等の従来周知のレーザを用いて直径が30〜300μｍ程度の貫通孔が形成されるとともに、その内部に銅や金・ニッケル・アルミニウム等の金属薄膜を被着して、信号配線３同士を電気的に接続する貫通導体６が形成されている。なお、絶縁層２となる乾燥後のフィルムは、エラストマーを含有することから、フィルム上面にポリエチレンシートを積層し、ロール状に巻き取ることにより容易に貯蔵できる。また、フィルムの厚さは自由に設定することができるが、絶縁性の観点からは20〜100μｍの範囲の厚さが好ましい。そして、絶縁層２は、このフィルムを絶縁基板１表面に真空ラミネータを用いて圧着し、オーブンで熱硬化することにより積層される。
【００２２】
また、絶縁層２表面には、信号配線３やベタパターンの接地導体層４・電源導体層５が形成され、これらは貫通導体６で電気的に接続されている。このような信号配線３や接地導体層４・電源導体層５は、配線基板８に搭載される半導体素子９を外部電気回路基板（図示せず）に電気的に接続する導電路としての機能を有する。また、信号配線３は、その幅が20〜100μｍであり、配線設計のし易さとその屈曲部でのクラック防止のため、一方向に伸びる配線導体３ａおよび一方向に対して45度の方向に伸びる配線導体３ｂで形成されている。一方、ベタパターンの接地導体層４や電源導体層５には、絶縁層２の樹脂が硬化する際に発生するガスを逃すために、および絶縁層２同士の密着性を向上させるために多数の格子状に配列された方形開口部７が形成されている。
【００２３】
信号配線３や接地導体層４・電源導体層５・貫通導体６を形成する金属材料としては、電気抵抗値が低いという観点からは銅や金・ニッケル・アルミニウム等の金属が好ましく、安価という観点からは銅が好ましい。なお、銅や金・ニッケル・アルミニウム等から成る金属薄膜の厚みは、高速の信号を伝達させるという観点からは３μｍ以上であることが好ましく、金属薄膜を絶縁基板１や絶縁層２に被着形成する際に金属薄膜に大きな応力を残留させず、金属薄膜が絶縁基板１や絶縁層２から剥離しにくいものとするためには50μｍ以下としておくことが好ましい。
【００２４】
このような金属薄膜は、次に述べる方法により形成される。まず、絶縁層２の所望の個所に、例えば炭酸レーザを用いて貫通孔を形成した後に、絶縁層２の表面および貫通孔内壁を過マンガン酸塩類水溶液等の粗化液に浸漬して粗化する。次に、絶縁層２の表面および貫通孔内壁を無電解めっきの触媒と成る例えばパラジウムの水溶液中に浸漬して絶縁層２表面と貫通孔内壁に触媒を被着させ、さらに、硫酸銅・ロッセル塩・ホルマリン・ＥＤＴＡナトリウム塩・安定剤等から成る無電解めっき液に約30分間浸漬して、数μｍの無電解銅めっき膜を析出させる。そして次に、絶縁層２の表面に感光性ドライフィルムレジストをラミネートし露光と現像により薄膜導体と成る所定の配線パターンを形成し、しかる後に、硫酸・硫酸銅５水和物・塩素・光沢剤等から成る電解銅めっき液に数Ａ／ｄｍ2の電流を印加しながら数時間浸漬することにより貫通導体６が貫通孔の内壁や内部に形成される。さらにまた、水酸化ナトリウムを用いて感光性ドライフィルムレジストを剥離し、しかる後、硫酸・過酸化水素水溶液でめっき膜表面をエッチングすることにより、絶縁層２の表面に信号配線３や格子状に配列された方形開口部７を有する接地導体層４・電源導体層５が形成される。
【００２５】
そして、このような信号配線３や接地導体層４・電源導体層５・貫通導体６を形成した絶縁層２の上面に、絶縁層２を積層するとともに上記と同じ工程を繰り返して信号配線３や接地導体層４・電源導体層５・貫通導体６を形成し、さらにこれを複数回繰り返すことにより絶縁層２が複数積層される。
【００２６】
なお、本発明の配線基板８において、信号配線３と接地導体層４または電源導体層５とは対に成るように設計されており、信号配線３の上下には絶縁層２を介して接地導体層４または電源導体層５が配置されている。
【００２７】
本発明の配線基板８においては、接地導体層４または電源導体層５の格子状に配列された方形開口部７が、一方向に伸びる配線導体３ａ・３ｂに対して15〜30度の方向に配列されている。また、このことが重要である。なお、ここで一方向に伸びる配線導体３ａ・３ｂに対して15〜30度の方向とは、例えば、配線導体３ａに対しては配線導体３ｂと同じ方向で15〜30度の範囲であり、配線導体３ｂに対しては配線導体３ａと同じ方向で15〜30度の範囲を示している。
【００２８】
本発明の配線基板８によれば、格子状に配列された方形開口部７が、一方向に伸びる配線導体３ａ・３ｂに対して15〜30度の方向に配列されていることから、配線基板８を平面視した時、信号配線３と方形開口部７とが平均的に重ね合わさり各信号配線３間で特性インピーダンスの差が生じることはなく、その結果、反射ノイズの発生が抑制され、高周波信号領域でも安定して信号が伝達される配線基板８とすることができる。なお、格子状に配列された方形開口部７が、一方向に伸びる配線導体３ａ・３ｂに対して15度より小さい角度の方向あるいは30度より大きい角度の方向に配列されていると、信号配線３と方形開口部７との重なりにバラツキが生じ、各信号配線３間で特性インピーダンスの値が大きく異ってしまい、高周波領域で特性インピーダンスの不整合による反射ノイズが発生し半導体素子が誤作動してしまう傾向がある。従って、格子状に配列された方形開口部７は、一方向に伸びる配線導体３ａ・３ｂに対して15〜30度の方向に配列されていることが好ましい。
【００２９】
なお、ここで反射ノイズとは、特性インピーダンスの不整合により電圧反射が生じることにより信号配線３の波形が階段的に乱れる現象であり、特に、高周波領域では、小さな特性インピーダンスの不整合でも反射ノイズが生じ易く、これにより配線基板８に搭載されている半導体素子９が誤作動することがある。
【００３０】
さらに、本発明の配線基板８においては、方形開口部７の開口の一辺が、0.10〜0.15ｍｍであるとともに開口間の間隔が0.3〜0.6ｍｍであることが好ましい。また、このことが重要である。
【００３１】
本発明の配線基板８によれば、方形開口部７の開口の一辺を0.10〜0.15ｍｍとするとともに開口間の間隔を0.3〜0.6ｍｍとしたことから、接地導体層４および電源導体層５のシールド効果で高周波領域における信号配線３間のクロストークノイズが低減できるとともに、絶縁層２の樹脂が硬化する際に発生するガスも容易に逃がすことができ、その結果、接地導体層４または電源導体層５に膨れや剥れの発生することのない配線基板８とすることができる。
【００３２】
なお、方形開口部７の開口の一辺が、0.10ｍｍより小さいと絶縁層２の樹脂が硬化する際に発生するガスが絶縁層２から容易に抜けず、接地導体層４または電源導体層５が膨れたり剥れたりしてしまう傾向があり、0.15ｍｍより大きいと接地導体層４または電源導体層５のシールド効果が小さくなり、クロストークノイズが発生し半導体素子９が誤作動してしまう危険性がある。従って、方形開口部７の開口の一辺は、0.10〜0.15ｍｍであることが好ましい。また、開口間の間隔が0.3ｍｍ未満であると、接地導体層４または電源導体層５と信号配線３とが重なる部分が増加し、接地導体層４および電源導体層５のシールド効果が小さくなりクロストークノイズが発生して半導体素子９が誤作動してしまう傾向にあり、0.6ｍｍより大きいと方形開口部７の数が少なくなり、絶縁層２の樹脂が硬化する際に発生するガスが絶縁層２から容易に抜けず、接地導体層４または電源導体層５が膨れたり剥れたりしてしまう傾向にある。従って、方形開口部７の開口間の間隔は、0.3〜0.6ｍｍであることが好ましい。
【００３３】
なお、クロストークノイズとは、信号が容量結合や誘電結合により他の信号配線へ誘起されて生じる現象であり、本発明においては、信号配線３の上下には絶縁層２を介して接地導体層４または電源導体層５を配置しているので、信号配線３から発生する電磁波を、接地導体層４または電源導体層５で渦電流に変換することによってシールドし、かかるシールド効果によって他の信号配線３でノイズが発生しないようにしている。
【００３４】
かくして、本発明の配線基板８によれば、方形開口部７の開口の一辺を0.10〜0.15ｍｍとするとともに開口間の間隔を0.3〜0.6ｍｍとしたことから、接地導体層４および電源導体層５のシールド効果で高周波領域における信号配線３間のクロストークノイズが低減できるとともに、絶縁層の樹脂が硬化する際に発生するガスを絶縁層２から容易に逃がすことができ、接地導体層４または電源導体層５に膨れや剥れのない配線基板８とすることができる。
【００３５】
なお、配線基板８に半導体素子９を実装する際の熱履歴から絶縁層２および実装用電極10を保護するために、絶縁層２の最外層表面に感光性樹脂から成る耐半田樹脂層12を被着形成してもよい。また、この場合、耐半田樹脂層12の実装用電極10上部には露光・現像により実装用電極10と半導体素子９の電極とを接続する導体バンプ13用の開口が形成される。さらに、開口底の実装用電極10表面にニッケル・金等の良導電性で耐腐蝕性に優れた金属をめっき法により１〜20μｍの厚さに被着させておくと、実装用電極10表面の酸化腐食を有効に防止できるとともに実装用電極10と導体バンプ13との接続を良好とすることができる。
【００３６】
また、本発明の半導体装置11は、配線基板８表面の実装用電極10と半導体素子９の電極とを導体バンプ13を介して電気的に接続することによって形成される。なお、実装用電極10上に被着された耐半田樹脂層12の開口の形状は円形状であることが望ましく、さらに、それらの径はフィリップチップ側が50〜300μｍ、ボールグリッドアレイ側が300〜800μｍの範囲とすることが好ましい。
【００３７】
導体バンプ13は、実装用電極10と半導体素子９の各電極とを電気的に接続する機能を有し、配線基板８表面の実装用電極10上に半田等の金属により形成されている。このような導体バンプ13は、金や鉛−錫・錫−亜鉛・錫−銀−ビスマス等の合金の導電材料から成り、例えば導電材料が鉛−錫から成る半田の場合、鉛−錫から成るぺーストを耐半田樹脂層12の開口にスクリーン印刷法によって印刷、あるいは鉛−錫から成る半田ボールを耐半田樹脂層12の開口に載置した後、リフロー炉を通すことによって実装用電極10上に半球状に固着形成される。しかる後、半導体素子９を導体バンプ13上に載置し、リフロー炉を通すことによって実装用電極10と半導体素子９の各回路とが電気的に接続される。なお、半導体素子９と配線基板８表面との間に、熱硬化性樹脂とフィラーとから成るアンダーフィル材14を注入することによって、導体バンプ13が保護されるとともに半導体素子９が配線基板８に強固に固着される。
【００３８】
かくして、本発明の半導体装置11によれば、上記の配線基板８の表面に信号配線３と電気的に接続された半導体素子９の実装用電極10を有するとともに、実装用電極10に半導体素子９の電極を電気的に接続して成ることから、配線基板８を平面視した時に、信号配線３と方形開口部７とが平均的に重なっていることから、各信号配線３間で特性インピーダンスの差が生じず、反射ノイズの発生が抑制されるので、高周波信号領域でも安定的に信号が伝達される半導体装置11とすることができる。
【００３９】
なお、本発明の配線基板８および半導体装置11は上述の実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能であることは言うまでもない。
【００４０】
【発明の効果】
本発明の配線基板によれば、一方向に伸びる配線導体および一方向に対して45度の方向に伸びる配線導体で形成された信号配線に対して接地または電源導体層に形成した方形開口部を15〜30度の方向に配列したことから、配線基板を平面視した時、信号配線と方形開口部とが平均的に重ね合わさり各信号配線間で特性インピーダンスの差が生じることはなく、その結果、反射ノイズの発生が抑制され、高周波信号領域でも安定して信号が伝達される配線基板とすることができる。
【００４１】
また、本発明の配線基板によれば、方形開口部の開口の一辺を0.10〜0.15ｍｍとするとともに開口間の間隔を0.3〜0.6ｍｍとしたことから、接地および電源導体層のシールド効果で高周波領域における信号配線間のクロストークノイズが低減できるとともに、絶縁層の樹脂が硬化する際に発生するガスを容易に逃がすことができ、その結果、接地または電源導体層に膨れや剥れのない配線基板とすることができる。
【００４２】
さらに、本発明の半導体装置によれば、上記の配線基板の表面に信号配線と電気的に接続された半導体素子の実装用電極を有するとともに、実装用電極に半導体素子の電極を電気的に接続して成ることから、配線基板を平面視した時に、信号配線と方形開口部とが平均的に重ね合わさり各信号配線間で特性インピーダンスの差が生じることはなく、その結果、反射ノイズの発生が抑制され、高周波信号領域でも安定的に信号が伝達される半導体装置とすることができる。
【図面の簡単な説明】
【図１】本発明の配線基板に半導体素子を搭載して成る半導体装置の実施の形態の一例を示す断面図である。
【図２】本発明の配線基板の信号配線と接地および電源導体層とを平面視した時の実施の形態の一例を示す透過平面図である。
【符号の説明】
１・・・・・・・絶縁基板
２・・・・・・・絶縁層
３・・・・・・・信号配線
3a・3b・・・・・配線導体
４・・・・・・・接地導体層
５・・・・・・・電源導体層
７・・・・・・・方形開口部
８・・・・・・・配線基板
９・・・・・・・半導体素子
10・・・・・・・実装用電極
11・・・・・・・半導体装置[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a wiring board used for mounting a semiconductor element and a semiconductor device having a semiconductor element mounted on the wiring board.
[0002]
[Prior art]
In general, current electronic devices are required to be small, thin, lightweight, high performance, high functionality, high quality, and high reliability, as represented by mobile communication devices. Electronic devices to be used are also required to be small and high density. Therefore, miniaturization / thinning / multi-terminals are also required for the wiring board constituting the semiconductor device, and in order to realize it, the width of the wiring such as the signal wiring is narrowed and the interval is narrowed, Furthermore, the density is increased by increasing the number of wirings and reducing the diameter of the through conductors connecting the wirings.
[0003]
As a wiring board capable of such high-density wiring, a multilayer wiring board manufactured by adopting a build-up method is known. The build-up method is, for example, on an insulating substrate that is compounded by impregnating a thermosetting resin typified by an epoxy resin having heat resistance and chemical resistance into a reinforcing material such as glass cloth or aramid nonwoven fabric, An insulating layer is formed by applying an adhesive made of a thermosetting resin such as an epoxy resin with a wiring conductor in between, and the insulating layer is heated and cured. Form a through hole of about ~ 200 μm, then chemically roughen the surface of the insulating layer, and further use the electroless copper plating method and the electrolytic copper plating method to form a conductor film on the wiring conductor on the side surface of the through hole and the bottom surface of the through hole A method of manufacturing a wiring board by forming a through conductor by coating, forming a wiring conductor connected to the through conductor on the surface of the insulating layer, and further repeating the formation of the insulating layer and the through conductor / wiring conductor multiple times. is there.
[0004]
The wiring conductor of such a wiring board is functionalized into a power supply conductor layer / ground conductor layer and a signal wiring depending on applications. Among these, the power supply conductor layer functions to supply power to the semiconductor element mounted on the wiring board, and is composed of a solid pattern thin film conductor in which substantially the entire surface of the insulating layer is plated. Further, the signal wiring functions to propagate an electric signal without electromagnetic interference, and is composed of a conductor patterned in a predetermined circuit shape. Furthermore, the ground conductor layer functions to shield electromagnetic waves generated by the current flowing through the power supply conductor layer and the signal wiring, and to prevent noise generated in other wiring conductors. It is comprised from the thin-film conductor of the solid pattern plated. That is, the electromagnetic wave generated from the signal wiring or the like is shielded by converting it into an eddy current in the ground conductor layer, and noise is not generated in the other signal wiring due to the shielding effect.
[0005]
The power supply conductor layer / signal wiring and grounding conductor layer that play such a role are electrically connected to the mounting electrodes for connecting external electric circuits provided on the surface of the wiring board, respectively, through the through conductors, and the wiring board It is arranged in a laminated structure that can supply power to the electronic components mounted on the board, transmit signals, or shield electromagnetic waves.
[0006]
In addition, the solid patterns of the power supply conductor layer and the ground conductor layer are provided with rectangular openings arranged in a lattice pattern so as to release gas generated when the resin of the insulating layer is cured. The rectangular openings arranged in such a lattice shape are arranged uniformly over the entire surface of the power supply conductor layer and the ground conductor layer when the wiring board is viewed in plan and are arranged in parallel with the signal wiring.
[0007]
[Problems to be solved by the invention]
However, in the conventional wiring board, when viewed in plan, the rectangular openings arranged in a lattice pattern and the signal wiring are arranged in parallel, so that some signal wirings are arranged to face each other through an insulating layer. A semiconductor element that is formed so as to overlap with the opening, or not overlap with the opening, has different characteristic impedances among the signal wirings, and generates reflection noise due to mismatch of characteristic impedance in the high frequency region. It had the problem of malfunctioning.
[0008]
In addition, if the opening of the conventional wiring board is too large, the shielding effect due to the solid pattern is reduced, and crosstalk noise is generated due to signal leakage. Conversely, if the opening is too small, the resin of the insulating layer is There is a problem in that the gas generated during curing does not easily escape and the ground or power conductor layer swells or peels off.
[0009]
The present invention has been completed in view of the problems of the prior art, and an object of the present invention is to reduce the occurrence of reflected noise by reducing the mismatch of characteristic impedance between the signal wirings, and to connect the ground or power supply conductor. The present invention provides a wiring board having no layer swelling or peeling and a semiconductor device using the wiring board.
[0010]
[Means for Solving the Problems]
The wiring board of the present invention is a signal wiring formed of a wiring conductor extending in one direction and a wiring conductor extending in a direction of 45 degrees with respect to one direction, and this signal wiring is arranged so as to face each other through an insulating layer. A wiring board having a ground or power supply conductor layer having a rectangular opening arranged in the rectangular opening, the rectangular opening being arranged in a direction of 15 to 30 degrees with respect to the one direction, and one side of the opening Is 0.10 to 0.15 mm, and the interval between the openings is 0.3 to 0.6 mm .
[0012]
Furthermore, the semiconductor device of the present invention has a mounting electrode for a semiconductor element electrically connected to the signal wiring on the surface of the wiring board, and electrically connects the electrode of the semiconductor element to the mounting electrode. It is characterized by comprising.
[0013]
According to the wiring board of the present invention, the rectangular opening formed in the ground or power supply conductor layer with respect to the signal wiring formed by the wiring conductor extending in one direction and the wiring conductor extending in the direction of 45 degrees with respect to one direction is provided. Since the wiring board is arranged in a direction of 15 to 30 degrees, when the wiring board is viewed in plan, the signal wiring and the rectangular opening are overlapped on average, and there is no difference in characteristic impedance between the signal wirings. Therefore, it is possible to provide a wiring board in which the generation of reflection noise is suppressed and a signal is stably transmitted even in a high-frequency signal region.
[0014]
In addition, according to the wiring board of the present invention, one side of the opening of the rectangular opening is set to 0.10 to 0.15 mm and the interval between the openings is set to 0.3 to 0.6 mm. Crosstalk noise between signal wirings in the area can be reduced, and gas generated when the resin of the insulating layer hardens can be easily released. As a result, wiring that does not swell or peel off to the ground or power conductor layer It can be a substrate.
[0015]
Furthermore, according to the semiconductor device of the present invention, the semiconductor device mounting electrode is electrically connected to the signal wiring on the surface of the wiring board, and the semiconductor element electrode is electrically connected to the mounting electrode. Therefore, when the wiring board is viewed in plan, the signal wiring and the square opening are overlapped on average, and there is no difference in characteristic impedance between the signal wirings. As a result, generation of reflected noise occurs. A semiconductor device that is suppressed and can stably transmit signals even in a high-frequency signal region can be obtained.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Next, a wiring board of the present invention and a semiconductor device using the same will be described in detail with reference to the accompanying drawings.
[0017]
FIG. 1 is a cross-sectional view showing an example of an embodiment of a semiconductor device in which a semiconductor element is mounted on a wiring board of the present invention. FIG. 2 shows signal wiring and ground conductor layers of the wiring board of the present invention. It is a permeation | transmission top view which shows an example of embodiment when planarly viewed. 2 may be a power supply conductor layer.
[0018]
In these drawings, 1 is an insulating substrate, 2 is an insulating layer, 3 is a signal wiring, 4 is a ground conductor layer, 5 is a power supply conductor layer, 6 is a through conductor, and 7 is a rectangular opening. The wiring board 8 is configured. Further, the semiconductor element 9 is mounted on the wiring board 8 and the mounting electrode 10 and the electrode of the semiconductor element 9 are electrically connected to form the semiconductor device 11 of the present invention. In the grounding conductor layer 4 and the power supply conductor layer 5 of the wiring board 8 of the present invention, rectangular openings 7 arranged in a grid are formed.
[0019]
The wiring substrate 8 has a function as a support member for the semiconductor element 9, and the insulating substrate 1 constituting the wiring substrate 8 in which a plurality of insulating layers 2 are stacked on the front surface and / or the back surface of the insulating substrate 1. Has a function as a support for the insulating layer 2, and is made of, for example, glass cloth-epoxy resin, glass cloth-bismaleimide triazine resin, glass cloth-polyphenylene ether resin, aramid fiber-epoxy resin, etc. Is done. In addition, a conductor layer such as a power supply conductor layer 5 is formed on the main surface of the insulating substrate 1, and these conductor layers are electrically connected by a through-hole conductor 15 formed inside the insulating substrate 1. Has been. Further, on the main surface of the insulating substrate 1, a signal wiring 3 made of a metal thin film such as copper, gold, nickel, and aluminum, a ground conductor layer 4, and a power supply conductor layer 5 are laminated via the insulating layer 3.
[0020]
The insulating layer 2 functions as a support member that supports the signal wiring 3, the ground conductor layer 4, and the power supply conductor layer 5. For example, the thermosetting resin such as epoxy resin, bismaleimide triazine resin, polyphenylene ether resin, elastomer, and inorganic insulation It consists of a functional filler. In addition, in order to make the adhesiveness with metal thin films, such as the signal wiring 3, the grounding conductor layer 4, and the power supply conductor layer 5, favorable, you may contain the thermoplastic resin component which can roughen the surface.
[0021]
Such an insulating layer 2 is obtained, for example, by kneading a mixture of an epoxy resin and a thermoplastic resin / elastomer / inorganic insulating filler added with a solvent to obtain a liquid varnish, and the liquid varnish is released from polyethylene terephthalate (PET). It is formed on a sheet by coating on a sheet and drying at a temperature of 60 to 100 ° C. The insulating layer 2 is formed with a through-hole having a diameter of about 30 to 300 μm using a conventionally known laser such as a carbon dioxide laser, a YAG laser, or a UV laser, and copper, gold, nickel, or aluminum is formed therein. A through conductor 6 for electrically connecting the signal wirings 3 to each other is formed by depositing a metal thin film or the like. In addition, since the film after drying used as the insulating layer 2 contains an elastomer, it can be easily stored by laminating a polyethylene sheet on the upper surface of the film and winding it into a roll. Moreover, although the thickness of a film can be set freely, the thickness of the range of 20-100 micrometers is preferable from an insulating viewpoint. And the insulating layer 2 is laminated | stacked by crimping | bonding this film on the insulating substrate 1 surface using a vacuum laminator, and thermosetting in oven.
[0022]
Further, on the surface of the insulating layer 2, a signal wiring 3 and a ground conductor layer 4 and a power supply conductor layer 5 having a solid pattern are formed, and these are electrically connected by a through conductor 6. The signal wiring 3, the ground conductor layer 4 and the power supply conductor layer 5 function as a conductive path for electrically connecting the semiconductor element 9 mounted on the wiring board 8 to an external electric circuit board (not shown). Have. Further, the signal wiring 3 has a width of 20 to 100 μm, and the wiring conductor 3a extending in one direction and a direction of 45 degrees with respect to the one direction for easy wiring design and prevention of cracks at the bent portion. The wiring conductor 3b extends. On the other hand, the solid conductor ground layer 4 and the power source conductor layer 5 have a large number of layers in order to escape gas generated when the resin of the insulating layer 2 is cured and to improve the adhesion between the insulating layers 2. Square openings 7 arranged in a lattice pattern are formed.
[0023]
The metal material for forming the signal wiring 3, the ground conductor layer 4, the power supply conductor layer 5, and the through conductor 6 is preferably a metal such as copper, gold, nickel, and aluminum from the viewpoint of low electrical resistance, and is inexpensive. Is preferably copper. The thickness of the metal thin film made of copper, gold, nickel, aluminum or the like is preferably 3 μm or more from the viewpoint of transmitting a high-speed signal, and the metal thin film is formed on the insulating substrate 1 or the insulating layer 2. In order to prevent a large stress from remaining on the metal thin film and to prevent the metal thin film from being peeled off from the insulating substrate 1 or the insulating layer 2, the thickness is preferably set to 50 μm or less.
[0024]
Such a metal thin film is formed by the method described below. First, a through hole is formed at a desired location of the insulating layer 2 using, for example, a carbonic acid laser, and then the surface of the insulating layer 2 and the inner wall of the through hole are immersed in a roughening solution such as an aqueous permanganate solution for roughening. To do. Next, the surface of the insulating layer 2 and the inner wall of the through hole are immersed in an aqueous solution of palladium, for example, as a catalyst for electroless plating, and the catalyst is deposited on the surface of the insulating layer 2 and the inner wall of the through hole. It is immersed in an electroless plating solution made of salt, formalin, EDTA sodium salt, stabilizer, etc. for about 30 minutes to deposit an electroless copper plating film of several μm. Then, a photosensitive dry film resist is laminated on the surface of the insulating layer 2 to form a predetermined wiring pattern that becomes a thin film conductor by exposure and development, and thereafter, sulfuric acid / copper sulfate pentahydrate / chlorine / brightening agent. The through conductor 6 is formed on the inner wall and inside of the through hole by dipping for several hours while applying a current of several A / dm 2 to an electrolytic copper plating solution made of, for example. Furthermore, the photosensitive dry film resist is peeled off using sodium hydroxide, and then the surface of the plating film is etched with sulfuric acid / hydrogen peroxide aqueous solution, so that the signal wiring 3 and the grid are formed on the surface of the insulating layer 2. The ground conductor layer 4 and the power supply conductor layer 5 having the square openings 7 arranged are formed.
[0025]
Then, the insulating layer 2 is laminated on the upper surface of the insulating layer 2 on which the signal wiring 3 and the ground conductor layer 4, the power source conductor layer 5, and the through conductor 6 are formed, and the signal wiring 3 and the signal wiring 3 A plurality of insulating layers 2 are laminated by forming a ground conductor layer 4, a power supply conductor layer 5, and a through conductor 6, and further repeating this multiple times.
[0026]
In the wiring board 8 of the present invention, the signal wiring 3 and the ground conductor layer 4 or the power supply conductor layer 5 are designed to be paired, and the ground conductor is provided above and below the signal wiring 3 via the insulating layer 2. Layer 4 or power supply conductor layer 5 is disposed.
[0027]
In the wiring board 8 of the present invention, the rectangular openings 7 arranged in a grid pattern of the ground conductor layer 4 or the power supply conductor layer 5 are in a direction of 15 to 30 degrees with respect to the wiring conductors 3a and 3b extending in one direction. It is arranged. This is also important. Here, the direction of 15 to 30 degrees with respect to the wiring conductors 3a and 3b extending in one direction is, for example, a range of 15 to 30 degrees in the same direction as the wiring conductor 3b with respect to the wiring conductor 3a. For the wiring conductor 3b, a range of 15 to 30 degrees is shown in the same direction as the wiring conductor 3a.
[0028]
According to the wiring board 8 of the present invention, the rectangular openings 7 arranged in a lattice pattern are arranged in a direction of 15 to 30 degrees with respect to the wiring conductors 3a and 3b extending in one direction. When the plane 8 is viewed in plan, the signal wiring 3 and the rectangular opening 7 are overlapped on average, so that there is no difference in characteristic impedance between the respective signal wirings 3. As a result, generation of reflection noise is suppressed, and high frequency The wiring board 8 can transmit signals stably even in the signal region. If the rectangular openings 7 arranged in a lattice pattern are arranged in an angle direction smaller than 15 degrees or an angle larger than 30 degrees with respect to the wiring conductors 3a and 3b extending in one direction, 3 and the square opening 7 vary, and the characteristic impedance values differ greatly between the signal wirings 3. Reflection noise is generated due to mismatching of the characteristic impedance in the high frequency region, causing the semiconductor device to malfunction. There is a tendency to end up. Therefore, it is preferable that the rectangular openings 7 arranged in a grid are arranged in a direction of 15 to 30 degrees with respect to the wiring conductors 3a and 3b extending in one direction.
[0029]
Here, the reflected noise is a phenomenon in which the waveform of the signal wiring 3 is disturbed in a stepwise manner due to voltage reflection caused by mismatching of characteristic impedances. As a result, the semiconductor element 9 mounted on the wiring board 8 may malfunction.
[0030]
Furthermore, in the wiring board 8 of the present invention, it is preferable that one side of the opening of the rectangular opening 7 is 0.10 to 0.15 mm and the interval between the openings is 0.3 to 0.6 mm. This is also important.
[0031]
According to the wiring board 8 of the present invention, since one side of the opening of the rectangular opening 7 is set to 0.10 to 0.15 mm and the interval between the openings is set to 0.3 to 0.6 mm, the ground conductor layer 4 and the power supply conductor layer 5 The crosstalk noise between the signal wirings 3 in the high frequency region can be reduced by the shielding effect, and the gas generated when the resin of the insulating layer 2 is cured can be easily released. As a result, the ground conductor layer 4 or the power conductor The wiring board 8 can be obtained in which the layer 5 does not swell or peel off.
[0032]
If one side of the opening of the rectangular opening 7 is smaller than 0.10 mm, the gas generated when the resin of the insulating layer 2 is cured does not easily escape from the insulating layer 2, and the ground conductor layer 4 or the power supply conductor layer 5 There is a tendency to swell or peel off, and if it is larger than 0.15 mm, the shielding effect of the ground conductor layer 4 or the power supply conductor layer 5 is reduced, and there is a risk that crosstalk noise occurs and the semiconductor element 9 malfunctions. There is. Therefore, it is preferable that one side of the opening of the rectangular opening 7 is 0.10 to 0.15 mm. If the distance between the openings is less than 0.3 mm, the portion where the ground conductor layer 4 or the power supply conductor layer 5 and the signal wiring 3 overlap increases, and the shielding effect of the ground conductor layer 4 and the power supply conductor layer 5 decreases. There is a tendency for the crosstalk noise to occur and the semiconductor element 9 to malfunction, and when it is larger than 0.6 mm, the number of the rectangular openings 7 is reduced, and the gas generated when the resin of the insulating layer 2 is cured is insulated. There is a tendency that the ground conductor layer 4 or the power supply conductor layer 5 does not easily come off from the layer 2 and swells or peels off. Therefore, the interval between the openings of the rectangular opening 7 is preferably 0.3 to 0.6 mm.
[0033]
The crosstalk noise is a phenomenon that occurs when a signal is induced to other signal wirings by capacitive coupling or dielectric coupling. In the present invention, the ground conductor layer is formed above and below the signal wiring 3 via the insulating layer 2. 4 or the power supply conductor layer 5 is disposed, the electromagnetic wave generated from the signal wiring 3 is shielded by converting it into an eddy current in the ground conductor layer 4 or the power supply conductor layer 5, and other signal wiring is obtained by the shielding effect. 3 prevents noise.
[0034]
Thus, according to the wiring board 8 of the present invention, since one side of the opening of the rectangular opening 7 is set to 0.10 to 0.15 mm and the interval between the openings is set to 0.3 to 0.6 mm, the ground conductor layer 4 and the power supply conductor layer are provided. 5 can reduce the crosstalk noise between the signal wirings 3 in the high-frequency region, and can easily escape the gas generated when the resin of the insulating layer is cured from the insulating layer 2. It is possible to obtain a wiring substrate 8 in which the power supply conductor layer 5 is not swollen or peeled off.
[0035]
In order to protect the insulating layer 2 and the mounting electrode 10 from the thermal history when the semiconductor element 9 is mounted on the wiring board 8, a solder-resistant resin layer 12 made of a photosensitive resin is provided on the outermost surface of the insulating layer 2. It may be deposited. In this case, an opening for the conductor bump 13 that connects the mounting electrode 10 and the electrode of the semiconductor element 9 is formed on the mounting electrode 10 of the solder-resistant resin layer 12 by exposure and development. Furthermore, if the surface of the mounting electrode 10 at the bottom of the opening is coated with a metal of good conductivity and corrosion resistance, such as nickel or gold, to a thickness of 1 to 20 μm by plating, the surface of the mounting electrode 10 In addition, it is possible to effectively prevent the oxidative corrosion of the metal and to improve the connection between the mounting electrode 10 and the conductor bump 13.
[0036]
The semiconductor device 11 of the present invention is formed by electrically connecting the mounting electrode 10 on the surface of the wiring substrate 8 and the electrode of the semiconductor element 9 via the conductor bumps 13. In addition, it is desirable that the shape of the opening of the solder-resistant resin layer 12 deposited on the mounting electrode 10 is circular, and the diameters thereof are 50 to 300 μm on the Philip chip side and 300 to 800 μm on the ball grid array side. It is preferable to set it as the range.
[0037]
The conductor bump 13 has a function of electrically connecting the mounting electrode 10 and each electrode of the semiconductor element 9 and is formed of a metal such as solder on the mounting electrode 10 on the surface of the wiring substrate 8. Such a conductor bump 13 is made of a conductive material of an alloy such as gold or lead-tin, tin-zinc, tin-silver-bismuth, for example, in the case where the conductive material is a solder made of lead-tin, and made of lead-tin. The paste is printed on the opening of the solder-resistant resin layer 12 by a screen printing method, or a solder ball made of lead-tin is placed on the opening of the solder-resistant resin layer 12 and then passed through a reflow furnace on the mounting electrode 10. It is fixed in a hemispherical form. Thereafter, the semiconductor element 9 is placed on the conductor bump 13 and passed through a reflow furnace, whereby the mounting electrode 10 and each circuit of the semiconductor element 9 are electrically connected. By injecting an underfill material 14 made of a thermosetting resin and a filler between the semiconductor element 9 and the surface of the wiring board 8, the conductor bumps 13 are protected and the semiconductor element 9 is applied to the wiring board 8. Firmly fixed.
[0038]
Thus, according to the semiconductor device 11 of the present invention, the mounting electrode 10 of the semiconductor element 9 electrically connected to the signal wiring 3 is provided on the surface of the wiring substrate 8, and the semiconductor element 9 is mounted on the mounting electrode 10. Since the signal wiring 3 and the rectangular opening 7 overlap on average when the wiring substrate 8 is viewed in plan, the characteristic impedance between the signal wirings 3 is Since the difference does not occur and the generation of reflection noise is suppressed, the semiconductor device 11 can stably transmit signals even in the high-frequency signal region.
[0039]
Note that the wiring board 8 and the semiconductor device 11 of the present invention are not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the scope of the present invention.
[0040]
【The invention's effect】
According to the wiring board of the present invention, the rectangular opening formed in the ground or power supply conductor layer with respect to the signal wiring formed by the wiring conductor extending in one direction and the wiring conductor extending in the direction of 45 degrees with respect to one direction is provided. Since the wiring board is arranged in a direction of 15 to 30 degrees, when the wiring board is viewed in plan, the signal wiring and the rectangular opening are overlapped on average, and there is no difference in characteristic impedance between the signal wirings. Therefore, it is possible to provide a wiring board in which the generation of reflection noise is suppressed and a signal is stably transmitted even in a high-frequency signal region.
[0041]
In addition, according to the wiring board of the present invention, one side of the opening of the rectangular opening is set to 0.10 to 0.15 mm and the interval between the openings is set to 0.3 to 0.6 mm. Crosstalk noise between signal wirings in the area can be reduced, and gas generated when the resin of the insulating layer hardens can be easily released. As a result, wiring that does not swell or peel off to the ground or power conductor layer It can be a substrate.
[0042]
Furthermore, according to the semiconductor device of the present invention, the semiconductor device mounting electrode is electrically connected to the signal wiring on the surface of the wiring board, and the semiconductor element electrode is electrically connected to the mounting electrode. Therefore, when the wiring board is viewed in plan, the signal wiring and the square opening are overlapped on average, and there is no difference in characteristic impedance between the signal wirings. As a result, generation of reflected noise occurs. A semiconductor device that is suppressed and can stably transmit signals even in a high-frequency signal region can be obtained.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an example of an embodiment of a semiconductor device in which a semiconductor element is mounted on a wiring board of the present invention.
FIG. 2 is a transparent plan view showing an example of the embodiment when the signal wiring, grounding, and power supply conductor layer of the wiring board of the present invention are viewed in plan.
[Explanation of symbols]
1 .... Insulating substrate 2 .... Insulating layer 3 .... Signal wiring
3a · 3b ··· Wiring conductor 4 ··· Ground conductor layer 5 ··· Power supply conductor layer 7 ······ Square opening 8 ···・ Wiring board 9 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Semiconductor element
10. ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Electrode for mounting
11 .... Semiconductor device

Claims (2)

一方向に伸びる配線導体および前記一方向に対して４５度の方向に伸びる配線導体で形成された信号配線と、該信号配線に絶縁層を介して対向配置され、格子状に配列された方形開口部を有する接地または電源導体層とを具備した配線基板であって、
前記方形開口部は、前記一方向に対して１５〜３０度の方向に配列されており、開口の一辺が０．１０〜０．１５ｍｍであるとともに前記開口間の間隔が０．３〜０．６ｍｍであることを特徴とする配線基板。A signal wiring formed of a wiring conductor extending in one direction and a wiring conductor extending in a direction of 45 degrees with respect to the one direction, and a rectangular opening arranged opposite to the signal wiring through an insulating layer and arranged in a lattice shape A wiring board having a ground or power supply conductor layer having a portion,
The rectangular openings are arranged in a direction of 15 to 30 degrees with respect to the one direction, one side of the opening is 0.10 to 0.15 mm, and a distance between the openings is 0.3 to 0.00. A wiring board characterized by being 6 mm . 請求項１記載の配線基板の表面に前記信号配線と電気的に接続された半導体素子の実装用電極を有するとともに、該実装用電極に前記半導体素子の電極を電気的に接続して成ることを特徴とする半導体装置。A wiring board for a semiconductor element electrically connected to the signal wiring is provided on the surface of the wiring board according to claim 1, and the electrode for the semiconductor element is electrically connected to the mounting electrode. A featured semiconductor device.
JP2001197518A 2001-06-28 2001-06-28 Wiring substrate and semiconductor device using the same Expired - Fee Related JP4540262B2 (en)

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JP4838006B2 (en) * 2006-02-21 2011-12-14 株式会社フジクラ Flexible printed wiring board
US7709962B2 (en) 2006-10-27 2010-05-04 Infineon Technologies Ag Layout structure having a fill element arranged at an angle to a conducting line
JP4922417B2 (en) * 2010-01-29 2012-04-25 株式会社東芝 Electronic equipment and circuit boards
WO2011132476A1 (en) * 2010-04-20 2011-10-27 株式会社 村田製作所 Electronic component with laminated substrate
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KR102632351B1 (en) * 2016-02-05 2024-02-02 삼성전기주식회사 Printed circuit board and package comprising the same
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CN115966547B (en) * 2021-09-17 2023-12-08 上海玻芯成微电子科技有限公司 Inductor and chip

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Publication number Priority date Publication date Assignee Title
JPH08506696A (en) * 1993-02-02 1996-07-16 エイ・エス・ティー・リサーチ・インコーポレイテッド Circuit board array including shield grid and structure thereof
JP2000114722A (en) * 1998-09-30 2000-04-21 Adtec:Kk Printed wiring device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08506696A (en) * 1993-02-02 1996-07-16 エイ・エス・ティー・リサーチ・インコーポレイテッド Circuit board array including shield grid and structure thereof
JP2000114722A (en) * 1998-09-30 2000-04-21 Adtec:Kk Printed wiring device

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