JP2003017613A - Circuit board and semiconductor device using the same - Google Patents

Circuit board and semiconductor device using the same

Info

Publication number
JP2003017613A
JP2003017613A JP2001197518A JP2001197518A JP2003017613A JP 2003017613 A JP2003017613 A JP 2003017613A JP 2001197518 A JP2001197518 A JP 2001197518A JP 2001197518 A JP2001197518 A JP 2001197518A JP 2003017613 A JP2003017613 A JP 2003017613A
Authority
JP
Japan
Prior art keywords
wiring
wiring board
conductor layer
signal
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001197518A
Other languages
Japanese (ja)
Other versions
JP4540262B2 (en
Inventor
Kenichiro Haruta
健一郎 春田
Takashi Inoue
貴志 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2001197518A priority Critical patent/JP4540262B2/en
Publication of JP2003017613A publication Critical patent/JP2003017613A/en
Application granted granted Critical
Publication of JP4540262B2 publication Critical patent/JP4540262B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a circuit board capable of reducing occurrence of a reflected noise by decreasing mismatches of characteristic impedances between signal wirings and having no bulge or no peeling of a ground or a power source conductor layer, and to provide a semiconductor device using the same. SOLUTION: The circuit board 8 comprises signal wirings 3 formed of wiring conductors 3a extended in one direction and wiring conductors 3b extended in a direction of 45 deg. to the one direction, and the ground or the power source conductor layer 5 disposed oppositely to the wirings 3 via an insulating layer 2 and having rectangular openings 7 arranged in a lattice state. In this case, the openings 7 are arranged in a direction of 15 to 30 deg. to the one direction.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子を搭載
するために用いられる配線基板およびこの配線基板に半
導体素子を搭載して成る半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board used for mounting a semiconductor element and a semiconductor device having the semiconductor element mounted on the wiring board.

【0002】[0002]

【従来の技術】一般に、現在の電子機器は、移動体通信
機器に代表されるように小型・薄型・軽量・高性能・高
機能・高品質・高信頼性が要求されてきており、このよ
うな電子機器に搭載される電子装置も小型・高密度化が
要求されるようになってきている。そのため、半導体装
置を構成する配線基板にも小型化・薄型化・多端子化が
求められてきており、それを実現するために信号配線等
の配線の幅を細くするとともにその間隔を狭くし、さら
に配線の多層化・配線間を接続する貫通導体の小径化に
より高密度化が図られている。
2. Description of the Related Art Generally, current electronic devices are required to be small, thin, lightweight, high-performance, high-performance, high-quality and highly reliable as represented by mobile communication devices. Electronic devices mounted on various electronic devices are also required to be small and have high density. Therefore, there is a demand for miniaturization, thinning, and multi-terminals in wiring boards that form semiconductor devices, and in order to achieve this, the widths of wirings such as signal wirings are narrowed and their intervals are narrowed. Further, the wiring density has been increased by increasing the number of wiring layers and the diameter of the through conductors connecting the wirings.

【0003】このような高密度配線が可能な配線基板と
して、ビルドアップ法を採用して製作された多層配線基
板が知られている。ビルドアップ法とは、例えば、ガラ
スクロスやアラミド不布織等の補強材に耐熱性や耐薬品
性を有するエポキシ樹脂に代表される熱硬化性樹脂を含
浸させて複合化した絶縁基板上に、間に配線導体を挟ん
でエポキシ樹脂等の熱硬化性樹脂から成る接着材を塗布
して絶縁層を形成するとともに絶縁層を加熱硬化させた
後、配線導体上部の絶縁層にレーザで径が50〜200μm
程度の貫通孔を形成し、しかる後、絶縁層表面を化学粗
化し、さらに無電解銅めっき法および電解銅めっき法を
用いて貫通孔側面および貫通孔底面の配線導体上に導体
膜を被着して貫通導体を形成するとともに絶縁層表面に
貫通導体と接続する配線導体を形成し、さらに、絶縁層
や貫通導体・配線導体の形成を複数回繰り返すことによ
り配線基板を製作する方法である。
As a wiring board capable of such high-density wiring, a multilayer wiring board manufactured by using a build-up method is known. The build-up method, for example, on a composite insulating substrate by impregnating a reinforcing material such as glass cloth or aramid non-woven fabric with a thermosetting resin typified by an epoxy resin having heat resistance and chemical resistance, After the wiring conductor is sandwiched between them, an adhesive made of a thermosetting resin such as epoxy resin is applied to form an insulating layer and the insulating layer is heated and hardened. ~ 200 μm
After forming through holes of a certain degree, the surface of the insulating layer is then chemically roughened, and a conductor film is deposited on the wiring conductors on the side surfaces of the through holes and the bottom surface of the through holes by electroless copper plating and electrolytic copper plating. Then, the through-hole conductor is formed, the wiring conductor connected to the through-hole conductor is formed on the surface of the insulating layer, and the formation of the insulating layer and the through-hole conductor / wiring conductor is repeated a plurality of times to manufacture the wiring board.

【0004】このような配線基板の配線導体は、用途に
よって、電源導体層・接地導体層および信号配線に機能
化されている。このうち電源導体層は、配線基板に実装
される半導体素子に電源を供給するために機能し、絶縁
層の略全面をめっきしたベタパターンの薄膜導体から構
成されている。また、信号配線は、電気信号を電磁波障
害なしに伝播させるために機能し、所定の回路形状にパ
ターン化した導体から構成されている。さらに、接地導
体層は、電源導体層や信号配線を流れる電流によって発
生する電磁波をシールドし、他の配線導体に生じるノイ
ズを防止するために機能し、電源導体層と同様に絶縁層
の略全面をめっきしたベタパターンの薄膜導体から構成
されている。すなわち、信号配線などから発生する電磁
波を、接地導体層で渦電流に変換することによってシー
ルドし、かかるシールド効果によって他の信号配線でノ
イズが発生しないように構成されている。
The wiring conductor of such a wiring board is functionalized as a power supply conductor layer / ground conductor layer and a signal wiring depending on the application. Of these, the power supply conductor layer functions to supply power to the semiconductor element mounted on the wiring board, and is composed of a solid pattern thin film conductor obtained by plating substantially the entire surface of the insulating layer. The signal wiring also functions to propagate an electric signal without electromagnetic interference, and is composed of a conductor patterned into a predetermined circuit shape. Further, the ground conductor layer functions to shield the electromagnetic waves generated by the current flowing through the power supply conductor layer and the signal wiring and prevent the noise generated in other wiring conductors. It is composed of a solid pattern thin film conductor plated with. That is, the electromagnetic wave generated from the signal wiring or the like is shielded by converting it into an eddy current in the ground conductor layer, and noise is not generated in other signal wiring due to the shielding effect.

【0005】このような役割を担う電源導体層・信号配
線および接地導体層は、それぞれ配線基板の表面に設け
られた外部電気回路接続用の実装用電極に貫通導体を介
して電気的に接続され、配線基板に実装される電子部品
への電力の供給・信号の伝達あるいは電磁波のシールド
を行うことができるような積層構造に配置されている。
The power supply conductor layer, the signal wiring, and the ground conductor layer, which play such a role, are electrically connected to the mounting electrodes for connecting an external electric circuit, which are provided on the surface of the wiring board, through through conductors. They are arranged in a laminated structure capable of supplying electric power to the electronic components mounted on the wiring board, transmitting signals, and shielding electromagnetic waves.

【0006】また、電源導体層および接地導体層のベタ
パターンには、絶縁層の樹脂が硬化する際に発生するガ
スを逃すために格子状に配列された方形開口部が設けら
れている。このような格子状に配列された方形開口部
は、配線基板を平面視した時に、電源導体層および接地
導体層の全面にわたって均一に配列されているとともに
信号配線と平行に配列されている。
Further, the solid patterns of the power supply conductor layer and the ground conductor layer are provided with rectangular openings arranged in a lattice shape so as to release gas generated when the resin of the insulating layer is cured. The rectangular openings arranged in a grid pattern are evenly arranged over the entire surface of the power supply conductor layer and the ground conductor layer and are arranged in parallel with the signal wiring when the wiring board is viewed in plan.

【0007】[0007]

【発明が解決しようとする課題】しかしながら従来の配
線基板では、これを平面視した時に、格子状に配列され
た方形開口部と信号配線とが平行に配列されているの
で、信号配線によっては、絶縁層を介して対向配置され
た開口部と重なって形成されたりあるいは開口部と重な
らずに形成され、各信号配線間で特性インピーダンスが
異なってしまい、高周波領域で特性インピーダンスの不
整合による反射ノイズが発生し搭載する半導体素子が誤
作動してしまうという問題点を有していた。
However, in the conventional wiring board, the rectangular openings arranged in a lattice and the signal wirings are arranged in parallel when viewed in a plan view. Therefore, depending on the signal wiring, Reflection due to mismatch of characteristic impedance in high frequency region due to characteristic impedance difference between each signal wiring, which is formed to overlap with the opening arranged oppositely through the insulating layer or not to overlap with the opening. There is a problem that noise is generated and a semiconductor element mounted is malfunctioning.

【0008】また、従来の配線基板は、その開口部が大
きすぎるとベタパターンによるシールド効果が小さくな
り、信号の漏れによるクロストークノイズが発生してし
まい、逆に開口部が小さすぎると絶縁層の樹脂が硬化す
る際に発生するガスが容易に抜けず、接地または電源導
体層が膨れたり剥れたりしまうという問題点を有してい
た。
Further, in the conventional wiring board, if the opening is too large, the shield effect due to the solid pattern becomes small, and crosstalk noise occurs due to signal leakage. On the contrary, if the opening is too small, the insulating layer is formed. There is a problem in that the gas generated when the resin is cured does not easily escape and the ground or power supply conductor layer swells or peels off.

【0009】本発明は、かかる従来技術の問題点に鑑み
完成されたものであり、その目的は、各信号配線間の特
性インピーダンスの不整合を小さくして反射ノイズの発
生を低減するとともに、接地または電源導体層の膨れや
剥れのない配線基板およびそれを用いた半導体装置を提
供するものである。
The present invention has been completed in view of the problems of the prior art, and an object thereof is to reduce the occurrence of reflection noise by reducing the mismatch of the characteristic impedance between the signal wirings and to ground. Another object of the present invention is to provide a wiring board in which the power supply conductor layer is not swollen or peeled off, and a semiconductor device using the wiring board.

【0010】[0010]

【課題を解決するための手段】本発明の配線基板は、一
方向に伸びる配線導体および一方向に対して45度の方向
に伸びる配線導体で形成された信号配線と、この信号配
線に絶縁層を介して対向配置され、格子状に配列された
方形開口部を有する接地または電源導体層とを具備した
配線基板であって、方形開口部は、前記一方向に対して
15〜30度の方向に配列されていることを特徴とするもの
である。
A wiring board according to the present invention comprises a signal wiring formed by a wiring conductor extending in one direction and a wiring conductor extending in a direction of 45 degrees with respect to one direction, and an insulating layer on the signal wiring. And a grounding or power supply conductor layer having square openings arranged in a grid pattern, the square openings being provided with respect to the one direction.
It is characterized by being arranged in the direction of 15 to 30 degrees.

【0011】また、本発明の配線基板は、方形開口部の
開口の一辺が0.10〜0.15mmであるとともに開口間の間
隔が0.3〜0.6mmであることを特徴とするものである。
Further, the wiring board of the present invention is characterized in that one side of the opening of the rectangular opening is 0.10 to 0.15 mm and the interval between the openings is 0.3 to 0.6 mm.

【0012】さらに、本発明の半導体装置は、上記の配
線基板の表面に信号配線と電気的に接続された半導体素
子の実装用電極を有するとともに、この実装用電極に半
導体素子の電極を電気的に接続して成ることを特徴とす
るものである。
Further, the semiconductor device of the present invention has a mounting electrode for the semiconductor element electrically connected to the signal wiring on the surface of the wiring board, and the electrode for the semiconductor element is electrically connected to this mounting electrode. It is characterized by being connected to.

【0013】本発明の配線基板によれば、一方向に伸び
る配線導体および一方向に対して45度の方向に伸びる配
線導体で形成された信号配線に対して接地または電源導
体層に形成した方形開口部を15〜30度の方向に配列した
ことから、配線基板を平面視した時、信号配線と方形開
口部とが平均的に重ね合わさり各信号配線間で特性イン
ピーダンスの差が生じることはなく、その結果、反射ノ
イズの発生が抑制され、高周波信号領域でも安定して信
号が伝達される配線基板とすることができる。
According to the wiring board of the present invention, a square formed on the ground or power supply conductor layer for the signal wiring formed by the wiring conductor extending in one direction and the wiring conductor extending in the direction of 45 degrees with respect to one direction. Since the openings are arranged in the direction of 15 to 30 degrees, when the wiring board is viewed in plan, the signal wiring and the rectangular opening do not overlap with each other evenly, and there is no difference in characteristic impedance between the signal wirings. As a result, it is possible to obtain a wiring board in which the generation of reflection noise is suppressed and signals are stably transmitted even in a high frequency signal region.

【0014】また、本発明の配線基板によれば、方形開
口部の開口の一辺を0.10〜0.15mmとするとともに開口
間の間隔を0.3〜0.6mmとしたことから、接地および電
源導体層のシールド効果で高周波領域における信号配線
間のクロストークノイズが低減できるとともに、絶縁層
の樹脂が硬化する際に発生するガスを容易に逃がすこと
ができ、その結果、接地または電源導体層に膨れや剥れ
のない配線基板とすることができる。
Further, according to the wiring board of the present invention, one side of the opening of the rectangular opening is set to 0.10 to 0.15 mm and the interval between the openings is set to 0.3 to 0.6 mm. As a result, crosstalk noise between signal wires in the high frequency range can be reduced, and the gas generated when the resin in the insulating layer cures can be easily released, resulting in swelling or peeling of the ground or power supply conductor layer. It is possible to make a wiring board without a wiring board.

【0015】さらに、本発明の半導体装置によれば、上
記の配線基板の表面に信号配線と電気的に接続された半
導体素子の実装用電極を有するとともに、実装用電極に
半導体素子の電極を電気的に接続して成ることから、配
線基板を平面視した時に、信号配線と方形開口部とが平
均的に重ね合わさり各信号配線間で特性インピーダンス
の差が生じることはなく、その結果、反射ノイズの発生
が抑制され、高周波信号領域でも安定的に信号が伝達さ
れる半導体装置とすることができる。
Further, according to the semiconductor device of the present invention, a mounting electrode for the semiconductor element electrically connected to the signal wiring is provided on the surface of the wiring board, and the electrode for the semiconductor element is electrically connected to the mounting electrode. The signal wiring and the rectangular opening do not overlap each other evenly when the wiring board is viewed in plan, and there is no difference in the characteristic impedance between the signal wirings. It is possible to provide a semiconductor device in which the occurrence of noise is suppressed and a signal is stably transmitted even in a high frequency signal region.

【0016】[0016]

【発明の実施の形態】次に、本発明の配線基板およびこ
れを用いた半導体装置を添付の図面に基づいて詳細に説
明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a wiring board of the present invention and a semiconductor device using the same will be described in detail with reference to the accompanying drawings.

【0017】図1は、本発明の配線基板に半導体素子を
搭載して成る半導体装置の実施の形態の一例を示す断面
図であり、図2は、本発明の配線基板の信号配線と接地
導体層とを平面視した時の実施の形態の一例を示す透過
平面図である。なお、図2の接地導体層は、電源導体層
であってもよい。
FIG. 1 is a sectional view showing an example of an embodiment of a semiconductor device in which a semiconductor element is mounted on a wiring board of the present invention, and FIG. 2 is a signal wiring and a ground conductor of the wiring board of the present invention. FIG. 3 is a transparent plan view showing an example of an embodiment when a layer and a layer are viewed in a plan view. The ground conductor layer in FIG. 2 may be a power conductor layer.

【0018】これらの図において、1は絶縁基板、2は
絶縁層、3は信号配線、4は接地導体層、5は電源導体
層、6は貫通導体、7は方形開口部で、主にこれらで本
発明の配線基板8が構成される。また、この配線基板8
に半導体素子9を搭載し、実装用電極10と半導体素子9
の電極とを電気的に接続することにより本発明の半導体
装置11と成る。なお、本発明の配線基板8の接地導体層
4および電源導体層5には、格子状に配列された方形開
口部7が形成されている。
In these figures, 1 is an insulating substrate, 2 is an insulating layer, 3 is signal wiring, 4 is a ground conductor layer, 5 is a power conductor layer, 6 is a through conductor, and 7 is a square opening. The wiring board 8 of the present invention is constituted by. Also, this wiring board 8
The semiconductor element 9 is mounted on the mounting electrode 10 and the semiconductor element 9
The semiconductor device 11 of the present invention is formed by electrically connecting the electrodes of the above. The ground conductor layer 4 and the power conductor layer 5 of the wiring board 8 of the present invention are formed with the rectangular openings 7 arranged in a grid pattern.

【0019】配線基板8は、半導体素子9の支持部材と
しての機能を有し、絶縁基板1の表面および/または裏
面の主面に複数の絶縁層2が積層されている 配線基板8を構成する絶縁基板1は、絶縁層2の支持体
としての機能を有し、例えばガラスクロス−エポキシ樹
脂やガラスクロス−ビスマレイミドトリアジン樹脂・ガ
ラスクロス−ポリフェニレンエーテル樹脂・アラミド繊
維−エポキシ樹脂等から成り、常法により製作される。
また、絶縁基板1の主面には、電源導体層5等の導体層
が被着形成されており、これらの導体層は、絶縁基板1
内部に形成されたスルーホール導体15で電気的に接続さ
れている。さらに、絶縁基板1の主面には、銅や金・ニ
ッケル・アルミニウム等の金属薄膜からなる信号配線3
や接地導体層4・電源導体層5が絶縁層3を介して積層
されている。
The wiring board 8 has a function as a support member for the semiconductor element 9, and constitutes the wiring board 8 in which a plurality of insulating layers 2 are laminated on the main surface of the insulating substrate 1 on the front surface and / or the back surface. The insulating substrate 1 has a function as a support for the insulating layer 2, and is made of, for example, glass cloth-epoxy resin or glass cloth-bismaleimide triazine resin / glass cloth-polyphenylene ether resin / aramid fiber-epoxy resin. It is manufactured by the method.
Further, conductor layers such as the power supply conductor layer 5 are adhered and formed on the main surface of the insulating substrate 1, and these conductor layers are formed on the insulating substrate 1.
It is electrically connected by a through-hole conductor 15 formed inside. Furthermore, on the main surface of the insulating substrate 1, signal wiring 3 made of a metal thin film of copper, gold, nickel, aluminum, etc.
The ground conductor layer 4 and the power supply conductor layer 5 are laminated with the insulating layer 3 in between.

【0020】絶縁層2は、信号配線3や接地導体層4・
電源導体層5を支持する支持部材として機能し、例えば
エポキシ樹脂やビスマレイミドトリアジン樹脂・ポリフ
ェニレンエーテル樹脂等の熱硬化性樹脂とエラストマー
と無機絶縁性フィラーとから成る。なお、信号配線3や
接地導体層4・電源導体層5等の金属薄膜との密着性を
良好となすために、表面を粗化できる熱可塑性樹脂成分
も含有してもよい。
The insulating layer 2 includes the signal wiring 3 and the ground conductor layer 4.
It functions as a support member that supports the power supply conductor layer 5, and is made of, for example, a thermosetting resin such as an epoxy resin, a bismaleimide triazine resin or a polyphenylene ether resin, an elastomer, and an inorganic insulating filler. A thermoplastic resin component capable of roughening the surface may also be contained in order to improve the adhesion to the metal thin film such as the signal wiring 3, the ground conductor layer 4, and the power conductor layer 5.

【0021】このような絶縁層2は、例えばエポキシ樹
脂と熱可塑性樹脂・エラストマー・無機絶縁性フィラー
に溶剤等を添加した混合物を混練して液状ワニスを得、
この液状ワニスをポリエチレンテレフタレート(PE
T)製離型シート上に塗布し、60〜100℃の温度で乾燥
することによりフィルム状に成形される。また、絶縁層
2には、炭酸ガスレーザやYAGレーザ・UVレーザ等
の従来周知のレーザを用いて直径が30〜300μm程度の
貫通孔が形成されるとともに、その内部に銅や金・ニッ
ケル・アルミニウム等の金属薄膜を被着して、信号配線
3同士を電気的に接続する貫通導体6が形成されてい
る。なお、絶縁層2となる乾燥後のフィルムは、エラス
トマーを含有することから、フィルム上面にポリエチレ
ンシートを積層し、ロール状に巻き取ることにより容易
に貯蔵できる。また、フィルムの厚さは自由に設定する
ことができるが、絶縁性の観点からは20〜100μmの範
囲の厚さが好ましい。そして、絶縁層2は、このフィル
ムを絶縁基板1表面に真空ラミネータを用いて圧着し、
オーブンで熱硬化することにより積層される。
For such an insulating layer 2, for example, a liquid varnish is obtained by kneading a mixture of an epoxy resin, a thermoplastic resin, an elastomer, and an inorganic insulating filler to which a solvent is added.
Polyethylene terephthalate (PE
T) A release sheet is applied and dried at a temperature of 60 to 100 ° C to form a film. Further, the insulating layer 2 is formed with a through hole having a diameter of about 30 to 300 μm by using a well-known laser such as a carbon dioxide laser, a YAG laser or a UV laser, and copper, gold, nickel, aluminum is formed inside the through hole. The through conductor 6 for electrically connecting the signal wirings 3 to each other is formed by depositing a metal thin film such as. Since the dried film to be the insulating layer 2 contains an elastomer, it can be easily stored by laminating a polyethylene sheet on the upper surface of the film and winding it into a roll. The thickness of the film can be set freely, but from the viewpoint of insulation, a thickness in the range of 20 to 100 μm is preferable. The insulating layer 2 is formed by pressing the film onto the surface of the insulating substrate 1 using a vacuum laminator.
It is laminated by thermosetting in an oven.

【0022】また、絶縁層2表面には、信号配線3やベ
タパターンの接地導体層4・電源導体層5が形成され、
これらは貫通導体6で電気的に接続されている。このよ
うな信号配線3や接地導体層4・電源導体層5は、配線
基板8に搭載される半導体素子9を外部電気回路基板
(図示せず)に電気的に接続する導電路としての機能を
有する。また、信号配線3は、その幅が20〜100μmで
あり、配線設計のし易さとその屈曲部でのクラック防止
のため、一方向に伸びる配線導体3aおよび一方向に対
して45度の方向に伸びる配線導体3bで形成されてい
る。一方、ベタパターンの接地導体層4や電源導体層5
には、絶縁層2の樹脂が硬化する際に発生するガスを逃
すために、および絶縁層2同士の密着性を向上させるた
めに多数の格子状に配列された方形開口部7が形成され
ている。
On the surface of the insulating layer 2, the signal wiring 3, the solid conductor ground conductor layer 4 and the power conductor conductor layer 5 are formed.
These are electrically connected by a through conductor 6. The signal wiring 3, the ground conductor layer 4, and the power supply conductor layer 5 function as a conductive path that electrically connects the semiconductor element 9 mounted on the wiring board 8 to an external electric circuit board (not shown). Have. Further, the signal wiring 3 has a width of 20 to 100 μm, and in order to facilitate wiring design and prevent cracks at the bent portions, the wiring conductor 3a extends in one direction and the wiring conductor 3a extends in a direction of 45 degrees with respect to one direction. It is formed by the extending wiring conductor 3b. On the other hand, a solid ground conductor layer 4 and a power conductor layer 5
In order to escape the gas generated when the resin of the insulating layer 2 is cured and to improve the adhesion between the insulating layers 2, a large number of square openings 7 arranged in a lattice are formed. There is.

【0023】信号配線3や接地導体層4・電源導体層5
・貫通導体6を形成する金属材料としては、電気抵抗値
が低いという観点からは銅や金・ニッケル・アルミニウ
ム等の金属が好ましく、安価という観点からは銅が好ま
しい。なお、銅や金・ニッケル・アルミニウム等から成
る金属薄膜の厚みは、高速の信号を伝達させるという観
点からは3μm以上であることが好ましく、金属薄膜を
絶縁基板1や絶縁層2に被着形成する際に金属薄膜に大
きな応力を残留させず、金属薄膜が絶縁基板1や絶縁層
2から剥離しにくいものとするためには50μm以下とし
ておくことが好ましい。
Signal wiring 3, ground conductor layer 4 and power conductor layer 5
As the metal material forming the through conductor 6, a metal such as copper or gold, nickel, aluminum or the like is preferable from the viewpoint of low electric resistance value, and copper is preferable from the viewpoint of low cost. The thickness of the metal thin film made of copper, gold, nickel, aluminum or the like is preferably 3 μm or more from the viewpoint of transmitting a high-speed signal, and the metal thin film is adhered to the insulating substrate 1 or the insulating layer 2. In order to prevent a large stress from remaining in the metal thin film and prevent the metal thin film from peeling off from the insulating substrate 1 or the insulating layer 2 at the time of being formed, the thickness is preferably 50 μm or less.

【0024】このような金属薄膜は、次に述べる方法に
より形成される。まず、絶縁層2の所望の個所に、例え
ば炭酸レーザを用いて貫通孔を形成した後に、絶縁層2
の表面および貫通孔内壁を過マンガン酸塩類水溶液等の
粗化液に浸漬して粗化する。次に、絶縁層2の表面およ
び貫通孔内壁を無電解めっきの触媒と成る例えばパラジ
ウムの水溶液中に浸漬して絶縁層2表面と貫通孔内壁に
触媒を被着させ、さらに、硫酸銅・ロッセル塩・ホルマ
リン・EDTAナトリウム塩・安定剤等から成る無電解
めっき液に約30分間浸漬して、数μmの無電解銅めっき
膜を析出させる。そして次に、絶縁層2の表面に感光性
ドライフィルムレジストをラミネートし露光と現像によ
り薄膜導体と成る所定の配線パターンを形成し、しかる
後に、硫酸・硫酸銅5水和物・塩素・光沢剤等から成る
電解銅めっき液に数A/dm2の電流を印加しながら数
時間浸漬することにより貫通導体6が貫通孔の内壁や内
部に形成される。さらにまた、水酸化ナトリウムを用い
て感光性ドライフィルムレジストを剥離し、しかる後、
硫酸・過酸化水素水溶液でめっき膜表面をエッチングす
ることにより、絶縁層2の表面に信号配線3や格子状に
配列された方形開口部7を有する接地導体層4・電源導
体層5が形成される。
Such a metal thin film is formed by the method described below. First, a through hole is formed at a desired portion of the insulating layer 2 by using, for example, a carbon dioxide laser, and then the insulating layer 2 is formed.
The surface and the inner wall of the through-hole are roughened by immersing them in a roughening liquid such as an aqueous solution of permanganates. Next, the surface of the insulating layer 2 and the inner wall of the through hole are immersed in an aqueous solution of palladium, which serves as a catalyst for electroless plating, to deposit the catalyst on the surface of the insulating layer 2 and the inner wall of the through hole, and further, copper sulfate / Rosell Immerse in an electroless plating solution consisting of salt, formalin, EDTA sodium salt, stabilizer, etc. for about 30 minutes to deposit an electroless copper plating film of several μm. Then, a photosensitive dry film resist is laminated on the surface of the insulating layer 2 to form a predetermined wiring pattern to be a thin film conductor by exposure and development, and thereafter, sulfuric acid, copper sulfate pentahydrate, chlorine, and a brightening agent. The through conductor 6 is formed on the inner wall or the inside of the through hole by immersing the electrolytic copper plating solution including the above for several hours while applying a current of several A / dm 2 . Furthermore, the photosensitive dry film resist is peeled off using sodium hydroxide, and then,
By etching the surface of the plating film with an aqueous solution of sulfuric acid / hydrogen peroxide, the ground conductor layer 4 and the power conductor layer 5 having the signal wirings 3 and the rectangular openings 7 arranged in a grid pattern are formed on the surface of the insulating layer 2. It

【0025】そして、このような信号配線3や接地導体
層4・電源導体層5・貫通導体6を形成した絶縁層2の
上面に、絶縁層2を積層するとともに上記と同じ工程を
繰り返して信号配線3や接地導体層4・電源導体層5・
貫通導体6を形成し、さらにこれを複数回繰り返すこと
により絶縁層2が複数積層される。
Then, the insulating layer 2 is laminated on the upper surface of the insulating layer 2 on which the signal wiring 3, the ground conductor layer 4, the power source conductor layer 5, and the through conductor 6 are formed, and the same steps as described above are repeated to repeat the signal. Wiring 3, ground conductor layer 4, power supply conductor layer 5,
A plurality of insulating layers 2 are laminated by forming the penetrating conductor 6 and repeating this a plurality of times.

【0026】なお、本発明の配線基板8において、信号
配線3と接地導体層4または電源導体層5とは対に成る
ように設計されており、信号配線3の上下には絶縁層2
を介して接地導体層4または電源導体層5が配置されて
いる。
In the wiring board 8 of the present invention, the signal wiring 3 and the ground conductor layer 4 or the power supply conductor layer 5 are designed to form a pair, and the insulating layer 2 is formed above and below the signal wiring 3.
The ground conductor layer 4 or the power supply conductor layer 5 is arranged via the.

【0027】本発明の配線基板8においては、接地導体
層4または電源導体層5の格子状に配列された方形開口
部7が、一方向に伸びる配線導体3a・3bに対して15
〜30度の方向に配列されている。また、このことが重要
である。なお、ここで一方向に伸びる配線導体3a・3
bに対して15〜30度の方向とは、例えば、配線導体3a
に対しては配線導体3bと同じ方向で15〜30度の範囲で
あり、配線導体3bに対しては配線導体3aと同じ方向
で15〜30度の範囲を示している。
In the wiring board 8 of the present invention, the rectangular openings 7 arranged in the grid pattern of the ground conductor layer 4 or the power conductor layer 5 are arranged at 15 positions with respect to the wiring conductors 3a and 3b extending in one direction.
They are arranged in the direction of ~ 30 degrees. This is also important. Here, the wiring conductors 3a, 3 extending in one direction
The direction of 15 to 30 degrees with respect to b is, for example, the wiring conductor 3a.
Shows a range of 15 to 30 degrees in the same direction as the wiring conductor 3b, and shows a range of 15 to 30 degrees in the same direction as the wiring conductor 3a for the wiring conductor 3b.

【0028】本発明の配線基板8によれば、格子状に配
列された方形開口部7が、一方向に伸びる配線導体3a
・3bに対して15〜30度の方向に配列されていることか
ら、配線基板8を平面視した時、信号配線3と方形開口
部7とが平均的に重ね合わさり各信号配線3間で特性イ
ンピーダンスの差が生じることはなく、その結果、反射
ノイズの発生が抑制され、高周波信号領域でも安定して
信号が伝達される配線基板8とすることができる。な
お、格子状に配列された方形開口部7が、一方向に伸び
る配線導体3a・3bに対して15度より小さい角度の方
向あるいは30度より大きい角度の方向に配列されている
と、信号配線3と方形開口部7との重なりにバラツキが
生じ、各信号配線3間で特性インピーダンスの値が大き
く異ってしまい、高周波領域で特性インピーダンスの不
整合による反射ノイズが発生し半導体素子が誤作動して
しまう傾向がある。従って、格子状に配列された方形開
口部7は、一方向に伸びる配線導体3a・3bに対して
15〜30度の方向に配列されていることが好ましい。
According to the wiring board 8 of the present invention, the rectangular openings 7 arranged in a lattice form extend in one direction.
Since they are arranged in the direction of 15 to 30 degrees with respect to 3b, when the wiring board 8 is viewed in plan, the signal wiring 3 and the rectangular opening 7 are superposed on each other evenly, and the characteristics between the respective signal wirings 3 are increased. There is no difference in impedance, and as a result, the generation of reflection noise is suppressed, and the wiring board 8 can be provided in which signals are stably transmitted even in the high frequency signal region. If the square openings 7 arranged in a grid pattern are arranged in an angle direction smaller than 15 degrees or larger than 30 degrees with respect to the wiring conductors 3a and 3b extending in one direction, the signal wiring is 3 and the rectangular opening 7 are unevenly overlapped, the value of the characteristic impedance is greatly different between the signal wirings 3, reflection noise is generated due to the characteristic impedance mismatch in the high frequency region, and the semiconductor element malfunctions. Tend to do. Therefore, the rectangular openings 7 arranged in a grid pattern are arranged with respect to the wiring conductors 3a and 3b extending in one direction.
It is preferably arranged in the direction of 15 to 30 degrees.

【0029】なお、ここで反射ノイズとは、特性インピ
ーダンスの不整合により電圧反射が生じることにより信
号配線3の波形が階段的に乱れる現象であり、特に、高
周波領域では、小さな特性インピーダンスの不整合でも
反射ノイズが生じ易く、これにより配線基板8に搭載さ
れている半導体素子9が誤作動することがある。
Here, the reflection noise is a phenomenon in which the waveform of the signal wiring 3 is stepwise disturbed due to the voltage reflection caused by the mismatch of the characteristic impedance, and in particular, in the high frequency region, the mismatch of the small characteristic impedance is caused. However, reflection noise is likely to occur, which may cause the semiconductor element 9 mounted on the wiring board 8 to malfunction.

【0030】さらに、本発明の配線基板8においては、
方形開口部7の開口の一辺が、0.10〜0.15mmであると
ともに開口間の間隔が0.3〜0.6mmであることが好まし
い。また、このことが重要である。
Further, in the wiring board 8 of the present invention,
It is preferable that one side of the opening of the rectangular opening 7 is 0.10 to 0.15 mm and the interval between the openings is 0.3 to 0.6 mm. This is also important.

【0031】本発明の配線基板8によれば、方形開口部
7の開口の一辺を0.10〜0.15mmとするとともに開口間
の間隔を0.3〜0.6mmとしたことから、接地導体層4お
よび電源導体層5のシールド効果で高周波領域における
信号配線3間のクロストークノイズが低減できるととも
に、絶縁層2の樹脂が硬化する際に発生するガスも容易
に逃がすことができ、その結果、接地導体層4または電
源導体層5に膨れや剥れの発生することのない配線基板
8とすることができる。
According to the wiring board 8 of the present invention, one side of the opening of the rectangular opening 7 is set to 0.10 to 0.15 mm and the interval between the openings is set to 0.3 to 0.6 mm. Cross-talk noise between the signal wirings 3 in the high frequency region can be reduced by the shielding effect of the layer 5, and the gas generated when the resin of the insulating layer 2 is cured can be easily released, and as a result, the ground conductor layer 4 Alternatively, the wiring board 8 can be obtained in which the power supply conductor layer 5 does not swell or peel off.

【0032】なお、方形開口部7の開口の一辺が、0.10
mmより小さいと絶縁層2の樹脂が硬化する際に発生す
るガスが絶縁層2から容易に抜けず、接地導体層4また
は電源導体層5が膨れたり剥れたりしてしまう傾向があ
り、0.15mmより大きいと接地導体層4または電源導体
層5のシールド効果が小さくなり、クロストークノイズ
が発生し半導体素子9が誤作動してしまう危険性があ
る。従って、方形開口部7の開口の一辺は、0.10〜0.15
mmであることが好ましい。また、開口間の間隔が0.3
mm未満であると、接地導体層4または電源導体層5と
信号配線3とが重なる部分が増加し、接地導体層4およ
び電源導体層5のシールド効果が小さくなりクロストー
クノイズが発生して半導体素子9が誤作動してしまう傾
向にあり、0.6mmより大きいと方形開口部7の数が少
なくなり、絶縁層2の樹脂が硬化する際に発生するガス
が絶縁層2から容易に抜けず、接地導体層4または電源
導体層5が膨れたり剥れたりしてしまう傾向にある。従
って、方形開口部7の開口間の間隔は、0.3〜0.6mmで
あることが好ましい。
One side of the opening of the rectangular opening 7 is 0.10.
If it is smaller than mm, the gas generated when the resin of the insulating layer 2 is cured does not easily escape from the insulating layer 2 and the ground conductor layer 4 or the power conductor layer 5 tends to swell or peel off. If it is larger than mm, the shield effect of the ground conductor layer 4 or the power conductor layer 5 becomes small, and there is a risk that crosstalk noise occurs and the semiconductor element 9 malfunctions. Therefore, one side of the opening of the rectangular opening 7 is 0.10 to 0.15.
It is preferably mm. Also, the spacing between the openings is 0.3
If it is less than mm, the portion where the ground conductor layer 4 or the power supply conductor layer 5 and the signal wiring 3 overlap with each other increases, the shield effect of the ground conductor layer 4 and the power supply conductor layer 5 becomes small, and crosstalk noise occurs, which causes semiconductors. The element 9 tends to malfunction, and if it is larger than 0.6 mm, the number of the rectangular openings 7 becomes small, and the gas generated when the resin of the insulating layer 2 is cured does not easily escape from the insulating layer 2. The ground conductor layer 4 or the power supply conductor layer 5 tends to swell or peel off. Therefore, the distance between the openings of the rectangular openings 7 is preferably 0.3 to 0.6 mm.

【0033】なお、クロストークノイズとは、信号が容
量結合や誘電結合により他の信号配線へ誘起されて生じ
る現象であり、本発明においては、信号配線3の上下に
は絶縁層2を介して接地導体層4または電源導体層5を
配置しているので、信号配線3から発生する電磁波を、
接地導体層4または電源導体層5で渦電流に変換するこ
とによってシールドし、かかるシールド効果によって他
の信号配線3でノイズが発生しないようにしている。
Crosstalk noise is a phenomenon that occurs when a signal is induced in another signal wiring by capacitive coupling or dielectric coupling, and in the present invention, the insulating layer 2 is provided above and below the signal wiring 3. Since the ground conductor layer 4 or the power conductor layer 5 is arranged, the electromagnetic wave generated from the signal wiring 3
The grounding conductor layer 4 or the power supply conductor layer 5 converts the eddy current to shield it, and the shielding effect prevents the other signal wiring 3 from generating noise.

【0034】かくして、本発明の配線基板8によれば、
方形開口部7の開口の一辺を0.10〜0.15mmとするとと
もに開口間の間隔を0.3〜0.6mmとしたことから、接地
導体層4および電源導体層5のシールド効果で高周波領
域における信号配線3間のクロストークノイズが低減で
きるとともに、絶縁層の樹脂が硬化する際に発生するガ
スを絶縁層2から容易に逃がすことができ、接地導体層
4または電源導体層5に膨れや剥れのない配線基板8と
することができる。
Thus, according to the wiring board 8 of the present invention,
Since the side of the opening of the rectangular opening 7 is set to 0.10 to 0.15 mm and the interval between the openings is set to 0.3 to 0.6 mm, the shielding effect of the ground conductor layer 4 and the power supply conductor layer 5 causes a gap between the signal wirings 3 in the high frequency region. The crosstalk noise can be reduced, and the gas generated when the resin of the insulating layer is cured can be easily escaped from the insulating layer 2, so that the ground conductor layer 4 or the power conductor layer 5 does not swell or peel off. It can be the substrate 8.

【0035】なお、配線基板8に半導体素子9を実装す
る際の熱履歴から絶縁層2および実装用電極10を保護す
るために、絶縁層2の最外層表面に感光性樹脂から成る
耐半田樹脂層12を被着形成してもよい。また、この場
合、耐半田樹脂層12の実装用電極10上部には露光・現像
により実装用電極10と半導体素子9の電極とを接続する
導体バンプ13用の開口が形成される。さらに、開口底の
実装用電極10表面にニッケル・金等の良導電性で耐腐蝕
性に優れた金属をめっき法により1〜20μmの厚さに被
着させておくと、実装用電極10表面の酸化腐食を有効に
防止できるとともに実装用電極10と導体バンプ13との接
続を良好とすることができる。
Incidentally, in order to protect the insulating layer 2 and the mounting electrode 10 from the heat history when the semiconductor element 9 is mounted on the wiring board 8, a solder resistant resin made of a photosensitive resin is formed on the outermost surface of the insulating layer 2. Layer 12 may be deposited. Further, in this case, an opening for the conductor bump 13 for connecting the mounting electrode 10 and the electrode of the semiconductor element 9 is formed on the mounting electrode 10 of the solder-resistant resin layer 12 by exposure and development. Furthermore, when a metal having good conductivity and excellent corrosion resistance such as nickel and gold is deposited on the surface of the mounting electrode 10 at the bottom of the opening by plating to a thickness of 1 to 20 μm, the surface of the mounting electrode 10 It is possible to effectively prevent the above-mentioned oxidative corrosion and to improve the connection between the mounting electrode 10 and the conductor bump 13.

【0036】また、本発明の半導体装置11は、配線基板
8表面の実装用電極10と半導体素子9の電極とを導体バ
ンプ13を介して電気的に接続することによって形成され
る。なお、実装用電極10上に被着された耐半田樹脂層12
の開口の形状は円形状であることが望ましく、さらに、
それらの径はフィリップチップ側が50〜300μm、ボー
ルグリッドアレイ側が300〜800μmの範囲とすることが
好ましい。
Further, the semiconductor device 11 of the present invention is formed by electrically connecting the mounting electrodes 10 on the surface of the wiring substrate 8 and the electrodes of the semiconductor element 9 via the conductor bumps 13. Note that the solder-resistant resin layer 12 deposited on the mounting electrode 10
It is desirable that the shape of the opening is circular, and
It is preferable that their diameters are in the range of 50 to 300 μm on the Philip chip side and 300 to 800 μm on the ball grid array side.

【0037】導体バンプ13は、実装用電極10と半導体素
子9の各電極とを電気的に接続する機能を有し、配線基
板8表面の実装用電極10上に半田等の金属により形成さ
れている。このような導体バンプ13は、金や鉛−錫・錫
−亜鉛・錫−銀−ビスマス等の合金の導電材料から成
り、例えば導電材料が鉛−錫から成る半田の場合、鉛−
錫から成るぺーストを耐半田樹脂層12の開口にスクリー
ン印刷法によって印刷、あるいは鉛−錫から成る半田ボ
ールを耐半田樹脂層12の開口に載置した後、リフロー炉
を通すことによって実装用電極10上に半球状に固着形成
される。しかる後、半導体素子9を導体バンプ13上に載
置し、リフロー炉を通すことによって実装用電極10と半
導体素子9の各回路とが電気的に接続される。なお、半
導体素子9と配線基板8表面との間に、熱硬化性樹脂と
フィラーとから成るアンダーフィル材14を注入すること
によって、導体バンプ13が保護されるとともに半導体素
子9が配線基板8に強固に固着される。
The conductor bump 13 has a function of electrically connecting the mounting electrode 10 and each electrode of the semiconductor element 9, and is formed of a metal such as solder on the mounting electrode 10 on the surface of the wiring board 8. There is. Such a conductive bump 13 is made of a conductive material such as gold or an alloy such as lead-tin, tin-zinc, tin-silver-bismuth. For example, when the conductive material is lead-tin solder, the lead-
A paste made of tin is printed on the opening of the solder resistant resin layer 12 by screen printing, or a solder ball made of lead-tin is placed on the opening of the solder resistant resin layer 12 and then passed through a reflow oven for mounting. It is fixedly formed on the electrode 10 in a hemispherical shape. Thereafter, the semiconductor element 9 is placed on the conductor bumps 13 and passed through a reflow furnace, so that the mounting electrode 10 and each circuit of the semiconductor element 9 are electrically connected. By injecting an underfill material 14 composed of a thermosetting resin and a filler between the semiconductor element 9 and the surface of the wiring board 8, the conductor bumps 13 are protected and the semiconductor element 9 is placed on the wiring board 8. It is firmly fixed.

【0038】かくして、本発明の半導体装置11によれ
ば、上記の配線基板8の表面に信号配線3と電気的に接
続された半導体素子9の実装用電極10を有するととも
に、実装用電極10に半導体素子9の電極を電気的に接続
して成ることから、配線基板8を平面視した時に、信号
配線3と方形開口部7とが平均的に重なっていることか
ら、各信号配線3間で特性インピーダンスの差が生じ
ず、反射ノイズの発生が抑制されるので、高周波信号領
域でも安定的に信号が伝達される半導体装置11とするこ
とができる。
Thus, according to the semiconductor device 11 of the present invention, the mounting electrode 10 for the semiconductor element 9 electrically connected to the signal wiring 3 is provided on the surface of the wiring board 8 and the mounting electrode 10 is provided. Since the electrodes of the semiconductor element 9 are electrically connected, when the wiring board 8 is viewed in plan view, the signal wiring 3 and the rectangular opening 7 are overlapped on average, so that the respective signal wirings 3 are Since there is no difference in characteristic impedance and the occurrence of reflection noise is suppressed, it is possible to obtain the semiconductor device 11 in which signals are stably transmitted even in a high frequency signal region.

【0039】なお、本発明の配線基板8および半導体装
置11は上述の実施例に限定されるものではなく、本発明
の要旨を逸脱しない範囲であれば種々の変更は可能であ
ることは言うまでもない。
Needless to say, the wiring board 8 and the semiconductor device 11 of the present invention are not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the present invention. .

【0040】[0040]

【発明の効果】本発明の配線基板によれば、一方向に伸
びる配線導体および一方向に対して45度の方向に伸びる
配線導体で形成された信号配線に対して接地または電源
導体層に形成した方形開口部を15〜30度の方向に配列し
たことから、配線基板を平面視した時、信号配線と方形
開口部とが平均的に重ね合わさり各信号配線間で特性イ
ンピーダンスの差が生じることはなく、その結果、反射
ノイズの発生が抑制され、高周波信号領域でも安定して
信号が伝達される配線基板とすることができる。
According to the wiring board of the present invention, the signal wiring formed by the wiring conductor extending in one direction and the wiring conductor extending in the direction of 45 degrees with respect to one direction is formed in the ground or power supply conductor layer. Since the rectangular openings are arranged in the direction of 15 to 30 degrees, when the wiring board is viewed in plan, the signal wiring and the rectangular opening are overlapped on average, and a difference in characteristic impedance occurs between the signal wirings. As a result, it is possible to obtain a wiring board in which the generation of reflection noise is suppressed and signals are stably transmitted even in a high frequency signal region.

【0041】また、本発明の配線基板によれば、方形開
口部の開口の一辺を0.10〜0.15mmとするとともに開口
間の間隔を0.3〜0.6mmとしたことから、接地および電
源導体層のシールド効果で高周波領域における信号配線
間のクロストークノイズが低減できるとともに、絶縁層
の樹脂が硬化する際に発生するガスを容易に逃がすこと
ができ、その結果、接地または電源導体層に膨れや剥れ
のない配線基板とすることができる。
Further, according to the wiring board of the present invention, one side of the opening of the rectangular opening is set to 0.10 to 0.15 mm and the interval between the openings is set to 0.3 to 0.6 mm. As a result, crosstalk noise between signal wires in the high frequency range can be reduced, and the gas generated when the resin in the insulating layer cures can be easily released, resulting in swelling or peeling of the ground or power supply conductor layer. It is possible to make a wiring board without a wiring board.

【0042】さらに、本発明の半導体装置によれば、上
記の配線基板の表面に信号配線と電気的に接続された半
導体素子の実装用電極を有するとともに、実装用電極に
半導体素子の電極を電気的に接続して成ることから、配
線基板を平面視した時に、信号配線と方形開口部とが平
均的に重ね合わさり各信号配線間で特性インピーダンス
の差が生じることはなく、その結果、反射ノイズの発生
が抑制され、高周波信号領域でも安定的に信号が伝達さ
れる半導体装置とすることができる。
Further, according to the semiconductor device of the present invention, a mounting electrode for the semiconductor element electrically connected to the signal wiring is provided on the surface of the wiring board, and the electrode for the semiconductor element is electrically connected to the mounting electrode. The signal wiring and the rectangular opening do not overlap each other evenly when the wiring board is viewed in plan, and there is no difference in the characteristic impedance between the signal wirings. It is possible to provide a semiconductor device in which the occurrence of noise is suppressed and a signal is stably transmitted even in a high frequency signal region.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の配線基板に半導体素子を搭載して成る
半導体装置の実施の形態の一例を示す断面図である。
FIG. 1 is a cross-sectional view showing an example of an embodiment of a semiconductor device in which a semiconductor element is mounted on a wiring board of the present invention.

【図2】本発明の配線基板の信号配線と接地および電源
導体層とを平面視した時の実施の形態の一例を示す透過
平面図である。
FIG. 2 is a transparent plan view showing an example of an embodiment when the signal wiring of the wiring board of the present invention and the ground and power supply conductor layers are viewed in a plan view.

【符号の説明】[Explanation of symbols]

1・・・・・・・絶縁基板 2・・・・・・・絶縁層 3・・・・・・・信号配線 3a・3b・・・・・配線導体 4・・・・・・・接地導体層 5・・・・・・・電源導体層 7・・・・・・・方形開口部 8・・・・・・・配線基板 9・・・・・・・半導体素子 10・・・・・・・実装用電極 11・・・・・・・半導体装置 1 ... Insulating substrate 2 ... Insulation layer 3 ... Signal wiring 3a ・ 3b ・ ・ ・ ・ ・ Wiring conductor 4 ... Ground conductor layer 5 ... Power supply conductor layer 7 ... Square opening 8 ... Wiring board 9 ... Semiconductor element 10 --- Electrode for mounting 11 --- ・ Semiconductor device

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 一方向に伸びる配線導体および前記一方
向に対して45度の方向に伸びる配線導体で形成された
信号配線と、該信号配線に絶縁層を介して対向配置さ
れ、格子状に配列された方形開口部を有する接地または
電源導体層とを具備した配線基板であって、前記方形開
口部は、前記一方向に対して15〜30度の方向に配列
されていることを特徴とする配線基板。
1. A signal wiring formed by a wiring conductor extending in one direction and a wiring conductor extending in a direction of 45 degrees with respect to the one direction, and the signal wiring is arranged so as to face each other with an insulating layer interposed therebetween, and has a grid shape. A wiring board comprising a ground or power supply conductor layer having arrayed rectangular openings, wherein the rectangular openings are arrayed in a direction of 15 to 30 degrees with respect to the one direction. Wiring board to do.
【請求項2】 前記方形開口部は、開口の一辺が0.1
0〜0.15mmであるとともに前記開口間の間隔が
0.3〜0.6mmであることを特徴とする請求項1に
記載の配線基板。
2. The rectangular opening has one side of the opening of 0.1.
The wiring board according to claim 1, wherein the wiring board has a distance of 0 to 0.15 mm and a distance between the openings is 0.3 to 0.6 mm.
【請求項3】 請求項1または請求項2記載の配線基板
の表面に前記信号配線と電気的に接続された半導体素子
の実装用電極を有するとともに、該実装用電極に前記半
導体素子の電極を電気的に接続して成ることを特徴とす
る半導体装置。
3. The wiring board according to claim 1 or 2, wherein the surface of the wiring board has a mounting electrode for a semiconductor element electrically connected to the signal wiring, and the mounting electrode has an electrode for the semiconductor element. A semiconductor device characterized by being electrically connected.
JP2001197518A 2001-06-28 2001-06-28 Wiring substrate and semiconductor device using the same Expired - Fee Related JP4540262B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001197518A JP4540262B2 (en) 2001-06-28 2001-06-28 Wiring substrate and semiconductor device using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001197518A JP4540262B2 (en) 2001-06-28 2001-06-28 Wiring substrate and semiconductor device using the same

Publications (2)

Publication Number Publication Date
JP2003017613A true JP2003017613A (en) 2003-01-17
JP4540262B2 JP4540262B2 (en) 2010-09-08

Family

ID=19035108

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001197518A Expired - Fee Related JP4540262B2 (en) 2001-06-28 2001-06-28 Wiring substrate and semiconductor device using the same

Country Status (1)

Country Link
JP (1) JP4540262B2 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007227469A (en) * 2006-02-21 2007-09-06 Fujikura Ltd Flexible printed wiring board
US7709962B2 (en) 2006-10-27 2010-05-04 Infineon Technologies Ag Layout structure having a fill element arranged at an angle to a conducting line
JP2011159737A (en) * 2010-01-29 2011-08-18 Toshiba Corp Electronic apparatus and circuit board
WO2011132476A1 (en) * 2010-04-20 2011-10-27 株式会社 村田製作所 Electronic component with laminated substrate
JP2016181574A (en) * 2015-03-24 2016-10-13 京セラ株式会社 Wiring board
JP2017139463A (en) * 2016-02-05 2017-08-10 サムソン エレクトロ−メカニックス カンパニーリミテッド. Printed circuit board and package board including the same
JP2019079988A (en) * 2017-10-26 2019-05-23 京セラ株式会社 Wiring board
CN115966547A (en) * 2021-09-17 2023-04-14 上海玻芯成微电子科技有限公司 Inductor and chip

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08506696A (en) * 1993-02-02 1996-07-16 エイ・エス・ティー・リサーチ・インコーポレイテッド Circuit board array including shield grid and structure thereof
JP2000114722A (en) * 1998-09-30 2000-04-21 Adtec:Kk Printed wiring device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08506696A (en) * 1993-02-02 1996-07-16 エイ・エス・ティー・リサーチ・インコーポレイテッド Circuit board array including shield grid and structure thereof
JP2000114722A (en) * 1998-09-30 2000-04-21 Adtec:Kk Printed wiring device

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007227469A (en) * 2006-02-21 2007-09-06 Fujikura Ltd Flexible printed wiring board
US7709962B2 (en) 2006-10-27 2010-05-04 Infineon Technologies Ag Layout structure having a fill element arranged at an angle to a conducting line
US8331104B2 (en) 2010-01-29 2012-12-11 Kabushiki Kaisha Toshiba Electronic device and circuit board
JP2011159737A (en) * 2010-01-29 2011-08-18 Toshiba Corp Electronic apparatus and circuit board
US8802995B2 (en) 2010-04-20 2014-08-12 Murata Manufacturing Co., Ltd Electronic component including multilayer substrate
JPWO2011132476A1 (en) * 2010-04-20 2013-07-18 株式会社村田製作所 Electronic component with multilayer substrate
WO2011132476A1 (en) * 2010-04-20 2011-10-27 株式会社 村田製作所 Electronic component with laminated substrate
JP2016181574A (en) * 2015-03-24 2016-10-13 京セラ株式会社 Wiring board
JP2017139463A (en) * 2016-02-05 2017-08-10 サムソン エレクトロ−メカニックス カンパニーリミテッド. Printed circuit board and package board including the same
JP7031942B2 (en) 2016-02-05 2022-03-08 サムソン エレクトロ-メカニックス カンパニーリミテッド. Printed circuit board and package board including it
JP2019079988A (en) * 2017-10-26 2019-05-23 京セラ株式会社 Wiring board
CN115966547A (en) * 2021-09-17 2023-04-14 上海玻芯成微电子科技有限公司 Inductor and chip
CN115966547B (en) * 2021-09-17 2023-12-08 上海玻芯成微电子科技有限公司 Inductor and chip

Also Published As

Publication number Publication date
JP4540262B2 (en) 2010-09-08

Similar Documents

Publication Publication Date Title
KR20180037914A (en) Multilayer Flexible Printed Wiring Board and Method for Producing Same
JP3853219B2 (en) Semiconductor element built-in substrate and multilayer circuit board
KR20070081770A (en) Method and process for embedding electrically conductive elements in a dielectric layer
CN211909269U (en) Resin multilayer substrate, electronic component, and mounting structure thereof
JP5311653B2 (en) Wiring board
JP2011159879A (en) Flexible printed wiring board with shield, method for manufacturing the same, and electronic apparatus
JP2003273525A (en) Wiring board
JP4540262B2 (en) Wiring substrate and semiconductor device using the same
JP5473074B2 (en) Wiring board
JP2002261455A (en) Multilayer interconnection board and electronic device using it
US11277910B2 (en) Wiring substrate
JP3801880B2 (en) Wiring substrate and semiconductor device using the same
JP2003224227A (en) Wiring board and semiconductor device employing it
JP5432800B2 (en) Wiring board manufacturing method
JP4315580B2 (en) Printed wiring board and printed wiring board manufacturing method
JP2003198146A (en) Multilayer wiring substrate and electronic device using the same
JP2004063929A (en) Wiring board and electronic equipment using it
JP2005019732A (en) Wiring substrate and electronic device using it
JP4508540B2 (en) Wiring board and electronic device
JP4437361B2 (en) Printed wiring board and printed wiring board manufacturing method
JP2004241496A (en) Wiring substrate and electronic device employing the same
KR100704927B1 (en) Pcb using paste bump and method of manufacturing thereof
JP3840148B2 (en) WIRING BOARD AND ELECTRONIC DEVICE USING THE SAME
JP3990578B2 (en) WIRING BOARD AND ELECTRONIC DEVICE USING THE SAME
JP4492071B2 (en) Wiring board manufacturing method

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080317

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100208

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100225

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100419

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100525

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100622

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130702

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees