JP4517599B2 - Capacitance detection device - Google Patents
Capacitance detection device Download PDFInfo
- Publication number
- JP4517599B2 JP4517599B2 JP2003207935A JP2003207935A JP4517599B2 JP 4517599 B2 JP4517599 B2 JP 4517599B2 JP 2003207935 A JP2003207935 A JP 2003207935A JP 2003207935 A JP2003207935 A JP 2003207935A JP 4517599 B2 JP4517599 B2 JP 4517599B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- semiconductor device
- thin film
- capacitance detection
- mis
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Measurement Of The Respiration, Hearing Ability, Form, And Blood Characteristics Of Living Organisms (AREA)
- Image Input (AREA)
- Facsimile Heads (AREA)
- Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
Description
【0001】
【発明の属する技術分野】
本願発明は指紋等の微細な凹凸を有する対象物の表面形状を、対象物表面との距離に応じて変化する静電容量を検出する事に依り読み取る静電容量検出装置に関する。
【0002】
【従来の技術】
従来、指紋センサ等に用いられる静電容量検出装置はセンサ電極と当該センサ電極上に設けられた誘電体膜とを単結晶硅素基板に行列状に形成していた(特開平11−118415、特開2000−346608、特開2001−56204、特開2001−133213等)。図1は従来の静電容量検出装置の動作原理を説明している。センサ電極と誘電体膜とがコンデンサーの一方の電極と誘電体膜とを成し、人体が接地された他方の電極と成る。このコンデンサーの静電容量CFは誘電体膜表面に接した指紋の凹凸に応じて変化する。一方、半導体基板には静電容量CSを成すコンデンサーを準備し、此等二つのコンデンサーを直列接続して、所定の電圧を印可する。斯うする事で二つのコンデンサーの間には指紋の凹凸に応じた電荷Qが発生する。この電荷Qを通常の半導体技術を用いて検出し、対象物の表面形状を読み取っていた。
【0003】
【発明が解決しようとする課題】
しかしながら此等従来の静電容量検出装置は、当該装置が単結晶硅素基板上に形成されて居る為に、指紋センサとして用いると指を強く押しつけた際に当該装置が割れて仕舞うとの課題を有して居た。
【0004】
更に指紋センサはその用途から必然的に20mm×20mm程度の大きさが求められ、静電容量検出装置面積の大部分はセンサ電極にて占められる。センサ電極は無論単結晶硅素基板上に作られるが、膨大なエネルギーと労力とを費やして作成された単結晶硅素基板の大部分(センサ電極下部)は単なる支持体としての役割しか演じてない。即ち従来の静電容量検出装置は高価なだけでは無く、多大なる無駄と浪費の上に形成されて居るとの課題を有する。
【0005】
加えて近年、クレジットカードやキャッシュカード等のカード上に個人認証機能を設けてカードの安全性を高めるべきとの指摘が強い。然るに従来の単結晶硅素基板上に作られた静電容量検出装置は柔軟性に欠ける為に、当該装置をプラスティック基板上に作成し得ないとの課題を有している。
【0006】
そこで本発明は上述の諸事情を鑑み、その目的とする所は安定に動作し、更に製造時に不要なエネルギーや労力を削減し得、又単結晶硅素基板以外にも作成し得る優良な静電容量検出装置を提供する事に有る。
【0007】
【課題を解決するための手段】
本発明は対象物との距離に応じて変化する静電容量を検出する事に依り、対象物の表面形状を読み取る静電容量検出装置に於いて、静電容量検出装置はM行N列の行列状に配置されたM本の電源線と、N本の出力線、及び各電源線(i行目の電源線PLi、iは1からM迄の整数)と各出力線(j列目の出力線OLj、jは1からN迄の整数)との交点に設けられた静電容量検出素子(i行j列に位置する静電容量検出素子ECSEij)とを具備し、此の静電容量検出素子(ECSEij)は信号検出素子(SSEij)と信号増幅素子(SAEij)と信号転送素子(STEij)とを含み、信号検出素子は容量検出電極と容量検出誘電体膜とを含み、信号増幅素子はゲート電極とゲート絶縁膜と半導体膜とから成る信号増幅用MIS型薄膜半導体装置(TSD-SAij)から成り、信号転送素子はゲート電極とゲート絶縁膜と半導体膜とから成る信号転送用MIS型薄膜半導体装置(TSD-STij)から成る事を特徴とする。更に此の静電容量検出装置はN本の列線を具備し、信号増幅用MIS型薄膜半導体装置(TSD-SAij)のソース領域はj列目の出力線(OLj)に接続され、信号増幅用MIS型薄膜半導体装置(TSD-SAij)のドレイン領域と信号転送用MIS型薄膜半導体装置(TSD-STij)のソース領域とが接続され、信号転送用MIS型薄膜半導体装置(TSD-STij)のドレイン領域はi行目の電源線(PLi)に接続され、信号増幅用MIS型薄膜半導体装置(TSD-SAij)のゲート電極は前記容量検出電極に接続され、信号転送用MIS型薄膜半導体装置(TSD-STij)のゲート電極はj列目の列線(CLj)に接続される事を特徴とする。或いは信号転送用MIS型薄膜半導体装置(TSD-STij)と信号増幅用MIS型薄膜半導体装置(TSD-SAij)との静電容量検出素子(ECSEij)内に於ける位置関係を交換しても良い。具体的には此の静電容量検出装置はN本の列線を具備し、信号増幅用MIS型薄膜半導体装置(TSD-SAij)のドレイン領域がi行目の電源線(PLi)に接続され、信号増幅用MIS型薄膜半導体装置(TSD-SAij)のソース領域と信号転送用MIS型薄膜半導体装置(TSD-STij)のドレイン領域とが接続され、信号転送用MIS型薄膜半導体装置(TSD-STij)のソース領域はj列目の出力線(OLj)に接続され、信号増幅用MIS型薄膜半導体装置(TSD-SAij)のゲート電極は前記容量検出電極に接続され、信号転送用MIS型薄膜半導体装置(TSD-STij)のゲート電極はj列目の列線(CLj)に接続される事も特徴と為す。更に本発明の静電容量検出装置は出力線と列線は第一配線にて配線され、電源線は第二配線にて配線され、第一配線と第二配線とは絶縁膜を介して異なった層上に形成されて居る事も特徴と為す。更に容量検出電極が第三配線にて配線され、第一配線及び第二配線と、第三配線とは絶縁膜を介して異なった層上に形成されて居る事を特徴とする。更に第三配線が静電容量検出装置の配線の中で最も表面側に位置する事を特徴とする。
【0008】
本発明は対象物との距離に応じて変化する静電容量を検出する事に依り、対象物の表面形状を読み取る静電容量検出装置に於いて、静電容量検出装置はM行N列の行列状に配置されたM本の電源線と、N本の出力線、N本の列線、及び各電源線(i行目の電源線PLi、iは1からM迄の整数)と各出力線(j列目の出力線OLj、jは1からN迄の整数)との交点に設けられた静電容量検出素子(i行j列に位置する静電容量検出素子ECSEij)、N本の出力線及びN本の列線に接続する出力信号選択回路とを具備し、此の静電容量検出素子(ECSEij)は信号検出素子(SSEij)と信号増幅素子(SAEij)及び信号転送素子(STEij)とを含み、出力信号選択回路は共通出力線と出力信号用パスゲート(j列目に位置する出力信号用パスゲートOLPGEj)を含み、信号検出素子(SSEij)は容量検出電極と容量検出誘電体膜とを含み、信号増幅素子(SAEij)はゲート電極とゲート絶縁膜と半導体膜から成る信号増幅用MIS型薄膜半導体装置(TSD-SAij)から成り、信号転送素子(STEij)はゲート電極とゲート絶縁膜と半導体膜から成る信号転送用MIS型薄膜半導体装置(TSD-STij)から成り、出力信号用パスゲート(OLPGEj)はゲート電極とゲート絶縁膜と半導体膜から成る出力信号パスゲート用MIS型薄型半導体装置(TSD-OLPGj)から成る事を特徴する。更に信号増幅用MIS型薄膜半導体装置(TSD-SAij)のソース領域はj列目の出力線(OLj)に接続され、信号増幅用MIS型薄膜半導体装置(TSD-SAij)のドレイン領域と信号転送用MIS型薄膜半導体装置(TSD-STij)のソース領域とが接続され、信号転送用MIS型薄膜半導体装置(TSD-STij)のドレイン領域はi行目の電源線(PLi)に接続され、信号増幅用MIS型薄膜半導体装置(TSD-SAij)のゲート電極は前記容量検出電極に接続され、信号転送用MIS型薄膜半導体装置(TSD-STij)のゲート電極はj列目の列線(CLj)に接続され、出力信号パスゲート用MIS型薄膜半導体装置(TSD-OLPGj)のソース領域は前記共通出力線に接続され、出力信号パスゲート用MIS型薄膜半導体装置(TSD-OLPGj)のドレイン領域はj列目の出力線(OLj)に接続され、出力信号パスゲート用MIS型薄膜半導体装置(TSD-OLPGj)のゲート電極はj列目の列線(CLj)に接続される事を特徴とする。或いは信号転送用MIS型薄膜半導体装置(TSD-STij)と信号増幅用MIS型薄膜半導体装置(TSD-SAij)との静電容量検出素子(ECSEij)内に於ける位置関係を交換しても良い。具体的には信号増幅用MIS型薄膜半導体装置(TSD-SAij)のドレイン領域はi行目の電源線(PLi)に接続され、前記信号増幅用MIS型薄膜半導体装置(TSD-SAij)のソース領域と前記信号転送用MIS型薄膜半導体装置(TSD-STij)のドレイン領域とが接続され、前記信号転送用MIS型薄膜半導体装置(TSD-STij)のソース領域はj列目の出力線(OLj)に接続され、前記信号増幅用MIS型薄膜半導体装置(TSD-SAij)のゲート電極は前記容量検出電極に接続され、前記信号転送用MIS型薄膜半導体装置(TSD-STij)のゲート電極はj列目の列線(CLj)に接続され、前記出力信号パスゲート用MIS型薄膜半導体装置(TSD-OLPGj)のソース領域は前記共通出力線に接続され、前記出力信号パスゲート用MIS型薄膜半導体装置(TSD-OLPGj)のドレイン領域はj列目の出力線(OLj)に接続され、前記出力信号パスゲート用MIS型薄膜半導体装置(TSD-OLPGj)のゲート電極はj列目の列線(CLj)に接続される事を特徴する。
【0009】
本発明の静電容量検出装置では出力線と列線とが第一配線にて配線され、電源線と共通出力線とが第二配線にて配線され、此等第一配線と第二配線とは絶縁膜を介して異なった層上に形成されて居る事も特徴と為す。更に容量検出電極が第三配線にて配線され、第一配線及び第二配線と、第三配線とは絶縁膜を介して異なった層上に形成されて居る事を特徴とする。更に、第三配線が静電容量検出装置の配線の中で最も表面側に位置する事を特徴とする。
【0010】
【発明の実施の形態】
本発明は対象物との距離に応じて変化する静電容量を検出する事に依り、対象物の表面形状を読み取る静電容量検出装置を金属−絶縁膜−半導体膜から成るMIS型薄膜半導体装置を用いて作成する。薄膜半導体装置は通常、硝子基板上に作成され、大面積を要する半導体集積回路を安価に製造する技術として知られて居る。具体例としては、昨今は液晶表示装置等に応用されている。従って指紋センサ等に適応される静電容量検出装置を薄膜半導体装置にて作成すると、単結晶硅素基板と云った多大なエネルギーを消費して作られた高価な基板を使用する必要がなく、貴重な地球資源を浪費する事なく安価に当該装置を作成し得る。又、薄膜半導体装置はSUFTLA(特開平11−312811やS. Utsunomiya et. al. Society for Information Display p. 916 (2000))と呼ばれる転写技術を適応する事で、半導体集積回路をプラスティック基板上に作成出来るので、静電容量検出装置も単結晶硅素基板から解放されてプラスティック基板上に形成し得るので有る。
【0011】
さて、図1に示すが如き従来の動作原理を適応した静電容量検出装置を薄膜半導体装置にて作成するのは、現在の薄膜半導体装置の技術を以ってしては不可能である。二つの直列接続されたコンデンサー間に誘起される電荷Qは非常に小さい為に、高精度感知を可能とする単結晶硅素LSI技術を用いれば電荷Qを正確に読み取れるが、薄膜半導体装置ではトランジスタ特性が単結晶硅素LSI技術程には優れず、又薄膜半導体装置間の特性偏差も大きいが故に電荷Qを正確に読み取れない。
【0012】
そこで本発明の静電容量検出装置は、少なくともM行N列の行列状に配置されたM本(Mは1以上の整数)の電源線と、N本(Nは1以上の整数)の出力線、及び各電源線(i行目の電源線PLi、iは1からM迄の整数)と各出力線(j列目の出力線OLj、jは1からN迄の整数)との交点に設けられた静電容量検出素子(i行j列に位置する静電容量検出素子ECSEij)とを具備し、此の静電容量検出素子は信号検出素子と信号増幅素子とを最少の構成要素として含む。斯うした構成である静電容量検出装置の一例を図4Aに示す。信号検出素子は容量検出電極と容量検出誘電体膜とを含み、容量検出電極には静電容量に応じて電荷Qが発生する。本発明ではこの電荷Qを各静電容量検出素子に設けられた信号増幅素子にて増幅し、電流又は電圧に変換する。具体的には信号増幅素子はゲート電極とゲート絶縁膜と半導体膜とから成る信号増幅用MIS型薄膜半導体装置から成り、信号増幅用MIS型薄膜半導体装置のゲート電極が容量検出電極に接続される。
【0013】
図2に本願発明の動作原理図を示す。静電容量Csを持つコンデンサーと、対象物の表面形状に応じて変化する静電容量CFを有するコンデンサーとの間に容量結合にて分割された電圧は信号増幅用MIS型薄膜半導体装置のゲート電位を変化させる。斯うして此の薄膜半導体装置のドレイン領域に所定の電圧を印可すると、容量結合にて誘起された電圧に応じて薄膜半導体装置のソースドレイン間に流れる電流Iが著しく増幅される。ゲート電極に誘起された電荷Q自体は何処にも流れずに保存されるので、ドレイン電圧を高くしたり或いは測定時間を長くする等で電流Idsの測定も容易になり、従って薄膜半導体装置を用いても対象物の表面形状を十分正確に計測出来る様になる。
【0014】
前述の如く本願発明では信号増幅素子として信号増幅用MIS型薄膜半導体装置を用いて居る。この場合、静電容量Csを持つコンデンサーを信号増幅用MIS型薄膜半導体装置其の物で兼用し得る。即ち静電容量Csに代わる新たな静電容量を信号増幅用MIS型薄膜半導体装置のトランジスタ容量CTとするので有る。斯うする事で静電容量検出素子から静電容量Csを持つコンデンサーを省略出来、構造が簡素化されると同時に製造工程も容易と化す。加えて図2に描かれて居る二つの電源を共通の電源Vddとして纏める事も静電容量検出装置内に於ける余計な配線を省略し得るとの観点で効果的と言える。斯様な状態に於ける動作原理に関する等価回路図を図3に示す。対象物の表面形状に応じて変化する静電容量CFを有するコンデンサーとトランジスタ容量CTを有するコンデンサーとが直列に接続されて居る。厳密にはトランジスタ容量CTは信号増幅用MIS型薄膜半導体装置のドレイン電極とゲート電極との間に形成される静電容量である。図3の構成を実現させるには、図4に示すが如く信号増幅用MIS型薄膜半導体装置のソース領域を出力線に接続し、信号増幅用MIS型薄膜半導体装置のドレイン領域を電源線に接続した上で、電源線に電圧Vddを印可し、出力線より対象物の表面形状に応じて変化する電流Idsを取り出せば良い。例えば各容量を適当に設定し、指紋の山が信号検出素子に接した時には信号増幅素子は高抵抗となって電源線と出力線とを遮断し(電流Idsを殆ど通過させず)、反対に指紋の谷が信号検出素子に面した時には信号増幅素子は低抵抗となって電源線と出力線とを導通させる(電流Idsを通過させる)。斯うした電流量の変化や出力線に掛かる電圧変化を感知して指紋形状等に起因する静電容量を検出する。
【0015】
原理的には斯うした構成で指紋等の表面形状情報を採取可能で有るが、行列状に配置された各電源線及び各出力線には其々複数の静電容量検出素子が接続されている為、静電容量検出素子間で情報の干渉が生じて仕舞う。図4Aに示した構成の静電容量検出装置にて静電容量検出素子ECSEijに依り対象物の表面形状を読み取る場合、電源線PLiに電圧Vddを印可し、出力線OLjから出力信号OSijを取り出す。もし信号増幅素子SAEijが高抵抗で有れば出力線OLjは低電位で有らねば成らない。所がこの時、電源線PLiに接続された全ての静電容量検出素子ECSEiy(yは1からN迄の総ての整数)にも電圧Vddが印可される為、各出力線OLyには、静電容量検出素子ECSEiyを通じて読み取られた表面形状に応じた出力信号OSiyが流れる。例えば信号増幅素子SEAij+1が低抵抗状態に有れば出力線OLj+1は出力信号OSij+1を介して高電位と成る。更に、出力線OLyに接続された静電容量検出素子ECSExy(xはiを除く1からM迄の整数)を通して、電源線PLxにも電流が流れ得る。例えば出力線OLj+1が高電位になった状態で信号増幅素子SAEi-1j+1が低抵抗ならば、信号増幅素子SAEi-1j+1を介して逆方向の出力信号OSi-1j+1が存在し得、本来低電位でなければならない電源線PLi-1を高電位として仕舞う。斯うして本来低電位に有るべき非選択電源線PLx(xはiを除く1からM迄の整数)に通った電流が非選択電源線を高電位に変えて仕舞う。非選択電源線が高電位に変わると、静電容量検出素子ECSExjを介して出力信号OSxjが出力線OLjに流れる。先の例に戻ると例えば信号増幅素子SAEi-1jが低抵抗だと出力信号OSi-1jが出力線OLjに流入する。この結果、出力線OLjには本来検出すべきOSijの他にOSi-1jなど他の出力信号が重畳して仕舞う。換言すると電源線PLiと出力線OLjとの間に静電容量検出装置ECSEij以外の電流経路が存在するのである。電源線PLiを選択して電圧Vddを印可したとしても、実質的には電源線の選択が機能せず、出力線OLjには複数の静電容量検出素子を通して複数の出力信号が流れ込み、精度良く表面形状を読み取る事が困難となる。
【0016】
そこで本発明では各静電容量検出素子を確実に選択し、その動作を制御する信号転送素子を用いる事に依り、検出情報の素子間干渉を防ぎ、精度の高い静電容量の検出を可能とする。本発明の静電容量検出装置はM行N列の行列状に配置されたM本(Mは1以上の整数)の電源線と、N本(Nは1以上の整数)の出力線、及び各電源線(i行目の電源線PLi、iは1からM迄の整数)と各出力線(j列目の出力線OLj、jは1からN迄の整数)との交点に設けられた静電容量検出素子(i行j列に位置する静電容量検出素子ECSEij)とを具備し、此の静電容量検出素子ECSEijは信号検出素子SSEijと信号増幅素子SAEijと信号転送素子STEijとを含む。信号検出素子SSEijは容量検出電極と容量検出誘電体膜とを含み、静電容量を検出して静電容量を電圧に変換する。信号増幅素子SAEijはゲート電極とゲート絶縁膜と半導体膜とから成る信号増幅用MIS型薄膜半導体装置TSD-SAijから成り、信号転送素子STEijはゲート電極とゲート絶縁膜と半導体膜とから成る信号転送用MIS型薄膜半導体装置TSD-STijから成る。信号増幅用MIS型薄膜半導体装置TSD-SAijと信号転送用MIS型薄膜半導体装置TSD-STijとは静電容量検出素子ECSEij内に於いて直列に接続される。
【0017】
斯うした構成を実現する静電容量検出装置の一例を図4Bと図4Cとを用いて詳述する。(図4Bと図4CとではMIS型薄膜半導体装置のソース領域をS、ドレイン領域をD、ゲート電極をGにて表示して居る。又、ソース領域とドレイン領域はN型半導体装置では電位の低い方をソース領域と定義し、P型半導体装置では電位の高い方をソース領域と定義する。)図4Bと図4Cの静電容量検出素子ECSEijでは、信号増幅用MIS型薄膜半導体装置TSD-SAijと信号転送用MIS型薄膜半導体装置TSD-STijとが電源線PLiと出力線OLjとの間にて直列に接続されている。これに依り静電容量検出素子間での出力信号干渉を防ぎ、検出精度の高い静電容量検出装置を実現し得る。実際、静電容量検出素子ECSEijからの出力信号を読み出す際には、i行目電源線を選択して高電位とし、その状態にて信号転送用MIS型薄膜半導体装置TSD-STijのゲート電極に印加する電圧を制御する事で、静電容量検出素子ECSEijのみを選択出来る様になる。先の例に倣うと、図4Aでは出力信号の干渉がOSijからOSij+1を経て、逆出力信号OSi-1j+1、OSi-1jとの経路で出力線OLjに発生していた。所が、本発明(図4Bと図4C)の構成では列側の選択を信号転送素子にて行っているが故、j列に位置する静電容量検出素子ECSEijを選択した状態では他列の信号転送素子は必ず高抵抗状態に保たれる。この為にOSij+1や逆出力信号OSi-1j+1は遮断され、出力線OLjに選択した静電容量検出素子ECSEij以外の出力信号が重畳する事はなくなる。信号転送用MIS型薄膜半導体装置TSD-STijのソース・ドレイン間が電気的に導通状態である(信号転送素子が選択状態である)時のみ静電容量検出素子ECSEijだけが動作し、信号転送用MIS型薄膜半導体装置TSD-STijのソース・ドレイン間が電気的に導通状態でない(信号転送素子が非選択状態である)時には、静電容量検出素子ECSEijは動作しないのである。
【0018】
此迄述べて来た様に、信号転送素子を含む静電容量検出装置を用いて表面形状情報の採取時に生じる情報の干渉を防ぐ一つの方法は、列選択に依り静電容量検出素子の動作を制御する事にある。そこで本発明の静電容量検出装置では、列毎に静電容量検出素子の動作を制御する列線CLjを設け、此の列線CLjに印加する電圧に応じて信号転送素子STEijの選択(信号転送素子STEijが低抵抗で導通状態)か非選択(信号転送素子STEijが高抵抗で遮断状態)かを切り替え、静電容量検出素子ECSEijの動作を制御する。具体的には本発明の静電容量検出装置はN本の列線CLjをも具備して居る。即ちM行N列の行列を含む静電容量検出装置の各行列要素は電源線PLiと出力線OLj、列線CLj、及び静電容量検出素子ECSEijとから成る。信号増幅用MIS型薄膜半導体装置TSD-SAijのソース領域はj列目の出力線OLjに電気的に接続され、信号増幅用MIS型薄膜半導体装置TSD-SAijのドレイン領域と信号転送用MIS型薄膜半導体装置TSD-STijのソース領域とが電気的に接続され、更に信号転送用MIS型薄膜半導体装置TSD-STijのドレイン領域はi行目の電源線PLiに電気的に接続される。電気的に接続されるとは直接此等が繋がれる事の他にも、何らかのスイッチ素子を介して導通が取られる事をも意味している。例えば信号転送素子と電源線との間に更に他のトランジスタを直列に配置しても良い。配置されたトランジスタが選択状態となり低抵抗ならば、信号転送素子と電源線との間は導通が取られるので、信号転送素子と電源線とは電気的に接続されていると言える。信号増幅用MIS型薄膜半導体装置TSD-SAijのゲート電極は容量検出電極に電気的に接続され、信号転送用MIS型薄膜半導体装置TSD-STijのゲート電極はj列目の列線CLjに電気的に接続される。斯うした構成となる静電容量検出装置の全体構造が図4Bに示されて居る。上述の構成とは反対に信号転送用MIS型薄膜半導体装置TSD-STijと信号増幅用MIS型薄膜半導体装置TSD-SAijとの静電容量検出素子ECSEij内に於ける位置関係を交換しても良い。具体的には本発明の別な形態となる静電容量検出素子はN本の列線CLjを具備し、信号増幅用MIS型薄膜半導体装置TSD-SAijのドレイン領域がi行目の電源線PLiに電気的に接続され、信号増幅用MIS型薄膜半導体装置TSD-SAijのソース領域と信号転送用MIS型薄膜半導体装置TSD-STijのドレイン領域とが電気的に接続され、信号転送用MIS型薄膜半導体装置TSD-STijのソース領域はi行目の出力線OLjに電気的に接続される。信号増幅用MIS型薄膜半導体装置TSD-SAijのゲート電極は容量検出電極に電気的に接続され、信号転送用MIS型薄膜半導体装置TSD-STijのゲート電極はj列目の列線CLjに電気的に接続される。斯うした構成となる静電容量検出装置の全体構造が図4Cに示されて居る。斯うした構成を成す事に依り、電源線PLiに高電位Vddを印可してi行を選択出来、列線CLjに所定の選択電位を印可してj列を選択する。斯くして静電容量検出素子ECSEijが表面形状に応じて読み取った出力信号OSij(電圧Vij又は電流Iij)を正確に出力線OLjから取り出すことが可能と化す。例えば図4Bや図4Cの構成にて静電容量検出素子ECSEijに依り表面形状を測定する場合には、電源線PLiに電圧Vddを印可してi行を選択し、列線CLjにも同じ電圧Vddを印可してj列を選択する。まず正電源電圧Vddが印加された電源線PLiに接続されているN個の静電容量検出素子ECSEib(bは1からN迄の整数)が選択され、更にその中から列線CLjに依り選択されて居るj列に属する静電容量検出素子ECSEijだけが選択され、動作状態とされる。斯うして非選択列の静電容量検出装置ECSEiy、(yはiを除く1からM迄の整数)を経由した出力情報の拡散が排除され、電源線PLiと出力線OLjとの間には静電容量検出素子ECSEij以外の情報流入経路が断たれる。故に出力線OLjには静電容量検出素子ECSEijだけを通して表面形状に応じた出力信号OSij(電圧Vij又は電流Iij)が出力されるるに至り、静電容量検出素子間の情報干渉を防止し得る。
【0019】
斯様な構成の静電容量検出装置を効果的に機能させる為に、本発明の静電容量検出装置では出力線と列線とが第一配線にて配線され、電源線が第二配線にて配線され、此等第一配線と第二配線とは絶縁膜を介して異なった層上に形成される。更に容量検出電極は絶縁膜にて第一配線及び第二配線と異なった層上に形成されて居る第三配線にて配線される。又、容量検出電極は第一配線から第三配線の何れにて配線し得るが、静電容量検出装置中の配線の中で最も表面側に第三配線を位置させる。斯うした構成を成す事で余分な配線を除去し、以て各配線間に生ずる寄生容量を最小化せしめ、故に微少な静電容量を高感度にて検出せしめる訳である。本発明を具現化する静電容量検出素子の構造の一例を図5を用いて説明する。図5ではMIS型薄膜半導体装置のソース領域をS、ドレイン領域をD、ゲート電極をGにて表示して居る。静電容量検出素子の信号増幅素子を成す信号増幅用MIS型薄膜半導体装置及び信号転送素子を構成する信号転送用MIS型薄膜半導体装置は、其々ソース領域とチャンネル形成領域とドレイン領域とを含む半導体膜とゲート絶縁膜とゲート電極とを不可欠な構成要件としている。図5の構成例では信号増幅用MIS型薄膜半導体装置のドレイン領域と信号転送用MIS型半導体装置のソース領域は一つの領域として設けられていて、信号増幅用MIS型薄膜半導体装置と信号転送用MIS型薄膜半導体装置を第一層間絶縁膜が覆っている。信号増幅用MIS型薄膜半導体装置のソース領域には第一配線が接続され、信号転送用MIS型薄膜半導体装置のドレイン領域には第二配線が接続される。或いは信号増幅用MIS型薄膜半導体装置のドレイン領域に第一配線が接続され、信号転送用MIS型薄膜半導体装置のソース領域に第二配線が接続されても良い。第一配線と第二配線との間には第二層間絶縁膜が設けられ、第一配線と第二配線とは異なった層上に形成される。勿論、第二配線を第一層間絶縁膜上に形成し、第一配線を第二層間絶縁膜上に形成する事も可能である。静電容量検出素子の信号検出素子を成す容量検出電極は第三配線として設けられ、信号増幅用MIS型薄膜半導体装置のゲート電極に接続される。第三配線は第二層間絶縁膜の上に設けられた第三層間絶縁膜上に形成され、第一配線及び第二配線とは更に異なった層上に形成される。容量検出電極と、第一配線乃至は第二配線とは電気的に導通が取られている部位(電気抵抗がゼロとの理想系にて等電位と化す部位)以外とは異なった層上にあってもお互いに重なり合わない様に配置する。微小な静電容量を検出する為には寄生容量を最小とする必要があり、上述の構成を取る事で容量検出電極と第二配線、乃至は容量検出電極と第二配線寄生容量を最小と出来、それ故に高感度の静電容量検出装置が実現する。容量検出電極上は容量検出誘電体膜が被い、容量検出誘電体膜は静電容量検出装置の最表面に位置する。容量検出誘電体膜は静電容量検出装置の保護膜の役割も同時に演ずる。保護膜として効率よく機能するには容量検出誘電体膜の比誘電率が第二層間絶縁膜や第三層間絶縁膜の比誘電率よりも大きい事が望まれる。
【0020】
次に本発明に依る静電容量検出装置からの出力信号読み出し方法を図4Bと図4Cとを用いて説明する。本発明の静電容量検出素子はM行N列の行列状に配置されている為、対象物の表面形状を読み取るには行と列とを其々順次走査し、M×N個の静電容量検出素子を適当な順番にて選択して行く。即ち電源線PLiに電圧Vddを印可した上で、列線CLjを順次選択して行き、出力線OLjに現れる出力信号OSijを読み取るとの作業を繰り返す。此の時に各静電容量検出素子から如何なる順序にて検出された出力信号を読み出すかを定めるのが出力信号選択回路である。具体的には、本発明の静電容量検出装置はM行N列の行列状に配置されたM本の電源線と、N本の出力線、N本の列線、及び各電源線(i行目の電源線PLi、iは1からM迄の整数)と各出力線(j列目の出力線OLj、jは1からN迄の整数)との交点に設けられた静電容量検出素子(i行j列に位置する静電容量検出素子ECSEij)、N本の出力線及びN本の列線に接続する出力信号選択回路とを具備する。M行N列行列の各行列要素は電源線PLiと出力線OLj、列線CLj、及び静電容量検出素子ECSEijから構成される。各行列要素に繋がるN本の出力線とN本の列線は出力信号選択回路に繋がる。静電容量検出素子ECSEijは信号検出素子SSEijと信号増幅素子SAEij及び信号転送素子STEijとを含む。出力信号選択回路は共通出力線(LDOUT)と出力信号用パスゲート(j列目に位置する出力信号用パスゲートOLPGEj)を少なくとも含むで居る。信号検出素子SSEijは容量検出電極と容量検出誘電体膜とを含む。信号増幅素子SAEijはゲート電極とゲート絶縁膜と半導体膜とから成る信号増幅用MIS型薄膜半導体装置TSD-SAijから構成され、信号転送素子STEijはゲート電極とゲート絶縁膜と半導体膜とから成る信号転送用MIS型薄膜半導体装置TSD-STijから構成され、出力信号用パスゲートOLPGEjはゲート電極とゲート絶縁膜と半導体膜とから成る出力信号パスゲート用MIS型薄型半導体装置TSD-OLPGjから構成される。出力信号選択回路はデコーダーやシフトレジスタなどに依り選択された列からの出力信号を共通出力線に取り出す。即ちN本の列線の内でj列目の列線CLjが選択された際に、N本の出力線の内でj列目の出力線OLjに現れた出力信号OSjを選択的に共通出力線に取り出す。本発明の静電容量検出装置では全ての出力信号を共通出力線に出力する。斯様な構成にせねば、各出力信号OSjを検出する際に、各出力線OLj上に出力信号を検出する装置を個別に設けねばならず、製造が困難を窮めると共に、N個の接続端子にも接続のばらつきが生じるので測定誤差を大きくする要因と成る。そこで本発明の静電容量検出装置では全ての出力信号を数本(一本から八本程度)の共通出力線から出力し、外部回路との実装工程等を容易にすると共に、接続端子に起因する接続のばらつきを最小とし、精度の高い測定を実現している。又、単純に共通出力線と出力線とを接続するだけでは(それでも測定は可能だが)、共通出力線を介して其々の出力線同士が直接接続され、出力信号が広く他の出力線に拡散して仕舞う。此は微弱な出力信号を高速で且つ高精度に検出をする上では好ましくない。そこで本発明の静電容量検出装置では各出力線OLjと共通出力線との間に出力信号の電気的導通を制御する出力信号用パスゲートOLPGEjを設ける。斯様な構成下では出力信号OSijは選択された出力線OLijと共通出力線内だけに止まり、その他の非選択状態の出力線へは広がらない。例えば出力信号を電圧で読む場合、選択された出力線と共通出力線だけの電位を変えれる事になるので短時間で精度の高い検出が可能とされる。
【0021】
本発明の静電容量検出装置に於いて、共通出力線から効率良く出力信号を読み出すには列線CLjに依って選択された列の出力線OLjのみが共通出力線と電気的に導通する必要がある。そこで本発明の静電容量検出素子では列線CLjに依りj列に位置する静電容量検出素子ECSEijを選択すると同時にj列目の出力線OLjに繋がった出力信号用パスゲートOLPGEjの電気導通状態を制御する。出力信号用パスゲートOLPGEjは一例として出力信号パスゲート用MIS型薄膜半導体装置TSD-OLPGjから成る。より詳細には、本発明の静電容量検出装置は信号増幅用MIS型薄膜半導体装置TSD-SAijのソース領域がj列目の出力線OLjに電気的に接続され、信号増幅用MIS型薄膜半導体装置TSD-SAijのドレイン領域と信号転送用MIS型薄膜半導体装置TSD-STijのソース領域とが電気的に接続され、信号転送用MIS型薄膜半導体装置TSD-STijのドレイン領域がi行目の電源線PLiに電気的に接続され、信号増幅用MIS型薄膜半導体装置TSD-SAijのゲート電極が容量検出電極に電気的に接続され、信号転送用MIS型薄膜半導体装置TSD-STijのゲート電極がj列目の列線CLjに電気的に接続され、j列目に設けられた出力信号パスゲート用MIS型薄膜半導体装置TSD-OLPGjのソース領域が共通出力線に電気的に接続され、出力信号パスゲート用MIS型薄膜半導体装置TSD-OLPGjのドレイン領域がj列目の出力線OLjに電気的に接続され、出力信号パスゲート用MIS型薄膜半導体装置TSD-OLPGjのゲート電極がj列目の列線CLjに電気的に接続される。斯うした構成に有る静電容量検出装置の全体構造を図4Bに示す。或いは信号転送用MIS型薄膜半導体装置TSD-STijと信号増幅用MIS型薄膜半導体装置TSD-SAijとの静電容量検出素子ECSEij内に於ける位置関係を交換しても良い。具体的には、本発明の静電容量検出装置は、信号増幅用MIS型薄膜半導体装置TSD-SAijのドレイン領域がi行目の電源線PLiに電気的に接続され、信号増幅用MIS型薄膜半導体装置TSD-SAijのソース領域と信号転送用MIS型薄膜半導体装置TSD-STijのドレイン領域とが電気的に接続され、信号転送用MIS型薄膜半導体装置TSD-STijのソース領域がj列目の出力線OLjに電気的に接続され、信号増幅用MIS型薄膜半導体装置TSD-SAijのゲート電極が容量検出電極に電気的に接続され、信号転送用MIS型薄膜半導体装置TSD-STijのゲート電極がj列目の列線CLjに電気的に接続され、出力信号パスゲート用MIS型薄膜半導体装置TSD-OLPGjのソース領域が共通出力線に電気的に接続され、出力信号パスゲート用MIS型薄膜半導体装置TSD-OLPGjのドレイン領域がj列目の出力線OLjに接続され、出力信号パスゲート用MIS型薄膜半導体装置TSD-OLPGjのゲート電極がj列目の列線CLjに接続される。斯うした構成に有る静電容量検出装置の全体構造を図4Cに示す。電気的に接続されるとは先に述べた如く直接乃至は間接的に電気的導通が取られる事を意味する。
【0022】
斯様な構成を取ると、N本の列線の内からj列目の列線CLjを選択すると、同時にN本の出力線の内でj列目に位置する只一本の出力線OLjを選択する事に成り、出力信号が他の出力線へ拡散される事態を防止し得る。その結果、電源線PLi及び列線CLjに依り選択された静電容量検出素子ECSEijからの出力信号OSijは、出力線OLjにのみと出力信号用パスゲートOLPGEjを介して共通出力線とに出力され、高速で精度の高い検出が実現する。
【0023】
実際に列を走査する際に列線に供給される信号(列選択信号)としては、シフトレジスタからの出力やデコーダーからの出力などが利用される。列選択信号を供給するシフトレジスタやデコーダーも薄膜半導体装置にて作成しても良い。列選択信号を生成する回路をシフトレジスタとすると、シフトレジスタは各出力段に転送されて来る信号から列選択信号を作成し、これを順次列線に供給して行く。列選択信号を生成する回路をデコーダーとすると、デコーダーはデコーダーへの入力信号に応じてN個の出力段から特定の出力段を選定し、この出力段に列選択信号を供給する。即ち選定された出力段に接続した列線が選択される事に成る。此の様にしてN個の出力信号用パスゲートOLPGEjと静電容量検出素子ECSEijとには列線から適時選択信号が入力される。静電容量検出素子ECSEijは適時選択され、出力信号OSijは共通出力線に出力されて行く。
【0024】
先と同様、静電容量検出装置を効果的に機能させる為に、本発明の静電容量検出装置では出力線と列線とが第一配線にて配線され、電源線と共通出力線の一部乃至は全部が第二配線にて配線され、此等第一配線と第二配線とは絶縁膜を介して異なった層上に形成されて居る。更に容量検出電極は絶縁膜にて第一配線及び第二配線と異なった層上に形成されて居る第三配線にて配線される。又、容量検出電極は第一配線から第三配線の何れにて配線し得るが、静電容量検出装置中の配線の中で最も表面側に第三配線を位置させる。斯うした構成を成す事で余分な配線を除去し、以て各配線間に生ずる寄生容量を最小化せしめ、故に微少な静電容量を高感度にて検出せしめる訳である。
【0025】
斯様な静電容量検出素子は前述のSUFTLA技術を用いて、プラスティック基板上に形成され得る。単結晶硅素技術に基づく指紋センサはプラスティック上では直ぐに割れて仕舞ったり、或いは十分な大きさを有さぬが為に実用性に乏しい。これに対して本願発明に依るプラスティック基板上の静電容量検出素子は、プラスティック基板上で指を被うに十分に大きい面積としても静電容量検出素子が割れる心配もなく、プラスティック基板上での指紋センサとして利用し得る。具体的には本願発明により個人認証機能を兼ね備えたスマートカードが実現される。個人認証機能を備えたスマートカードは銀行カード(bankcard)やクレジットカード(credit card)、身分証明書(Identity card)等で使用され、此等のセキュリティーレベルを著しく高めた上で尚、個人指紋情報をカード外に流出させずに保護するとの優れた機能を有する。
(実施例1)
ガラス基板上に薄膜半導体装置からなる静電容量検出装置を製造した上で、此の静電容量検出装置をSUFTLA技術を用いてプラスティック基板上に転写し、プラスティック基板上に静電容量検出装置を作成した。静電容量検出装置は304行304列の行列状に並んだ静電容量検出素子から構成される。行列部の大きさは20mm角の正方形である。
【0026】
基板は厚み200μmのポリエーテルスルフォン(PES)である。信号増幅用MIS型薄膜半導体装置も信号転送用MIS型薄膜半導体装置も、出力信号パスゲート用MIS型薄膜半導体装置も、総て同じ断面構造を有する薄膜トランジスタにて作られている。薄膜トランジスタは図5に示すトップゲート型で工程最高温度425℃の低温工程にて作成される。半導体膜はレーザー結晶化にて得られた多結晶硅素薄膜でその厚みは50nmである。又、ゲート絶縁膜は化学気相堆積法(CVD法)にて形成された40nm厚の酸化硅素膜で、ゲート電極は厚み400nmのタンタル薄膜から成る。ゲート絶縁膜を成す酸化硅素膜の比誘電率はCV測定により約3.9と求められた。第一層間絶縁膜と第二層間絶縁膜及び第三層間絶縁膜は原料物質としてテトラエチルオーソシリケート(TEOS:Si(OCH2CH3)4)と酸素とを用いてCVD法にて形成した酸化硅素膜である。第一層間絶縁膜はゲート電極(本実施例では400nm)よりも20%程度以上厚く、第二層間絶縁膜よりも薄いのが望ましい。斯うするとゲート電極を確実に覆って、ゲート電極と第一配線乃至は第二配線との短絡を防止し、同時に第二層間絶縁膜を厚くし得るからである。本実施例では第一層間絶縁膜を500nmとした。第三層間絶縁膜は第二配線と容量検出電極とを分離し短絡を防止して居る。第一配線と容量検出電極とは第二層間絶縁膜と第三層間絶縁膜とによって分離されている。従って第一配線と容量検出電極との間に生ずる寄生容量を最小とし、好感度の静電容量検出装置を実現するには第二層間絶縁膜の誘電率と第三層間絶縁膜の誘電率とは出来る限り小さく、その厚みは出来る限り厚い方が好ましい。而るにCVD法にて積層された酸化硅素膜の総厚みが2μm程度を越えると酸化膜に亀裂が生ずる場合があり、歩留まりの低下をもたらす。従って第一層間絶縁膜と第二層間絶縁膜と第三層間絶縁膜との和は2μm程度以下とする。斯うする事で静電容量検出装置の生産性が向上する。先にも述べた様に第二層間絶縁膜と第三層間絶縁膜とは厚い方が好ましいので、第一層間絶縁膜よりも厚くする。第一層間絶縁膜はゲート電極よりも20%程度以上厚く、第二層間絶縁膜と第三層間絶縁膜とは第一層間絶縁膜よりも厚く、第一層間絶縁膜と第二層間絶縁膜と第三層間絶縁膜との和は2μm程度以下が理想的と言える。本実施例では第二層間絶縁膜の厚みを1μmとした。第一配線と第二配線は何れも500nm厚のアルミニウムより成り、配線幅は5μmである。第一配線に依り出力線と列線が形成され、第二配線にて電源線と共通出力線が形成され、インジウム錫酸化物(ITO)から成る第三配線に依り容量検出電極が配線された。容量検出電極と第二配線とは重なり部がない。此等の距離を余り離すと容量検出電極が小さくなって測定感度が落ちる為、第二配線と容量検出電極との距離は0.5μmから5μmの間とすべきである。本実施例では静電容量検出装置を成す行列のピッチを66μmとし、解像度を385dpi(dots per inch)としている。容量検出電極面積は1200μm2から1600μm2で有った。容量検出誘電体膜は厚み300nmの窒化硅素膜にて形成された。CV測定からこの窒化硅素膜の比誘電率は略7.5であった。
【0027】
回路構成は図4Bとし、信号増幅用MIS型薄膜半導体装置と信号転送用MIS型薄膜半導体装置はN型薄膜トランジスタにて形成し、出力信号パスゲート用MIS型薄膜半導体装置はCMOS薄膜トランジスタにて形成した。列線には選択時に正電源電位Vdd(4.0V)を供給し、非選択時には負電源電位Vss(0V)を供給した。又電源線には選択時に正電源電位Vdd(4.0V)を供給し、非選択時には負電源電位Vss(0V)を供給した。列線の選択も電源線の選択もCMOS薄膜トランジスタにて作られたシフトレジスタからの信号を利用した。信号増幅用MIS型薄膜半導体装置と信号転送用MIS型薄膜半導体装置のゲート長は3μmで、ゲート幅は10μmであった。又、出力信号パスゲート用薄膜半導体装置を為すN型及びP型薄膜トランジスタのゲート長は共に3μmで、ゲート幅は共に270μmであった。CMOSパスゲートを構成するN型薄膜トランジスタのゲート電極には列線に供給される列選択信号を入力し、P型薄膜トランジスタのゲート電極には列選択信号を反転させた信号を入力した。
【0028】
此の様な構成にて静電容量検出装置を作成したところフレーム周波数5Hzにて良好な指紋画像が採取された。
【0029】
【発明の効果】
以上詳述してきた様に、従来の単結晶硅素基板を用いた技術では数mm×数mm程度の小さな静電容量検出装置しかプラスティック基板上に形成出来なかったが、本願発明に依るとその百倍もの面積を有する静電容量検出装置をプラスティク基板上に作成する事が実現し、しかも対象物の凹凸情報を窮めて高精度に検出出来る様になった。その結果、例えばスマートカードのセキュリティーレベルを著しく向上せしめるとの効果が認められる。又、単結晶硅素基板を用いた従来の静電容量検出装置は装置面積の極一部しか単結晶硅素半導体を利用して居らず、莫大なエネルギーと労力とを無駄に費やしていた。これに対し本願発明では斯様な浪費を排除し、地球環境の保全に役立つとの効果を有する。
【図面の簡単な説明】
【図1】 従来技術に於ける動作原理を説明した図。
【図2】 本願発明に於ける動作原理を説明した図。
【図3】 本願発明に於ける動作原理を説明した図。
【図4】A 信号転送素子を持たない静電容量検出装置を説明した図。B 本願発明全体構成を説明した図。C 本願発明全体構成を説明した図。
【図5】 本願発明の素子構造を説明した図。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a capacitance detection device that reads the surface shape of an object having fine irregularities such as fingerprints by detecting the capacitance that changes according to the distance from the object surface.
[0002]
[Prior art]
Conventionally, a capacitance detection device used for a fingerprint sensor or the like has formed a sensor electrode and a dielectric film provided on the sensor electrode in a matrix on a single crystal silicon substrate (Japanese Patent Application Laid-Open No. 11-118415, special feature). (Open 2000-346608, JP 2001-56204 A, JP 2001-133213 A, etc.). FIG. 1 illustrates the principle of operation of a conventional capacitance detection device. The sensor electrode and the dielectric film form one electrode of the capacitor and the dielectric film, and the other body is grounded. Capacitance C of this capacitor F Changes according to the unevenness of the fingerprint in contact with the surface of the dielectric film. On the other hand, the capacitance C S Is prepared, and these two capacitors are connected in series, and a predetermined voltage is applied. As a result, a charge Q corresponding to the unevenness of the fingerprint is generated between the two capacitors. This electric charge Q was detected using ordinary semiconductor technology, and the surface shape of the object was read.
[0003]
[Problems to be solved by the invention]
However, since these conventional capacitance detection devices are formed on a single crystal silicon substrate, when the device is used as a fingerprint sensor, when the finger is pressed strongly, the device breaks down. I had it.
[0004]
Furthermore, the fingerprint sensor is inevitably required to have a size of about 20 mm × 20 mm depending on its use, and most of the capacitance detection device area is occupied by the sensor electrode. Of course, the sensor electrode is made on a single crystal silicon substrate, but most of the single crystal silicon substrate (bottom part of the sensor electrode) produced by expending enormous energy and labor plays only a role as a support. That is, the conventional capacitance detection device is not only expensive, but has a problem that it is formed on a great deal of waste and waste.
[0005]
In addition, in recent years, it is strongly pointed out that a personal authentication function should be provided on a card such as a credit card or a cash card to enhance the safety of the card. However, since a conventional capacitance detection device made on a single crystal silicon substrate lacks flexibility, there is a problem that the device cannot be made on a plastic substrate.
[0006]
In view of the above-mentioned circumstances, the present invention is intended to operate stably, further reduce unnecessary energy and labor at the time of manufacture, and excellent electrostatic capacity that can be created other than a single crystal silicon substrate. To provide a capacity detection device.
[0007]
[Means for Solving the Problems]
The present invention is based on detecting a capacitance that changes in accordance with the distance from an object, and is a capacitance detection device that reads the surface shape of an object. The capacitance detection device has M rows and N columns. M power lines arranged in a matrix, N output lines, each power line (i-th power line PLi, i is an integer from 1 to M) and each output line (j-th column) A capacitance detecting element (capacitance detecting element ECSEij located in i row and j column) provided at an intersection with the output line OLj, j is an integer from 1 to N, and this capacitance The detection element (ECSEij) includes a signal detection element (SSEij), a signal amplification element (SAEij), and a signal transfer element (STEij). The signal detection element includes a capacitance detection electrode and a capacitance detection dielectric film. Consists of a MIS thin film semiconductor device for signal amplification (TSD-SAij) consisting of a gate electrode, a gate insulating film, and a semiconductor film. Characterized in that consisting of a gate insulating film and the MIS type thin film semiconductor device for signal transfer comprising a semiconductor film (TSD-STij). Further, this capacitance detection device has N column lines, and the source region of the MIS type thin film semiconductor device (TSD-SAij) for signal amplification is connected to the output line (OLj) of the jth column for signal amplification. The drain region of the MIS type thin film semiconductor device (TSD-SAij) for use and the source region of the MIS type thin film semiconductor device for signal transfer (TSD-STij) are connected, and the MIS type thin film semiconductor device for signal transfer (TSD-STij) The drain region is connected to the i-th power line (PLi), the gate electrode of the signal amplification MIS thin film semiconductor device (TSD-SAij) is connected to the capacitance detection electrode, and the signal transfer MIS thin film semiconductor device ( The gate electrode of TSD-STij is connected to the column line (CLj) of the j-th column. Alternatively, the positional relationship in the capacitance detection element (ECSEij) between the MIS thin film semiconductor device for signal transfer (TSD-STij) and the MIS thin film semiconductor device for signal amplification (TSD-SAij) may be exchanged. . Specifically, this capacitance detection device has N column lines, and the drain region of the signal amplification MIS type thin film semiconductor device (TSD-SAij) is connected to the i-th power supply line (PLi). The source region of the MIS thin film semiconductor device for signal amplification (TSD-SAij) and the drain region of the MIS thin film semiconductor device for signal transfer (TSD-STij) are connected, and the MIS thin film semiconductor device for signal transfer (TSD- The source region of STij) is connected to the output line (OLj) of the j-th column, the gate electrode of the signal amplification MIS thin film semiconductor device (TSD-SAij) is connected to the capacitance detection electrode, and the signal transfer MIS thin film Another feature is that the gate electrode of the semiconductor device (TSD-STij) is connected to the j-th column line (CLj). Furthermore, in the capacitance detection device of the present invention, the output line and the column line are wired by the first wiring, the power line is wired by the second wiring, and the first wiring and the second wiring are different through an insulating film. It is also characterized by being formed on a layer. Further, the capacitance detection electrode is wired by a third wiring, and the first wiring, the second wiring, and the third wiring are formed on different layers through an insulating film. Furthermore, the third wiring is characterized in that it is located on the most surface side of the wiring of the capacitance detection device.
[0008]
The present invention is based on detecting a capacitance that changes in accordance with the distance from an object, and is a capacitance detection device that reads the surface shape of an object. The capacitance detection device has M rows and N columns. M power lines arranged in a matrix, N output lines, N column lines, power lines (i-th power line PLi, i is an integer from 1 to M) and outputs Capacitance detection element (capacitance detection element ECSEij located in i row and j column) provided at the intersection with the line (j-th output line OLj, j is an integer from 1 to N), N lines An output signal selection circuit connected to the output line and the N column lines. The capacitance detection element (ECSEij) includes a signal detection element (SSEij), a signal amplification element (SAEij), and a signal transfer element (STEij). The output signal selection circuit includes a common output line and an output signal pass gate (output signal pass gate OLPGEj located in the j-th column), and a signal detection element (SSEij). Includes a capacitance detection electrode and a capacitance detection dielectric film, and the signal amplification element (SAEij) is composed of a signal amplification MIS type thin film semiconductor device (TSD-SAij) composed of a gate electrode, a gate insulating film, and a semiconductor film. The element (STEij) comprises a signal transfer MIS thin film semiconductor device (TSD-STij) comprising a gate electrode, a gate insulating film and a semiconductor film, and the output signal pass gate (OLPGEj) comprises a gate electrode, a gate insulating film and a semiconductor film. It is characterized by comprising a MIS type thin semiconductor device (TSD-OLPGj) for an output signal pass gate. Further, the source region of the MIS thin film semiconductor device for signal amplification (TSD-SAij) is connected to the output line (OLj) of the jth column, and the signal transfer with the drain region of the MIS thin film semiconductor device for signal amplification (TSD-SAij) Is connected to the source region of the MIS thin film semiconductor device (TSD-STij) for use, and the drain region of the MIS thin film semiconductor device for signal transfer (TSD-STij) is connected to the power line (PLi) of the i row. The gate electrode of the amplification MIS thin film semiconductor device (TSD-SAij) is connected to the capacitance detection electrode, and the gate electrode of the signal transfer MIS thin film semiconductor device (TSD-STij) is the column line (CLj) of the jth column. The source region of the MIS thin film semiconductor device for output signal pass gate (TSD-OLPGj) is connected to the common output line, and the drain region of the MIS thin film semiconductor device for output signal pass gate (TSD-OLPGj) is j columns. The output signal is connected to the output line (OLj) of the eye. The gate electrode of the MIS thin film semiconductor device (TSD-OLPGj) for signal pass gate is connected to the column line (CLj) of the j-th column. Alternatively, the positional relationship in the capacitance detection element (ECSEij) between the MIS thin film semiconductor device for signal transfer (TSD-STij) and the MIS thin film semiconductor device for signal amplification (TSD-SAij) may be exchanged. . Specifically, the drain region of the MIS thin film semiconductor device for signal amplification (TSD-SAij) is connected to the i-th power line (PLi), and the source of the MIS thin film semiconductor device for signal amplification (TSD-SAij). And the drain region of the MIS thin film semiconductor device for signal transfer (TSD-STij) is connected, and the source region of the MIS thin film semiconductor device for signal transfer (TSD-STij) is an output line (OLj ), The gate electrode of the MIS thin film semiconductor device for signal amplification (TSD-SAij) is connected to the capacitance detection electrode, and the gate electrode of the MIS thin film semiconductor device for signal transfer (TSD-STij) is j Connected to the column line (CLj) of the column, the source region of the MIS thin film semiconductor device for output signal pass gate (TSD-OLPGj) is connected to the common output line, and the MIS thin film semiconductor device for output signal pass gate ( TSD-OLPGj) drain region is j columns The gate electrode of the MIS type thin film semiconductor device (TSD-OLPGj) for the output signal pass gate is connected to the j-th column line (CLj).
[0009]
In the capacitance detection device of the present invention, the output line and the column line are wired by the first wiring, and the power supply line and the common output line are wired by the second wiring. It is also characterized by being formed on different layers via an insulating film. Further, the capacitance detection electrode is wired by a third wiring, and the first wiring, the second wiring, and the third wiring are formed on different layers through an insulating film. Further, the third wiring is characterized in that it is located on the most surface side among the wirings of the capacitance detection device.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
According to the present invention, an electrostatic capacity detection device that reads a surface shape of an object by detecting an electrostatic capacity that changes in accordance with the distance to the object is a MIS type thin film semiconductor device comprising a metal-insulating film-semiconductor film. Create using. A thin-film semiconductor device is generally known as a technique for manufacturing a semiconductor integrated circuit requiring a large area on a glass substrate at low cost. As a specific example, it has recently been applied to a liquid crystal display device or the like. Therefore, when a capacitance detection device adapted to a fingerprint sensor or the like is made with a thin film semiconductor device, it is not necessary to use an expensive substrate made by consuming a great amount of energy such as a single crystal silicon substrate. Therefore, the apparatus can be produced at low cost without wasting valuable earth resources. In addition, a thin film semiconductor device adopts a transfer technique called SUFTLA (Japanese Patent Laid-Open No. 11-312811 and S. Utsunomiya et. Al. Society for Information Display p. 916 (2000)), so that a semiconductor integrated circuit is formed on a plastic substrate. Since it can be made, the capacitance detecting device can be released from the single crystal silicon substrate and formed on the plastic substrate.
[0011]
Now, as shown in FIG. 1, it is impossible to produce a capacitance detecting device to which a conventional operation principle is applied using a thin film semiconductor device with the current technology of the thin film semiconductor device. Since the charge Q induced between two capacitors connected in series is very small, the charge Q can be accurately read using single crystal silicon LSI technology that enables high-precision sensing. However, the charge Q cannot be read accurately because it is not as good as single crystal silicon LSI technology and the characteristic deviation between thin film semiconductor devices is large.
[0012]
Accordingly, the capacitance detection device of the present invention has at least M (M is an integer of 1 or more) power supply lines and N (N is an integer of 1 or more) outputs arranged in a matrix of at least M rows and N columns. Line and each power line (i-th power line PLi, i is an integer from 1 to M) and each output line (j-th output line OLj, j is an integer from 1 to N) Provided with a capacitance detection element (capacitance detection element ECSEij located in i row and j column), and this capacitance detection element has a signal detection element and a signal amplification element as minimum components. Including. An example of the capacitance detection device having such a configuration is shown in FIG. 4A. The signal detection element includes a capacitance detection electrode and a capacitance detection dielectric film, and a charge Q is generated in the capacitance detection electrode according to the capacitance. In the present invention, this electric charge Q is amplified by a signal amplifying element provided in each capacitance detecting element and converted into a current or a voltage. Specifically, the signal amplifying element includes a signal amplifying MIS thin film semiconductor device including a gate electrode, a gate insulating film, and a semiconductor film, and the gate electrode of the signal amplifying MIS thin film semiconductor device is connected to the capacitance detection electrode. .
[0013]
FIG. 2 shows an operation principle diagram of the present invention. Capacitance C s And a capacitance C that changes according to the surface shape of the object F The voltage divided by the capacitive coupling with the capacitor having, changes the gate potential of the MIS thin film semiconductor device for signal amplification. Thus, when a predetermined voltage is applied to the drain region of this thin film semiconductor device, the current I flowing between the source and drain of the thin film semiconductor device is significantly amplified according to the voltage induced by capacitive coupling. Since the charge Q itself induced in the gate electrode does not flow anywhere and is stored, the current Ids can be easily measured by increasing the drain voltage or lengthening the measurement time. Therefore, the thin film semiconductor device is used. However, the surface shape of the object can be measured sufficiently accurately.
[0014]
As described above, in the present invention, the signal amplifying MIS thin film semiconductor device is used as the signal amplifying element. In this case, the capacitance C s The capacitor having MIS can be used as the MIS type thin film semiconductor device for signal amplification. That is, capacitance C s Transistor capacitance C of MIS type thin film semiconductor device for signal amplification T Yes. By doing so, the capacitance C is changed from the capacitance detection element. s Capacitors with can be omitted, the structure is simplified and the manufacturing process is simplified. In addition, it can be said that combining the two power sources depicted in FIG. 2 as a common power source Vdd is effective from the viewpoint that unnecessary wiring in the capacitance detection device can be omitted. FIG. 3 shows an equivalent circuit diagram relating to the operating principle in such a state. Capacitance C that changes according to the surface shape of the object F Capacitor and transistor capacitance C T Is connected in series with a capacitor having Strictly speaking, transistor capacity C T Is a capacitance formed between the drain electrode and the gate electrode of the MIS thin film semiconductor device for signal amplification. To realize the configuration of FIG. 3, as shown in FIG. 4, the source region of the signal amplifying MIS thin film semiconductor device is connected to the output line, and the drain region of the signal amplifying MIS thin film semiconductor device is connected to the power supply line. Then, the voltage Vdd is applied to the power supply line, and the current Ids that changes in accordance with the surface shape of the object is extracted from the output line. For example, if each capacitor is set appropriately, and the peak of the fingerprint touches the signal detection element, the signal amplification element becomes a high resistance and cuts off the power line and the output line (almost no current Ids is passed). When the valley of the fingerprint faces the signal detecting element, the signal amplifying element has a low resistance and conducts the power line and the output line (passes the current Ids). Such a change in the amount of current and a change in the voltage applied to the output line are sensed to detect the capacitance caused by the fingerprint shape and the like.
[0015]
In principle, it is possible to collect surface shape information such as fingerprints with such a configuration, but a plurality of capacitance detection elements are connected to each power supply line and each output line arranged in a matrix. As a result, interference of information occurs between the capacitance detection elements. When the surface shape of the object is read by the capacitance detection element ECSEij in the capacitance detection device having the configuration shown in FIG. 4A, the voltage Vdd is applied to the power supply line PLi, and the output signal OSij is extracted from the output line OLj. . If the signal amplification element SAEij has a high resistance, the output line OLj must have a low potential. At this time, since the voltage Vdd is also applied to all the capacitance detection elements ECSEiy (y is an integer from 1 to N) connected to the power line PLi, each output line OLy has An output signal OSiy corresponding to the surface shape read through the capacitance detection element ECSEiy flows. For example, if the signal amplifying element SEAij + 1 is in a low resistance state, the output
[0016]
Therefore, in the present invention, it is possible to reliably detect the capacitance by accurately selecting each capacitance detection element and using a signal transfer element for controlling the operation to prevent interference between detection information elements. To do. The capacitance detection device of the present invention includes M (M is an integer of 1 or more) power supply lines arranged in a matrix of M rows and N columns, N (N is an integer of 1 or more) output lines, and Provided at the intersection of each power line (i-th power line PLi, i is an integer from 1 to M) and each output line (j-th output line OLj, j is an integer from 1 to N) A capacitance detection element (capacitance detection element ECSEij located in i row and j column), and this capacitance detection element ECSEij includes a signal detection element SSEij, a signal amplification element SAEij, and a signal transfer element STEij. Including. The signal detection element SSEij includes a capacitance detection electrode and a capacitance detection dielectric film, detects the capacitance, and converts the capacitance into a voltage. The signal amplification element SAEij is composed of a signal amplification MIS type thin film semiconductor device TSD-SAij composed of a gate electrode, a gate insulating film and a semiconductor film, and the signal transfer element STEij is composed of a signal transfer composed of a gate electrode, a gate insulating film and a semiconductor film. MIS type thin film semiconductor device TSD-STij. The MIS thin film semiconductor device TSD-SAij for signal amplification and the MIS thin film semiconductor device TSD-STij for signal transfer are connected in series in the capacitance detection element ECSEij.
[0017]
An example of a capacitance detection device that realizes such a configuration will be described in detail with reference to FIGS. 4B and 4C. (In FIG. 4B and FIG. 4C, the source region of the MIS thin film semiconductor device is indicated by S, the drain region is indicated by D, and the gate electrode is indicated by G. The source region and drain region are potentials in the N type semiconductor device. The lower one is defined as the source region, and in the P-type semiconductor device, the higher potential is defined as the source region.) In the electrostatic capacitance detection element ECSEij in FIGS. 4B and 4C, the signal amplification MIS thin film semiconductor device TSD- SAij and the MIS thin film semiconductor device TSD-STij for signal transfer are connected in series between the power supply line PLi and the output line OLj. Accordingly, output signal interference between the capacitance detection elements can be prevented, and a capacitance detection device with high detection accuracy can be realized. Actually, when the output signal from the capacitance detection element ECSEij is read out, the i-th power line is selected to be a high potential, and in this state, the signal is transferred to the gate electrode of the MIS thin film semiconductor device TSD-STij. By controlling the applied voltage, only the capacitance detection element ECSEij can be selected. According to the previous example, in FIG. 4A, the interference of the output signal has occurred in the output line OLj through the path from OSij to OSij + 1 and the reverse output signals OSi-
[0018]
As described so far, one method of preventing interference of information generated when collecting surface shape information using a capacitance detection device including a signal transfer element is based on column selection. Is to control. Therefore, in the capacitance detection device of the present invention, a column line CLj for controlling the operation of the capacitance detection element is provided for each column, and the signal transfer element STEij is selected (signal) according to the voltage applied to the column line CLj. The operation of the capacitance detection element ECSEij is controlled by switching between the transfer element STEij being in a conductive state with a low resistance) or non-selection (the signal transfer element STEij being in a high resistance and a cutoff state). Specifically, the capacitance detection device of the present invention also includes N column lines CLj. That is, each matrix element of the capacitance detection device including a matrix of M rows and N columns includes a power supply line PLi, an output line OLj, a column line CLj, and a capacitance detection element ECSEij. The source region of the signal amplification MIS thin film semiconductor device TSD-SAij is electrically connected to the output line OLj of the jth column, and the drain region of the signal amplification MIS thin film semiconductor device TSD-SAij and the signal transfer MIS thin film. The source region of the semiconductor device TSD-STij is electrically connected, and the drain region of the signal transfer MIS thin film semiconductor device TSD-STij is electrically connected to the i-th power line PLi. Being electrically connected means not only that they are directly connected but also that electrical connection is established through some kind of switch element. For example, another transistor may be arranged in series between the signal transfer element and the power supply line. If the arranged transistor is in a selected state and has a low resistance, it can be said that the signal transfer element and the power supply line are electrically connected since conduction is established between the signal transfer element and the power supply line. The gate electrode of the signal amplification MIS thin film semiconductor device TSD-SAij is electrically connected to the capacitance detection electrode, and the gate electrode of the signal transfer MIS thin film semiconductor device TSD-STij is electrically connected to the column line CLj of the j-th column. Connected to. The overall structure of the capacitance detection device having such a configuration is shown in FIG. 4B. Contrary to the above configuration, the positional relationship in the electrostatic capacitance detection element ECSEij between the signal transfer MIS thin film semiconductor device TSD-STij and the signal amplification MIS thin film semiconductor device TSD-SAij may be exchanged. . Specifically, the capacitance detection element according to another embodiment of the present invention includes N column lines CLj, and the drain region of the signal amplification MIS thin film semiconductor device TSD-SAij is the power line PLi of the i-th row. MIS type thin film semiconductor device TSD-SAij for signal amplification and the drain region of MIS type thin film semiconductor device TSD-STij for signal transfer are electrically connected to each other, and the MIS type thin film for signal transfer is connected. The source region of the semiconductor device TSD-STij is electrically connected to the i-th output line OLj. The gate electrode of the signal amplification MIS thin film semiconductor device TSD-SAij is electrically connected to the capacitance detection electrode, and the gate electrode of the signal transfer MIS thin film semiconductor device TSD-STij is electrically connected to the column line CLj of the j-th column. Connected to. The overall structure of the capacitance detecting device having such a configuration is shown in FIG. 4C. With such a configuration, a high potential Vdd can be applied to the power supply line PLi to select the i row, and a predetermined selection potential is applied to the column line CLj to select the j column. Thus, the output signal OSij (voltage Vij or current Iij) read by the capacitance detection element ECSEij according to the surface shape can be accurately taken out from the output line OLj. For example, when the surface shape is measured by the capacitance detection element ECSEij in the configuration of FIG. 4B or 4C, the voltage Vdd is applied to the power supply line PLi, the i row is selected, and the same voltage is applied to the column line CLj. Apply Vdd and select column j. First, N electrostatic capacity detection elements ECSEib (b is an integer from 1 to N) connected to the power supply line PLi to which the positive power supply voltage Vdd is applied are selected, and further, the selection is made based on the column line CLj. Only the electrostatic capacitance detection element ECSEij belonging to the j column is selected and put into operation. Thus, the diffusion of output information via the capacitance detection device ECSEiy of the non-selected column (y is an integer from 1 to M excluding i) is eliminated, and between the power supply line PLi and the output line OLj The information inflow path other than the capacitance detection element ECSEij is cut off. Therefore, the output signal OSij (voltage Vij or current Iij) corresponding to the surface shape is output to the output line OLj only through the capacitance detection element ECSEij, and information interference between the capacitance detection elements can be prevented.
[0019]
In order to effectively function the capacitance detection device having such a configuration, in the capacitance detection device of the present invention, the output line and the column line are wired by the first wiring, and the power supply line is the second wiring. The first wiring and the second wiring are formed on different layers through an insulating film. Furthermore, the capacitance detection electrode is wired with a third wiring formed on a different layer from the first wiring and the second wiring with an insulating film. Further, the capacitance detection electrode can be wired by any of the first wiring to the third wiring, but the third wiring is positioned on the most surface side among the wiring in the capacitance detection device. By forming such a configuration, excess wiring is removed, thereby minimizing the parasitic capacitance generated between the respective wirings, and thus detecting a very small capacitance with high sensitivity. An example of the structure of a capacitance detection element embodying the present invention will be described with reference to FIG. In FIG. 5, the source region of the MIS type thin film semiconductor device is indicated by S, the drain region is indicated by D, and the gate electrode is indicated by G. The signal amplifying MIS thin film semiconductor device constituting the signal amplifying element of the capacitance detecting element and the signal transferring MIS thin film semiconductor device constituting the signal transfer element each include a source region, a channel forming region, and a drain region. The semiconductor film, the gate insulating film, and the gate electrode are indispensable constituent requirements. In the configuration example of FIG. 5, the drain region of the signal amplification MIS thin film semiconductor device and the source region of the signal transfer MIS semiconductor device are provided as one region. The first interlayer insulating film covers the MIS type thin film semiconductor device. A first wiring is connected to the source region of the MIS thin film semiconductor device for signal amplification, and a second wiring is connected to the drain region of the MIS thin film semiconductor device for signal transfer. Alternatively, the first wiring may be connected to the drain region of the signal amplification MIS thin film semiconductor device, and the second wiring may be connected to the source region of the signal transfer MIS thin film semiconductor device. A second interlayer insulating film is provided between the first wiring and the second wiring, and the first wiring and the second wiring are formed on different layers. Of course, the second wiring can be formed on the first interlayer insulating film, and the first wiring can be formed on the second interlayer insulating film. A capacitance detection electrode constituting a signal detection element of the capacitance detection element is provided as a third wiring and is connected to the gate electrode of the signal amplification MIS thin film semiconductor device. The third wiring is formed on a third interlayer insulating film provided on the second interlayer insulating film, and is formed on a layer different from the first wiring and the second wiring. The capacitance detection electrode and the first wiring or the second wiring are on layers different from those other than the part that is electrically connected (the part that is made equipotential in an ideal system with zero electrical resistance). Arrange them so that they do not overlap each other. In order to detect a minute capacitance, it is necessary to minimize the parasitic capacitance. By adopting the above configuration, the capacitance detection electrode and the second wiring, or the capacitance detection electrode and the second wiring parasitic capacitance are minimized. Therefore, a highly sensitive capacitance detection device is realized. A capacitance detection dielectric film covers the capacitance detection electrode, and the capacitance detection dielectric film is located on the outermost surface of the capacitance detection device. The capacitance detection dielectric film also plays the role of a protective film of the capacitance detection device. In order to function efficiently as a protective film, it is desirable that the relative dielectric constant of the capacitance detection dielectric film be larger than that of the second interlayer insulating film or the third interlayer insulating film.
[0020]
Next, a method for reading an output signal from the capacitance detection device according to the present invention will be described with reference to FIGS. 4B and 4C. Since the capacitance detection elements of the present invention are arranged in a matrix of M rows and N columns, in order to read the surface shape of the object, the rows and columns are sequentially scanned, and M × N electrostatic capacitances are detected. Capacitance detection elements are selected in an appropriate order. That is, after applying the voltage Vdd to the power line PLi, the column line CLj is sequentially selected, and the operation of reading the output signal OSij appearing on the output line OLj is repeated. At this time, the output signal selection circuit determines in what order the output signals detected from the respective capacitance detection elements are read out. Specifically, the capacitance detection device of the present invention includes M power supply lines arranged in a matrix of M rows and N columns, N output lines, N column lines, and power supply lines (i Capacitance detection element provided at the intersection of the power line PLi, i in the row, i is an integer from 1 to M) and each output line (output line OLj in the j-th column, j is an integer from 1 to N) (Capacitance detection element ECSEij located in i row j column), N output lines, and an output signal selection circuit connected to the N column lines. Each matrix element of the M rows and N columns matrix is composed of a power supply line PLi, an output line OLj, a column line CLj, and a capacitance detection element ECSEij. N output lines and N column lines connected to each matrix element are connected to an output signal selection circuit. The capacitance detection element ECSEij includes a signal detection element SSEij, a signal amplification element SAEij, and a signal transfer element STEij. The output signal selection circuit includes at least a common output line (LDOUT) and an output signal pass gate (output signal pass gate OLPGEj located in the j-th column). The signal detection element SSEij includes a capacitance detection electrode and a capacitance detection dielectric film. The signal amplifying element SAEij is composed of a signal amplifying MIS type thin film semiconductor device TSD-SAij composed of a gate electrode, a gate insulating film and a semiconductor film, and the signal transfer element STEij is composed of a signal composed of a gate electrode, a gate insulating film and a semiconductor film. The MIS type thin film semiconductor device TSD-STij for transfer and the output signal pass gate OLPGEj are constituted by the MIS type thin semiconductor device TSD-OLPGj for output signal pass gate comprising a gate electrode, a gate insulating film, and a semiconductor film. The output signal selection circuit takes out an output signal from a column selected by a decoder, a shift register or the like to a common output line. That is, when the j-th column line CLj is selected among the N column lines, the output signal OSj appearing on the j-th output line OLj among the N output lines is selectively output in common. Take out to the line. In the capacitance detection device of the present invention, all output signals are output to a common output line. With such a configuration, when detecting each output signal OSj, it is necessary to provide a device for detecting the output signal on each output line OLj individually, which makes it difficult to manufacture and provides N connection terminals. This also causes a variation in connection, which increases the measurement error. Therefore, in the capacitance detection device of the present invention, all output signals are output from several (about 1 to 8) common output lines, facilitating the mounting process with an external circuit and the like, and resulting from the connection terminals. This minimizes the variation in connection to achieve high-accuracy measurement. Also, simply connecting the common output line and the output line (although measurement is still possible), the output lines are connected directly via the common output line, and the output signal is widely distributed to other output lines. Spread and finish. This is not preferable for detecting a weak output signal at high speed and with high accuracy. Therefore, in the capacitance detection device of the present invention, an output signal pass gate OLPGEj for controlling the electrical conduction of the output signal is provided between each output line OLj and the common output line. Under such a configuration, the output signal OSij stops only in the selected output line OLij and the common output line, and does not spread to other unselected output lines. For example, when the output signal is read as a voltage, the potentials of only the selected output line and the common output line can be changed, so that highly accurate detection can be performed in a short time.
[0021]
In the capacitance detection device of the present invention, in order to efficiently read out the output signal from the common output line, only the output line OLj of the column selected by the column line CLj needs to be electrically connected to the common output line. There is. Therefore, in the capacitance detection element of the present invention, the capacitance detection element ECSEij located in the j-th column is selected by the column line CLj, and at the same time, the electrical conduction state of the output signal pass gate OLPGEj connected to the j-th output line OLj is determined. Control. As an example, the output signal pass gate OLPGEj includes an output signal pass gate MIS type thin film semiconductor device TSD-OLPGj. More specifically, in the capacitance detection device of the present invention, the source region of the signal amplification MIS type thin film semiconductor device TSD-SAij is electrically connected to the output line OLj of the jth column, and the signal amplification MIS type thin film semiconductor. The drain region of the device TSD-SAij is electrically connected to the source region of the signal transfer MIS thin film semiconductor device TSD-STij, and the drain region of the signal transfer MIS thin film semiconductor device TSD-STij is the power supply in the i-th row. Electrically connected to the line PLi, the gate electrode of the signal amplification MIS thin film semiconductor device TSD-SAij is electrically connected to the capacitance detection electrode, and the gate electrode of the signal transfer MIS thin film semiconductor device TSD-STij is j The source region of the MIS type thin film semiconductor device TSD-OLPGj for the output signal pass gate provided in the j-th column is electrically connected to the common output line and is electrically connected to the column line CLj of the column. MIS type thin film semiconductor device TSD-OLPGj The rain region is electrically connected to the j-th column output line OLj, and the gate electrode of the output signal pass gate MIS thin film semiconductor device TSD-OLPGj is electrically connected to the j-th column line CLj. FIG. 4B shows the overall structure of the capacitance detection device having such a configuration. Alternatively, the positional relationship in the capacitance detection element ECSEij between the MIS thin film semiconductor device TSD-STij for signal transfer and the MIS thin film semiconductor device TSD-SAij for signal amplification may be exchanged. Specifically, in the capacitance detection device of the present invention, the drain region of the signal amplification MIS thin film semiconductor device TSD-SAij is electrically connected to the i-th power line PLi, and the signal amplification MIS thin film. The source region of the semiconductor device TSD-SAij and the drain region of the signal transfer MIS thin film semiconductor device TSD-STij are electrically connected, and the source region of the signal transfer MIS thin film semiconductor device TSD-STij is in the jth column. The gate electrode of the signal amplification MIS thin film semiconductor device TSD-SAij is electrically connected to the capacitance detection electrode, and the gate electrode of the signal transfer MIS thin film semiconductor device TSD-STij is electrically connected to the output line OLj. The MIS type thin film semiconductor device TSD-OLPGj for output signal pass gate is electrically connected to the common output line and is electrically connected to the column line CLj of the jth column, and the MIS type thin film semiconductor device TSD for output signal pass gate is used. -OLPGj drain region is jth column The output signal pass gate MIS type thin film semiconductor device TSD-OLPGj is connected to the j-th column line CLj. FIG. 4C shows the overall structure of the capacitance detection device having such a configuration. Electrically connected means that electrical continuity is taken directly or indirectly as described above.
[0022]
With such a configuration, when the j-th column line CLj is selected from among the N column lines, one output line OLj located in the j-th column among the N output lines is simultaneously selected. This makes it possible to prevent the output signal from being diffused to other output lines. As a result, the output signal OSij from the capacitance detection element ECSEij selected by the power supply line PLi and the column line CLj is output only to the output line OLj and to the common output line via the output signal pass gate OLPGEj. High-speed and high-precision detection is realized.
[0023]
As a signal (column selection signal) supplied to the column line when actually scanning the column, an output from a shift register, an output from a decoder, or the like is used. A shift register and a decoder for supplying a column selection signal may also be formed by a thin film semiconductor device. If a circuit for generating a column selection signal is a shift register, the shift register creates a column selection signal from signals transferred to each output stage, and sequentially supplies this to the column lines. If the circuit that generates the column selection signal is a decoder, the decoder selects a specific output stage from the N output stages according to the input signal to the decoder, and supplies the column selection signal to this output stage. That is, the column line connected to the selected output stage is selected. In this way, selection signals are appropriately input from the column lines to the N output signal pass gates OLPGEj and the capacitance detection elements ECSEij. The capacitance detection element ECSEij is selected as appropriate, and the output signal OSij is output to the common output line.
[0024]
As before, in order for the capacitance detection device to function effectively, in the capacitance detection device of the present invention, the output line and the column line are wired by the first wiring, and one of the power supply line and the common output line is used. Parts or all are wired by the second wiring, and the first wiring and the second wiring are formed on different layers through an insulating film. Furthermore, the capacitance detection electrode is wired with a third wiring formed on a different layer from the first wiring and the second wiring with an insulating film. Further, the capacitance detection electrode can be wired by any of the first wiring to the third wiring, but the third wiring is positioned on the most surface side among the wiring in the capacitance detection device. By forming such a configuration, excess wiring is removed, thereby minimizing the parasitic capacitance generated between the respective wirings, and thus detecting a very small capacitance with high sensitivity.
[0025]
Such a capacitance detection element can be formed on a plastic substrate using the above-described SUFTLA technology. A fingerprint sensor based on single-crystal silicon technology is not practical because it does not break down on a plastic, or does not have a sufficient size. On the other hand, the capacitance detection element on the plastic substrate according to the present invention does not have to worry about the capacitance detection element being cracked even if the area is sufficiently large to cover the finger on the plastic substrate, and the fingerprint on the plastic substrate. It can be used as a sensor. Specifically, a smart card having a personal authentication function is realized by the present invention. Smart cards with a personal authentication function are used for bank cards, credit cards, identity cards, etc., and with their security level significantly increased, personal fingerprint information It has an excellent function of protecting the card without flowing out of the card.
Example 1
After manufacturing a capacitance detection device made of a thin film semiconductor device on a glass substrate, the capacitance detection device is transferred onto a plastic substrate using SUFTLA technology, and the capacitance detection device is placed on the plastic substrate. Created. The capacitance detection device is composed of capacitance detection elements arranged in a matrix of 304 rows and 304 columns. The size of the matrix portion is a 20 mm square.
[0026]
The substrate is polyethersulfone (PES) having a thickness of 200 μm. The MIS thin film semiconductor device for signal amplification, the MIS thin film semiconductor device for signal transfer, and the MIS thin film semiconductor device for output signal pass gate are all made of thin film transistors having the same cross-sectional structure. The thin film transistor is a top gate type shown in FIG. The semiconductor film is a polycrystalline silicon thin film obtained by laser crystallization and has a thickness of 50 nm. The gate insulating film is a 40 nm thick silicon oxide film formed by chemical vapor deposition (CVD), and the gate electrode is a 400 nm thick tantalum thin film. The relative dielectric constant of the silicon oxide film forming the gate insulating film was determined to be about 3.9 by CV measurement. The first interlayer insulating film, the second interlayer insulating film and the third interlayer insulating film are made of tetraethyl orthosilicate (TEOS: Si (OCH 2 CH Three ) Four And a silicon oxide film formed by CVD using oxygen. The first interlayer insulating film is preferably about 20% or more thicker than the gate electrode (400 nm in this embodiment) and thinner than the second interlayer insulating film. This is because the gate electrode can be securely covered, a short circuit between the gate electrode and the first wiring or the second wiring can be prevented, and at the same time, the second interlayer insulating film can be thickened. In this embodiment, the first interlayer insulating film is 500 nm. The third interlayer insulating film separates the second wiring and the capacitance detection electrode to prevent a short circuit. The first wiring and the capacitance detection electrode are separated by the second interlayer insulating film and the third interlayer insulating film. Therefore, in order to minimize the parasitic capacitance generated between the first wiring and the capacitance detection electrode and realize a favorable capacitance detection device, the dielectric constant of the second interlayer insulating film and the dielectric constant of the third interlayer insulating film Is as small as possible, and the thickness is preferably as thick as possible. Thus, if the total thickness of the silicon oxide films laminated by the CVD method exceeds about 2 μm, cracks may occur in the oxide film, resulting in a decrease in yield. Accordingly, the sum of the first interlayer insulating film, the second interlayer insulating film, and the third interlayer insulating film is about 2 μm or less. By doing so, the productivity of the capacitance detection device is improved. As described above, since the second interlayer insulating film and the third interlayer insulating film are preferably thicker, they are made thicker than the first interlayer insulating film. The first interlayer insulating film is about 20% or more thicker than the gate electrode, the second interlayer insulating film and the third interlayer insulating film are thicker than the first interlayer insulating film, and the first interlayer insulating film and the second interlayer insulating film. The sum of the insulating film and the third interlayer insulating film is ideally about 2 μm or less. In this embodiment, the thickness of the second interlayer insulating film is 1 μm. Both the first wiring and the second wiring are made of aluminum having a thickness of 500 nm, and the wiring width is 5 μm. Output lines and column lines are formed by the first wiring, power supply lines and common output lines are formed by the second wiring, and capacitance detection electrodes are wired by the third wiring made of indium tin oxide (ITO). . There is no overlap between the capacitance detection electrode and the second wiring. If these distances are too far apart, the capacitance detection electrode becomes smaller and the measurement sensitivity decreases, so the distance between the second wiring and the capacitance detection electrode should be between 0.5 μm and 5 μm. In this embodiment, the pitch of the matrix forming the capacitance detection device is 66 μm, and the resolution is 385 dpi (dots per inch). Capacity detection electrode area is 1200μm 2 To 1600μm 2 It was in. The capacitance detection dielectric film was formed of a silicon nitride film having a thickness of 300 nm. From the CV measurement, the relative dielectric constant of this silicon nitride film was approximately 7.5.
[0027]
The circuit configuration is as shown in FIG. 4B. The MIS thin film semiconductor device for signal amplification and the MIS thin film semiconductor device for signal transfer are formed of N type thin film transistors, and the MIS thin film semiconductor device for output signal pass gate is formed of CMOS thin film transistors. A positive power supply potential Vdd (4.0 V) was supplied to the column line when selected, and a negative power supply potential Vss (0 V) was supplied when not selected. The positive power supply potential Vdd (4.0 V) was supplied to the power supply line when selected, and the negative power supply potential Vss (0 V) was supplied when not selected. The signal from the shift register made of CMOS thin film transistors was used for both the selection of the column lines and the selection of the power supply lines. The gate length of the MIS thin film semiconductor device for signal amplification and the MIS thin film semiconductor device for signal transfer was 3 μm and the gate width was 10 μm. The gate lengths of the N-type and P-type thin film transistors constituting the thin film semiconductor device for output signal pass gate were both 3 μm and the gate width was 270 μm. A column selection signal supplied to the column line is inputted to the gate electrode of the N-type thin film transistor constituting the CMOS pass gate, and a signal obtained by inverting the column selection signal is inputted to the gate electrode of the P-type thin film transistor.
[0028]
When a capacitance detecting device having such a configuration was produced, a good fingerprint image was collected at a frame frequency of 5 Hz.
[0029]
【The invention's effect】
As described above in detail, the conventional technology using a single crystal silicon substrate can form only a small capacitance detection device of about several mm × several mm on a plastic substrate. It is now possible to create a capacitance detection device having a large area on a plastic substrate, and it is possible to detect the unevenness information of an object with high accuracy. As a result, for example, the effect of significantly improving the security level of the smart card is recognized. Further, the conventional capacitance detection device using a single crystal silicon substrate uses a single crystal silicon semiconductor for only a very small part of the device area, and wastes enormous energy and labor. In contrast, the present invention has the effect of eliminating such waste and helping to preserve the global environment.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an operation principle in the prior art.
FIG. 2 is a diagram illustrating an operation principle in the present invention.
FIG. 3 is a diagram illustrating an operation principle in the present invention.
FIG. 4 is a diagram illustrating a capacitance detection device that does not have an A signal transfer element. B is a diagram illustrating the overall configuration of the present invention. C is a diagram illustrating the overall configuration of the present invention.
FIG. 5 is a diagram illustrating an element structure of the present invention.
Claims (10)
該静電容量検出装置はM行N列の行列状に配置されたM本の電源線と、N本の出力線、N本の列線、及び該電源線と該出力線との交点に設けられた静電容量検出素子とを具備し、
該静電容量検出素子は信号検出素子と信号増幅素子及び信号転送素子とを含み、
該信号検出素子は容量検出電極と容量検出誘電体膜とを含み、
該信号増幅素子はゲート電極とゲート絶縁膜と半導体膜とから成る信号増幅用MIS型薄膜半導体装置から成り、
該信号転送素子はゲート電極とゲート絶縁膜と半導体膜とから成る信号転送用MIS型薄膜半導体装置から成り、
前記信号増幅用MIS型薄膜半導体装置のソース領域は前記出力線に接続され、
前記信号増幅用MIS型薄膜半導体装置のドレイン領域と前記信号転送用MIS型薄膜半導体装置のソース領域とが接続され、
前記信号転送用MIS型薄膜半導体装置のドレイン領域は前記電源線に接続され、
前記信号増幅用MIS型薄膜半導体装置のゲート電極は前記容量検出電極に接続され、
前記信号転送用MIS型薄膜半導体装置のゲート電極は前記列線に接続される事を特徴とする静電容量検出装置。In the capacitance detection device that reads the surface shape of the object by detecting the capacitance that changes according to the distance to the object,
The capacitance detection device is provided at an intersection of M power lines arranged in a matrix of M rows and N columns, N output lines, N column lines, and the power lines and the output lines. A capacitance detecting element provided,
The capacitance detection element includes a signal detection element, a signal amplification element, and a signal transfer element,
The signal detection element includes a capacitance detection electrode and a capacitance detection dielectric film,
The signal amplifying element comprises a MIS thin film semiconductor device for signal amplification comprising a gate electrode, a gate insulating film, and a semiconductor film,
The signal transfer element Ri consists signal transfer MIS thin film semiconductor device including a gate electrode, a gate insulating film and the semiconductor film,
A source region of the MIS thin film semiconductor device for signal amplification is connected to the output line,
A drain region of the MIS thin film semiconductor device for signal amplification and a source region of the MIS thin film semiconductor device for signal transfer are connected;
A drain region of the MIS thin film semiconductor device for signal transfer is connected to the power line,
The gate electrode of the MIS thin film semiconductor device for signal amplification is connected to the capacitance detection electrode,
A capacitance detecting device, wherein a gate electrode of the MIS thin film semiconductor device for signal transfer is connected to the column line .
該静電容量検出装置はM行N列の行列状に配置されたM本の電源線と、N本の出力線、N本の列線、及び該電源線と該出力線との交点に設けられた静電容量検出素子とを具備し、
該静電容量検出素子は信号検出素子と信号増幅素子及び信号転送素子とを含み、
該信号検出素子は容量検出電極と容量検出誘電体膜とを含み、
該信号増幅素子はゲート電極とゲート絶縁膜と半導体膜とから成る信号増幅用MIS型薄膜半導体装置から成り、
該信号転送素子はゲート電極とゲート絶縁膜と半導体膜とから成る信号転送用MIS型薄膜半導体装置から成り、
前記信号増幅用MIS型薄膜半導体装置のドレイン領域は前記電源線に接続され、
前記信号増幅用MIS型薄膜半導体装置のソース領域と前記信号転送用MIS型薄膜半導体装置のドレイン領域とが接続され、
前記信号転送用MIS型薄膜半導体装置のソース領域は前記出力線に接続され、
前記信号増幅用MIS型薄膜半導体装置のゲート電極は前記容量検出電極に接続され、
前記信号転送用MIS型薄膜半導体装置のゲート電極は前記列線に接続される事を特徴とする静電容量検出装置。In the capacitance detection device that reads the surface shape of the object by detecting the capacitance that changes according to the distance to the object,
The capacitance detection device is provided at an intersection of M power lines arranged in a matrix of M rows and N columns, N output lines, N column lines, and the power lines and the output lines. A capacitance detecting element provided,
The capacitance detection element includes a signal detection element, a signal amplification element, and a signal transfer element,
The signal detection element includes a capacitance detection electrode and a capacitance detection dielectric film,
The signal amplifying element comprises a MIS thin film semiconductor device for signal amplification comprising a gate electrode, a gate insulating film, and a semiconductor film,
The signal transfer element Ri consists signal transfer MIS thin film semiconductor device including a gate electrode, a gate insulating film and the semiconductor film,
The drain region of the MIS thin film semiconductor device for signal amplification is connected to the power supply line,
A source region of the MIS thin film semiconductor device for signal amplification and a drain region of the MIS thin film semiconductor device for signal transfer are connected;
A source region of the MIS thin film semiconductor device for signal transfer is connected to the output line,
The gate electrode of the MIS thin film semiconductor device for signal amplification is connected to the capacitance detection electrode,
A capacitance detecting device, wherein a gate electrode of the MIS thin film semiconductor device for signal transfer is connected to the column line .
該静電容量検出装置はM行N列の行列状に配置されたM本の電源線と、N本の出力線、N本の列線及び該電源線と該出力線との交点に設けられた静電容量検出素子、該N本の出力線及び該N本の列線に接続する出力信号選択回路とを具備し、
該静電容量検出素子は信号検出素子と信号増幅素子及び信号転送素子を含み、
該出力信号選択回路は共通出力線と出力信号用パスゲートを含み、
該信号検出素子は容量検出電極と容量検出誘電体膜とを含み、
該信号増幅素子はゲート電極とゲート絶縁膜と半導体膜から成る信号増幅用MIS型薄膜半導体装置から成り、
該信号転送素子はゲート電極とゲート絶縁膜と半導体膜から成る信号転送用MIS型薄膜半導体装置から成り、
該出力信号用パスゲートはゲート電極とゲート絶縁膜と半導体膜から成る出力信号パスゲート用MIS型薄型半導体装置から成り、
前記信号増幅用MIS型薄膜半導体装置のソース領域は前記出力線に接続され、
前記信号増幅用MIS型薄膜半導体装置のドレイン領域と前記信号転送用MIS型薄膜半導体装置のソース領域とが接続され、
前記信号転送用MIS型薄膜半導体装置のドレイン領域は前記電源線に接続され、
前記信号増幅用MIS型薄膜半導体装置のゲート電極は前記容量検出電極に接続され、
前記信号転送用MIS型薄膜半導体装置のゲート電極は前記列線に接続され、
前記出力信号パスゲート用MIS型薄膜半導体装置のソース領域は前記共通出力線に接続され、
前記出力信号パスゲート用MIS型薄膜半導体装置のドレイン領域は前記出力線に接続され、
前記出力信号パスゲート用MIS型薄膜半導体装置のゲート電極は前記列線に接続される事を特徴とする静電容量検出装置。In the capacitance detection device that reads the surface shape of the object by detecting the capacitance that changes according to the distance to the object,
The capacitance detection device is provided at an intersection of M power lines arranged in a matrix of M rows and N columns, N output lines, N column lines, and the power lines and the output lines. A capacitance detection element, an output signal selection circuit connected to the N output lines and the N column lines,
The capacitance detection element includes a signal detection element, a signal amplification element, and a signal transfer element,
The output signal selection circuit includes a common output line and an output signal pass gate,
The signal detection element includes a capacitance detection electrode and a capacitance detection dielectric film,
The signal amplifying element comprises a signal amplifying MIS type thin film semiconductor device comprising a gate electrode, a gate insulating film and a semiconductor film,
The signal transfer element comprises a signal transfer MIS thin film semiconductor device comprising a gate electrode, a gate insulating film, and a semiconductor film,
Pass gate for output signal Ri consists output signal path gate for MIS type thin semiconductor device comprising a gate electrode, a gate insulating film and the semiconductor film,
A source region of the MIS thin film semiconductor device for signal amplification is connected to the output line,
A drain region of the MIS thin film semiconductor device for signal amplification and a source region of the MIS thin film semiconductor device for signal transfer are connected;
A drain region of the MIS thin film semiconductor device for signal transfer is connected to the power line,
The gate electrode of the MIS thin film semiconductor device for signal amplification is connected to the capacitance detection electrode,
The gate electrode of the MIS thin film semiconductor device for signal transfer is connected to the column line,
A source region of the MIS type thin film semiconductor device for the output signal pass gate is connected to the common output line,
The drain region of the MIS type thin film semiconductor device for output signal pass gate is connected to the output line,
A capacitance detecting device, wherein a gate electrode of the MIS type thin film semiconductor device for output signal pass gate is connected to the column line .
該静電容量検出装置はM行N列の行列状に配置されたM本の電源線と、N本の出力線、N本の列線及び該電源線と該出力線との交点に設けられた静電容量検出素子、該N本の出力線及び該N本の列線に接続する出力信号選択回路とを具備し、
該静電容量検出素子は信号検出素子と信号増幅素子及び信号転送素子を含み、
該出力信号選択回路は共通出力線と出力信号用パスゲートを含み、
該信号検出素子は容量検出電極と容量検出誘電体膜とを含み、
該信号増幅素子はゲート電極とゲート絶縁膜と半導体膜から成る信号増幅用MIS型薄膜半導体装置から成り、
該信号転送素子はゲート電極とゲート絶縁膜と半導体膜から成る信号転送用MIS型薄膜半導体装置から成り、
該出力信号用パスゲートはゲート電極とゲート絶縁膜と半導体膜から成る出力信号パスゲート用MIS型薄型半導体装置から成り、
前記信号増幅用MIS型薄膜半導体装置のドレイン領域は前記電源線に接続され、
前記信号増幅用MIS型薄膜半導体装置のソース領域と前記信号転送用MIS型薄膜半導体装置のドレイン領域とが接続され、
前記信号転送用MIS型薄膜半導体装置のソース領域は前記出力線に接続され、
前記信号増幅用MIS型薄膜半導体装置のゲート電極は前記容量検出電極に接続され、
前記信号転送用MIS型薄膜半導体装置のゲート電極は前記列線に接続され、
前記出力信号パスゲート用MIS型薄膜半導体装置のソース領域は前記共通出力線に接続され、
前記出力信号パスゲート用MIS型薄膜半導体装置のドレイン領域は前記出力線に接続され、
前記出力信号パスゲート用MIS型薄膜半導体装置のゲート電極は前記列線に接続される事を特徴とする静電容量検出装置。In the capacitance detection device that reads the surface shape of the object by detecting the capacitance that changes according to the distance to the object,
The capacitance detection device is provided at an intersection of M power lines arranged in a matrix of M rows and N columns, N output lines, N column lines, and the power lines and the output lines. A capacitance detection element, an output signal selection circuit connected to the N output lines and the N column lines,
The capacitance detection element includes a signal detection element, a signal amplification element, and a signal transfer element,
The output signal selection circuit includes a common output line and an output signal pass gate,
The signal detection element includes a capacitance detection electrode and a capacitance detection dielectric film,
The signal amplifying element comprises a signal amplifying MIS type thin film semiconductor device comprising a gate electrode, a gate insulating film and a semiconductor film,
The signal transfer element comprises a signal transfer MIS thin film semiconductor device comprising a gate electrode, a gate insulating film, and a semiconductor film,
Pass gate for output signal Ri consists output signal path gate for MIS type thin semiconductor device comprising a gate electrode, a gate insulating film and the semiconductor film,
The drain region of the MIS thin film semiconductor device for signal amplification is connected to the power supply line,
A source region of the MIS thin film semiconductor device for signal amplification and a drain region of the MIS thin film semiconductor device for signal transfer are connected;
A source region of the MIS thin film semiconductor device for signal transfer is connected to the output line,
The gate electrode of the MIS thin film semiconductor device for signal amplification is connected to the capacitance detection electrode,
The gate electrode of the MIS thin film semiconductor device for signal transfer is connected to the column line,
A source region of the MIS type thin film semiconductor device for the output signal pass gate is connected to the common output line,
The drain region of the MIS type thin film semiconductor device for output signal pass gate is connected to the output line,
A capacitance detecting device, wherein a gate electrode of the MIS type thin film semiconductor device for output signal pass gate is connected to the column line .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003207935A JP4517599B2 (en) | 2003-08-19 | 2003-08-19 | Capacitance detection device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003207935A JP4517599B2 (en) | 2003-08-19 | 2003-08-19 | Capacitance detection device |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005061878A JP2005061878A (en) | 2005-03-10 |
JP4517599B2 true JP4517599B2 (en) | 2010-08-04 |
Family
ID=34364224
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003207935A Expired - Fee Related JP4517599B2 (en) | 2003-08-19 | 2003-08-19 | Capacitance detection device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4517599B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006133217A (en) | 2004-10-05 | 2006-05-25 | Seiko Epson Corp | Capacitance detector and smart card |
JP2006138675A (en) | 2004-11-10 | 2006-06-01 | Seiko Epson Corp | Capacitance detector |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1070278A (en) * | 1996-08-27 | 1998-03-10 | Sony Corp | Thin film semiconductor device |
JPH11316105A (en) * | 1998-03-09 | 1999-11-16 | St Microelectronics Inc | Capacitive distance sensor |
JP2000279397A (en) * | 1999-03-31 | 2000-10-10 | Mitsubishi Electric Corp | Unevenness detective sensor, unevenness detective device, fingerprint checking device, and individual discriminant device |
JP2001311752A (en) * | 1999-10-26 | 2001-11-09 | Citizen Watch Co Ltd | Electrostatic capacity detecting device |
JP2002013993A (en) * | 2000-04-25 | 2002-01-18 | Sony Corp | Active matrix circuit and driving method thereof, and surface pressure distribution detecting device |
JP2002048507A (en) * | 2000-08-01 | 2002-02-15 | Sony Corp | Semiconductor device, and method of manufacturing the same |
-
2003
- 2003-08-19 JP JP2003207935A patent/JP4517599B2/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1070278A (en) * | 1996-08-27 | 1998-03-10 | Sony Corp | Thin film semiconductor device |
JPH11316105A (en) * | 1998-03-09 | 1999-11-16 | St Microelectronics Inc | Capacitive distance sensor |
JP2000279397A (en) * | 1999-03-31 | 2000-10-10 | Mitsubishi Electric Corp | Unevenness detective sensor, unevenness detective device, fingerprint checking device, and individual discriminant device |
JP2001311752A (en) * | 1999-10-26 | 2001-11-09 | Citizen Watch Co Ltd | Electrostatic capacity detecting device |
JP2002013993A (en) * | 2000-04-25 | 2002-01-18 | Sony Corp | Active matrix circuit and driving method thereof, and surface pressure distribution detecting device |
JP2002048507A (en) * | 2000-08-01 | 2002-02-15 | Sony Corp | Semiconductor device, and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
JP2005061878A (en) | 2005-03-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3858728B2 (en) | Capacitance detection device | |
JP4432625B2 (en) | Capacitance detection device | |
US7205778B2 (en) | Electrostatic capacitance detecting device | |
JP3858864B2 (en) | Capacitance detection device | |
CN1266450C (en) | Capacitor detecting device and its driving method, fingerprint sensor and biological identification device | |
JP3858865B2 (en) | Capacitance detection device | |
US7208961B2 (en) | Electrostatic capacitance detection device | |
JP2006133217A (en) | Capacitance detector and smart card | |
JP3909712B2 (en) | Capacitance detection device | |
JP4517599B2 (en) | Capacitance detection device | |
JP4059470B2 (en) | Reader | |
JP4539044B2 (en) | Capacitance detection device | |
JP4400357B2 (en) | Capacitance detection device | |
JP2005077105A (en) | Electrostatic capacitance detecting apparatus and its driving method | |
JP2005091278A (en) | Capacitance detector | |
JP2005077101A (en) | Electrostatic capacity detector |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060817 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090123 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100209 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100406 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100427 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100510 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130528 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140528 Year of fee payment: 4 |
|
LAPS | Cancellation because of no payment of annual fees |