JP2005061878A

JP2005061878A - Electrostatic capacity detector

Info

Publication number: JP2005061878A
Application number: JP2003207935A
Authority: JP
Inventors: Hirotomo Ebihara; 弘知海老原; Mitsutoshi Miyasaka; 光敏宮坂
Original assignee: Seiko Epson Corp
Current assignee: Seiko Epson Corp
Priority date: 2003-08-19
Filing date: 2003-08-19
Publication date: 2005-03-10
Anticipated expiration: 2023-08-19
Also published as: JP4517599B2

Abstract

<P>PROBLEM TO BE SOLVED: To provide a superior electrostatic capacity detector which operates stably, capable of reducing unnecessary energy and labor required in manufacturing, and allowing preparation other than single-crystal silicon substrates. <P>SOLUTION: This detector is provided with M-pieces of power source lines arranged into a matrix form by M-rows and N-columns, N-pieces of output lines, and electrostatic capacity detecting elements provided in the intersections thereof. The electrostatic capacity detecting element includes a signal-detecting element, a signal-amplifying element and a signal transfer element, the signal-detecting element includes a capacity-detecting element and a capacity-detecting dielectric membrane, the signal-amplifying element comprises a signal amplifying MIS type thin film semiconductor device comprising a gate electrode, a gate insulating film and a semiconductor film, and the signal transfer element comprises a signal transfer MIS type thin-film semiconductor device comprising a gate electrode, a gate insulating film and a semiconductor film. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本願発明は指紋等の微細な凹凸を有する対象物の表面形状を、対象物表面との距離に応じて変化する静電容量を検出する事に依り読み取る静電容量検出装置に関する。
【０００２】
【従来の技術】
従来、指紋センサ等に用いられる静電容量検出装置はセンサ電極と当該センサ電極上に設けられた誘電体膜とを単結晶硅素基板に行列状に形成していた（特開平１１−１１８４１５、特開２０００−３４６６０８、特開２００１−５６２０４、特開２００１−１３３２１３等）。図１は従来の静電容量検出装置の動作原理を説明している。センサ電極と誘電体膜とがコンデンサーの一方の電極と誘電体膜とを成し、人体が接地された他方の電極と成る。このコンデンサーの静電容量Ｃ_Ｆは誘電体膜表面に接した指紋の凹凸に応じて変化する。一方、半導体基板には静電容量Ｃ_Ｓを成すコンデンサーを準備し、此等二つのコンデンサーを直列接続して、所定の電圧を印可する。斯うする事で二つのコンデンサーの間には指紋の凹凸に応じた電荷Ｑが発生する。この電荷Ｑを通常の半導体技術を用いて検出し、対象物の表面形状を読み取っていた。
【０００３】
【発明が解決しようとする課題】
しかしながら此等従来の静電容量検出装置は、当該装置が単結晶硅素基板上に形成されて居る為に、指紋センサとして用いると指を強く押しつけた際に当該装置が割れて仕舞うとの課題を有して居た。
【０００４】
更に指紋センサはその用途から必然的に２０ｍｍ×２０ｍｍ程度の大きさが求められ、静電容量検出装置面積の大部分はセンサ電極にて占められる。センサ電極は無論単結晶硅素基板上に作られるが、膨大なエネルギーと労力とを費やして作成された単結晶硅素基板の大部分（センサ電極下部）は単なる支持体としての役割しか演じてない。即ち従来の静電容量検出装置は高価なだけでは無く、多大なる無駄と浪費の上に形成されて居るとの課題を有する。
【０００５】
加えて近年、クレジットカードやキャッシュカード等のカード上に個人認証機能を設けてカードの安全性を高めるべきとの指摘が強い。然るに従来の単結晶硅素基板上に作られた静電容量検出装置は柔軟性に欠ける為に、当該装置をプラスティック基板上に作成し得ないとの課題を有している。
【０００６】
そこで本発明は上述の諸事情を鑑み、その目的とする所は安定に動作し、更に製造時に不要なエネルギーや労力を削減し得、又単結晶硅素基板以外にも作成し得る優良な静電容量検出装置を提供する事に有る。
【０００７】
【課題を解決するための手段】
本発明は対象物との距離に応じて変化する静電容量を検出する事に依り、対象物の表面形状を読み取る静電容量検出装置に於いて、静電容量検出装置はＭ行Ｎ列の行列状に配置されたＭ本の電源線と、Ｎ本の出力線、及び各電源線（ｉ行目の電源線ＰＬｉ、ｉは１からＭ迄の整数）と各出力線（ｊ列目の出力線ＯＬｊ、ｊは１からＮ迄の整数）との交点に設けられた静電容量検出素子（ｉ行ｊ列に位置する静電容量検出素子ＥＣＳＥｉｊ）とを具備し、此の静電容量検出素子（ＥＣＳＥｉｊ）は信号検出素子（ＳＳＥｉｊ）と信号増幅素子（ＳＡＥｉｊ）と信号転送素子（ＳＴＥｉｊ）とを含み、信号検出素子は容量検出電極と容量検出誘電体膜とを含み、信号増幅素子はゲート電極とゲート絶縁膜と半導体膜とから成る信号増幅用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＡｉｊ）から成り、信号転送素子はゲート電極とゲート絶縁膜と半導体膜とから成る信号転送用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＴｉｊ）から成る事を特徴とする。更に此の静電容量検出装置はＮ本の列線を具備し、信号増幅用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＡｉｊ）のソース領域はｊ列目の出力線（ＯＬｊ）に接続され、信号増幅用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＡｉｊ）のドレイン領域と信号転送用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＴｉｊ）のソース領域とが接続され、信号転送用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＴｉｊ）のドレイン領域はｉ行目の電源線（ＰＬｉ）に接続され、信号増幅用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＡｉｊ）のゲート電極は前記容量検出電極に接続され、信号転送用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＴｉｊ）のゲート電極はｊ列目の列線（ＣＬｊ）に接続される事を特徴とする。或いは信号転送用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＴｉｊ）と信号増幅用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＡｉｊ）との静電容量検出素子（ＥＣＳＥｉｊ）内に於ける位置関係を交換しても良い。具体的には此の静電容量検出装置はＮ本の列線を具備し、信号増幅用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＡｉｊ）のドレイン領域がｉ行目の電源線（ＰＬｉ）に接続され、信号増幅用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＡｉｊ）のソース領域と信号転送用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＴｉｊ）のドレイン領域とが接続され、信号転送用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＴｉｊ）のソース領域はｊ列目の出力線（ＯＬｊ）に接続され、信号増幅用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＡｉｊ）のゲート電極は前記容量検出電極に接続され、信号転送用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＴｉｊ）のゲート電極はｊ列目の列線（ＣＬｊ）に接続される事も特徴と為す。更に本発明の静電容量検出装置は出力線と列線は第一配線にて配線され、電源線は第二配線にて配線され、第一配線と第二配線とは絶縁膜を介して異なった層上に形成されて居る事も特徴と為す。更に容量検出電極が第三配線にて配線され、第一配線及び第二配線と、第三配線とは絶縁膜を介して異なった層上に形成されて居る事を特徴とする。更に第三配線が静電容量検出装置の配線の中で最も表面側に位置する事を特徴とする。
【０００８】
本発明は対象物との距離に応じて変化する静電容量を検出する事に依り、対象物の表面形状を読み取る静電容量検出装置に於いて、静電容量検出装置はＭ行Ｎ列の行列状に配置されたＭ本の電源線と、Ｎ本の出力線、Ｎ本の列線、及び各電源線（ｉ行目の電源線ＰＬｉ、ｉは１からＭ迄の整数）と各出力線（ｊ列目の出力線ＯＬｊ、ｊは１からＮ迄の整数）との交点に設けられた静電容量検出素子（ｉ行ｊ列に位置する静電容量検出素子ＥＣＳＥｉｊ）、Ｎ本の出力線及びＮ本の列線に接続する出力信号選択回路とを具備し、此の静電容量検出素子（ＥＣＳＥｉｊ）は信号検出素子（ＳＳＥｉｊ）と信号増幅素子（ＳＡＥｉｊ）及び信号転送素子（ＳＴＥｉｊ）とを含み、出力信号選択回路は共通出力線と出力信号用パスゲート（ｊ列目に位置する出力信号用パスゲートＯＬＰＧＥｊ）を含み、信号検出素子（ＳＳＥｉｊ）は容量検出電極と容量検出誘電体膜とを含み、信号増幅素子（ＳＡＥｉｊ）はゲート電極とゲート絶縁膜と半導体膜から成る信号増幅用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＡｉｊ）から成り、信号転送素子（ＳＴＥｉｊ）はゲート電極とゲート絶縁膜と半導体膜から成る信号転送用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＴｉｊ）から成り、出力信号用パスゲート（ＯＬＰＧＥｊ）はゲート電極とゲート絶縁膜と半導体膜から成る出力信号パスゲート用ＭＩＳ型薄型半導体装置（ＴＳＤ−ＯＬＰＧｊ）から成る事を特徴する。更に信号増幅用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＡｉｊ）のソース領域はｊ列目の出力線（ＯＬｊ）に接続され、信号増幅用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＡｉｊ）のドレイン領域と信号転送用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＴｉｊ）のソース領域とが接続され、信号転送用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＴｉｊ）のドレイン領域はｉ行目の電源線（ＰＬｉ）に接続され、信号増幅用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＡｉｊ）のゲート電極は前記容量検出電極に接続され、信号転送用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＴｉｊ）のゲート電極はｊ列目の列線（ＣＬｊ）に接続され、出力信号パスゲート用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＯＬＰＧｊ）のソース領域は前記共通出力線に接続され、出力信号パスゲート用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＯＬＰＧｊ）のドレイン領域はｊ列目の出力線（ＯＬｊ）に接続され、出力信号パスゲート用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＯＬＰＧｊ）のゲート電極はｊ列目の列線（ＣＬｊ）に接続される事を特徴とする。或いは信号転送用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＴｉｊ）と信号増幅用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＡｉｊ）との静電容量検出素子（ＥＣＳＥｉｊ）内に於ける位置関係を交換しても良い。具体的には信号増幅用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＡｉｊ）のドレイン領域はｉ行目の電源線（ＰＬｉ）に接続され、前記信号増幅用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＡｉｊ）のソース領域と前記信号転送用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＴｉｊ）のドレイン領域とが接続され、前記信号転送用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＴｉｊ）のソース領域はｊ列目の出力線（ＯＬｊ）に接続され、前記信号増幅用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＡｉｊ）のゲート電極は前記容量検出電極に接続され、前記信号転送用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＳＴｉｊ）のゲート電極はｊ列目の列線（ＣＬｊ）に接続され、前記出力信号パスゲート用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＯＬＰＧｊ）のソース領域は前記共通出力線に接続され、前記出力信号パスゲート用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＯＬＰＧｊ）のドレイン領域はｊ列目の出力線（ＯＬｊ）に接続され、前記出力信号パスゲート用ＭＩＳ型薄膜半導体装置（ＴＳＤ−ＯＬＰＧｊ）のゲート電極はｊ列目の列線（ＣＬｊ）に接続される事を特徴する。
【０００９】
本発明の静電容量検出装置では出力線と列線とが第一配線にて配線され、電源線と共通出力線とが第二配線にて配線され、此等第一配線と第二配線とは絶縁膜を介して異なった層上に形成されて居る事も特徴と為す。更に容量検出電極が第三配線にて配線され、第一配線及び第二配線と、第三配線とは絶縁膜を介して異なった層上に形成されて居る事を特徴とする。更に、第三配線が静電容量検出装置の配線の中で最も表面側に位置する事を特徴とする。
【００１０】
【発明の実施の形態】
本発明は対象物との距離に応じて変化する静電容量を検出する事に依り、対象物の表面形状を読み取る静電容量検出装置を金属−絶縁膜−半導体膜から成るＭＩＳ型薄膜半導体装置を用いて作成する。薄膜半導体装置は通常、硝子基板上に作成され、大面積を要する半導体集積回路を安価に製造する技術として知られて居る。具体例としては、昨今は液晶表示装置等に応用されている。従って指紋センサ等に適応される静電容量検出装置を薄膜半導体装置にて作成すると、単結晶硅素基板と云った多大なエネルギーを消費して作られた高価な基板を使用する必要がなく、貴重な地球資源を浪費する事なく安価に当該装置を作成し得る。又、薄膜半導体装置はＳＵＦＴＬＡ（特開平１１−３１２８１１やＳ．Ｕｔｓｕｎｏｍｉｙａｅｔ．ａｌ．ＳｏｃｉｅｔｙｆｏｒＩｎｆｏｒｍａｔｉｏｎＤｉｓｐｌａｙｐ．９１６（２０００））と呼ばれる転写技術を適応する事で、半導体集積回路をプラスティック基板上に作成出来るので、静電容量検出装置も単結晶硅素基板から解放されてプラスティック基板上に形成し得るので有る。
【００１１】
さて、図１に示すが如き従来の動作原理を適応した静電容量検出装置を薄膜半導体装置にて作成するのは、現在の薄膜半導体装置の技術を以ってしては不可能である。二つの直列接続されたコンデンサー間に誘起される電荷Ｑは非常に小さい為に、高精度感知を可能とする単結晶硅素ＬＳＩ技術を用いれば電荷Ｑを正確に読み取れるが、薄膜半導体装置ではトランジスタ特性が単結晶硅素ＬＳＩ技術程には優れず、又薄膜半導体装置間の特性偏差も大きいが故に電荷Ｑを正確に読み取れない。
【００１２】
そこで本発明の静電容量検出装置は、少なくともＭ行Ｎ列の行列状に配置されたＭ本（Ｍは１以上の整数）の電源線と、Ｎ本（Ｎは１以上の整数）の出力線、及び各電源線（ｉ行目の電源線ＰＬｉ、ｉは１からＭ迄の整数）と各出力線（ｊ列目の出力線ＯＬｊ、ｊは１からＮ迄の整数）との交点に設けられた静電容量検出素子（ｉ行ｊ列に位置する静電容量検出素子ＥＣＳＥｉｊ）とを具備し、此の静電容量検出素子は信号検出素子と信号増幅素子とを最少の構成要素として含む。斯うした構成である静電容量検出装置の一例を図４Ａに示す。信号検出素子は容量検出電極と容量検出誘電体膜とを含み、容量検出電極には静電容量に応じて電荷Ｑが発生する。本発明ではこの電荷Ｑを各静電容量検出素子に設けられた信号増幅素子にて増幅し、電流又は電圧に変換する。具体的には信号増幅素子はゲート電極とゲート絶縁膜と半導体膜とから成る信号増幅用ＭＩＳ型薄膜半導体装置から成り、信号増幅用ＭＩＳ型薄膜半導体装置のゲート電極が容量検出電極に接続される。
【００１３】
図２に本願発明の動作原理図を示す。静電容量Ｃ_ｓを持つコンデンサーと、対象物の表面形状に応じて変化する静電容量Ｃ_Ｆを有するコンデンサーとの間に容量結合にて分割された電圧は信号増幅用ＭＩＳ型薄膜半導体装置のゲート電位を変化させる。斯うして此の薄膜半導体装置のドレイン領域に所定の電圧を印可すると、容量結合にて誘起された電圧に応じて薄膜半導体装置のソースドレイン間に流れる電流Ｉが著しく増幅される。ゲート電極に誘起された電荷Ｑ自体は何処にも流れずに保存されるので、ドレイン電圧を高くしたり或いは測定時間を長くする等で電流Ｉｄｓの測定も容易になり、従って薄膜半導体装置を用いても対象物の表面形状を十分正確に計測出来る様になる。
【００１４】
前述の如く本願発明では信号増幅素子として信号増幅用ＭＩＳ型薄膜半導体装置を用いて居る。この場合、静電容量Ｃ_ｓを持つコンデンサーを信号増幅用ＭＩＳ型薄膜半導体装置其の物で兼用し得る。即ち静電容量Ｃ_ｓに代わる新たな静電容量を信号増幅用ＭＩＳ型薄膜半導体装置のトランジスタ容量Ｃ_Ｔとするので有る。斯うする事で静電容量検出素子から静電容量Ｃ_ｓを持つコンデンサーを省略出来、構造が簡素化されると同時に製造工程も容易と化す。加えて図２に描かれて居る二つの電源を共通の電源Ｖｄｄとして纏める事も静電容量検出装置内に於ける余計な配線を省略し得るとの観点で効果的と言える。斯様な状態に於ける動作原理に関する等価回路図を図３に示す。対象物の表面形状に応じて変化する静電容量Ｃ_Ｆを有するコンデンサーとトランジスタ容量Ｃ_Ｔを有するコンデンサーとが直列に接続されて居る。厳密にはトランジスタ容量Ｃ_Ｔは信号増幅用ＭＩＳ型薄膜半導体装置のドレイン電極とゲート電極との間に形成される静電容量である。図３の構成を実現させるには、図４に示すが如く信号増幅用ＭＩＳ型薄膜半導体装置のソース領域を出力線に接続し、信号増幅用ＭＩＳ型薄膜半導体装置のドレイン領域を電源線に接続した上で、電源線に電圧Ｖｄｄを印可し、出力線より対象物の表面形状に応じて変化する電流Ｉｄｓを取り出せば良い。例えば各容量を適当に設定し、指紋の山が信号検出素子に接した時には信号増幅素子は高抵抗となって電源線と出力線とを遮断し（電流Ｉｄｓを殆ど通過させず）、反対に指紋の谷が信号検出素子に面した時には信号増幅素子は低抵抗となって電源線と出力線とを導通させる（電流Ｉｄｓを通過させる）。斯うした電流量の変化や出力線に掛かる電圧変化を感知して指紋形状等に起因する静電容量を検出する。
【００１５】
原理的には斯うした構成で指紋等の表面形状情報を採取可能で有るが、行列状に配置された各電源線及び各出力線には其々複数の静電容量検出素子が接続されている為、静電容量検出素子間で情報の干渉が生じて仕舞う。図４Ａに示した構成の静電容量検出装置にて静電容量検出素子ＥＣＳＥｉｊに依り対象物の表面形状を読み取る場合、電源線ＰＬｉに電圧Ｖｄｄを印可し、出力線ＯＬｊから出力信号ＯＳｉｊを取り出す。もし信号増幅素子ＳＡＥｉｊが高抵抗で有れば出力線ＯＬｊは低電位で有らねば成らない。所がこの時、電源線ＰＬｉに接続された全ての静電容量検出素子ＥＣＳＥｉｙ（ｙは１からＮ迄の総ての整数）にも電圧Ｖｄｄが印可される為、各出力線ＯＬｙには、静電容量検出素子ＥＣＳＥｉｙを通じて読み取られた表面形状に応じた出力信号ＯＳｉｙが流れる。例えば信号増幅素子ＳＥＡｉｊ＋１が低抵抗状態に有れば出力線ＯＬｊ＋１は出力信号ＯＳｉｊ＋１を介して高電位と成る。更に、出力線ＯＬｙに接続された静電容量検出素子ＥＣＳＥｘｙ（ｘはｉを除く１からＭ迄の整数）を通して、電源線ＰＬｘにも電流が流れ得る。例えば出力線ＯＬｊ＋１が高電位になった状態で信号増幅素子ＳＡＥｉ−１ｊ＋１が低抵抗ならば、信号増幅素子ＳＡＥｉ−１ｊ＋１を介して逆方向の出力信号ＯＳｉ−１ｊ＋１が存在し得、本来低電位でなければならない電源線ＰＬｉ−１を高電位として仕舞う。斯うして本来低電位に有るべき非選択電源線ＰＬｘ（ｘはｉを除く１からＭ迄の整数）に通った電流が非選択電源線を高電位に変えて仕舞う。非選択電源線が高電位に変わると、静電容量検出素子ＥＣＳＥｘｊを介して出力信号ＯＳｘｊが出力線ＯＬｊに流れる。先の例に戻ると例えば信号増幅素子ＳＡＥｉ−１ｊが低抵抗だと出力信号ＯＳｉ−１ｊが出力線ＯＬｊに流入する。この結果、出力線ＯＬｊには本来検出すべきＯＳｉｊの他にＯＳｉ−１ｊなど他の出力信号が重畳して仕舞う。換言すると電源線ＰＬｉと出力線ＯＬｊとの間に静電容量検出装置ＥＣＳＥｉｊ以外の電流経路が存在するのである。電源線ＰＬｉを選択して電圧Ｖｄｄを印可したとしても、実質的には電源線の選択が機能せず、出力線ＯＬｊには複数の静電容量検出素子を通して複数の出力信号が流れ込み、精度良く表面形状を読み取る事が困難となる。
【００１６】
そこで本発明では各静電容量検出素子を確実に選択し、その動作を制御する信号転送素子を用いる事に依り、検出情報の素子間干渉を防ぎ、精度の高い静電容量の検出を可能とする。本発明の静電容量検出装置はＭ行Ｎ列の行列状に配置されたＭ本（Ｍは１以上の整数）の電源線と、Ｎ本（Ｎは１以上の整数）の出力線、及び各電源線（ｉ行目の電源線ＰＬｉ、ｉは１からＭ迄の整数）と各出力線（ｊ列目の出力線ＯＬｊ、ｊは１からＮ迄の整数）との交点に設けられた静電容量検出素子（ｉ行ｊ列に位置する静電容量検出素子ＥＣＳＥｉｊ）とを具備し、此の静電容量検出素子ＥＣＳＥｉｊは信号検出素子ＳＳＥｉｊと信号増幅素子ＳＡＥｉｊと信号転送素子ＳＴＥｉｊとを含む。信号検出素子ＳＳＥｉｊは容量検出電極と容量検出誘電体膜とを含み、静電容量を検出して静電容量を電圧に変換する。信号増幅素子ＳＡＥｉｊはゲート電極とゲート絶縁膜と半導体膜とから成る信号増幅用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＡｉｊから成り、信号転送素子ＳＴＥｉｊはゲート電極とゲート絶縁膜と半導体膜とから成る信号転送用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＴｉｊから成る。信号増幅用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＡｉｊと信号転送用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＴｉｊとは静電容量検出素子ＥＣＳＥｉｊ内に於いて直列に接続される。
【００１７】
斯うした構成を実現する静電容量検出装置の一例を図４Ｂと図４Ｃとを用いて詳述する。（図４Ｂと図４ＣとではＭＩＳ型薄膜半導体装置のソース領域をＳ、ドレイン領域をＤ、ゲート電極をＧにて表示して居る。又、ソース領域とドレイン領域はＮ型半導体装置では電位の低い方をソース領域と定義し、Ｐ型半導体装置では電位の高い方をソース領域と定義する。）図４Ｂと図４Ｃの静電容量検出素子ＥＣＳＥｉｊでは、信号増幅用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＡｉｊと信号転送用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＴｉｊとが電源線ＰＬｉと出力線ＯＬｊとの間にて直列に接続されている。これに依り静電容量検出素子間での出力信号干渉を防ぎ、検出精度の高い静電容量検出装置を実現し得る。実際、静電容量検出素子ＥＣＳＥｉｊからの出力信号を読み出す際には、ｉ行目電源線を選択して高電位とし、その状態にて信号転送用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＴｉｊのゲート電極に印加する電圧を制御する事で、静電容量検出素子ＥＣＳＥｉｊのみを選択出来る様になる。先の例に倣うと、図４Ａでは出力信号の干渉がＯＳｉｊからＯＳｉｊ＋１を経て、逆出力信号ＯＳｉ−１ｊ＋１、ＯＳｉ−１ｊとの経路で出力線ＯＬｊに発生していた。所が、本発明（図４Ｂと図４Ｃ）の構成では列側の選択を信号転送素子にて行っているが故、ｊ列に位置する静電容量検出素子ＥＣＳＥｉｊを選択した状態では他列の信号転送素子は必ず高抵抗状態に保たれる。この為にＯＳｉｊ＋１や逆出力信号ＯＳｉ−１ｊ＋１は遮断され、出力線ＯＬｊに選択した静電容量検出素子ＥＣＳＥｉｊ以外の出力信号が重畳する事はなくなる。信号転送用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＴｉｊのソース・ドレイン間が電気的に導通状態である（信号転送素子が選択状態である）時のみ静電容量検出素子ＥＣＳＥｉｊだけが動作し、信号転送用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＴｉｊのソース・ドレイン間が電気的に導通状態でない（信号転送素子が非選択状態である）時には、静電容量検出素子ＥＣＳＥｉｊは動作しないのである。
【００１８】
此迄述べて来た様に、信号転送素子を含む静電容量検出装置を用いて表面形状情報の採取時に生じる情報の干渉を防ぐ一つの方法は、列選択に依り静電容量検出素子の動作を制御する事にある。そこで本発明の静電容量検出装置では、列毎に静電容量検出素子の動作を制御する列線ＣＬｊを設け、此の列線ＣＬｊに印加する電圧に応じて信号転送素子ＳＴＥｉｊの選択（信号転送素子ＳＴＥｉｊが低抵抗で導通状態）か非選択（信号転送素子ＳＴＥｉｊが高抵抗で遮断状態）かを切り替え、静電容量検出素子ＥＣＳＥｉｊの動作を制御する。具体的には本発明の静電容量検出装置はＮ本の列線ＣＬｊをも具備して居る。即ちＭ行Ｎ列の行列を含む静電容量検出装置の各行列要素は電源線ＰＬｉと出力線ＯＬｊ、列線ＣＬｊ、及び静電容量検出素子ＥＣＳＥｉｊとから成る。信号増幅用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＡｉｊのソース領域はｊ列目の出力線ＯＬｊに電気的に接続され、信号増幅用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＡｉｊのドレイン領域と信号転送用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＴｉｊのソース領域とが電気的に接続され、更に信号転送用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＴｉｊのドレイン領域はｉ行目の電源線ＰＬｉに電気的に接続される。電気的に接続されるとは直接此等が繋がれる事の他にも、何らかのスイッチ素子を介して導通が取られる事をも意味している。例えば信号転送素子と電源線との間に更に他のトランジスタを直列に配置しても良い。配置されたトランジスタが選択状態となり低抵抗ならば、信号転送素子と電源線との間は導通が取られるので、信号転送素子と電源線とは電気的に接続されていると言える。信号増幅用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＡｉｊのゲート電極は容量検出電極に電気的に接続され、信号転送用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＴｉｊのゲート電極はｊ列目の列線ＣＬｊに電気的に接続される。斯うした構成となる静電容量検出装置の全体構造が図４Ｂに示されて居る。上述の構成とは反対に信号転送用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＴｉｊと信号増幅用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＡｉｊとの静電容量検出素子ＥＣＳＥｉｊ内に於ける位置関係を交換しても良い。具体的には本発明の別な形態となる静電容量検出素子はＮ本の列線ＣＬｊを具備し、信号増幅用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＡｉｊのドレイン領域がｉ行目の電源線ＰＬｉに電気的に接続され、信号増幅用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＡｉｊのソース領域と信号転送用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＴｉｊのドレイン領域とが電気的に接続され、信号転送用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＴｉｊのソース領域はｉ行目の出力線ＯＬｊに電気的に接続される。信号増幅用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＡｉｊのゲート電極は容量検出電極に電気的に接続され、信号転送用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＴｉｊのゲート電極はｊ列目の列線ＣＬｊに電気的に接続される。斯うした構成となる静電容量検出装置の全体構造が図４Ｃに示されて居る。斯うした構成を成す事に依り、電源線ＰＬｉに高電位Ｖｄｄを印可してｉ行を選択出来、列線ＣＬｊに所定の選択電位を印可してｊ列を選択する。斯くして静電容量検出素子ＥＣＳＥｉｊが表面形状に応じて読み取った出力信号ＯＳｉｊ（電圧Ｖｉｊ又は電流Ｉｉｊ）を正確に出力線ＯＬｊから取り出すことが可能と化す。例えば図４Ｂや図４Ｃの構成にて静電容量検出素子ＥＣＳＥｉｊに依り表面形状を測定する場合には、電源線ＰＬｉに電圧Ｖｄｄを印可してｉ行を選択し、列線ＣＬｊにも同じ電圧Ｖｄｄを印可してｊ列を選択する。まず正電源電圧Ｖｄｄが印加された電源線ＰＬｉに接続されているＮ個の静電容量検出素子ＥＣＳＥｉｂ（ｂは１からＮ迄の整数）が選択され、更にその中から列線ＣＬｊに依り選択されて居るｊ列に属する静電容量検出素子ＥＣＳＥｉｊだけが選択され、動作状態とされる。斯うして非選択列の静電容量検出装置ＥＣＳＥｉｙ、（ｙはｉを除く１からＭ迄の整数）を経由した出力情報の拡散が排除され、電源線ＰＬｉと出力線ＯＬｊとの間には静電容量検出素子ＥＣＳＥｉｊ以外の情報流入経路が断たれる。故に出力線ＯＬｊには静電容量検出素子ＥＣＳＥｉｊだけを通して表面形状に応じた出力信号ＯＳｉｊ（電圧Ｖｉｊ又は電流Ｉｉｊ）が出力されるるに至り、静電容量検出素子間の情報干渉を防止し得る。
【００１９】
斯様な構成の静電容量検出装置を効果的に機能させる為に、本発明の静電容量検出装置では出力線と列線とが第一配線にて配線され、電源線が第二配線にて配線され、此等第一配線と第二配線とは絶縁膜を介して異なった層上に形成される。更に容量検出電極は絶縁膜にて第一配線及び第二配線と異なった層上に形成されて居る第三配線にて配線される。又、容量検出電極は第一配線から第三配線の何れにて配線し得るが、静電容量検出装置中の配線の中で最も表面側に第三配線を位置させる。斯うした構成を成す事で余分な配線を除去し、以て各配線間に生ずる寄生容量を最小化せしめ、故に微少な静電容量を高感度にて検出せしめる訳である。本発明を具現化する静電容量検出素子の構造の一例を図５を用いて説明する。図５ではＭＩＳ型薄膜半導体装置のソース領域をＳ、ドレイン領域をＤ、ゲート電極をＧにて表示して居る。静電容量検出素子の信号増幅素子を成す信号増幅用ＭＩＳ型薄膜半導体装置及び信号転送素子を構成する信号転送用ＭＩＳ型薄膜半導体装置は、其々ソース領域とチャンネル形成領域とドレイン領域とを含む半導体膜とゲート絶縁膜とゲート電極とを不可欠な構成要件としている。図５の構成例では信号増幅用ＭＩＳ型薄膜半導体装置のドレイン領域と信号転送用ＭＩＳ型半導体装置のソース領域は一つの領域として設けられていて、信号増幅用ＭＩＳ型薄膜半導体装置と信号転送用ＭＩＳ型薄膜半導体装置を第一層間絶縁膜が覆っている。信号増幅用ＭＩＳ型薄膜半導体装置のソース領域には第一配線が接続され、信号転送用ＭＩＳ型薄膜半導体装置のドレイン領域には第二配線が接続される。或いは信号増幅用ＭＩＳ型薄膜半導体装置のドレイン領域に第一配線が接続され、信号転送用ＭＩＳ型薄膜半導体装置のソース領域に第二配線が接続されても良い。第一配線と第二配線との間には第二層間絶縁膜が設けられ、第一配線と第二配線とは異なった層上に形成される。勿論、第二配線を第一層間絶縁膜上に形成し、第一配線を第二層間絶縁膜上に形成する事も可能である。静電容量検出素子の信号検出素子を成す容量検出電極は第三配線として設けられ、信号増幅用ＭＩＳ型薄膜半導体装置のゲート電極に接続される。第三配線は第二層間絶縁膜の上に設けられた第三層間絶縁膜上に形成され、第一配線及び第二配線とは更に異なった層上に形成される。容量検出電極と、第一配線乃至は第二配線とは電気的に導通が取られている部位（電気抵抗がゼロとの理想系にて等電位と化す部位）以外とは異なった層上にあってもお互いに重なり合わない様に配置する。微小な静電容量を検出する為には寄生容量を最小とする必要があり、上述の構成を取る事で容量検出電極と第二配線、乃至は容量検出電極と第二配線寄生容量を最小と出来、それ故に高感度の静電容量検出装置が実現する。容量検出電極上は容量検出誘電体膜が被い、容量検出誘電体膜は静電容量検出装置の最表面に位置する。容量検出誘電体膜は静電容量検出装置の保護膜の役割も同時に演ずる。保護膜として効率よく機能するには容量検出誘電体膜の比誘電率が第二層間絶縁膜や第三層間絶縁膜の比誘電率よりも大きい事が望まれる。
【００２０】
次に本発明に依る静電容量検出装置からの出力信号読み出し方法を図４Ｂと図４Ｃとを用いて説明する。本発明の静電容量検出素子はＭ行Ｎ列の行列状に配置されている為、対象物の表面形状を読み取るには行と列とを其々順次走査し、Ｍ×Ｎ個の静電容量検出素子を適当な順番にて選択して行く。即ち電源線ＰＬｉに電圧Ｖｄｄを印可した上で、列線ＣＬｊを順次選択して行き、出力線ＯＬｊに現れる出力信号ＯＳｉｊを読み取るとの作業を繰り返す。此の時に各静電容量検出素子から如何なる順序にて検出された出力信号を読み出すかを定めるのが出力信号選択回路である。具体的には、本発明の静電容量検出装置はＭ行Ｎ列の行列状に配置されたＭ本の電源線と、Ｎ本の出力線、Ｎ本の列線、及び各電源線（ｉ行目の電源線ＰＬｉ、ｉは１からＭ迄の整数）と各出力線（ｊ列目の出力線ＯＬｊ、ｊは１からＮ迄の整数）との交点に設けられた静電容量検出素子（ｉ行ｊ列に位置する静電容量検出素子ＥＣＳＥｉｊ）、Ｎ本の出力線及びＮ本の列線に接続する出力信号選択回路とを具備する。Ｍ行Ｎ列行列の各行列要素は電源線ＰＬｉと出力線ＯＬｊ、列線ＣＬｊ、及び静電容量検出素子ＥＣＳＥｉｊから構成される。各行列要素に繋がるＮ本の出力線とＮ本の列線は出力信号選択回路に繋がる。静電容量検出素子ＥＣＳＥｉｊは信号検出素子ＳＳＥｉｊと信号増幅素子ＳＡＥｉｊ及び信号転送素子ＳＴＥｉｊとを含む。出力信号選択回路は共通出力線（ＬＤＯＵＴ）と出力信号用パスゲート（ｊ列目に位置する出力信号用パスゲートＯＬＰＧＥｊ）を少なくとも含むで居る。信号検出素子ＳＳＥｉｊは容量検出電極と容量検出誘電体膜とを含む。信号増幅素子ＳＡＥｉｊはゲート電極とゲート絶縁膜と半導体膜とから成る信号増幅用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＡｉｊから構成され、信号転送素子ＳＴＥｉｊはゲート電極とゲート絶縁膜と半導体膜とから成る信号転送用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＴｉｊから構成され、出力信号用パスゲートＯＬＰＧＥｊはゲート電極とゲート絶縁膜と半導体膜とから成る出力信号パスゲート用ＭＩＳ型薄型半導体装置ＴＳＤ−ＯＬＰＧｊから構成される。出力信号選択回路はデコーダーやシフトレジスタなどに依り選択された列からの出力信号を共通出力線に取り出す。即ちＮ本の列線の内でｊ列目の列線ＣＬｊが選択された際に、Ｎ本の出力線の内でｊ列目の出力線ＯＬｊに現れた出力信号ＯＳｊを選択的に共通出力線に取り出す。本発明の静電容量検出装置では全ての出力信号を共通出力線に出力する。斯様な構成にせねば、各出力信号ＯＳｊを検出する際に、各出力線ＯＬｊ上に出力信号を検出する装置を個別に設けねばならず、製造が困難を窮めると共に、Ｎ個の接続端子にも接続のばらつきが生じるので測定誤差を大きくする要因と成る。そこで本発明の静電容量検出装置では全ての出力信号を数本（一本から八本程度）の共通出力線から出力し、外部回路との実装工程等を容易にすると共に、接続端子に起因する接続のばらつきを最小とし、精度の高い測定を実現している。又、単純に共通出力線と出力線とを接続するだけでは（それでも測定は可能だが）、共通出力線を介して其々の出力線同士が直接接続され、出力信号が広く他の出力線に拡散して仕舞う。此は微弱な出力信号を高速で且つ高精度に検出をする上では好ましくない。そこで本発明の静電容量検出装置では各出力線ＯＬｊと共通出力線との間に出力信号の電気的導通を制御する出力信号用パスゲートＯＬＰＧＥｊを設ける。斯様な構成下では出力信号ＯＳｉｊは選択された出力線ＯＬｉｊと共通出力線内だけに止まり、その他の非選択状態の出力線へは広がらない。例えば出力信号を電圧で読む場合、選択された出力線と共通出力線だけの電位を変えれる事になるので短時間で精度の高い検出が可能とされる。
【００２１】
本発明の静電容量検出装置に於いて、共通出力線から効率良く出力信号を読み出すには列線ＣＬｊに依って選択された列の出力線ＯＬｊのみが共通出力線と電気的に導通する必要がある。そこで本発明の静電容量検出素子では列線ＣＬｊに依りｊ列に位置する静電容量検出素子ＥＣＳＥｉｊを選択すると同時にｊ列目の出力線ＯＬｊに繋がった出力信号用パスゲートＯＬＰＧＥｊの電気導通状態を制御する。出力信号用パスゲートＯＬＰＧＥｊは一例として出力信号パスゲート用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＯＬＰＧｊから成る。より詳細には、本発明の静電容量検出装置は信号増幅用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＡｉｊのソース領域がｊ列目の出力線ＯＬｊに電気的に接続され、信号増幅用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＡｉｊのドレイン領域と信号転送用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＴｉｊのソース領域とが電気的に接続され、信号転送用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＴｉｊのドレイン領域がｉ行目の電源線ＰＬｉに電気的に接続され、信号増幅用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＡｉｊのゲート電極が容量検出電極に電気的に接続され、信号転送用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＴｉｊのゲート電極がｊ列目の列線ＣＬｊに電気的に接続され、ｊ列目に設けられた出力信号パスゲート用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＯＬＰＧｊのソース領域が共通出力線に電気的に接続され、出力信号パスゲート用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＯＬＰＧｊのドレイン領域がｊ列目の出力線ＯＬｊに電気的に接続され、出力信号パスゲート用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＯＬＰＧｊのゲート電極がｊ列目の列線ＣＬｊに電気的に接続される。斯うした構成に有る静電容量検出装置の全体構造を図４Ｂに示す。或いは信号転送用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＴｉｊと信号増幅用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＡｉｊとの静電容量検出素子ＥＣＳＥｉｊ内に於ける位置関係を交換しても良い。具体的には、本発明の静電容量検出装置は、信号増幅用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＡｉｊのドレイン領域がｉ行目の電源線ＰＬｉに電気的に接続され、信号増幅用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＡｉｊのソース領域と信号転送用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＴｉｊのドレイン領域とが電気的に接続され、信号転送用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＴｉｊのソース領域がｊ列目の出力線ＯＬｊに電気的に接続され、信号増幅用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＡｉｊのゲート電極が容量検出電極に電気的に接続され、信号転送用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＳＴｉｊのゲート電極がｊ列目の列線ＣＬｊに電気的に接続され、出力信号パスゲート用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＯＬＰＧｊのソース領域が共通出力線に電気的に接続され、出力信号パスゲート用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＯＬＰＧｊのドレイン領域がｊ列目の出力線ＯＬｊに接続され、出力信号パスゲート用ＭＩＳ型薄膜半導体装置ＴＳＤ−ＯＬＰＧｊのゲート電極がｊ列目の列線ＣＬｊに接続される。斯うした構成に有る静電容量検出装置の全体構造を図４Ｃに示す。電気的に接続されるとは先に述べた如く直接乃至は間接的に電気的導通が取られる事を意味する。
【００２２】
斯様な構成を取ると、Ｎ本の列線の内からｊ列目の列線ＣＬｊを選択すると、同時にＮ本の出力線の内でｊ列目に位置する只一本の出力線ＯＬｊを選択する事に成り、出力信号が他の出力線へ拡散される事態を防止し得る。その結果、電源線ＰＬｉ及び列線ＣＬｊに依り選択された静電容量検出素子ＥＣＳＥｉｊからの出力信号ＯＳｉｊは、出力線ＯＬｊにのみと出力信号用パスゲートＯＬＰＧＥｊを介して共通出力線とに出力され、高速で精度の高い検出が実現する。
【００２３】
実際に列を走査する際に列線に供給される信号（列選択信号）としては、シフトレジスタからの出力やデコーダーからの出力などが利用される。列選択信号を供給するシフトレジスタやデコーダーも薄膜半導体装置にて作成しても良い。列選択信号を生成する回路をシフトレジスタとすると、シフトレジスタは各出力段に転送されて来る信号から列選択信号を作成し、これを順次列線に供給して行く。列選択信号を生成する回路をデコーダーとすると、デコーダーはデコーダーへの入力信号に応じてＮ個の出力段から特定の出力段を選定し、この出力段に列選択信号を供給する。即ち選定された出力段に接続した列線が選択される事に成る。此の様にしてＮ個の出力信号用パスゲートＯＬＰＧＥｊと静電容量検出素子ＥＣＳＥｉｊとには列線から適時選択信号が入力される。静電容量検出素子ＥＣＳＥｉｊは適時選択され、出力信号ＯＳｉｊは共通出力線に出力されて行く。
【００２４】
先と同様、静電容量検出装置を効果的に機能させる為に、本発明の静電容量検出装置では出力線と列線とが第一配線にて配線され、電源線と共通出力線の一部乃至は全部が第二配線にて配線され、此等第一配線と第二配線とは絶縁膜を介して異なった層上に形成されて居る。更に容量検出電極は絶縁膜にて第一配線及び第二配線と異なった層上に形成されて居る第三配線にて配線される。又、容量検出電極は第一配線から第三配線の何れにて配線し得るが、静電容量検出装置中の配線の中で最も表面側に第三配線を位置させる。斯うした構成を成す事で余分な配線を除去し、以て各配線間に生ずる寄生容量を最小化せしめ、故に微少な静電容量を高感度にて検出せしめる訳である。
【００２５】
斯様な静電容量検出素子は前述のＳＵＦＴＬＡ技術を用いて、プラスティック基板上に形成され得る。単結晶硅素技術に基づく指紋センサはプラスティック上では直ぐに割れて仕舞ったり、或いは十分な大きさを有さぬが為に実用性に乏しい。これに対して本願発明に依るプラスティック基板上の静電容量検出素子は、プラスティック基板上で指を被うに十分に大きい面積としても静電容量検出素子が割れる心配もなく、プラスティック基板上での指紋センサとして利用し得る。具体的には本願発明により個人認証機能を兼ね備えたスマートカードが実現される。個人認証機能を備えたスマートカードは銀行カード（ｂａｎｋｃａｒｄ）やクレジットカード（ｃｒｅｄｉｔｃａｒｄ）、身分証明書（Ｉｄｅｎｔｉｔｙｃａｒｄ）等で使用され、此等のセキュリティーレベルを著しく高めた上で尚、個人指紋情報をカード外に流出させずに保護するとの優れた機能を有する。
（実施例１）
ガラス基板上に薄膜半導体装置からなる静電容量検出装置を製造した上で、此の静電容量検出装置をＳＵＦＴＬＡ技術を用いてプラスティック基板上に転写し、プラスティック基板上に静電容量検出装置を作成した。静電容量検出装置は３０４行３０４列の行列状に並んだ静電容量検出素子から構成される。行列部の大きさは２０ｍｍ角の正方形である。
【００２６】
基板は厚み２００μｍのポリエーテルスルフォン（ＰＥＳ）である。信号増幅用ＭＩＳ型薄膜半導体装置も信号転送用ＭＩＳ型薄膜半導体装置も、出力信号パスゲート用ＭＩＳ型薄膜半導体装置も、総て同じ断面構造を有する薄膜トランジスタにて作られている。薄膜トランジスタは図５に示すトップゲート型で工程最高温度４２５℃の低温工程にて作成される。半導体膜はレーザー結晶化にて得られた多結晶硅素薄膜でその厚みは５０ｎｍである。又、ゲート絶縁膜は化学気相堆積法（ＣＶＤ法）にて形成された４０ｎｍ厚の酸化硅素膜で、ゲート電極は厚み４００ｎｍのタンタル薄膜から成る。ゲート絶縁膜を成す酸化硅素膜の比誘電率はＣＶ測定により約３．９と求められた。第一層間絶縁膜と第二層間絶縁膜及び第三層間絶縁膜は原料物質としてテトラエチルオーソシリケート（ＴＥＯＳ：Ｓｉ（ＯＣＨ_２ＣＨ_３）_４）と酸素とを用いてＣＶＤ法にて形成した酸化硅素膜である。第一層間絶縁膜はゲート電極（本実施例では４００ｎｍ）よりも２０％程度以上厚く、第二層間絶縁膜よりも薄いのが望ましい。斯うするとゲート電極を確実に覆って、ゲート電極と第一配線乃至は第二配線との短絡を防止し、同時に第二層間絶縁膜を厚くし得るからである。本実施例では第一層間絶縁膜を５００ｎｍとした。第三層間絶縁膜は第二配線と容量検出電極とを分離し短絡を防止して居る。第一配線と容量検出電極とは第二層間絶縁膜と第三層間絶縁膜とによって分離されている。従って第一配線と容量検出電極との間に生ずる寄生容量を最小とし、好感度の静電容量検出装置を実現するには第二層間絶縁膜の誘電率と第三層間絶縁膜の誘電率とは出来る限り小さく、その厚みは出来る限り厚い方が好ましい。而るにＣＶＤ法にて積層された酸化硅素膜の総厚みが２μｍ程度を越えると酸化膜に亀裂が生ずる場合があり、歩留まりの低下をもたらす。従って第一層間絶縁膜と第二層間絶縁膜と第三層間絶縁膜との和は２μｍ程度以下とする。斯うする事で静電容量検出装置の生産性が向上する。先にも述べた様に第二層間絶縁膜と第三層間絶縁膜とは厚い方が好ましいので、第一層間絶縁膜よりも厚くする。第一層間絶縁膜はゲート電極よりも２０％程度以上厚く、第二層間絶縁膜と第三層間絶縁膜とは第一層間絶縁膜よりも厚く、第一層間絶縁膜と第二層間絶縁膜と第三層間絶縁膜との和は２μｍ程度以下が理想的と言える。本実施例では第二層間絶縁膜の厚みを１μｍとした。第一配線と第二配線は何れも５００ｎｍ厚のアルミニウムより成り、配線幅は５μｍである。第一配線に依り出力線と列線が形成され、第二配線にて電源線と共通出力線が形成され、インジウム錫酸化物（ＩＴＯ）から成る第三配線に依り容量検出電極が配線された。容量検出電極と第二配線とは重なり部がない。此等の距離を余り離すと容量検出電極が小さくなって測定感度が落ちる為、第二配線と容量検出電極との距離は０．５μｍから５μｍの間とすべきである。本実施例では静電容量検出装置を成す行列のピッチを６６μｍとし、解像度を３８５ｄｐｉ（ｄｏｔｓｐｅｒｉｎｃｈ）としている。容量検出電極面積は１２００μｍ^２から１６００μｍ^２で有った。容量検出誘電体膜は厚み３００ｎｍの窒化硅素膜にて形成された。ＣＶ測定からこの窒化硅素膜の比誘電率は略７．５であった。
【００２７】
回路構成は図４Ｂとし、信号増幅用ＭＩＳ型薄膜半導体装置と信号転送用ＭＩＳ型薄膜半導体装置はＮ型薄膜トランジスタにて形成し、出力信号パスゲート用ＭＩＳ型薄膜半導体装置はＣＭＯＳ薄膜トランジスタにて形成した。列線には選択時に正電源電位Ｖｄｄ（４．０Ｖ）を供給し、非選択時には負電源電位Ｖｓｓ（０Ｖ）を供給した。又電源線には選択時に正電源電位Ｖｄｄ（４．０Ｖ）を供給し、非選択時には負電源電位Ｖｓｓ（０Ｖ）を供給した。列線の選択も電源線の選択もＣＭＯＳ薄膜トランジスタにて作られたシフトレジスタからの信号を利用した。信号増幅用ＭＩＳ型薄膜半導体装置と信号転送用ＭＩＳ型薄膜半導体装置のゲート長は３μｍで、ゲート幅は１０μｍであった。又、出力信号パスゲート用薄膜半導体装置を為すＮ型及びＰ型薄膜トランジスタのゲート長は共に３μｍで、ゲート幅は共に２７０μｍであった。ＣＭＯＳパスゲートを構成するＮ型薄膜トランジスタのゲート電極には列線に供給される列選択信号を入力し、Ｐ型薄膜トランジスタのゲート電極には列選択信号を反転させた信号を入力した。
【００２８】
此の様な構成にて静電容量検出装置を作成したところフレーム周波数５Ｈｚにて良好な指紋画像が採取された。
【００２９】
【発明の効果】
以上詳述してきた様に、従来の単結晶硅素基板を用いた技術では数ｍｍ×数ｍｍ程度の小さな静電容量検出装置しかプラスティック基板上に形成出来なかったが、本願発明に依るとその百倍もの面積を有する静電容量検出装置をプラスティク基板上に作成する事が実現し、しかも対象物の凹凸情報を窮めて高精度に検出出来る様になった。その結果、例えばスマートカードのセキュリティーレベルを著しく向上せしめるとの効果が認められる。又、単結晶硅素基板を用いた従来の静電容量検出装置は装置面積の極一部しか単結晶硅素半導体を利用して居らず、莫大なエネルギーと労力とを無駄に費やしていた。これに対し本願発明では斯様な浪費を排除し、地球環境の保全に役立つとの効果を有する。
【図面の簡単な説明】
【図１】従来技術に於ける動作原理を説明した図。
【図２】本願発明に於ける動作原理を説明した図。
【図３】本願発明に於ける動作原理を説明した図。
【図４】Ａ信号転送素子を持たない静電容量検出装置を説明した図。Ｂ本願発明全体構成を説明した図。Ｃ本願発明全体構成を説明した図。
【図５】本願発明の素子構造を説明した図。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a capacitance detection device that reads the surface shape of an object having fine irregularities such as fingerprints by detecting the capacitance that changes according to the distance from the object surface.
[0002]
[Prior art]
Conventionally, a capacitance detection device used for a fingerprint sensor or the like has formed a sensor electrode and a dielectric film provided on the sensor electrode in a matrix on a single crystal silicon substrate (Japanese Patent Application Laid-Open No. 11-118415, special feature). (Open 2000-346608, JP 2001-56204 A, JP 2001-133213 A, etc.). FIG. 1 illustrates the principle of operation of a conventional capacitance detection device. The sensor electrode and the dielectric film form one electrode of the capacitor and the dielectric film, and the other body is grounded. Capacitance C of this capacitor _F Changes according to the unevenness of the fingerprint in contact with the surface of the dielectric film. On the other hand, the capacitance C _S Is prepared, and these two capacitors are connected in series, and a predetermined voltage is applied. As a result, a charge Q corresponding to the unevenness of the fingerprint is generated between the two capacitors. This electric charge Q was detected using ordinary semiconductor technology, and the surface shape of the object was read.
[0003]
[Problems to be solved by the invention]
However, since these conventional capacitance detection devices are formed on a single crystal silicon substrate, when the device is used as a fingerprint sensor, when the finger is pressed strongly, the device breaks down. I had it.
[0004]
Furthermore, the fingerprint sensor is inevitably required to have a size of about 20 mm × 20 mm depending on its use, and most of the capacitance detection device area is occupied by the sensor electrode. Of course, the sensor electrode is made on a single crystal silicon substrate, but most of the single crystal silicon substrate (bottom part of the sensor electrode) produced by expending enormous energy and labor plays only a role as a support. That is, the conventional capacitance detection device is not only expensive, but has a problem that it is formed on a great deal of waste and waste.
[0005]
In addition, in recent years, it is strongly pointed out that a personal authentication function should be provided on a card such as a credit card or a cash card to enhance the safety of the card. However, since a conventional capacitance detection device made on a single crystal silicon substrate lacks flexibility, there is a problem that the device cannot be made on a plastic substrate.
[0006]
In view of the above-mentioned circumstances, the present invention is intended to operate stably, further reduce unnecessary energy and labor at the time of manufacture, and excellent electrostatic capacity that can be created other than a single crystal silicon substrate. To provide a capacity detection device.
[0007]
[Means for Solving the Problems]
The present invention is based on detecting a capacitance that changes in accordance with the distance from an object, and is a capacitance detection device that reads the surface shape of an object. The capacitance detection device has M rows and N columns. M power lines arranged in a matrix, N output lines, each power line (i-th power line PLi, i is an integer from 1 to M) and each output line (j-th column) A capacitance detection element (capacitance detection element ECSEij located in i row and j column) provided at an intersection with the output line OLj, j is an integer from 1 to N, and this capacitance The detection element (ECSEij) includes a signal detection element (SSEij), a signal amplification element (SAEij), and a signal transfer element (STEij). The signal detection element includes a capacitance detection electrode and a capacitance detection dielectric film. Is a signal amplifying MIS type comprising a gate electrode, a gate insulating film, and a semiconductor film. Consists semiconductor device (TSD-SAij), signal transfer device is characterized in that it consists of MIS type thin film semiconductor device for signal transfer including a gate electrode, a gate insulating film and the semiconductor film (TSD-STij). Further, this electrostatic capacitance detection device has N column lines, and the source region of the signal amplification MIS thin film semiconductor device (TSD-SAij) is connected to the output line (OLj) of the jth column for signal amplification. The drain region of the MIS type thin film semiconductor device for use (TSD-SAij) and the source region of the MIS type thin film semiconductor device for signal transfer (TSD-STij) are connected, and the MIS type thin film semiconductor device for signal transfer (TSD-STij) The drain region is connected to the i-th power line (PLi), the gate electrode of the signal amplification MIS thin film semiconductor device (TSD-SAij) is connected to the capacitance detection electrode, and the signal transfer MIS thin film semiconductor device ( The gate electrode of TSD-STij is connected to the column line (CLj) of the j-th column. Alternatively, the positional relationship in the electrostatic capacitance detection element (ECSEij) between the MIS thin film semiconductor device for signal transfer (TSD-STij) and the MIS thin film semiconductor device for signal amplification (TSD-SAij) may be exchanged. . Specifically, this capacitance detection device has N column lines, and the drain region of the signal amplification MIS type thin film semiconductor device (TSD-SAij) is connected to the i-th power supply line (PLi). The source region of the MIS thin film semiconductor device for signal amplification (TSD-SAij) and the drain region of the MIS thin film semiconductor device for signal transfer (TSD-STij) are connected, and the MIS thin film semiconductor device for signal transfer (TSD- The source region of STij) is connected to the output line (OLj) of the jth column, the gate electrode of the signal amplification MIS thin film semiconductor device (TSD-SAij) is connected to the capacitance detection electrode, and the signal transfer MIS thin film. A feature of the semiconductor device (TSD-STij) is that the gate electrode is connected to the column line (CLj) of the j-th column. Furthermore, in the capacitance detection device of the present invention, the output line and the column line are wired by the first wiring, the power line is wired by the second wiring, and the first wiring and the second wiring are different through an insulating film. It is also characterized by being formed on a layer. Further, the capacitance detection electrode is wired by a third wiring, and the first wiring, the second wiring, and the third wiring are formed on different layers through an insulating film. Furthermore, the third wiring is characterized in that it is located on the most surface side of the wiring of the capacitance detection device.
[0008]
The present invention is based on detecting a capacitance that changes in accordance with the distance from an object, and is a capacitance detection device that reads the surface shape of an object. The capacitance detection device has M rows and N columns. M power lines arranged in a matrix, N output lines, N column lines, power lines (i-th power line PLi, i is an integer from 1 to M) and outputs Capacitance detection element (capacitance detection element ECSEij located in i row and j column) provided at the intersection with the line (j-th output line OLj, j is an integer from 1 to N), N lines An output signal selection circuit connected to the output line and the N column lines. The capacitance detection element (ECSEij) includes a signal detection element (SSEij), a signal amplification element (SAEij), and a signal transfer element (STEij). The output signal selection circuit includes a common output line and an output signal pass gate (position j). The signal detection element (SSEij) includes a capacitance detection electrode and a capacitance detection dielectric film, and the signal amplification element (SAEij) includes a gate electrode, a gate insulating film, and a semiconductor film. MIS type thin film semiconductor device (TSD-SAij) for signal transfer, the signal transfer element (STEij) is made up of MIS type thin film semiconductor device for signal transfer (TSD-STij) consisting of a gate electrode, a gate insulating film and a semiconductor film, and an output signal The pass gate (OLPGGEj) for use is characterized by comprising an MIS type thin semiconductor device (TSD-OLPGj) for an output signal pass gate comprising a gate electrode, a gate insulating film and a semiconductor film. Further, the source region of the MIS thin film semiconductor device for signal amplification (TSD-SAij) is connected to the output line (OLj) of the jth column, and the signal transfer with the drain region of the MIS thin film semiconductor device for signal amplification (TSD-SAij). The source region of the MIS type thin film semiconductor device (TSD-STij) is connected to the drain region of the signal transfer MIS type thin film semiconductor device (TSD-STij) and connected to the power line (PLi) of the i-th row. The gate electrode of the amplification MIS type thin film semiconductor device (TSD-SAij) is connected to the capacitance detection electrode, and the gate electrode of the signal transfer MIS type thin film semiconductor device (TSD-STij) is the j-th column line (CLj). The source region of the MIS thin film semiconductor device (TSD-OLPGj) for output signal pass gate is connected to the common output line, and is connected to the output signal pass gate. The drain region of the gate MIS thin film semiconductor device (TSD-OLPGj) is connected to the jth output line (OLj), and the gate electrode of the output signal pass gate MIS thin film semiconductor device (TSD-OLPGj) is j columns. It is connected to the column line (CLj) of the eye. Alternatively, the positional relationship in the electrostatic capacitance detection element (ECSEij) between the MIS thin film semiconductor device for signal transfer (TSD-STij) and the MIS thin film semiconductor device for signal amplification (TSD-SAij) may be exchanged. . Specifically, the drain region of the MIS thin film semiconductor device for signal amplification (TSD-SAij) is connected to the i-th power line (PLi), and the source of the MIS thin film semiconductor device for signal amplification (TSD-SAij). And the drain region of the signal transfer MIS thin film semiconductor device (TSD-STij) is connected, and the source region of the signal transfer MIS thin film semiconductor device (TSD-STij) is the j-th output line (OLj). ), The gate electrode of the signal amplification MIS type thin film semiconductor device (TSD-SAij) is connected to the capacitance detection electrode, and the gate electrode of the signal transfer MIS type thin film semiconductor device (TSD-STij) is j The source region of the MIS thin film semiconductor device (TSD-OLPGj) connected to the column line (CLj) of the column is common to the output signal pass gate MIS type thin film semiconductor device (TSD-OLPGj). The drain region of the MIS thin film semiconductor device for output signal pass gate (TSD-OLPGj) is connected to the output line (OLj) of the j-th column and is connected to the force line, and the MIS thin film semiconductor device (TSD for output signal pass gate). The gate electrode of -OLPGj) is connected to the column line (CLj) of the jth column.
[0009]
In the capacitance detection device of the present invention, the output line and the column line are wired by the first wiring, and the power supply line and the common output line are wired by the second wiring. It is also characterized by being formed on different layers via an insulating film. Further, the capacitance detection electrode is wired by a third wiring, and the first wiring, the second wiring, and the third wiring are formed on different layers through an insulating film. Further, the third wiring is characterized in that it is located on the most surface side among the wirings of the capacitance detection device.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
According to the present invention, an electrostatic capacity detection device that reads a surface shape of an object by detecting an electrostatic capacity that changes in accordance with the distance to the object is a MIS type thin film semiconductor device comprising a metal-insulating film-semiconductor film. Create using. A thin-film semiconductor device is generally known as a technique for manufacturing a semiconductor integrated circuit requiring a large area on a glass substrate at low cost. As a specific example, it has recently been applied to a liquid crystal display device or the like. Therefore, when a capacitance detection device adapted to a fingerprint sensor or the like is made with a thin film semiconductor device, it is not necessary to use an expensive substrate made by consuming a great amount of energy such as a single crystal silicon substrate. Therefore, the apparatus can be produced at low cost without wasting valuable earth resources. A thin film semiconductor device adopts a transfer technology called SUFTLA (Japanese Patent Laid-Open No. 11-312811 or S. Utsunomiya et al. Society for Information Display p. 916 (2000)), so that a semiconductor integrated circuit is formed on a plastic substrate. Since it can be made, the capacitance detecting device can be released from the single crystal silicon substrate and formed on the plastic substrate.
[0011]
Now, as shown in FIG. 1, it is impossible to produce a capacitance detecting device to which a conventional operation principle is applied using a thin film semiconductor device with the current technology of the thin film semiconductor device. Since the charge Q induced between two capacitors connected in series is very small, the charge Q can be accurately read using single crystal silicon LSI technology that enables high-precision sensing. However, the charge Q cannot be read accurately because it is not as good as single crystal silicon LSI technology and the characteristic deviation between thin film semiconductor devices is large.
[0012]
Accordingly, the capacitance detection device of the present invention has at least M (M is an integer of 1 or more) power supply lines and N (N is an integer of 1 or more) outputs arranged in a matrix of at least M rows and N columns. Line and each power line (i-th power line PLi, i is an integer from 1 to M) and each output line (j-th output line OLj, j is an integer from 1 to N) A capacitance detection element (capacitance detection element ECSEij located in i row and j column), and the capacitance detection element includes a signal detection element and a signal amplification element as minimum components. Including. An example of the capacitance detection device having such a configuration is shown in FIG. 4A. The signal detection element includes a capacitance detection electrode and a capacitance detection dielectric film, and a charge Q is generated in the capacitance detection electrode according to the capacitance. In the present invention, this electric charge Q is amplified by a signal amplifying element provided in each capacitance detecting element and converted into a current or a voltage. Specifically, the signal amplifying element includes a signal amplifying MIS thin film semiconductor device including a gate electrode, a gate insulating film, and a semiconductor film, and the gate electrode of the signal amplifying MIS thin film semiconductor device is connected to the capacitance detection electrode. .
[0013]
FIG. 2 shows an operation principle diagram of the present invention. Capacitance C _s And a capacitance C that changes according to the surface shape of the object _F The voltage divided by the capacitive coupling with the capacitor having, changes the gate potential of the MIS thin film semiconductor device for signal amplification. Thus, when a predetermined voltage is applied to the drain region of this thin film semiconductor device, the current I flowing between the source and drain of the thin film semiconductor device is significantly amplified according to the voltage induced by capacitive coupling. Since the charge Q itself induced in the gate electrode does not flow anywhere and is stored, the current Ids can be easily measured by increasing the drain voltage or extending the measurement time. Therefore, the thin film semiconductor device is used. However, the surface shape of the object can be measured sufficiently accurately.
[0014]
As described above, in the present invention, the signal amplifying MIS thin film semiconductor device is used as the signal amplifying element. In this case, the capacitance C _s The capacitor having MIS can be used as the MIS type thin film semiconductor device for signal amplification. That is, capacitance C _s Transistor capacitance C of MIS type thin film semiconductor device for signal amplification _T Yes. By doing so, the capacitance C is changed from the capacitance detection element. _s Capacitors with can be omitted, the structure is simplified and the manufacturing process is simplified. In addition, it can be said that combining the two power sources depicted in FIG. 2 as a common power source Vdd is effective from the viewpoint that unnecessary wiring in the capacitance detection device can be omitted. FIG. 3 shows an equivalent circuit diagram relating to the operating principle in such a state. Capacitance C that changes according to the surface shape of the object _F Capacitor and transistor capacitance C _T Is connected in series with a capacitor having Strictly speaking, transistor capacity C _T Is a capacitance formed between the drain electrode and the gate electrode of the MIS thin film semiconductor device for signal amplification. To realize the configuration of FIG. 3, as shown in FIG. 4, the source region of the signal amplifying MIS thin film semiconductor device is connected to the output line, and the drain region of the signal amplifying MIS thin film semiconductor device is connected to the power supply line. Then, the voltage Vdd is applied to the power supply line, and the current Ids that changes in accordance with the surface shape of the object is extracted from the output line. For example, if each capacitor is set appropriately and the peak of the fingerprint is in contact with the signal detection element, the signal amplification element becomes high resistance and cuts off the power supply line and the output line (almost no current Ids is passed). When the valley of the fingerprint faces the signal detecting element, the signal amplifying element has a low resistance and conducts the power supply line and the output line (passes current Ids). Such a change in the amount of current and a change in the voltage applied to the output line are sensed to detect the capacitance caused by the fingerprint shape and the like.
[0015]
In principle, it is possible to collect surface shape information such as fingerprints with such a configuration, but a plurality of capacitance detection elements are connected to each power supply line and each output line arranged in a matrix. As a result, interference of information occurs between the capacitance detection elements. When the surface shape of the object is read by the capacitance detection element ECSEij with the capacitance detection device having the configuration shown in FIG. 4A, the voltage Vdd is applied to the power supply line PLi, and the output signal OSij is extracted from the output line OLj. . If the signal amplifying element SAEij has a high resistance, the output line OLj must have a low potential. At this time, since the voltage Vdd is also applied to all the capacitance detection elements ECSEiy (y is an integer from 1 to N) connected to the power supply line PLi, each output line OLy has An output signal OSiy corresponding to the surface shape read through the capacitance detection element ECSEiy flows. For example, if the signal amplification element SEAij + 1 is in a low resistance state, the output line OLj + 1 becomes a high potential via the output signal OSij + 1. Furthermore, a current can also flow through the power supply line PLx through the capacitance detection element ECSExy (x is an integer from 1 to M except i) connected to the output line OLy. For example, if the signal amplifying element SAEi-1j + 1 has a low resistance in a state where the output line OLj + 1 is at a high potential, the output signal OSi-1j + 1 in the reverse direction may exist via the signal amplifying element SAEi-1j + 1, The power supply line PLi-1 that must be present is brought to a high potential. Thus, the current passed through the non-selected power supply line PLx (x is an integer from 1 to M excluding i) that should originally be at a low potential changes the non-selected power supply line to a high potential. When the non-selected power supply line changes to a high potential, the output signal OSxj flows to the output line OLj via the capacitance detection element ECSExj. Returning to the previous example, for example, if the signal amplifying element SAEi-1j has a low resistance, the output signal OSi-1j flows into the output line OLj. As a result, other output signals such as OSi-1j are superimposed on the output line OLj in addition to OSij that should be detected. In other words, there is a current path other than the capacitance detection device ECSEij between the power supply line PLi and the output line OLj. Even if the power supply line PLi is selected and the voltage Vdd is applied, the selection of the power supply line does not substantially function, and a plurality of output signals flow into the output line OLj through a plurality of capacitance detection elements, and the accuracy is high. It becomes difficult to read the surface shape.
[0016]
Therefore, in the present invention, it is possible to reliably detect the capacitance by accurately selecting each capacitance detection element and using a signal transfer element for controlling the operation to prevent interference between detection information elements. To do. The capacitance detection device of the present invention includes M (M is an integer of 1 or more) power supply lines arranged in a matrix of M rows and N columns, N (N is an integer of 1 or more) output lines, and Provided at the intersection of each power line (i-th power line PLi, i is an integer from 1 to M) and each output line (j-th output line OLj, j is an integer from 1 to N) A capacitance detection element (capacitance detection element ECSEij located in i row and j column), and this capacitance detection element ECSEij includes a signal detection element SSEij, a signal amplification element SAEij, and a signal transfer element STEij. Including. The signal detection element SSEij includes a capacitance detection electrode and a capacitance detection dielectric film, detects the capacitance, and converts the capacitance into a voltage. The signal amplifying element SAEij includes a signal amplifying MIS thin film semiconductor device TSD-SAij including a gate electrode, a gate insulating film, and a semiconductor film, and the signal transfer element STEij includes a signal transfer including a gate electrode, a gate insulating film, and a semiconductor film. MIS type thin film semiconductor device TSD-STij. The signal amplification MIS type thin film semiconductor device TSD-SAij and the signal transfer MIS type thin film semiconductor device TSD-STij are connected in series in the capacitance detection element ECSEij.
[0017]
An example of a capacitance detection device that realizes such a configuration will be described in detail with reference to FIGS. 4B and 4C. (In FIGS. 4B and 4C, the source region of the MIS thin film semiconductor device is indicated by S, the drain region is indicated by D, and the gate electrode is indicated by G. The source region and drain region are potentials of the N type semiconductor device. The lower one is defined as the source region, and in the P-type semiconductor device, the higher potential is defined as the source region.) In the capacitance detection element ECSEij of FIGS. 4B and 4C, the MIS thin film semiconductor device TSD- for signal amplification SAij and the MIS thin film semiconductor device TSD-STij for signal transfer are connected in series between the power supply line PLi and the output line OLj. Accordingly, output signal interference between the capacitance detection elements can be prevented, and a capacitance detection device with high detection accuracy can be realized. Actually, when the output signal from the capacitance detection element ECSEij is read, the i-th power line is selected to be a high potential, and in that state, the signal transfer MIS thin film semiconductor device TSD-STij is applied to the gate electrode. By controlling the applied voltage, only the capacitance detection element ECSEij can be selected. According to the previous example, in FIG. 4A, the interference of the output signal has occurred in the output line OLj through the path of the reverse output signals OSi-1j + 1 and OSi-1j via OSij to OSij + 1. However, in the configuration of the present invention (FIGS. 4B and 4C), the column side selection is performed by the signal transfer element, so that when the capacitance detection element ECSEij located in the j column is selected, the other column is selected. The signal transfer element is always kept in a high resistance state. For this reason, OSij + 1 and the reverse output signal OSi-1j + 1 are blocked, and output signals other than the selected capacitance detection element ECSEij are not superimposed on the output line OLj. Only when the MIS thin film semiconductor device TSD-STij for signal transfer is electrically connected between the source and the drain (the signal transfer element is in a selected state), only the capacitance detection element ECSEij is operated and is used for signal transfer. When the source and drain of the MIS thin film semiconductor device TSD-STij are not electrically connected (the signal transfer element is not selected), the capacitance detection element ECSEij does not operate.
[0018]
As described so far, one method of preventing interference of information generated when collecting surface shape information using a capacitance detection device including a signal transfer element is based on column selection. Is to control. Therefore, in the capacitance detection device of the present invention, the column line CLj for controlling the operation of the capacitance detection element is provided for each column, and the selection (signal) of the signal transfer element STEij according to the voltage applied to the column line CLj. The operation of the capacitance detection element ECSEij is controlled by switching between the transfer element STEij being in a conductive state with a low resistance) or non-selection (the signal transfer element STEij being in a high resistance and a cutoff state). Specifically, the capacitance detection device of the present invention also includes N column lines CLj. That is, each matrix element of the capacitance detection device including a matrix of M rows and N columns includes a power supply line PLi, an output line OLj, a column line CLj, and a capacitance detection element ECSEij. The source region of the signal amplification MIS thin film semiconductor device TSD-SAij is electrically connected to the output line OLj of the jth column, and the drain region of the signal amplification MIS thin film semiconductor device TSD-SAij and the signal transfer MIS thin film. The source region of the semiconductor device TSD-STij is electrically connected, and the drain region of the signal transfer MIS thin film semiconductor device TSD-STij is electrically connected to the i-th power line PLi. Being electrically connected means not only that they are directly connected but also that electrical connection is established through some kind of switch element. For example, another transistor may be arranged in series between the signal transfer element and the power supply line. If the arranged transistor is in a selected state and has a low resistance, it can be said that the signal transfer element and the power supply line are electrically connected since conduction is established between the signal transfer element and the power supply line. The gate electrode of the signal amplification MIS thin film semiconductor device TSD-SAij is electrically connected to the capacitance detection electrode, and the gate electrode of the signal transfer MIS thin film semiconductor device TSD-STij is electrically connected to the column line CLj of the jth column. Connected to. The overall structure of the capacitance detection device having such a configuration is shown in FIG. 4B. Contrary to the above configuration, the positional relationship in the electrostatic capacitance detection element ECSEij between the MIS thin film semiconductor device TSD-STij for signal transfer and the MIS thin film semiconductor device TSD-SAij for signal amplification may be exchanged. . Specifically, the capacitance detection element according to another embodiment of the present invention includes N column lines CLj, and the drain region of the signal amplification MIS thin film semiconductor device TSD-SAij is the i-th power supply line PLi. MIS type thin film semiconductor device TSD-SAij for signal amplification and the drain region of MIS type thin film semiconductor device TSD-STij for signal transfer are electrically connected to each other, and the MIS type thin film for signal transfer The source region of the semiconductor device TSD-STij is electrically connected to the i-th output line OLj. The gate electrode of the signal amplification MIS thin film semiconductor device TSD-SAij is electrically connected to the capacitance detection electrode, and the gate electrode of the signal transfer MIS thin film semiconductor device TSD-STij is electrically connected to the column line CLj of the jth column. Connected to. The overall structure of the capacitance detecting device having such a configuration is shown in FIG. 4C. According to such a configuration, the i potential can be selected by applying the high potential Vdd to the power supply line PLi, and the j column can be selected by applying a predetermined selection potential to the column line CLj. Thus, the output signal OSij (voltage Vij or current Iij) read according to the surface shape by the capacitance detection element ECSEij can be accurately extracted from the output line OLj. For example, when the surface shape is measured by the capacitance detection element ECSEij in the configuration of FIG. 4B or 4C, the voltage Vdd is applied to the power supply line PLi, the i row is selected, and the same voltage is applied to the column line CLj. Apply Vdd and select column j. First, N capacitance detection elements ECSEib (b is an integer from 1 to N) connected to the power supply line PLi to which the positive power supply voltage Vdd is applied are selected, and further selected from among them are selected according to the column line CLj. Only the electrostatic capacitance detection element ECSEij belonging to the j column that has been selected is selected and put into an operating state. Thus, diffusion of output information via the capacitance detection device ECSEi, (y is an integer from 1 to M excluding i) in the non-selected column is eliminated, and between the power supply line PLi and the output line OLj The information inflow path other than the capacitance detection element ECSEij is cut off. Therefore, an output signal OSij (voltage Vij or current Iij) corresponding to the surface shape is output to the output line OLj only through the capacitance detection element ECSEij, and information interference between the capacitance detection elements can be prevented.
[0019]
In order to effectively function the capacitance detection device having such a configuration, in the capacitance detection device of the present invention, the output line and the column line are wired by the first wiring, and the power supply line is the second wiring. The first wiring and the second wiring are formed on different layers through an insulating film. Furthermore, the capacitance detection electrode is wired with a third wiring formed on a different layer from the first wiring and the second wiring with an insulating film. Further, the capacitance detection electrode can be wired by any of the first wiring to the third wiring, but the third wiring is positioned on the most surface side among the wiring in the capacitance detection device. By forming such a configuration, excess wiring is removed, thereby minimizing the parasitic capacitance generated between the respective wirings, and thus detecting a very small capacitance with high sensitivity. An example of the structure of a capacitance detection element embodying the present invention will be described with reference to FIG. In FIG. 5, the source region of the MIS type thin film semiconductor device is indicated by S, the drain region is indicated by D, and the gate electrode is indicated by G. The signal amplifying MIS thin film semiconductor device constituting the signal amplifying element of the capacitance detecting element and the signal transferring MIS thin film semiconductor device constituting the signal transfer element each include a source region, a channel forming region, and a drain region. The semiconductor film, the gate insulating film, and the gate electrode are indispensable constituent requirements. In the configuration example of FIG. 5, the drain region of the signal amplification MIS thin film semiconductor device and the source region of the signal transfer MIS semiconductor device are provided as one region. The first interlayer insulating film covers the MIS type thin film semiconductor device. A first wiring is connected to the source region of the MIS thin film semiconductor device for signal amplification, and a second wiring is connected to the drain region of the MIS thin film semiconductor device for signal transfer. Alternatively, the first wiring may be connected to the drain region of the signal amplification MIS thin film semiconductor device, and the second wiring may be connected to the source region of the signal transfer MIS thin film semiconductor device. A second interlayer insulating film is provided between the first wiring and the second wiring, and the first wiring and the second wiring are formed on different layers. Of course, the second wiring can be formed on the first interlayer insulating film, and the first wiring can be formed on the second interlayer insulating film. A capacitance detection electrode constituting a signal detection element of the capacitance detection element is provided as a third wiring and is connected to the gate electrode of the signal amplification MIS thin film semiconductor device. The third wiring is formed on a third interlayer insulating film provided on the second interlayer insulating film, and is formed on a layer different from the first wiring and the second wiring. The capacitance detection electrode and the first wiring or the second wiring are on layers different from those other than the part that is electrically connected (the part that is made equipotential in an ideal system with zero electrical resistance). Arrange them so that they do not overlap each other. In order to detect a minute capacitance, it is necessary to minimize the parasitic capacitance. By adopting the above configuration, the capacitance detection electrode and the second wiring, or the capacitance detection electrode and the second wiring parasitic capacitance are minimized. Therefore, a highly sensitive capacitance detection device is realized. A capacitance detection dielectric film covers the capacitance detection electrode, and the capacitance detection dielectric film is located on the outermost surface of the capacitance detection device. The capacitance detection dielectric film also plays the role of a protective film of the capacitance detection device. In order to function efficiently as a protective film, it is desirable that the relative dielectric constant of the capacitance detection dielectric film be larger than that of the second interlayer insulating film or the third interlayer insulating film.
[0020]
Next, a method for reading an output signal from the capacitance detection device according to the present invention will be described with reference to FIGS. 4B and 4C. Since the capacitance detection elements of the present invention are arranged in a matrix of M rows and N columns, in order to read the surface shape of the object, the rows and columns are sequentially scanned, and M × N electrostatic capacitances are detected. Capacitance detection elements are selected in an appropriate order. That is, after the voltage Vdd is applied to the power line PLi, the column line CLj is sequentially selected, and the operation of reading the output signal OSij appearing on the output line OLj is repeated. At this time, the output signal selection circuit determines in what order the output signals detected from the respective capacitance detection elements are read out. Specifically, the capacitance detection device of the present invention includes M power supply lines arranged in a matrix of M rows and N columns, N output lines, N column lines, and power supply lines (i Capacitance detection element provided at the intersection of the power supply line PLi, i in the row and an output line (the output line OLj, j in the j-th column is an integer from 1 to N) in the row (Capacitance detection element ECSEij located in i row and j column), N output lines, and an output signal selection circuit connected to the N column lines. Each matrix element of the M rows and N columns matrix includes a power supply line PLi, an output line OLj, a column line CLj, and a capacitance detection element ECSEij. N output lines and N column lines connected to each matrix element are connected to an output signal selection circuit. The capacitance detection element ECSEij includes a signal detection element SSEij, a signal amplification element SAEij, and a signal transfer element STEij. The output signal selection circuit includes at least a common output line (LDOUT) and an output signal pass gate (output signal pass gate OLPGEj located in the j-th column). The signal detection element SSEij includes a capacitance detection electrode and a capacitance detection dielectric film. The signal amplifying element SAEij is composed of a signal amplifying MIS thin film semiconductor device TSD-SAij composed of a gate electrode, a gate insulating film and a semiconductor film, and the signal transfer element STEij is a signal composed of a gate electrode, a gate insulating film and a semiconductor film. The MIS type thin film semiconductor device TSD-STij for transfer and the output signal pass gate OLPGEj are constituted by the MIS type thin semiconductor device TSD-OLPGj for output signal pass gate comprising a gate electrode, a gate insulating film and a semiconductor film. The output signal selection circuit takes out an output signal from a column selected by a decoder, a shift register or the like to a common output line. That is, when the j-th column line CLj is selected among the N column lines, the output signal OSj that appears on the j-th output line OLj among the N output lines is selectively output in common. Take out to the line. In the capacitance detection device of the present invention, all output signals are output to a common output line. With such a configuration, when detecting each output signal OSj, a device for detecting the output signal must be individually provided on each output line OLj, giving rise to difficulty in manufacturing and providing N connection terminals. This also causes a variation in connection, which increases the measurement error. Therefore, in the capacitance detection device of the present invention, all output signals are output from several (about 1 to 8) common output lines, facilitating the mounting process with an external circuit and the like, and resulting from the connection terminals. This minimizes the variation in connection to achieve high-accuracy measurement. Also, simply connecting the common output line and the output line (although measurement is still possible), the output lines are connected directly via the common output line, and the output signal is widely distributed to other output lines. Spread and finish. This is not preferable for detecting a weak output signal at high speed and with high accuracy. Therefore, in the capacitance detection device of the present invention, an output signal pass gate OLPGEj for controlling the electrical conduction of the output signal is provided between each output line OLj and the common output line. Under such a configuration, the output signal OSij remains only in the selected output line OLij and the common output line, and does not spread to other unselected output lines. For example, when the output signal is read as a voltage, the potentials of only the selected output line and the common output line can be changed, so that highly accurate detection can be performed in a short time.
[0021]
In the capacitance detection device of the present invention, in order to efficiently read out the output signal from the common output line, only the output line OLj of the column selected by the column line CLj needs to be electrically connected to the common output line. There is. Therefore, in the capacitance detection element of the present invention, the capacitance detection element ECSEij located in the j-th column is selected by the column line CLj, and at the same time, the electrical conduction state of the output signal pass gate OLPGEj connected to the j-th output line OLj is set. Control. As an example, the output signal pass gate OLPGEj includes an output signal pass gate MIS type thin film semiconductor device TSD-OLPGj. More specifically, in the capacitance detection device of the present invention, the source region of the signal amplification MIS type thin film semiconductor device TSD-SAij is electrically connected to the output line OLj of the jth column, and the signal amplification MIS type thin film semiconductor. The drain region of the device TSD-SAij is electrically connected to the source region of the signal transfer MIS thin film semiconductor device TSD-STij, and the drain region of the signal transfer MIS thin film semiconductor device TSD-STij is the power supply in the i-th row. The gate electrode of the signal amplification MIS thin film semiconductor device TSD-SAij is electrically connected to the capacitance detection electrode and the gate electrode of the signal transfer MIS thin film semiconductor device TSD-STij is j. The output signal pass gate MIS thin film semiconductor device TSD-OLPGj electrically connected to the column line CLj of the column and provided in the j-th column The source region is electrically connected to the common output line, and the drain region of the MIS thin film semiconductor device TSD-OLPGj for output signal pass gate is electrically connected to the output line OLj of the j-th column, and the MIS type for output signal pass gate The gate electrode of the thin film semiconductor device TSD-OLPGj is electrically connected to the j-th column line CLj. FIG. 4B shows the overall structure of the capacitance detection device having such a configuration. Alternatively, the positional relationship between the signal transfer MIS thin film semiconductor device TSD-STij and the signal amplification MIS thin film semiconductor device TSD-SAij in the capacitance detection element ECSEij may be exchanged. Specifically, in the capacitance detection device of the present invention, the drain region of the signal amplification MIS thin film semiconductor device TSD-SAij is electrically connected to the i-th power line PLi, and the signal amplification MIS thin film. The source region of the semiconductor device TSD-SAij is electrically connected to the drain region of the signal transfer MIS thin film semiconductor device TSD-STij, and the source region of the signal transfer MIS thin film semiconductor device TSD-STij is the jth column. The gate electrode of the signal amplification MIS thin film semiconductor device TSD-SAij is electrically connected to the capacitance detection electrode, and the gate electrode of the signal transfer MIS thin film semiconductor device TSD-STij is electrically connected to the output line OLj. The MIS type thin film semiconductor device TSD-OLPGj for output signal pass gate is electrically connected to the j-th column line CLj, and the source region is shared. The drain region of the MIS thin film semiconductor device TSD-OLPGj for output signal pass gate is electrically connected to the line, and the gate electrode of the MIS thin film semiconductor device TSD-OLPGj for output signal pass gate is connected to the output line OLj of the jth column. Are connected to the column line CLj of the j-th column. FIG. 4C shows the overall structure of the capacitance detection device having such a configuration. Electrically connected means that electrical continuity is taken directly or indirectly as described above.
[0022]
With such a configuration, when the j-th column line CLj is selected from among the N column lines, one output line OLj located in the j-th column among the N output lines is simultaneously selected. This makes it possible to prevent the output signal from being diffused to other output lines. As a result, the output signal OSij from the capacitance detection element ECSEij selected by the power supply line PLi and the column line CLj is output only to the output line OLj and to the common output line via the output signal pass gate OLPGEj. High-speed and high-precision detection is realized.
[0023]
As a signal (column selection signal) supplied to the column line when actually scanning the column, an output from a shift register, an output from a decoder, or the like is used. A shift register and a decoder for supplying a column selection signal may also be formed by a thin film semiconductor device. If a circuit for generating a column selection signal is a shift register, the shift register creates a column selection signal from signals transferred to each output stage, and sequentially supplies this to the column lines. If the circuit that generates the column selection signal is a decoder, the decoder selects a specific output stage from the N output stages according to the input signal to the decoder, and supplies the column selection signal to this output stage. That is, the column line connected to the selected output stage is selected. In this way, selection signals are appropriately input from the column lines to the N output signal pass gates OLPGEj and the capacitance detection element ECSEij. The electrostatic capacitance detection element ECSEij is selected as appropriate, and the output signal OSij is output to the common output line.
[0024]
As before, in order for the capacitance detection device to function effectively, in the capacitance detection device of the present invention, the output line and the column line are wired by the first wiring, and one of the power supply line and the common output line is used. Parts or all are wired by the second wiring, and the first wiring and the second wiring are formed on different layers through an insulating film. Furthermore, the capacitance detection electrode is wired with a third wiring formed on a different layer from the first wiring and the second wiring with an insulating film. Further, the capacitance detection electrode can be wired by any of the first wiring to the third wiring, but the third wiring is positioned on the most surface side among the wiring in the capacitance detection device. By forming such a configuration, excess wiring is removed, thereby minimizing the parasitic capacitance generated between the respective wirings, and thus detecting a very small capacitance with high sensitivity.
[0025]
Such a capacitance detection element can be formed on a plastic substrate using the above-described SUFTLA technology. A fingerprint sensor based on single-crystal silicon technology is not practical because it does not break down on a plastic, or does not have a sufficient size. On the other hand, the capacitance detection element on the plastic substrate according to the present invention does not have to worry about the capacitance detection element being cracked even if the area is sufficiently large to cover the finger on the plastic substrate, and the fingerprint on the plastic substrate. It can be used as a sensor. Specifically, a smart card having a personal authentication function is realized by the present invention. Smart cards equipped with a personal authentication function are used for bank cards, credit cards, identity cards, etc., and the security level of these cards has been remarkably enhanced. It has an excellent function of protecting the card without flowing out of the card.
(Example 1)
After manufacturing a capacitance detection device made of a thin film semiconductor device on a glass substrate, the capacitance detection device is transferred onto a plastic substrate using SUFTLA technology, and the capacitance detection device is placed on the plastic substrate. Created. The capacitance detection device is composed of capacitance detection elements arranged in a matrix of 304 rows and 304 columns. The size of the matrix portion is a 20 mm square.
[0026]
The substrate is polyethersulfone (PES) having a thickness of 200 μm. The MIS thin film semiconductor device for signal amplification, the MIS thin film semiconductor device for signal transfer, and the MIS thin film semiconductor device for output signal pass gate are all made of thin film transistors having the same cross-sectional structure. The thin film transistor is a top gate type shown in FIG. The semiconductor film is a polycrystalline silicon thin film obtained by laser crystallization and has a thickness of 50 nm. The gate insulating film is a 40 nm thick silicon oxide film formed by chemical vapor deposition (CVD), and the gate electrode is a 400 nm thick tantalum thin film. The relative dielectric constant of the silicon oxide film forming the gate insulating film was determined to be about 3.9 by CV measurement. The first interlayer insulating film, the second interlayer insulating film and the third interlayer insulating film are made of tetraethyl orthosilicate (TEOS: Si (OCH ₂ CH ₃ ) ₄ And a silicon oxide film formed by CVD using oxygen. The first interlayer insulating film is preferably about 20% or more thicker than the gate electrode (400 nm in this embodiment) and thinner than the second interlayer insulating film. This is because the gate electrode can be securely covered, a short circuit between the gate electrode and the first wiring or the second wiring can be prevented, and at the same time, the second interlayer insulating film can be thickened. In this embodiment, the first interlayer insulating film is 500 nm. The third interlayer insulating film separates the second wiring and the capacitance detection electrode to prevent a short circuit. The first wiring and the capacitance detection electrode are separated by the second interlayer insulating film and the third interlayer insulating film. Therefore, in order to minimize the parasitic capacitance generated between the first wiring and the capacitance detection electrode and realize a favorable capacitance detection device, the dielectric constant of the second interlayer insulating film and the dielectric constant of the third interlayer insulating film Is as small as possible, and the thickness is preferably as thick as possible. Thus, if the total thickness of the silicon oxide films laminated by the CVD method exceeds about 2 μm, cracks may occur in the oxide film, resulting in a decrease in yield. Accordingly, the sum of the first interlayer insulating film, the second interlayer insulating film, and the third interlayer insulating film is about 2 μm or less. By doing so, the productivity of the capacitance detection device is improved. As described above, since the second interlayer insulating film and the third interlayer insulating film are preferably thicker, they are made thicker than the first interlayer insulating film. The first interlayer insulating film is about 20% or more thicker than the gate electrode, the second interlayer insulating film and the third interlayer insulating film are thicker than the first interlayer insulating film, and the first interlayer insulating film and the second interlayer insulating film. The sum of the insulating film and the third interlayer insulating film is ideally about 2 μm or less. In this embodiment, the thickness of the second interlayer insulating film is 1 μm. Both the first wiring and the second wiring are made of aluminum having a thickness of 500 nm, and the wiring width is 5 μm. Output lines and column lines are formed by the first wiring, power supply lines and common output lines are formed by the second wiring, and capacitance detection electrodes are wired by the third wiring made of indium tin oxide (ITO). . There is no overlap between the capacitance detection electrode and the second wiring. If these distances are too far apart, the capacitance detection electrode becomes smaller and the measurement sensitivity decreases, so the distance between the second wiring and the capacitance detection electrode should be between 0.5 μm and 5 μm. In this embodiment, the pitch of the matrix forming the capacitance detection device is 66 μm, and the resolution is 385 dpi (dots per inch). Capacity detection electrode area is 1200μm ² To 1600μm ² It was in. The capacitance detection dielectric film was formed of a silicon nitride film having a thickness of 300 nm. From the CV measurement, the relative dielectric constant of this silicon nitride film was approximately 7.5.
[0027]
The circuit configuration is as shown in FIG. 4B. The MIS thin film semiconductor device for signal amplification and the MIS thin film semiconductor device for signal transfer are formed by N type thin film transistors, and the MIS thin film semiconductor device for output signal pass gates is formed by CMOS thin film transistors. A positive power supply potential Vdd (4.0 V) was supplied to the column line when selected, and a negative power supply potential Vss (0 V) was supplied when not selected. A positive power supply potential Vdd (4.0 V) was supplied to the power supply line when selected, and a negative power supply potential Vss (0 V) was supplied when not selected. The selection of the column line and the selection of the power supply line utilized signals from a shift register made of a CMOS thin film transistor. The gate length of the MIS thin film semiconductor device for signal amplification and the MIS thin film semiconductor device for signal transfer was 3 μm and the gate width was 10 μm. The gate lengths of the N-type and P-type thin film transistors constituting the thin film semiconductor device for output signal pass gate were both 3 μm and the gate width was 270 μm. A column selection signal supplied to the column line was input to the gate electrode of the N-type thin film transistor constituting the CMOS pass gate, and a signal obtained by inverting the column selection signal was input to the gate electrode of the P-type thin film transistor.
[0028]
When a capacitance detecting device having such a configuration was produced, a good fingerprint image was collected at a frame frequency of 5 Hz.
[0029]
【The invention's effect】
As described above in detail, the conventional technology using a single crystal silicon substrate can form only a small capacitance detection device of about several mm × several mm on a plastic substrate. It is now possible to create a capacitance detection device having a large area on a plastic substrate, and it is possible to detect the unevenness information of an object with high accuracy. As a result, for example, the effect of significantly improving the security level of the smart card is recognized. Further, the conventional capacitance detection device using a single crystal silicon substrate uses a single crystal silicon semiconductor for only a very small part of the device area, and wastes enormous energy and labor. In contrast, the present invention has the effect of eliminating such waste and helping to preserve the global environment.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an operation principle in a conventional technique.
FIG. 2 is a diagram illustrating an operation principle in the present invention.
FIG. 3 is a diagram illustrating an operation principle in the present invention.
FIG. 4 is a diagram illustrating a capacitance detection device that does not have an A signal transfer element. B is a diagram illustrating the overall configuration of the present invention. C is a diagram illustrating the overall configuration of the present invention.
FIG. 5 is a diagram illustrating an element structure of the present invention.

Claims

In the capacitance detection device that reads the surface shape of the object by detecting the capacitance that changes according to the distance to the object,
The electrostatic capacitance detection device includes M power supply lines arranged in a matrix of M rows and N columns, N output lines, and electrostatic capacitance detection provided at the intersections of the power supply lines and the output lines. Comprising an element,
The capacitance detection element includes a signal detection element, a signal amplification element, and a signal transfer element,
The signal detection element includes a capacitance detection electrode and a capacitance detection dielectric film,
The signal amplifying element comprises a MIS thin film semiconductor device for signal amplification comprising a gate electrode, a gate insulating film, and a semiconductor film,
The electrostatic capacitance detection device, wherein the signal transfer element is composed of a MIS thin film semiconductor device for signal transfer comprising a gate electrode, a gate insulating film, and a semiconductor film.

The capacitance detection device comprises N column lines,
A source region of the MIS thin film semiconductor device for signal amplification is connected to the output line,
A drain region of the MIS thin film semiconductor device for signal amplification and a source region of the MIS thin film semiconductor device for signal transfer are connected;
A drain region of the MIS thin film semiconductor device for signal transfer is connected to the power line,
The gate electrode of the MIS thin film semiconductor device for signal amplification is connected to the capacitance detection electrode,
2. The capacitance detecting device according to claim 1, wherein the gate electrode of the MIS thin film semiconductor device for signal transfer is connected to the column line.

The capacitance detection device comprises N column lines,
The drain region of the MIS thin film semiconductor device for signal amplification is connected to the power supply line,
A source region of the MIS thin film semiconductor device for signal amplification and a drain region of the MIS thin film semiconductor device for signal transfer are connected;
A source region of the MIS thin film semiconductor device for signal transfer is connected to the output line,
The gate electrode of the MIS thin film semiconductor device for signal amplification is connected to the capacitance detection electrode,
2. The capacitance detecting device according to claim 1, wherein the gate electrode of the MIS thin film semiconductor device for signal transfer is connected to the column line.

The output line and the column line are wired by a first wiring, the power line is wired by a second wiring, and the first wiring and the second wiring are formed on different layers through an insulating film. 4. The capacitance detection device according to claim 2, wherein the capacitance detection device is provided.

The capacitance detection electrode is wired by a third wiring, and the first wiring, the second wiring, and the third wiring are formed on different layers through an insulating film. 4. The capacitance detection device according to 4.

6. The capacitance detecting device according to claim 5, wherein the third wiring is located on the most surface side of the wiring of the capacitance detecting device.

In the capacitance detection device that reads the surface shape of the object by detecting the capacitance that changes according to the distance to the object,
The capacitance detection device is provided at an intersection of M power lines arranged in a matrix of M rows and N columns, N output lines, N column lines, and the power lines and the output lines. A capacitance detection element, an output signal selection circuit connected to the N output lines and the N column lines,
The capacitance detection element includes a signal detection element, a signal amplification element, and a signal transfer element,
The output signal selection circuit includes a common output line and an output signal pass gate,
The signal detection element includes a capacitance detection electrode and a capacitance detection dielectric film,
The signal amplifying element comprises a signal amplifying MIS type thin film semiconductor device comprising a gate electrode, a gate insulating film and a semiconductor film,
The signal transfer element comprises a signal transfer MIS thin film semiconductor device comprising a gate electrode, a gate insulating film, and a semiconductor film,
An output signal pass gate comprising a MIS type thin semiconductor device for output signal pass gate comprising a gate electrode, a gate insulating film and a semiconductor film.

A source region of the MIS thin film semiconductor device for signal amplification is connected to the output line,
A drain region of the MIS thin film semiconductor device for signal amplification and a source region of the MIS thin film semiconductor device for signal transfer are connected;
A drain region of the MIS thin film semiconductor device for signal transfer is connected to the power line,
The gate electrode of the MIS thin film semiconductor device for signal amplification is connected to the capacitance detection electrode,
The gate electrode of the MIS thin film semiconductor device for signal transfer is connected to the column line, and the source region of the MIS thin film semiconductor device for output signal pass gate is connected to the common output line,
The drain region of the MIS type thin film semiconductor device for output signal pass gate is connected to the output line,
8. The capacitance detection device according to claim 7, wherein the gate electrode of the MIS type thin film semiconductor device for output signal pass gate is connected to a column line.

The drain region of the MIS thin film semiconductor device for signal amplification is connected to the power supply line,
A source region of the MIS thin film semiconductor device for signal amplification and a drain region of the MIS thin film semiconductor device for signal transfer are connected;
A source region of the MIS thin film semiconductor device for signal transfer is connected to the output line,
The gate electrode of the MIS thin film semiconductor device for signal amplification is connected to the capacitance detection electrode,
The gate electrode of the MIS thin film semiconductor device for signal transfer is connected to the column line, and the source region of the MIS thin film semiconductor device for output signal pass gate is connected to the common output line,
The drain region of the MIS type thin film semiconductor device for output signal pass gate is connected to the output line,
8. The capacitance detection device according to claim 7, wherein the gate electrode of the MIS type thin film semiconductor device for output signal pass gate is connected to a column line.

The output line and the column line are wired by a first wiring, the power supply line and the common output line are wired by a second wiring, and the first wiring and the second wiring are different via an insulating film. 10. The capacitance detection device according to claim 8, wherein the capacitance detection device is formed on a layer.

The capacitance detection electrode is wired by a third wiring, and the first wiring, the second wiring, and the third wiring are formed on different layers through an insulating film. 10. The capacitance detection device according to 10.

12. The capacitance detection device according to claim 11, wherein the third wiring is located on the most surface side among the wires of the capacitance detection device.