JP4517387B2 - Display drive device, display device, and drive control method thereof - Google Patents

Description

  The present invention relates to a display drive device, a display device, and a drive control method thereof, and in particular, a display pixel including a current control type light emitting element that emits light at a predetermined luminance gradation by supplying a current according to display data. The present invention relates to a display drive device applicable to a display panel having a plurality of arrangements, the display device, and a drive control method in the display device.

  Conventionally, a current that emits light at a predetermined luminance gradation in accordance with a current value of a supplied drive current, such as an organic electroluminescence element (hereinafter abbreviated as “organic EL element”) or a light emitting diode (LED). 2. Description of the Related Art A light emitting element type display (display device) including a display panel in which display pixels each having a control type light emitting element are two-dimensionally arranged is known.

  In particular, a light-emitting element type display using an active matrix driving method has a higher display response speed and no viewing angle dependency compared to a liquid crystal display (LCD) which has been widely used in recent years. And display image quality, low power consumption, etc., and because it is composed of light emitting element type display pixels, it does not require a backlight as in the case of a liquid crystal display device. It is extremely advantageous in that it can be made thinner and lighter, and research and development are actively conducted as a next-generation display.

FIG. 11 is a schematic diagram illustrating a configuration example of a main part of a light emitting element type display according to the conventional technique, and FIG. 12 is an equivalent circuit diagram illustrating a configuration example of display pixels applied to the light emitting element type display according to the conventional technique. .
As shown in FIG. 11, the light emitting element display according to the prior art is roughly described in the vicinity of each intersection of a plurality of scanning lines SL and a plurality of data lines DL arranged so as to be orthogonal to each other. A display panel 110P in which a plurality of display pixels EM each provided with a light emission driving circuit (pixel driving circuit) and a current control type light emitting element (organic EL element) are arranged in a matrix (n rows × m columns), and the display panel A scanning driver 120P that is connected to the scanning line SL of 110P and sequentially applies the scanning signal Vsel to each scanning line SL at a predetermined timing to set (scan) the display pixels EM for each row; and a display panel 110P is connected to the data line DL, and the display data is taken in, and the gradation current (level) corresponding to the display data is input to each data line DL at a predetermined timing. It has a structure in which and a data driver 130P which supplies a signal) IPpix.

  In such a display, for example, the operation state of the scan driver 120P and the data driver 130P is controlled by a scan control signal and a data control signal generated based on a timing signal supplied from the outside, and the scan signal is applied. By writing a gradation current corresponding to the display data to the display pixels in each row set in the selected state, each display pixel emits light with a predetermined luminance gradation, and desired image information is displayed.

  In such a light emitting element type display, various drive control mechanisms and control methods for controlling light emission of the above-described current control type light emitting element have been proposed. For example, as described in Patent Document 1 and the like, for each display pixel constituting the display panel, in addition to the light-emitting element, a drive circuit including a plurality of switching means for controlling light emission of the light-emitting element ( Hereinafter, a device provided with a “light emission drive circuit” for convenience is known.

  Specifically, as shown in FIG. 12, the display pixels described in Patent Document 1 and the like are in the vicinity of intersections between a pair of scanning lines SL1 and SL2 and a data line DL arranged in parallel to each other. The thin film transistor Tr111 has a gate terminal connected to the scan line SL1, a source terminal and a drain terminal connected to the data line DL and the contact N111, a gate terminal connected to the scan line SL2, a source terminal and a drain terminal connected to the contact N111 and a contact N112, respectively. The thin film transistor Tr112 connected to each other, the gate terminal connected to the contact N112, the drain terminal connected to the contact N111, the thin film transistor Tr113 applied with the high power supply voltage Vdd to the source terminal, the gate terminal connected to the contact N112, the source Thin film transistor Tr114 having a high power supply voltage Vdd applied to its terminal And an organic EL element OEL in which the anode terminal is connected to the drain terminal of the thin film transistor Tr114 of the lower pixel drive circuit DP1 and the ground potential is applied to the cathode terminal. Yes.

Here, in FIG. 12, the thin film transistor Tr111 is composed of an n-channel field effect transistor, and the thin film transistors Tr112 to Tr114 are composed of p-channel field effect transistors. CP1 is a parasitic capacitance formed between the gate and source of the thin film transistors Tr113 and Tr114.
In the light emission driving circuit DP2 having such a configuration, the four transistors (switching means) composed of the thin film transistors Tr111 to Tr114 are controlled to be turned on and off at a predetermined timing, so that an organic EL can be obtained as shown below. The element OEL is controlled to emit light.

  That is, in the light emission drive circuit DP1, a high-level scanning signal Vsel1 is applied to the scanning line SL1 and a low-level scanning signal Vsel2 is applied to the scanning line SL2 by a scanning driver (not shown) to set the display pixel in a selected state. Then, the thin film transistors Tr111, Tr112, and Tr113 are turned on, and the gradation current Ipix that is supplied to the data line DL by the data driver (not shown) and flows according to the display data flows through the thin film transistors Tr113 and Tr111. At this time, since the gate and drain of Tr113 are electrically short-circuited by Tr112, Tr113 operates in the saturation region. As a result, the current level of the gradation current Ipix is converted to a voltage level by the thin film transistor Tr113, and a predetermined voltage is generated between the gate and the source (writing operation). The thin film transistor Tr114 is turned on according to the voltage generated between the gate and source of the thin film transistor Tr113, and a predetermined light emission drive current flows from the high power supply voltage Vdd to the ground potential via the thin film transistor Tr114 and the organic EL element OEL. The EL element OEL emits light (light emission operation).

  Next, for example, when a high level scanning signal Vsel2 is applied to the scanning line SL2, the thin film transistor Tr112 is turned off, whereby the voltage generated between the gate and the source of the thin film transistor Tr113 is held by the parasitic capacitance CP1, and then the scanning is performed. When the low level scanning signal Vsel1 is applied to the line SL1, the thin film transistor Tr111 is turned off, thereby electrically disconnecting the data line DL and the pixel driving circuit DP1. Thereby, the thin film transistor Tr114 is continuously turned on by the potential difference based on the voltage held in the parasitic capacitance CP1, and a predetermined light emission drive current is supplied from the high power supply voltage Vdd to the ground potential via the thin film transistor Tr114 and the organic EL element OEL. The organic EL element OEL continues to emit light.

Here, the light emission drive current supplied to the organic EL element OEL via the thin film transistor Tr114 is controlled to have a current value based on the luminance gradation of the display data, and this light emission operation is performed according to the next display data. Until the gradation current is written to each display pixel, for example, control is performed so as to continue for one frame period.
The drive control method in the pixel drive circuit having such a circuit configuration supplies each display pixel (the gate terminal of the thin film transistor Tr113) with a gradation current designating a current value corresponding to display data, and according to the current value. Based on the held voltage, the light emission driving current that flows through the organic EL element OEL is controlled to perform the light emission operation at a predetermined luminance gradation, so it is called a current designation method (or current application method). Yes.

  Although not shown, similar to FIG. 12, a gradation signal voltage designating a voltage value corresponding to display data is applied to a display pixel including a pixel driving circuit and an organic EL element, There is also known a voltage control method (or voltage application method) drive control method in which a light emission drive current passed through the organic EL element OEL is controlled in accordance with a voltage value to cause a light emission operation at a predetermined luminance gradation.

  Here, in the light emission drive circuit adopting the voltage designation method, the element characteristics (channel resistance of the thin film transistor, etc.) of the switch element responsible for the selection function and the light emission drive function are affected by the external environment (ambient temperature, etc.), usage time, etc. When the variation or fluctuation (deterioration) occurs depending on the light emission, the light emission drive current is affected, and the desired light emission characteristic (display with a predetermined luminance gradation) is stably realized over a long period of time. In other words, if each display pixel is miniaturized in order to increase the definition of the display panel, the operating characteristics of the switch elements (such as the current between the source and drain of the thin film transistor) vary. Therefore, there is a problem that appropriate gradation control cannot be performed, and the light emission characteristics of each display pixel vary, resulting in deterioration of display image quality.

  On the other hand, in the above-described current designating light emission driving circuit, the thin film transistor Tr113 (current / voltage conversion transistor) that converts the current level of the grayscale current corresponding to the display data supplied to each display pixel into a voltage level. ) And a thin film transistor Tr114 (light emission drive transistor) for supplying a drive current of a predetermined current value to the organic EL element OEL, and by setting the current value of the light emission drive current supplied to the organic EL element OEL, each thin film transistor Tr113 Since the influence of variation in the operating characteristics of Tr 114 can be suppressed, there is an advantage that the problem of the light emission drive circuit of the voltage designation system can be solved.

JP 2001-147659 A (pages 7 to 8, FIG. 1)

However, the light emission drive circuit adopting the current designating method as described above has the following problems.
That is, when the gradation current based on the display data with the lowest or relatively low luminance is written to each display pixel (at the time of low gradation display), a signal current having a small current value corresponding to the luminance gradation of the display data is displayed for each display. It is necessary to supply the pixel.

  Here, the operation of writing display data (gradation current) to each display pixel is equivalent to charging a capacitance component parasitic in the data line (a wiring capacitor and a storage capacitor constituting the display pixel) to a predetermined voltage. For example, when the wiring length of the data line is increased due to an increase in the size of the display panel and the number of display pixels connected to the data line is increased, the current value of the grayscale current becomes smaller (that is, The lower the gray scale display), the longer the charging time of the data line, the longer the writing operation to the display pixel takes place, and the writing to the display pixel is performed at a preset (default) writing time. Display data does not reach a sufficiently stable state (saturated state), so-called insufficient writing occurs. As a result, a display pixel that cannot emit light with an appropriate luminance gradation according to display data is generated, and there is a problem in that a luminance difference occurs in the display panel, resulting in deterioration of display image quality.

  Even when the number of scanning lines arranged on the display panel is increased and the selection period (that is, writing time) of each scanning line is set short in order to increase the definition of the display panel, As the current value of the adjustment current becomes smaller, the sufficient writing operation to each display pixel is not performed, and insufficient writing occurs, leading to deterioration of display image quality, and high definition of the display panel is restricted. Had a problem.

  Therefore, in view of the above-described problems, the present invention provides a display in which display data (gradation current) is written to a display pixel in a display that controls light emission of a light emitting element provided in the display pixel by a current designation method. An object of the present invention is to provide a display drive device, a display device, and a drive control method thereof that can suppress deterioration of display image quality due to insufficient insertion and can cope with a large screen and high definition of a display panel. And

According to a first aspect of the present invention, there is provided a display driving device for driving each display pixel by supplying gradation currents based on display data to a plurality of display pixels arranged in a two-dimensional array constituting a display panel. Pixel selection means for sequentially setting each of the display pixels in a predetermined plurality of adjacent rows of the display panel to a selected state sequentially at a predetermined timing having a non-overlapping period and a non-overlapping period; and Corresponding to current generating means for generating a signal current having a predetermined current value for controlling the luminance gradation of each display pixel based on display data, and the display pixels in the predetermined plurality of adjacent rows of the display panel And sequentially generating the gradation current based on the signal current, and setting the gradation current to the selected state corresponding to the predetermined timing. A period that overlaps the non-overlapping period via a plurality of data lines corresponding to each of the display pixels of the adjacent plurality of rows of the display panel on each of the display pixels of the predetermined plurality of rows. A current writing means that sequentially supplies the current writing means, and the current writing means comprises a plurality of current holding circuits that output the gradation current to the plurality of data lines at the predetermined timing, Each of the current holding circuits includes a signal holding unit that holds the signal current corresponding to the display pixels in each column of the plurality of adjacent rows of the display panel, and the signal current is supplied to the signal holding unit. A signal distribution unit that distributes, and a current corresponding to the signal current held in the signal holding unit is generated as the gradation current, and the gradation current is set over the period set in the selected state. Each of the predetermined plurality of lines A gradation current output unit that outputs the示画element comprises a plurality of current holding-output unit with the current holding circuit, by the current holding, the output of one, the one row of the plurality of rows By capturing and holding the signal current corresponding to the display pixel, and simultaneously outputting the gradation current based on the signal current to the data line corresponding to the row, and by any other current holding / output unit An operation of outputting the gradation current based on the signal current corresponding to the display pixel in the row adjacent to the one row to the data line corresponding to the row simultaneously in the overlapping period. execution be characterized by Rukoto.

According to a second aspect of the present invention, in the display driving device according to the first aspect, at least the current writing means is provided independently of a substrate on which the display panel is formed.

According to a third aspect of the present invention, in the display driving device according to the first aspect, the signal holding unit includes a charge accumulation unit that accumulates charges based on the signal current and holds them as voltage components. And
According to a fourth aspect of the present invention, in the display driving device according to any one of the first to third aspects, the gradation current output unit has a current mirror circuit configuration, and the signal supplied from the current generation unit. The gradation current having a current value with a predetermined current ratio is generated with respect to the current, and is output to the display pixels in each row.
According to a fifth aspect of the present invention, in the display driving device according to any one of the first to fourth aspects, at least the current writing unit is configured by using a field effect transistor having the same channel polarity. It is characterized by that.

The invention according to claim 6 is for a plurality of display pixels arranged in the vicinity of each intersection of a plurality of scanning lines arranged in the row direction of the display panel and a plurality of data lines arranged in the column direction. In a display device that displays desired image information on the display panel by driving the display pixels by supplying a grayscale current having a predetermined current value according to display data, at least adjacent to each column The display panel in which a data line group including a plurality of data lines corresponding to the display pixels in a plurality of predetermined rows is disposed, and the plurality of scans corresponding to the predetermined plurality of adjacent rows of the display panel. A scanning signal is sequentially applied to each of the lines at a predetermined timing having a period overlapping with each other, and the display pixels connected to each scanning line overlap each other with a period not overlapping each other. A scan driving circuit that sequentially sets the selected state in a period, and a current that generates a signal current having a predetermined current value for controlling the luminance gradation of each display pixel of the display panel based on the display data Generation means, and sequentially taking in the signal current corresponding to the display pixels of the predetermined plurality of rows of the display panel, generating the gradation current based on the signal current, and converting the gradation current into the selected state A signal drive circuit comprising current writing means for supplying the display pixels of the predetermined plurality of rows set to be provided with the non-overlapping period and the overlapping period, and the signal driving The current writing means of the circuit includes a plurality of current holding circuits that output the gradation current to the data line group of each column of the display panel at the predetermined timing, and each of the current holding circuits includes the display In front of the panel A signal holding unit that holds the signal current corresponding to the display pixels in each column of a predetermined plurality of rows, a signal distribution unit that distributes the signal current to the signal holding unit, and a signal holding unit that holds the signal current A current corresponding to the signal current is generated as the gradation current, and the gradation current is output to each display pixel in the predetermined plurality of rows over a period set in the selected state. A plurality of current holding / output units having a regulated current output unit , wherein the current holding circuit corresponds to the display pixels in one row of the plurality of rows by the one current holding / output unit. Simultaneously capturing and holding current, simultaneously outputting the grayscale current based on the signal current to the data line corresponding to the row, and adjacent to the one row by any other current holding / output unit The display pixel corresponding to the display pixel of the row The operation and for outputting the gradation current based on the signal current to the data line corresponding to the row, characterized that you used simultaneously in a period of the overlap.

According to a seventh aspect of the present invention, in the display device according to the sixth aspect , at least the signal driving circuit is provided independently of a substrate on which the display panel is formed.

According to an eighth aspect of the present invention, in the display device according to any one of the sixth to seventh aspects, the display pixels arranged in the display panel generate a predetermined light emission driving current based on the gradation current. A light-emitting driving circuit; and a current-controlled light-emitting element that emits light at a predetermined luminance gradation based on a current value of the light-emitting driving current supplied from the light-emitting driving circuit.

According to a ninth aspect of the present invention, in the display device according to the eighth aspect of the present invention, at least the light emission drive circuit is configured using field effect transistors having the same channel polarity.
According to a tenth aspect of the present invention, in the display device according to the eighth or ninth aspect , the light emitting element is an organic electroluminescent element.

According to the eleventh aspect of the present invention, in each display pixel of a display panel in which a plurality of display pixels are arranged in the vicinity of intersections of a plurality of scanning lines and data lines arranged in a row direction and a column direction, In the display device driving control method for driving the display pixels by supplying a corresponding gradation current to display desired image information on the display panel, the predetermined plurality of rows adjacent to the display panel Sequentially setting each of the display pixels to a selected state at a predetermined timing having a non-overlapping period and an overlapping period; and a predetermined gradation level for controlling the luminance gradation of each display pixel based on the display data Generating and outputting a signal current having a current value; and outputting the signal current to each of the plurality of display pixels in each column of the plurality of adjacent rows of the display panel. Each of the plurality of rows is sequentially fetched and held corresponding to each display pixel in each column of the plurality of rows, and the gradation current is generated based on the signal current, Corresponding to the predetermined timing, the grayscale current has a period that overlaps the non-overlapping period and the period of the selection state in the display pixels of each row set in the selection state. viewed contains a sequentially supplying step, the Te, the display pixels of the plurality of lines set in the selected state, the gradation current, and sequentially supplies the step has a duration of the overlap, the display panel Capturing and holding the signal current corresponding to the display pixels in one row of the plurality of adjacent rows, and simultaneously supplying the gradation current based on the signal current to the display pixels in the row; The row adjacent to one row And the operation for supplying the gradation current based on the signal current corresponding to示画element in the display pixel corresponding to the line, driving a display device, characterized by used simultaneously in a period of the overlap Control method.

That is, the present invention provides a display device that drives each display pixel by applying a gradation current corresponding to a display signal (display data) to each display pixel and displays desired image information on a display panel. For the display pixels arranged two-dimensionally on the display panel, the scan driver (pixel selection means, scan drive circuit) has a scan line of each row having a period not overlapping each other and a period overlapping each other between adjacent scan lines. By sequentially applying scanning signals at a predetermined timing, display pixels in adjacent rows are simultaneously set to a selected state in an overlapping period, and a current generation circuit provided in a data driver (signal driving circuit) ( The current generation means) generates a signal current corresponding to the display pixel of each row based on the display data, and supplies it from the current generation circuit by the current holding circuit (current writing means). The signal current is distributed and fetched to a plurality of latch units (current holding / output units) corresponding to the display pixels in each row of the display panel, and a gray-scale current based on the signal current is generated to enter the selected state. The display pixels in each row to be set are sequentially supplied with a non-overlapping period and an overlapping period over the period set in the selected state.

Here, at least the data driver (current generation circuit and current holding circuit) may be provided as a driver chip provided independently of a substrate on which a display panel is provided, for example. The degree of freedom in design can be improved in the layout process of each component of the display device.

  In addition, each latch unit in the current holding circuit, for example, supplies at least the signal current sequentially supplied from the current generation circuit and distributed by the signal distribution unit to each of the display pixels in a predetermined plurality of rows adjacent to the display panel. Correspondingly, a grayscale current having a current value of a predetermined current ratio with respect to the signal current is generated by using, for example, a signal holding unit that holds the capacitance component (charge storage unit) and a current mirror circuit configuration, for example. And a grayscale current output unit that outputs the same.

  With such a configuration, the signal current supplied from the current generation circuit is distributed to each latch unit, and the signal current corresponding to the display pixels in one row is captured and held by one latch unit, and at the same time, the signal current The operation of outputting the grayscale current based on the above and the operation of outputting the grayscale current based on the signal current corresponding to the display pixel in the row adjacent to the one row by the other latch unit simultaneously in the overlapping period. A drive control method executed in parallel can be applied.

  That is, a scan signal is sequentially applied to each of a plurality of adjacent (k rows) scan lines from a scan driver so as to overlap (overlap) for a predetermined period, thereby to obtain a plurality of rows (k rows). ) Display pixels are set to the selected state simultaneously in a predetermined period, and the data driver displays the display corresponding to the display pixels in each row in a current holding circuit (latch unit) provided for each column. Since the gray scale current can be supplied to the display pixels in each row at the same time as the data is distributed and individually captured, it can be simultaneously and simultaneously via each of the plurality of data lines constituting the data line group of each column. In particular, the gradation current based on the display data can be written to the display pixels in a plurality of rows, and the writing time of the gradation current can be set to be substantially multiple times (k times) longer. Can .

  Further, the number of display pixels connected to each data line constituting the data line group of each column is reduced (one per column) according to the number of rows (k) set in the selected state in parallel. Can be reduced to 1 / k compared to a conventional display device provided with the data line, so that the capacitance component (parasitic capacitance) parasitic on each data line can be greatly reduced. The delay time (time required for charging the data line) generated when the gradation current is supplied to the data line (display pixel) (when the display data is written) can be greatly reduced.

  Therefore, it is possible to ensure a sufficiently long writing time of display data to each display pixel, and to significantly reduce the parasitic capacitance of each data line and to suppress signal delay at the time of writing gradation current. Therefore, even when the display panel is enlarged or high-definition, or at the time of low gradation display, the parasitic capacitance of the data line is quickly charged sufficiently to a predetermined voltage and displayed. Insufficient data writing can be solved, and each display pixel is allowed to emit light at an appropriate luminance gradation according to the display data, greatly reducing the luminance gradient (display unevenness) that occurs in the display panel. The display image quality can be improved.

Hereinafter, a display device and a drive control method thereof according to the present invention will be described in detail with reference to embodiments.
<Display device>
First, a schematic configuration of a display device to which the display driving device according to the present invention can be applied will be described.
FIG. 1 is a schematic block diagram showing an overall configuration of a display device according to the present invention, and FIG. 2 is a schematic configuration diagram showing an example of a main configuration of the display device according to the present invention.

  As shown in FIGS. 1 and 2, the display device 100 according to the present embodiment is broadly divided into scan lines SLi (i is 1 ≦ i) arranged corresponding to each pixel row (each row). ≦ n is a positive integer; n is a positive integer, and is arranged corresponding to the total number of pixel rows set in the display panel 110 and each column (each column). , A plurality (two in FIG. 2) of data lines DLja and DLjb (j is a positive integer in the range of 1 ≦ j ≦ m; m is a positive integer and is a pixel column set in the display panel 110. Display pixels EM connected via selection transistors Trsel to each intersection with a data line group DGj (data line DLja or DLjb) having a set of (total number of pixels) as a set, a plurality of two-dimensional arrays (n rows × m columns). Connected to the scanning line SLi of the display panel 110 and the display panel 110, A scanning driver (pixel selection means, scanning) that sequentially sets the display pixels EM of each row (one row) connected to the scanning line SLi to a selected state by sequentially applying the scanning signal Vsel to the inspection line SLi at a predetermined timing. Drive circuit) 120 and each data line group DGj, and display data supplied from a display signal generation unit 150, which will be described later, is captured for each display pixel in each row, and a gradation current Ipix is generated at a predetermined timing. Supplied from a data driver (current generating means, current writing means, signal driving circuit) 130 that outputs sequentially (alternately) to the data lines DLja and DLjb corresponding to each column of each row, for example, from the display signal generating unit 150 Based on the timing signal, at least the scanning control signal and the data control for controlling the operating state of the scanning driver 120 and the data driver 130. Based on a system controller 140 that generates and outputs a control signal and, for example, a video signal supplied from the outside of the display device 100, display data (for example, digital data) is generated and supplied to the data driver 130. A display signal generation unit 150 that generates or extracts a timing signal (system clock or the like) for displaying the display data on the display panel 110 and supplies the timing signal to the system controller 140 is configured.

  In the display device according to the present embodiment, in particular, as shown in FIG. 2, the data driver 130 determines the luminance gradation value based on the display data based on the display data supplied from the display signal generation unit 150. Are individually connected to a current generation circuit (current generation means) CGN for generating a signal current Id having a current value corresponding to the data line group DGj of each column disposed in the display panel 110, and the data line group DGj The data lines DLja and DLjb constituting the current line are provided with a current holding unit CHL composed of a plurality of current holding circuits (current writing means) 136 that outputs the gradation current Ipix based on the signal current Id at a predetermined timing. It has a configuration.

  In the display device according to the present embodiment, the data driver 130 including the current generation circuit CGN and the current holding unit CHL is independent of the substrate BASE on which the display panel (pixel array) 110 is formed. It has the form of a triba chip. The circuit configuration of each display pixel EM and data driver (particularly the current holding unit CHL) will be described in detail later.

Hereafter, each said structure is demonstrated concretely.
(Display panel 110)
For example, as shown in FIG. 2, the display panel 110 applicable to the display device according to the present embodiment includes a scanning line SLi corresponding to each pixel row and two data lines DLja and DLjb. A data line group DGj corresponding to one pixel column is arranged so as to be orthogonal to each other, and in each of the odd-numbered scan lines SLi, at each intersection with the data line DLja in each column, The even-numbered scanning line SLi has a configuration in which a display pixel EM is connected to each intersection with the data line DLjb in each column.

  Here, in the configuration shown in FIG. 2, the configuration in which two data lines DLja and DLjb are combined as a data line group DGj arranged in each column is shown. However, the present invention is not limited to this. Instead of this, a set of two or more data lines may be used. In this case, for example, when the number of data lines constituting the data line group DGj is q (that is, q data lines DLj1 to DLjq), the line number is divided by q and the remainder is 1. The scanning lines (1, q + 1, 2q + 1,... Scanning lines in the rows) are the scanning lines in which the display pixels EM are connected to the intersections with the first data line DLj1 in each column and the remainder is 2. The line (2, q + 2, 2q + 2,... Scanning line in the row) is connected to the display pixel EM at each intersection with the second data line DLj2 in each column (hereinafter, the display pixel and the data have the same relationship). And the scanning line of the row where the remainder is zero (q, 2q, 3q,... Scanning line of the row) is connected to the qth (last) data line DLjq of each column. A structure in which a display pixel EM is connected to each intersection. Have a success.

  Each display pixel EM generally has a configuration in which a gate terminal is connected to each scanning line SLi and a source terminal is connected to a drain terminal of a selection transistor Trsel connected to each data line DLja or DLjb. Based on the gradation current Ipix supplied from each data line DLja or DLjb and the selection transistor Trsel from the current holding unit CHL (each current holding circuit 136) of the data driver 130, light is emitted at a predetermined luminance gradation. A current-controlled light-emitting element that operates is provided.

  In the display panel 110 having such a configuration, by applying a scanning signal Vsel to a scanning line SLi of a specific row from a scanning driver 120 described later, the selection transistor Trsel connected to the scanning line SLi is turned on. The display pixels EM in the row are set to the selected state all at once. In this selected state, the gradation current Ipix corresponding to the display data is simultaneously supplied from the data driver 130 (current generation circuit CGN and current holding unit CHL), which will be described later, to specific data lines of each data line group DGj. The display data is collectively written to the display pixels EM of the row set to the selected state via the selection transistor Trsel that is turned on. A specific circuit example and circuit operation of the display pixel EM including the selection transistor will be described in detail later.

(Scanning driver 120)
The scan driver 120 sequentially executes an operation of applying a scan signal Vsel of a selection level (for example, high level) to each of the scan lines SLi based on a scan control signal supplied from the system controller 140, thereby performing each scan. The display pixels EM of each row connected to the line SLi are simultaneously set to a selected state, and at least the display pixels EM of adjacent rows are simultaneously set to the selected state for a predetermined period, and a data driver described later The gradation current Ipix based on the display data supplied via each data line group DGj is controlled by 130 so as to be partially written in parallel to the display pixels EM of each row.

  For example, as shown in FIG. 2, the scan driver 120 includes a plurality of stages (FIG. 2) of shift blocks SB1, SB2,... SBi,. N stages), and based on a scanning control signal (scanning start signal SST, scanning clock signal SCK, etc.) supplied from a system controller 140, which will be described later, from above the display panel 110 by a shift register. A shift signal output while sequentially shifting downward is applied to each scan line group SGi as a scan signal Vsel having a predetermined selection level (high level) via a buffer.

  Here, in the present embodiment, in the scan driver having the above-described known configuration, for example, the normal time width (in which the scan clock signal SCK is selected for each row for a predetermined period (one horizontal scan period)) ( The selection time width for each row to which the scanning signal Vsel is applied is set, and the scanning start signal SST is set to the selection time width for two rows (two horizontal scanning periods), thereby having a time width for two rows. The shift signal is shifted between the respective shift blocks SB1, SB2,... SBi,... SBn, and at least for the adjacent scan line SLi, the scan signal Vsel based on the shift signal is a predetermined period. Are applied simultaneously (overlapping for a certain period).

(Data driver 130)
Based on a data control signal supplied from the system controller 140, the data driver 130 sequentially takes in display data supplied from a display signal generation unit 150, which will be described later, for each row at a predetermined timing, and the luminance of the display data A signal current Id having a current value corresponding to the gradation value is generated, and the signal current Id is used as the gradation current Ipix for the display pixels EM in a specific row set to the selected state by the scan driver 120 described above. The display pixels EM are supplied all at once through the data line group DGj of each column.

  Specifically, for example, as illustrated in FIG. 2, the data driver 130 generates a signal current Id corresponding to the luminance gradation value based on at least display data supplied from the display signal generation unit 150. Data provided from a system controller 140, which will be described later, includes a generation circuit CGN and a current holding unit CHL including a plurality of current holding circuits 136 connected to each data line group DGj arranged in the display panel 110. Based on the control signal, the signal current Id generated based on the display data supplied from the display signal generation unit 150 is sequentially captured by the current holding circuit 136 of each column for the display pixels of each row, and each data line. Supplied as a gradation current Ipix at a predetermined timing to the display pixels EM in each row set to the selected state via the group DGj That. The specific configuration and operation of the data driver will be described later in detail.

(System controller 140)
The system controller 140 outputs a scan control signal and a data control signal for controlling the operation state to the scan driver 120 and the data driver 130 described above, thereby causing the drivers 120 and 130 to operate at a predetermined timing for scanning. The signal Vsel and the gradation current Ipix (signal current Id) are generated and output, the display data generated by the display signal generation unit 150 is written into each display pixel EM, and the light emission operation is performed, and predetermined image information based on the video signal is generated. Control to display on the display panel 110 is performed.

(Display signal generator 150)
The display signal generation unit 150 extracts, for example, a luminance gradation signal component (luminance gradation value) from a video signal supplied from the outside of the display device 100, and a data driver as display data for each row of the display panel 110. 130. Here, when the video signal includes a timing signal component that defines the display timing of image information, such as a television broadcast signal (composite video signal), the display signal generation unit 150 displays the luminance gradation signal component. In addition to the function of extracting the timing signal component, the timing signal component may be extracted and supplied to the system controller 140. In this case, the system controller 140 generates a scanning control signal and a data control signal to be supplied to the scanning driver 120 and the data driver 130 based on the timing signal supplied from the display signal generation unit 150.

<Specific examples of data driver>
Next, one configuration example of the data driver applicable to the display device according to the present embodiment will be specifically described.
(Current generation circuit)
FIG. 3 is a block diagram illustrating a configuration example of a current generation circuit applicable to the data driver of the display device according to the present embodiment.

  The current generation circuit CGN applicable to the data driver 130 according to the present embodiment includes, for example, a sampling start signal STR based on a shift clock signal CLK supplied as a data control signal from the system controller 140, as shown in FIG. The shift register circuit 131 that outputs a shift signal while sequentially shifting the display data, and the display data D0 to Dm (digital data) for one row supplied from the display signal generation unit 150 in sequence based on the input timing of the shift signal Based on the data register circuit 132 to be fetched, the data latch circuit 133 holding the display data D0 to Dm for one row fetched by the data register circuit 132 based on the data latch signal STB, and supplied from the power supply means (not shown) On the basis of the gradation reference voltages V0 to Vp A D / A converter 134 that converts the held display data D0 to Dm into a predetermined analog signal voltage (grayscale voltage Vpix) and a signal current Id corresponding to the display data converted into the analog signal voltage are generated. And a voltage / current conversion / current supply circuit 135 that supplies the current holding unit CHL (each current holding circuit 136) all at once based on the output enable signal OE supplied from the system controller 140. ing.

(Current holding part)
FIG. 4 is a circuit configuration diagram showing a configuration example of a current holding unit (current holding circuit) applicable to the data driver of the display device according to the present embodiment. Note that the configuration of the current holding unit illustrated in FIG. 4 is merely a configuration example applicable to the data driver according to the present embodiment, and is not limited to this circuit configuration.

  As shown in FIG. 2, the current holding unit CHL applicable to the data driver 130 according to the present embodiment includes at least a plurality of current holding circuits 136 individually connected to each data line group DGj, and each current holding unit Specifically, as shown in FIG. 4, the circuit 136 is connected to a latch unit (current holding / output unit) 136a connected to the data line DLja constituting each data line group DGj, and to the data line DLjb. And a latch unit (current holding / output unit) 136b.

  For example, as illustrated in FIG. 4, the latch unit 136 a has a signal current Id having a current value corresponding to the luminance gradation value output from the current generation circuit CGN described above on one end side of the current path (source-drain). The other end side is connected to the contact N31a, and the current path is connected between the thin film transistor Tr31a to which the first current capture signal WTodd is applied to the control terminal (gate), and the contact N31a and the contact N32a. The thin film transistor Tr32a to which the first current capture signal WTodd is applied to the terminal, one end of the current path is connected to the contact N31a, the other end is connected to the low potential voltage (−Vcc), and the control terminal is connected to the contact N32a The thin film transistor Tr33a, one end of the current path is connected to the low potential voltage (-Vcc), the other end is connected to the data line DLja, and the control terminal is a contact point A thin film transistor Tr34a connected to 32a, and has a configuration including a storage capacitor Ca connected between the contact point N32a and a low level voltage (-Vcc).

  Similarly to the latch unit 136a, for example, as shown in FIG. 4, the latch unit 136b also supplies the signal current Id output from the current generation circuit CGN to one end side of the current path, and the other end side is a contact N31b. And a current path is connected between the thin film transistor Tr31b to which the second current capture signal WTevn is applied to the control terminal and the contact N31b and the contact N32b, and the second current capture signal WTevn is connected to the control terminal. The thin film transistor Tr32b to be applied, one end side of the current path is connected to the contact N31b, the other end side is connected to the low potential voltage (−Vcc), and the control terminal is connected to the contact N32b, and one end side of the current path is A thin film transistor connected to a low potential voltage (-Vcc), connected to the data line DLjb at the other end, and connected to the contact N32b at the control terminal. And Tr34b, has a configuration provided with a storage capacitor Cb connected between the contact point N32b and the low level voltage (-Vcc).

  Here, in the current holding unit CHL according to the present embodiment, as each of the thin film transistors Tr31a to Tr34a and Tr31b to Tr34b, for example, an n-channel type electric field using an amorphous silicon semiconductor layer or a polysilicon semiconductor layer as a channel layer. An effect transistor can be applied.

  In the current holding circuit 136 described above, the storage capacitors Ca and Cb constitute a signal holding unit and charge storage means according to the present invention, and the thin film transistors Tr31a, Tr32a and Tr31b and Tr32b constitute a signal distribution unit according to the present invention. The thin film transistors Tr33a, Tr34a and Tr33b, Tr34b constitute a gradation current output unit according to the present invention.

<Operation of current holding unit>
Next, the operation in the current holding unit (current holding circuit) having the above-described configuration will be described.
FIG. 5 is a conceptual diagram showing a schematic operation of a current holding unit applicable to the present embodiment.

  The operation in the current holding unit CHL (current holding circuit 136) according to the present embodiment is performed by display data (luminance) corresponding to display pixels of two rows (adjacent odd rows and even rows) sequentially supplied from the current generation circuit CGN. The signal current Id based on the gradation value) is sequentially captured at a predetermined timing by the latch units 136a and 136b connected in parallel for each column, and at the same time, the gradation current Ipix is generated based on the signal current Id. The current latch / output operation for individually outputting the data lines DLja and DLjb constituting the data line group DGj at a predetermined timing, and the output of the gradation current Ipix in the current latch / output operation for a predetermined period The current output holding operation continues, and the current latch / output operation and the current output holding operation are alternately repeated between the latch unit 136a side and the 136b side. It is controlled to return. Thereby, the output periods of the gradation currents Ipix from the respective latch units 136a and 136b in the current latch / output operation are set so as to partially overlap (overlap) each other.

Hereinafter, each operation will be specifically described with reference to the configuration of the above-described current holding unit (current holding circuit).
In the current holding circuit 136 (latch unit 136a, 136b) provided for each column described above, the first and second current capture signals WTodd, WTevn supplied as data control signals from the system controller 140 are selectively selected. By setting the high level, either one of the latch units 136a and 136b connected in parallel (the latch unit 136a or 136b) captures the signal current Id and simultaneously the signal current Id. Is set to a current latch / output operation state that outputs a gray-scale current Ipix corresponding to, and the other side latch unit (latch unit 136b or 136a) is in the current latch / output operation state at the previous timing. The current output holding operation state in which the output state is continued is set.

(Current latch / output operation)
Specifically, in the current latch / output operation, as shown in FIG. 5A, the first current capture signal WTodd is set to the high level and the second current capture signal WTevn is set to the low level. By setting the level, in the latch unit 136a, the thin film transistors Tr31a and Tr32a are turned on, and the thin film transistor Tr33a is electrically turned on when the thin film transistor Tr32a is turned on, and is turned on in the saturation region. To do. Thereby, the signal current Ida supplied from the current generation circuit CGN flows to the low potential voltage (−Vcc) side through the thin film transistors Tr31a and Tr33a of the latch unit 136a, and the current level of the signal current Ida is the gate of the thin film transistor Tr33a. -It is converted into a voltage level between the sources and is stored as a charge in the storage capacitor Ca.

  At this time, as the electric charge is accumulated in the storage capacitor Ca, the potential of the contact N32a rises, so that the thin film transistors Tr33a and Tr34a constituting the current mirror circuit are turned on, and the current Ida is reduced with respect to the signal current Ida. The gradation current Ipix having a predetermined current ratio set in the mirror circuit is supplied from the data line DLja side through the thin film transistor Tr34a to the low potential voltage (−Vcc) direction (that is, from the display pixel EM side to the latch unit 136a). It flows to be drawn.

(Current output holding operation)
In the current output holding operation, as shown in FIG. 5B, the first current capture signal WTodd is set to a low level and the second current capture signal WTevn is set to a high level. Thus, the thin film transistors Tr31a and Tr32a are turned off in the above-described latch portion 136a. At this time, since the potential (high voltage) based on the electric charge (signal current Ida) accumulated in the storage capacitor Ca by the current latch / output operation is held at the contact N32a, the thin film transistor Tr34a continues to be on. As a result, the operation state in which the gradation current Ipix is drawn from the data line DLja side toward the latch unit 136a (current holding circuit 136) is held.

  Further, the first current capture signal WTodd is set to the low level and the second current capture signal WTevn is set to the high level (that is, the current output holding operation state of the latch unit 136a described above). In the latch portion 136b connected in parallel to the latch portion 136a, the thin film transistors Tr31b and Tr32b are turned on, and the gate and drain are electrically short-circuited by the Tr32b and the Tr33b is turned on in the saturation region. The signal current Idb flows to the low potential voltage (−Vcc) side through the thin film transistors Tr31b and Tr33b of the latch portion 136b, and the current level of the signal current Idb is converted into the voltage level between the gate and the source of the thin film transistor Tr33b. , Accumulated as charge in the storage capacitor Cb, and the potential of the contact N32b Along with the rise, the thin film transistors Tr33b and Tr34b constituting the current mirror circuit are turned on, and the gradation current Ipix having a predetermined current ratio with respect to the signal current Idb is passed from the data line DLjb side through the thin film transistor Tr34b. A current latch / output operation that flows so as to be drawn in the low potential voltage (−Vcc) direction (that is, in the direction of the latch unit 136b from the display pixel EM side) is performed.

That is, during the period when either one of the latch units 136a and 136b is set to the current latch / output operation state, the other side is set to the current output holding operation state simultaneously.
In the current holding unit CHL according to the present embodiment, a positive signal current Id (Ida) supplied from the current generation circuit CGN is provided so as to correspond to a circuit configuration of a pixel driving circuit provided in the display pixel EM described later. , Idb), a case has been described in which a negative gradation current Ipix is generated and the gradation current Ipix is drawn from the data line (display pixel EM) side, depending on the circuit configuration of the display pixel EM, It may have a configuration in which a positive gradation current Ipix is generated and fed into a data line (display pixel EM).

<Display device drive control method>
Next, a drive control operation in the display device having the above-described configuration will be described.
FIG. 6 is a timing chart showing the drive control method of the display device according to the present embodiment.

  In the display device having the above-described configuration, first, the display data extracted by the display signal generation unit 150 is sent to the current generation circuit CGN of the data driver 130 at a timing based on the data control signal supplied from the system controller 140. Are sequentially captured for each row of the display panel 110, converted into a signal current Id corresponding to the display data, and applied to a current holding unit CHL provided with a current holding circuit 136 corresponding to the data line group DGj of each column. Is output.

  In the current holding unit CHL, as shown in FIG. 6, data control signals (a high level first current capture signal WTodd and a low level second current capture signal WTevn) supplied from the system controller 140. ), The latch unit 136a of the current holding circuit 136 provided in each column is set to the current latch / output operation state, whereby the display pixels EM in a specific odd-numbered row (for example, the first row) are set. The signal current Id (Ida) corresponding to the above is taken in and the charge based on the signal current Ida is stored in the storage capacitor Ca, and at the same time, the charge stored in the storage capacitor Ca and the current mirror circuit (thin film transistors Tr33a and Tr34a). Based on the set current ratio, a gradation current Ipix having a predetermined current value is generated, and the corresponding row is passed through each data line DLja. Current latch output operation to be supplied to each of the display pixels EM in the first row) is performed.

  Subsequently, after the current latch / output operation, based on the data control signals (the low-level first current capture signal WTodd and the high-level second current capture signal WTevn) supplied from the system controller 140. Thus, when the latch unit 136a of the current holding circuit 136 is set to the current output holding operation state, the gradation current Ipix based on the electric charge (that is, the signal current Ida) stored in the storage capacitor Ca in the latch unit 136a. However, a current output holding operation that is continuously supplied to each display pixel EM in the row (first row) is performed via each data line DLja.

  Further, in the period in which the current output holding operation is performed in the latch unit 136a, as shown in FIG. 6, the data control signal (the low-level first current capture signal WTodd, The latch circuit 136b of the current holding circuit 136 is set to the current latch / output operation state based on the high-level second current capture signal WTevn), and is supplied from the current generation circuit CGN. When the signal current Id (Idb) of the next even-numbered row (for example, the second row) adjacent to a specific odd-numbered row is taken into the latch unit 136b and electric charge is accumulated in the storage capacitor Cb. At the same time, based on the charge stored in the storage capacitor Cb and the current ratio set by the current mirror circuit (thin film transistors Tr33b, Tr34b). It generates the gradation current Ipix that has a predetermined current value, via the respective data lines DLjb, supplied to each of the display pixels EM in the row (second row) current latch output operation is performed.

  Next, after the current output holding operation in the latch unit 136a, the system controller 140 sets the first current capture signal WTodd again to the high level and the second current capture signal WTevn to the low level again. As a result, the latch unit 136a is again set to the current latch / output operation state, so that charges based on the signal current Id (Ida) of the next odd-numbered row (for example, the third row) are stored in the storage capacitor Ca. At the same time as the accumulation, the charge accumulated in the storage capacitor Ca and the gradation current Ipix based on the current ratio set by the current mirror circuit pass through each data line DLja in the row (third row). The current latch / output operation supplied to each display pixel EM is executed.

  At this time, since the latch unit 136b of the current holding circuit 136 is set to the current output holding operation state, the gradation current Ipix based on the charge stored in the storage capacitor Cb at the previous timing is changed to each data line. The current output holding operation that is continuously supplied to each display pixel EM in the row (second row) that is the target of the current latch / output operation is performed via DLjb.

  Thereby, in the current holding unit CHL, the current latch / output operation and the current output holding operation are simultaneously performed between the two-stage latch units 136a and 136b constituting each current holding circuit 136 provided corresponding to each column. By alternately repeating the control executed in parallel for each predetermined operation cycle, the signal current Id corresponding to the display data (luminance gradation value) of each row sequentially supplied from the current generation circuit CGN is continuously generated. At the same time as being fetched and held in the holding circuit 136, an operation of simultaneously supplying the gradation current Ipix to the display pixels in each row is executed.

  Therefore, as shown in FIG. 6, the gradation current Ipix is output from the current holding unit CHL (each current holding circuit 136) via the data line group DGj of each column, and the scan control signal supplied from the system controller 140 is output. The scanning driver 120 applies a high-level scanning signal Vsel at a timing based on the scanning lines SLi and SLi + 1 so as to overlap at least for a predetermined period (for example, one horizontal scanning period) (each row). The scanning signal Vsel of each of the above data is displayed on the display pixels EM in a plurality of rows (for example, two rows of the first row and the second row) corresponding to each scanning line SLi by performing two horizontal scanning periods. The gradation current Ipix sequentially supplied through the data lines DLja and DLjb of the line group DGj is written, and the light emission operation is performed at a predetermined luminance gradation based on the gradation current Ipix. Is executed.

  Thus, in the present embodiment, a plurality of adjacent rows (k rows; k is a positive integer equal to or greater than 2) from the scan driver to the display panel in which a plurality of display pixels are two-dimensionally arranged. In this case, a scanning signal is applied to a scanning line of 2 rows) so as to overlap for a predetermined period, so that display pixels for a plurality of rows (k rows) are simultaneously selected in parallel for a certain period. The display data corresponding to the display pixels in each row is captured and held in a current holding circuit in which a plurality of (k) latch portions are provided in parallel for each column by the data driver, and at the same time Since the display pixel is configured to supply gradation current to each of the display pixels, a plurality of rows of display pixels are provided with a configuration including latch units corresponding to the number of data lines (k) constituting the data line group of each column. Display data Gradation currents based concurrently that can be written, the writing time of the gradation current to substantially a multiple (k times), can be set longer.

  Specifically, as described above, the data line group arranged in each column is composed of two data lines, and two latch units are provided in the current holding unit corresponding to the data lines. In this case, by setting the half of the selection period of the display pixels in a specific row by the scanning signal so as to overlap with the selection period of the display pixels in the next row, for example, the i-th row ( i + 1) When the period in which the selection periods set in the display pixels in the row overlap each other is set to the normal one horizontal scanning period (1H), the selection period becomes twice the normal period, and the data driver (current holding unit) Can be written in each display pixel in twice the writing time.

  Further, the number of display pixels connected to each data line constituting the data line group of each column is 1 / k compared with a conventional display device in which one data line is provided in one column ( In this embodiment, the capacitance component (parasitic capacitance) parasitic to each data line can be greatly reduced by 1/2), and the gradation current is supplied to the data line (display pixel) ( The delay time (time required for charging the data line) generated when the display data is written can be greatly reduced.

Therefore, the writing time of display data to each display pixel can be secured sufficiently long and the parasitic capacitance of each data line can be greatly reduced. Or even when low gradation display, it is possible to quickly charge the parasitic capacitance of the data line sufficiently to a predetermined voltage, and to solve the shortage of writing display data. Can be caused to emit light at an appropriate luminance gradation in accordance with display data, and the luminance gradient (display unevenness) generated in the display panel can be greatly reduced to improve the display image quality.
In addition, the data driver including the current generation circuit and the current holding unit can be provided, for example, in the form of a driver chip independently of the substrate on which the display panel is formed. The degree of freedom in design can be improved.

  In the present embodiment, as described above, the display data corresponding to the display pixels in each row is captured and held in the latch unit by the data driver, and at the same time, the gradation currents in each row are generated and sequentially applied to the display pixels. Since it is configured to supply, it is necessary to quickly execute the latch operation in the current holding circuit (latch unit), and if the latch operation timing is shifted due to a signal delay or the like, the display operation is hindered. May come.

  Therefore, in this embodiment, the display data (signal current corresponding to the luminance gradation value) in the current holding circuit (latch unit) is latched quickly with a small current, and output to each data line. By applying the current mirror circuit configuration to the stage, the delay value of the latch operation can be suppressed by easily controlling the current value (absolute value) of the gradation current to increase the current.

<Specific circuit example of display pixel>
Next, specific circuit examples of display pixels applicable to the display device according to the present invention will be described with reference to the drawings.
FIG. 7 is a circuit configuration diagram showing a specific example of display pixels (pixel driving circuit, light emitting element) applicable to the display device according to the present invention.

  The display pixel EM applied to the display panel according to the present embodiment (strictly, the configuration including the display pixel EM and the selection transistor Trsel described above) is schematically illustrated in FIG. The display pixel EM is set to a selected state on the basis of the scanning signal Vsel applied from, and the gradation current Ipix supplied from the data driver 130 (current holding unit CHL) is captured in the selected state. A pixel driving circuit (including the above-described selection transistor Trsel; a light emitting driving circuit) DC that supplies a light emitting driving current in accordance with the light emitting element, and a predetermined luminance scale based on the light emitting driving current supplied from the pixel driving circuit DC. And a current-controlled light emitting element such as an organic EL element OEL that emits light in a tuned manner.

  Specifically, as shown in FIG. 7, in the pixel drive circuit DC, for example, a control terminal (gate terminal) is connected to the scanning line SLi, and a current path (source-drain) is connected to the power supply line VL and the contact N11. The n-channel thin film transistor Tr11, the control terminal to the scanning line SLi, the current path to the data line DLj (the data lines DLja and DLjb constituting the data line group DGj shown in the above-described embodiments) and the contact N12 Each connected n-channel type thin film transistor Tr12 is connected between the contact N11 and the contact N12, the control terminal is connected to the contact N11, and the current path is connected to the power line VL and the contact N12, respectively. A capacitor (holding capacity) Cs, and an anode end of the organic EL element OEL The child is connected to the contact N12, and the cathode terminal is connected to the ground potential. Here, the capacitor Cs may be a parasitic capacitance formed between the gate and the source of the thin film transistor Tr13. The thin film transistor Tr12 corresponds to the selection transistor Trsel shown in the above embodiment.

<Light emission drive control method of display pixel>
FIG. 8 is a conceptual diagram showing a drive control operation in the display pixel (pixel drive circuit) according to this configuration example, and FIG. 9 shows the drive control operation in the display device when the display pixel according to this configuration example is applied. It is a timing chart which shows. FIG. 10 is a schematic block diagram illustrating a configuration example of a display device to which the display pixel according to this configuration example is applied.

  For example, as shown in FIG. 9, the light emission drive control of the light emitting element (organic EL element OEL) in the pixel drive circuit DC having the above-described configuration is performed within one scan period Tsc with one scan period Tsc as one cycle. In addition, the display pixel EM connected to the scanning line SLi is selected, the gradation current Ipix based on the display data is written, the selection period (write operation period) Tse for holding as a voltage component, and the selection period Tse are written. Based on the held voltage component, a non-selection period (light emission operation period) Tnse for supplying a light emission drive current corresponding to the display data to the organic EL element OEL and performing a light emission operation at a predetermined luminance gradation is set. (Tsc = Tse + Tnse). Here, as shown in FIG. 9, the selection period set for the display pixels EM in each row is a predetermined period (a period of 1/2 of the selection period) between a plurality of adjacent rows (for example, two rows). ) And are set to overlap (overlap) in time. Hereinafter, for the sake of simplicity, as shown in the above-described embodiment, two data lines DLja and DLjb are provided in each column corresponding to two adjacent rows of display pixels EM (scanning lines SLi). A configuration in which a set of data line groups DGj is arranged will be specifically described.

(Selection period)
As shown in FIG. 9, in the selection period Tse of the display pixel EM, first, the high-level scanning signal Vsel is applied from the scanning driver 120 to the specific scanning line SLi to select the display pixel EM in the row. In the second half of the selection period Tse (a half period of the selection period Tse), the high level scanning signal Vsel is applied to the scanning line SLi + 1 of the next row. Thus, two rows of display pixels composed of odd and even rows adjacent to each other are set in a selected state so as to overlap in time for a predetermined period (a period that is 1/2 of the selection period Tse). In the selection period Tse, the low-level power supply voltage Vsc is applied to the power supply line VL of the display pixel EM in the row in synchronization with the application of the scanning signal Vsel.

  In synchronism with this timing, the data line group DGj of each column is configured on the display pixel EM of the row set to the selected state from the data driver 130 (each current holding circuit 136 of the current holding unit CHL). Via one of the data lines DLja, DLjb (via the data line DLja for the odd-numbered display pixels EM and via the data line DLjb for the even-numbered display pixels EM) The gradation current Ipix (negative polarity) based on the display data is supplied. Here, in a period in which two adjacent rows of display pixels are simultaneously set to the selected state, the display data of the display pixels EM in each row corresponds to the display data via the two data lines DLja and DLjb of the data line group DGj. The individual gradation currents Ipix are simultaneously supplied.

  As a result, as shown in FIG. 8A, the thin film transistors Tr11 and Tr12 constituting the pixel drive circuit DC are turned on, and the low-level power supply voltage Vsc becomes the contact N11 (that is, the gate terminal of the thin film transistor Tr13 and the capacitor Cs). Is applied to one end of the power source voltage), and the gradation current Ipix is drawn in the direction of the data driver 130 (current holding unit CHL) via the data line DLja or DLjb, thereby lowering the power supply voltage Vsc at a low level. The voltage level of the potential is applied to the contact N12 (that is, the source terminal of the thin film transistor Tr13 and the other end of the capacitor Cs).

  As described above, when the potential difference is generated between the contacts N11 and N12 (between the gate and the source of the thin film transistor Tr13), the thin film transistor Tr13 is turned on, and the thin film transistor Tr13, the contact N12, the thin film transistor Tr12, the data line DLja or the power line VL A write current Ia corresponding to the gradation current Ipix flows through the DLjb in the direction of the current holding unit CHL.

  At this time, a charge corresponding to a potential difference generated between the contacts N11 and N12 (between the gate and the source of the thin film transistor Tr13) is accumulated in the capacitor Cs and held (charged) as a voltage component. Further, the power supply line VL is applied with a power supply voltage Vsc having a voltage level equal to or lower than the ground potential, and the write current Ia is controlled to flow in the direction of the data line DL, so that the organic EL element OEL Since the potential applied to the anode terminal (contact N12) is lower than the potential of the cathode terminal (ground potential) and a reverse bias voltage is applied to the organic EL element OEL, the organic EL element OEL emits light. No drive current flows and no light emission operation is performed.

(Non-selection period)
Next, as shown in FIG. 9, in the non-selection period Tnse after the selection period Tse ends, the low-level scan signal Vsel is applied from the scan driver 120 to the specific scan line SLi to display pixels in the row. Is set to a non-selected state, and a high-level power supply voltage Vsc is applied to the power supply line VL of the display pixel in the row. In synchronism with this timing, the grayscale current Ipix drawing operation by the data driver 130 (current holding unit DHL) is stopped. At this time, the scanning signal Vsel at the high level is continuously applied to the scanning line SLi + 1 of the next row, and the selected state is maintained.

  As a result, as shown in FIG. 8B, the thin film transistors Tr11 and Tr12 constituting the pixel drive circuit DC are turned off, and the power supply voltage to the contact N11 (that is, the gate terminal of the thin film transistor Tr13 and one end of the capacitor Cs). While the application of Vsc is cut off, the application of the voltage level due to the drawing operation of the gradation current Ipix by the current holding part CHL to the contact N12 (that is, the source terminal of the thin film transistor Tr13 and the other end of the capacitor Cs) is cut off. Therefore, the capacitor Cs holds the charge accumulated in the selection period Tse described above.

  Thus, the capacitor Cs holds the charging voltage during the writing operation (selection period Tse), whereby the potential difference between the contacts N11 and N12 (between the gate and source of the thin film transistor Tr13) is held. The thin film transistor Tr13 is kept on. Further, since the power supply voltage Vsc having a voltage level higher than the ground potential is applied to the power supply line VL, the potential applied to the anode terminal (contact N12) of the organic EL element OEL is the potential of the cathode terminal (ground potential). ).

  Therefore, a predetermined light emission drive current Ib flows in the forward bias direction from the power supply line VL to the organic EL element OEL via the thin film transistor Tr13 and the contact N12, and the organic EL element OEL emits light. Here, the potential difference (charge voltage) held by the capacitor Cs corresponds to the potential difference when the write current Ia corresponding to the gradation current Ipix is caused to flow in the thin film transistor Tr13. Therefore, the light emission drive current flowing down to the organic EL element OEL. Ib has a current value equivalent to the write current Ia.

  Thereby, in the display pixel EM in a specific row, in the non-selection period Tnse after the selection period Tse, the thin film transistor Tr13 is based on the voltage component corresponding to the display data (gradation current Ipix) written in the selection period Tse. Through this, the light emission drive current is continuously supplied, and the organic EL element OEL continues the operation of emitting light at the luminance gradation corresponding to the display data.

  Then, as shown in FIG. 9, the above-described series of operations is performed for one scanning period SLi for all the scanning lines SLi constituting the display panel 110 based on the drive control operation (see FIG. 6) of the display device described above. The display data for one screen of the display panel is written and sequentially emitted so as to overlap with adjacent rows in time, so that the display data for one display panel is written and emits light at a predetermined luminance gradation. Then, desired image information is displayed.

  Here, in the pixel drive circuit DC according to the present embodiment, since the thin film transistors Tr11 to Tr13 can all be configured using thin film transistors having the same channel polarity (n-channel type), for example, an amorphous silicon semiconductor layer, Alternatively, an n-channel field effect transistor having a polysilicon semiconductor layer as a channel layer can be used. In this case, a field effect transistor with stable operating characteristics is relatively inexpensive by applying an amorphous silicon manufacturing process or a polysilicon manufacturing process that is technically established and has a lower manufacturing cost than the single crystal silicon manufacturing technology. Therefore, even when the display panel is increased in definition or size, a display device excellent in display image quality can be realized simply and inexpensively.

  Further, according to the pixel drive circuit DC having the circuit configuration as described above, the gradation current Ipix having a relatively large current value corresponding to the luminance gradation of the display data is supplied by the data driver 130, and the organic EL element Since the voltage corresponding to the gradation current Ipix can be satisfactorily charged (written) to the capacitor Cs provided between the gate and the source of the light emission control transistor (thin film transistor Tr13) for causing the OEL to emit light, the above-described operation is performed. By the drive control method of the display device, the writing time of the gradation current to the display pixel can be set longer, and the writing speed can be improved to further improve the display response characteristics and the display image quality.

  In the pixel drive circuit DC according to this configuration example, as a configuration for applying a predetermined power supply voltage Vcs to the power supply line VL, for example, as shown in FIG. 10, the power supply line VLi is parallel to the scanning line SLi of each row. As shown in FIG. 9, the display panel 110 is provided with a power supply driver 160 connected to the power supply line VLi in the peripheral region of the display panel 110 and based on the power supply control signal supplied from the system controller 140. In synchronization with the timing at which the scanning signal Vsel is output from the driver 120, the configuration in which the power supply voltage Vcs having the predetermined voltage value is applied to each power supply line VLi from the power supply driver 160 can be favorably applied.

  Note that the display pixel EM described above includes three thin film transistors as the pixel driving circuit DC, and a grayscale current in the direction of the data driver 130 (current holding unit DHL) via the data line group DGj (data lines DLja, DLjb). Although the circuit configuration corresponding to the current designation method of drawing Ipix is shown, the present invention is not limited to this embodiment, and is at least a display device including a pixel driving circuit to which the current designation method is applied. A light emission control transistor that controls the supply of the light emission drive current to the light emitting element and a write control transistor that controls the write operation of the gray scale current. ) Is held, and the light emission control transistor is turned on based on the gradation current to supply a light emission driving current, thereby causing the light emitting element to have a predetermined luminance gradation. As long as it emits light, it may have any other circuit configuration, for example, it may have a circuit configuration including four thin film transistors, and further, a data driver (current holding unit). The circuit configuration may be such that gradation current flows in the direction of the display pixel (pixel drive circuit) through the data line group.

  In the configuration example of the display pixel described above, a configuration in which an organic EL element is applied as the current-controlled light-emitting element is shown. However, the display device according to the present invention is not limited to this, and the supplied light emission. In addition to the organic EL elements described above, for example, light emitting diodes and other light emitting elements can be favorably applied as long as the light emitting elements emit light with a predetermined luminance gradation according to the current value of the drive current.

It is a schematic block diagram which shows the whole structure of the display apparatus which concerns on this invention. It is a schematic block diagram which shows an example of the principal part structure of the display apparatus which concerns on this invention. It is a block diagram which shows the example of 1 structure of the electric current generation circuit applicable to the data driver of the display apparatus which concerns on this embodiment. It is a circuit block diagram which shows one structural example of the electric current holding part (current holding circuit) applicable to the data driver of the display apparatus which concerns on this embodiment. It is a conceptual diagram which shows schematic operation | movement of the electric current holding | maintenance part applicable to this embodiment. 4 is a timing chart illustrating a drive control method for the display device according to the embodiment. FIG. 6 is a circuit configuration diagram showing a specific example of display pixels (pixel drive circuit, light emitting element) applicable to the display device according to the present invention. It is a conceptual diagram which shows the drive control operation | movement in the display pixel (pixel drive circuit) which concerns on this structural example. It is a timing chart which shows drive control operation in a display device at the time of applying a display pixel concerning this example of composition. It is a schematic block diagram which shows one structural example of the display apparatus to which the display pixel which concerns on this structural example is applied. It is the schematic which shows the principal part structural example of the light emitting element type display in a prior art. It is an equivalent circuit diagram which shows the structural example of the display pixel applied to the light emitting element type display in a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Display apparatus 110 Display panel 120 Scan driver 130 Data driver 136 Current holding circuit 140 System controller 150 Display signal generation part CGN Current generation circuit CHL Current holding part SLi Scan line DGj Data line group EM Display pixel DC Pixel drive circuit OEL Organic EL element

Claims (11)

In a display driving device for driving each display pixel by supplying gradation current based on display data to a plurality of display pixels arranged in a two-dimensional array constituting a display panel.
at least,
Pixel selection means for sequentially setting each of the display pixels in a plurality of adjacent rows of the display panel to a selected state at a predetermined timing having a period that does not overlap each other and a period that overlaps each other;
Current generating means for generating a signal current having a predetermined current value for controlling the luminance gradation of each display pixel based on the display data;
The signal currents corresponding to the display pixels in the predetermined plurality of adjacent rows of the display panel are sequentially fetched, the gradation current based on the signal current is generated, and the gradation current is set at the predetermined timing. Correspondingly to each of the display pixels of the predetermined plurality of rows set in the selected state via a plurality of data lines corresponding to each of the display pixels of the adjacent rows of the display panel Current writing means for sequentially supplying the non-overlapping period and the overlapping period;
And the current writing means includes a plurality of current holding circuits that output the gradation current to the plurality of data lines at the predetermined timing,
Each of the current holding circuits includes a signal holding unit that holds the signal current corresponding to the display pixels in each column of the plurality of adjacent rows of the display panel, and the signal current is supplied to the signal holding unit. A signal distribution unit that distributes, and a current corresponding to the signal current held in the signal holding unit is generated as the gradation current, and the gradation current is set over the period set in the selected state. A plurality of current holding / output units having gradation current output units that output to the display pixels of the predetermined plurality of rows ,
The current holding circuit captures and holds the signal current corresponding to the display pixels in one row of the plurality of rows by one current holding / output unit, and at the same time, the gradation current based on the signal current. The gradation output based on the signal current corresponding to the display pixel in the row adjacent to the one row by the operation of outputting to the data line corresponding to the row and any other current holding / output unit the operation for outputting a current to the data line corresponding to the row display driving apparatus characterized that you used simultaneously in a period of the overlap. 2. The display driving apparatus according to claim 1, wherein at least the current writing means is provided independently of a substrate on which the display panel is formed. The display driving device according to claim 1, wherein the signal holding unit includes charge accumulation means for accumulating electric charges based on the signal current and holding the electric charges as voltage components. The gradation current output unit has a current mirror circuit configuration, generates the gradation current having a current value of a predetermined current ratio with respect to the signal current supplied from the current generation unit, and The display driving device according to claim 1, wherein the display driving device outputs to the display pixels in each row. At least, the current writing means, the display driving device according to any one of claims 1 to 4, characterized in that it is configured with a field effect transistor having the same channel polarity. A predetermined current corresponding to display data for a plurality of display pixels arranged in the vicinity of intersections of a plurality of scanning lines arranged in the row direction of the display panel and a plurality of data lines arranged in the column direction. In the display device that drives the display pixel by supplying a gradation current having a value and displays desired image information on the display panel,
at least,
The display panel in which a data line group including a plurality of data lines corresponding to the display pixels in a predetermined plurality of adjacent rows is disposed in each column;
A scanning signal is sequentially applied to each of the plurality of scanning lines corresponding to the plurality of adjacent rows on the display panel at a predetermined timing having overlapping periods, and connected to the scanning lines. A scan driving circuit for sequentially setting the display pixels to a selected state having a period that does not overlap with each other and a period that overlaps each other;
Current generation means for generating a signal current having a predetermined current value for controlling the luminance gradation of each display pixel of the display panel based on the display data, and display of the predetermined plurality of rows of the display panel The signal currents corresponding to the pixels are sequentially taken in, the gradation current based on the signal current is generated, and the gradation current is applied to each of the display pixels in the predetermined plurality of rows set in the selected state. A signal drive circuit comprising current writing means for supplying the non-overlapping period and the overlapping period;
With
The current writing means of the signal driving circuit includes a plurality of current holding circuits that output the grayscale current to the data line group of each column of the display panel at the predetermined timing,
Each current holding circuit holds a signal current corresponding to the display pixel in each column of the predetermined plurality of rows of the display panel, and distributes the signal current to the signal holding unit A signal distribution unit; and a current corresponding to the signal current held in the signal holding unit is generated as the gradation current, and the gradation current is set to the predetermined state over a period set in the selected state. A plurality of current holding / output units having gradation current output units that output to the display pixels of the plurality of rows ,
The current holding circuit captures and holds the signal current corresponding to the display pixels in one row of the plurality of rows by one current holding / output unit, and at the same time, the gradation current based on the signal current The gradation current based on the signal current corresponding to the display pixel in the row adjacent to the one row by the operation of outputting to the data line corresponding to the row and any other current holding / output unit a display device an operation and for outputting to the data lines corresponding to the row, characterized that you used simultaneously in a period of the overlap. The display device according to claim 6 , wherein at least the signal driving circuit is provided independently of a substrate on which the display panel is formed. The display pixels arranged in the display panel are:
A light emission drive circuit that generates a predetermined light emission drive current based on the gradation current;
A current-controlled light-emitting element that emits light at a predetermined luminance gradation based on the current value of the light emission drive current supplied from the light emission drive circuit;
Display device according to any one of claims 6-7, characterized in that it comprises a. 9. The display device according to claim 8 , wherein at least the light emission drive circuit is configured using field effect transistors having the same channel polarity. The light emitting device, a display device according to claim 8 or 9, characterized in that an organic electroluminescence element. A gradation current corresponding to display data is supplied to each display pixel of a display panel in which a plurality of display pixels are arranged in the vicinity of intersections of a plurality of scanning lines and data lines arranged in a row direction and a column direction. In the display device driving control method for driving the display pixels and displaying desired image information on the display panel,
Sequentially setting each of the display pixels in a plurality of adjacent rows of the display panel to a selected state at a predetermined timing having a period that does not overlap each other and a period that overlaps each other;
Generating and outputting a signal current having a predetermined current value for controlling the luminance gradation of each display pixel based on the display data;
The output signal current is distributed corresponding to each of the plurality of display pixels in each column of the plurality of adjacent rows of the display panel, and the distributed signal current is sequentially captured, and the plurality of rows Each row is held corresponding to each display pixel in each column, and the gradation current based on the signal current is generated, and the gradation current is set in the selected state in correspondence with the predetermined timing. Sequentially supplying the display pixels with the non-overlapping period and the overlapping period over the period of the selection state;
Only including,
The step of sequentially supplying the gradation current to the display pixels in the plurality of rows set in the selected state with the overlapping period includes the steps of: An operation of supplying the gradation current based on the signal current to the display pixel of the row at the same time as capturing and holding the signal current corresponding to the display pixel of the row, and the display pixel of the row adjacent to the one row An operation of supplying the gradation current based on the signal current corresponding to the display pixel corresponding to the row to the display pixel corresponding to the row simultaneously in the overlapping period. .

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